
********Hello Huawei LiteOS********

KpxxxxIMU Firmware Version : VX.X.X
LiteOS Kernel Version : 5.7.0
Run on ChipVersion[0] Node[0] Die[2]
build time : Oct 27 2025 20:30:00

**********************************

main core booting up...
start set affinity

mpidr = 0x81020000
sram ecc state: 0x0, sram ecc cnt: 0x0
[0.00.00.032]node 0 begins init all serdes.
BoardInfo->NodeNum 2.
BoardInfo->NodeId 0.
BoardInfo->InfoVersion 5.
BoardInfo->NASerdesSceneMode 3.
BoardInfo->NBSerdesSceneMode 3.
BoardInfo->HccsTopologyType 0.
BoardInfo->BoardId 0.
ChipVersionIsPro: 0.
BoardInfo Node 0, SerdesUseMode: 1 2 1 1 1 1 1  1 1 1 4 4 1 12 
BoardInfo Node 1, SerdesUseMode: 1 1 1 1 1 1 1  12 13 1 4 4 1 1 
BoardInfo Node 0, SerdesRxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 1, SerdesRxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 0, SerdesTxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 1, SerdesTxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
serdessdk version: 2.0_5.0_20241203_imu
node_id 0, die 0, ind 0, usemode 1 begin serdes-init.
node_id 0, die 0, ind 1, usemode 2 begin serdes-init.
node_id 0, die 2, ind 0, usemode 1 begin serdes-init.
node_id 0, die 2, ind 1, usemode 1 begin serdes-init.
node_id 0, die 2, ind 6, usemode 12 begin serdes-init.
chip_id 0, die 2, ind 6, usemode 12 don't support, power down macro!
NodeId 0, DieId 2, Macro 6, power-down DS succeed.
NodeId 0, DieId 2, Macro 6, power-down DS succeed.
NodeId 0, DieId 2, Macro 6, power-down DS succeed.
NodeId 0, DieId 2, Macro 6, power-down DS succeed.
NodeId 0, DieId 2, Macro 6, power-down DS succeed.
NodeId 0, DieId 2, Macro 6, power-down DS succeed.
NodeId 0, DieId 2, Macro 6, power-down DS succeed.
NodeId 0, DieId 2, Macro 6, power-down DS succeed.
chip serdes init status:0x0.
[0.00.00.432]node 0 ends init all serdes.
link[4] freq_type:1 | peer_chip_type:1 | peer_node_id:1 | peer_link_id:5
link[5] freq_type:1 | peer_chip_type:1 | peer_node_id:1 | peer_link_id:4
register hccs done
IsFfeAdapt = 0.Use Default HCCS FFE Paras.
nodeId 0, dieId 1, linkId 0, FFE info: fir_pre1 -8, fir_main 55, fir_post1 0
node_id 0, die 2, ind 4, usemode 4 begin serdes-init.
IsFfeAdapt = 0.Use Default HCCS FFE Paras.
nodeId 0, dieId 1, linkId 1, FFE info: fir_pre1 -8, fir_main 55, fir_post1 0
node_id 0, die 2, ind 3, usemode 4 begin serdes-init.
hccs init start...
pa ring link down success
reset pa success
link[4] pcs init success
link[5] pcs init success
release reset pa success
link[4] macro adapt done (lane_mask=0xff) (0ms)
link[5] macro adapt done (lane_mask=0xff) (0ms)
link[4] pcs training success (10ms)
link[5] pcs training success (10ms)
link[4] training success (20ms)
link[5] training success (20ms)
link[4]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link[5]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link training success
pa[0] linkEn = 0x0
pa[0] allNodeLink0 = 0x0
pa[0] allNodeLink1 = 0x0
pa[1] linkEn = 0x3
pa[1] allNodeLink0 = 0x30
pa[1] allNodeLink1 = 0x0
pa init success
COM_PAID_INTLV_REG = 0x2
paid decode init success
pa[0] PA_PM_BASE_INFO = 0x0
pa[0] PA_PM_MAP_LINK_NUM = 0x0
pa[1] PA_PM_BASE_INFO = 0x330021
pa[1] PA_PM_MAP_LINK_NUM = 0x12
hccs performace config success
pa ring link up success
hccs init done
hccs access test start
node[0] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[1] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[1] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
hccs access test success
======hccs status======
  node[0] mask: expected = 0x30, link up = 0x30, width reduction = 0x0, link down = 0x0
  node[1] mask: expected = 0x30, link up = 0x30, width reduction = 0x0, link down = 0x0
==========end==========
report hccs status success
node[0] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
LRDXSD_LOCK_OFFSET = 0x0
LRDXSD_ERRIMSK_OFFSET = 0x0
LRDXSD_DBG_OTIMSK_OFFSET = 0x0
LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
LRDXSD_DBG_EN_OFFSET = 0x1
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
ID[0x1a67c8]!
[ERR]Don't support the flash, CS[0] ID[0x1a67c8]!!
ID[0x0]!
[ERR]Don't support the flash, CS[1] ID[0x0]!!
[ERR]Warnning, Select Default flash 
sfdp detect, try to get dummy data from hboot1 first.
ID[0x1a67c8]!
flash 0 support sfdp.
Interrupt 423 register OK
Interrupt 425 register OK
Interrupt 427 register OK
Interrupt 429 register OK
Interrupt 430 register OK
Interrupt 431 register OK
Interrupt 436 register OK

cpu 0 entering scheduler
[IMU] Watchdog Initialization done!
ScmiTaskEntry start.
Interrupt 456 register OK
Interrupt 469 register OK
Interrupt 482 register OK
Interrupt 495 register OK
starting Fpc Isolation Task end
starting fdm Err Info Task end
starting Roce recovery Task end
starting Ce_Storm Contrl Task end
starting Ras_Data_Update Task end
power register ubios call id
print register ubios call id
Interrupt 459 register OK
Interrupt 472 register OK
Interrupt 485 register OK
Interrupt 498 register OK
[0.00.13.273]Real time now 2026.3.17 07:25:26
NIC CARD[0][0]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[0][1]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[1][0]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[1][1]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
Init heart-beat-task end
Init SeamlessUpdateTask end
Init alarm-report-task end
pool addr          pool size    used size     free size    max free node size   used node num     free node num      UsageWaterLine
---------------    --------     -------       --------     --------------       -------------      ------------      ------------
0x8409090488       0x1e740      0x1b420       0x30b0       0x30b0               0x6c               0x1                0x1b690        
Get Setup Config.
pwr cap[0]: 0, 63
Node 0, Die 0 ImpState is 0 skip exec.
Node 0, Die 2 ImpState is 0 skip exec.
Node 1, Die 0 ImpState is 0 skip exec.
Node 1, Die 2 ImpState is 0 skip exec.
pwr cap[1]: f, 27
pwr cap[2]: 1, 3
[0.00.36.416]DDR Rreserved for IMU: len = 3e00000
[LOG]head = 0x0, tail = 0x1a1f, logSize = 0x1a1f
copy registry.json file success
Set component all release version to sram end.
ipcMsgSend success
[0.00.36.453]starting ras Init
nodeId = 0, dieId = 0, isSasExist = 0.
nodeId = 0, dieId = 2, isSasExist = 0.
nodeId = 1, dieId = 0, isSasExist = 0.
nodeId = 1, dieId = 2, isSasExist = 0.
Mce Table head exist!
RasIntRegister init 452 
RasIntRegister init 453 
RasIntRegister init 465 
RasIntRegister init 466 
RasIntRegister init 86 
RasIntRegister init 87 
RasIntRegister init 478 
RasIntRegister init 479 
RasIntRegister init 491 
RasIntRegister init 492 
RasIntRegister init 130 
RasIntRegister init 131 
RasIntRegister init 98 
RasIntRegister init 142 
[0.00.36.502]starting ras end
[0.00.43.704][ERR]cmd not support! cmd = 0xd
[0.00.57.865]PCIE INIT DONE.
Interrupt 454 register OK
Interrupt 467 register OK
Interrupt 480 register OK
Interrupt 493 register OK
data = 0x0
pmt Init done

Add ep: bdf=300 eid=9 epCnt=1 eid_alloc=a
mctp task ok.
[0.01.27.555]BIOS POST END.
Create SetReportPcieMmioToBmc ok.
Start SetReportPcieMmioToBmc ok.
slotNum = 0x18
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[0] port:4  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[1] port:6  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[2] port:12  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[3] port:14  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[4] port:16  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[5] port:18  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[6] port:20  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[7] port:22  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[8] port:24  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[9] port:26  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[10] port:32  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[11] port:34  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[12] port:0  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[13] port:2  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[14] port:12  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[15] port:14  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[16] port:16  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[17] port:18  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[18] port:24  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[19] port:26  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[20] port:32  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[21] port:34  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[22] port:36  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[23] port:38  pcieSlotCtrl.data (after)0x7c0.

Enter current value process


HSM_LOG:
[00:00:00.000][info] succeed to do thirdparty dfx_pabuk init
[00:00:00.000][info] succeed to do thirdparty crypto_driver init


0>[TracePoint] type[  0] cmd[  1] data[  4]
0>
Board Info:
0>  chip version        : 0
0>  efuse pg cluster TB : 0x0
0>  ak mode             : 0
0>
0>[TracePoint] type[  0] cmd[  1] data[  5]
0>Voltage Type[3]
0>Core Vmin Formula:
0>Totem[1] Core 400MHZ Vol Changed From [790] mv to [810] mv
0>Totem[1] Core 400MHZ -> Vol[790] mv
0>Totem[1] Core 2000MHZ Vol Changed From [763] mv to [810] mv
0>Totem[1] Core 2000MHZ -> Vol[763] mv
0>Totem[1] Core 2300MHZ -> Vol[833] mv
0>Totem[1] Core 2600MHZ -> Vol[911] mv
0>Totem[1] Core 2900MHZ -> Vol[986] mv
0>Totem[1] Core 3100MHZ -> Vol[1032] mv
0>Uncore Vmin Formula:
0>Totem Uncore 400MHZ -> Vol[830] mv
0>Totem[1] Uncore 2000MHZ Vol Changed From [766] mv to [830] mv
0>Totem Uncore 2000MHZ -> Vol[766] mv
0>Totem[2] Uncore 2300MHZ Vol Changed From [816] mv to [830] mv
0>Totem Uncore 2300MHZ -> Vol[816] mv
0>Totem Uncore 2500MHZ -> Vol[848] mv
0>Totem Uncore 2700MHZ -> Vol[891] mv
0>Totem Uncore 2900MHZ -> Vol[933] mv
0>Core VF curve:
0>[ 400]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[ 450]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[ 500]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[ 550]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[ 600]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[ 650]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[ 700]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[ 750]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[ 800]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[ 850]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[ 900]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[ 950]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1000]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1050]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1100]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1150]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1200]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1250]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1300]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1350]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1400]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1450]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1500]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1550]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1600]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1650]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1700]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1750]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1800]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1850]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1900]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1950]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[2000]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[2050]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[2100]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[2150]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[2200]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[2250]MHZ -> Vol TA[ 810]mv TB[ 821]mv
0>[2300]MHZ -> Vol TA[ 810]mv TB[ 833]mv
0>[2350]MHZ -> Vol TA[ 810]mv TB[ 846]mv
0>[2400]MHZ -> Vol TA[ 810]mv TB[ 859]mv
0>[2450]MHZ -> Vol TA[ 810]mv TB[ 872]mv
0>[2500]MHZ -> Vol TA[ 810]mv TB[ 885]mv
0>[2550]MHZ -> Vol TA[ 810]mv TB[ 898]mv
0>[2600]MHZ -> Vol TA[ 810]mv TB[ 911]mv
0>[2650]MHZ -> Vol TA[ 810]mv TB[ 923]mv
0>[2700]MHZ -> Vol TA[ 810]mv TB[ 936]mv
0>[2750]MHZ -> Vol TA[ 810]mv TB[ 948]mv
0>[2800]MHZ -> Vol TA[ 810]mv TB[ 961]mv
0>[2850]MHZ -> Vol TA[ 810]mv TB[ 973]mv
0>[2900]MHZ -> Vol TA[ 810]mv TB[ 986]mv
0>[2950]MHZ -> Vol TA[ 810]mv TB[ 997]mv
0>[3000]MHZ -> Vol TA[ 810]mv TB[1009]mv
0>[3050]MHZ -> Vol TA[ 810]mv TB[1020]mv
0>[3100]MHZ -> Vol TA[ 810]mv TB[1032]mv
0>Uncore VF curve:
0>Uncore [   0]MHZ -> Vol [ 830]mv
0>Uncore [ 100]MHZ -> Vol [ 830]mv
0>Uncore [ 200]MHZ -> Vol [ 830]mv
0>Uncore [ 300]MHZ -> Vol [ 830]mv
0>Uncore [ 400]MHZ -> Vol [ 830]mv
0>Uncore [ 500]MHZ -> Vol [ 830]mv
0>Uncore [ 600]MHZ -> Vol [ 830]mv
0>Uncore [ 700]MHZ -> Vol [ 830]mv
0>Uncore [ 800]MHZ -> Vol [ 830]mv
0>Uncore [ 900]MHZ -> Vol [ 830]mv
0>Uncore [1000]MHZ -> Vol [ 830]mv
0>Uncore [1100]MHZ -> Vol [ 830]mv
0>Uncore [1200]MHZ -> Vol [ 830]mv
0>Uncore [1300]MHZ -> Vol [ 830]mv
0>Uncore [1400]MHZ -> Vol [ 830]mv
0>Uncore [1500]MHZ -> Vol [ 830]mv
0>Uncore [1600]MHZ -> Vol [ 830]mv
0>Uncore [1700]MHZ -> Vol [ 830]mv
0>Uncore [1800]MHZ -> Vol [ 830]mv
0>Uncore [1900]MHZ -> Vol [ 830]mv
0>Uncore [2000]MHZ -> Vol [ 830]mv
0>Uncore [2100]MHZ -> Vol [ 830]mv
0>Uncore [2200]MHZ -> Vol [ 830]mv
0>Uncore [2300]MHZ -> Vol [ 830]mv
0>Uncore [2400]MHZ -> Vol [ 832]mv
0>Uncore [2500]MHZ -> Vol [ 848]mv
0>Uncore [2600]MHZ -> Vol [ 869]mv
0>Uncore [2700]MHZ -> Vol [ 891]mv
0>Uncore [2800]MHZ -> Vol [ 912]mv
0>Uncore [2900]MHZ -> Vol [ 933]mv
0>Uncore [3000]MHZ -> Vol [1100]mv
0>[TracePoint] type[  0] cmd[  1] data[  6]
0>[TracePoint] type[  0] cmd[  1] data[  7]
0>
********Hello Huawei LiteOS********

KpxxxxIPU Firmware Version : VX.X.X
LiteOS Kernel Version : 5.7.0
0>Run on ChipVersion[0] Node[0] Die[0]
0>build time : Oct 27 2025 20:30:00

0>**********************************
0>
main core booting up...
0>start set affinity
0>
mpidr = 0x81000000
0>sram ecc state: 0x0, sram ecc cnt: 0x0
0>[TracePoint] type[  0] cmd[  2] data[  1]
0>[TracePoint] type[  0] cmd[  2] data[  2]
0>LRDXSD_LOCK_OFFSET = 0x0
0>LRDXSD_ERRIMSK_OFFSET = 0x0
0>LRDXSD_DBG_OTIMSK_OFFSET = 0x0
0>LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
0>LRDXSD_DBG_EN_OFFSET = 0x1
0>======tsensor params======
0>  is_trimmed       : 1
0>  underclocking_en : 1
0>===========end============
0>soc tsensor init done
0>========vrd info from cpld========
0>vrd_id | u64                | pmbus_en | avsbus_en | loop | pmbus_id | pmbus_addr | avs_sw | pmbus_sw | addr_9545 | domain_type | die_mask | reserved
0>  00   | 0x0003000300002b15 | 0x1      | 0x0       | 0x1  | 0x1      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x3         | 0x0300   | 0x0
0>  01   | 0x000001050000201b | 0x1      | 0x1       | 0x2  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0001   | 0x0
0>  02   | 0x0002000100002017 | 0x1      | 0x1       | 0x1  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0200   | 0x0
0>  03   | 0x0003000200002027 | 0x1      | 0x1       | 0x1  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x2         | 0x0300   | 0x0
0>  04   | 0x000002050000202b | 0x1      | 0x1       | 0x2  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0002   | 0x0
0>  05   | 0x0003000400002b19 | 0x1      | 0x0       | 0x2  | 0x1      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x4         | 0x0300   | 0x0
0>  06   | 0x0000000000000000 | 0x0      | 0x0       | 0x0  | 0x0      | 0x00       | 0x0    | 0x0      | 0x0       | 0x0         | 0x0000   | 0x0
0>================end===============
0>[ERR]0>vrd[6] info invalid, vrd_info = 0x0
0>default power domain data used
0>=============vrd info=============
0>power domain num: 6
0>power domain[00] id:2 | CORE_DVFS_TB       | PMBus NA | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
0>power domain[01] id:4 | IO_DVDD_NA         | PMBus NA | cap:0x3 | rail:1 | addr:0x20 | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
0>power domain[02] id:3 | UNCORE_DVFS        | PMBus NB | cap:0x3 | rail:0 | addr:0x20 | def_volt: 848 mV | min_volt: 750 mV | max_volt:1100 mV
0>power domain[03] id:5 | IO_DVDD_NB         | PMBus NB | cap:0x3 | rail:1 | addr:0x20 | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
0>power domain[04] id:1 | DDR_VDD            | PMBus NA | cap:0x1 | rail:0 | addr:0x2b | def_volt: 765 mV | min_volt: 650 mV | max_volt: 850 mV
0>power domain[05] id:6 | DDR_VDDQ           | PMBus NA | cap:0x1 | rail:1 | addr:0x2b | def_volt:1100 mV | min_volt:1000 mV | max_volt:1200 mV
0>================end===============
0>pmbus[0] init done
0>pmbus[1] init done
0>power domain[2] CORE_DVFS_TB       | NA PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
0>power domain[4] IO_DVDD_NA         | NA PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 800 mV | pmu:MP2882
0>power domain[3] UNCORE_DVFS        | NB PMBus/AVSBus | rail:0 | addr:0x20 | def_volt: 848 mV | pmu:MP2882
0>power domain[5] IO_DVDD_NB         | NB PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 800 mV | pmu:MP2882
0>power domain[1] DDR_VDD            | NA PMBus        | rail:0 | addr:0x2b | def_volt: 765 mV | pmu:MP2882
0>power domain[6] DDR_VDDQ           | NA PMBus        | rail:1 | addr:0x2b | def_volt:1100 mV | pmu:MP2882
0>power domain[2] CORE_DVFS_TB       is transferred to AVSBus mode
0>power domain[4] IO_DVDD_NA         is transferred to AVSBus mode
0>power domain[3] UNCORE_DVFS        is transferred to AVSBus mode
0>power domain[5] IO_DVDD_NB         is transferred to AVSBus mode
0>avsbus resync success
0>avsbus[0] init done
0>avsbus resync success
0>avsbus[1] init done
0>============volt boot============
0>power domain[2] volt = 1105 mV
0>power domain[4] volt =  804 mV
0>power domain[3] volt = 1005 mV
0>power domain[5] volt =  804 mV
0>power domain[1] volt =  767 mV
0>power domain[6] volt = 1103 mV
0>===============end===============
0>power domain[0] not exist
0>--w&h rd rail:0, 1105, CORE_DVFS_TB
0>--w&h rd rail:1, 800, CORE_DVFS_TB
0>power domain[2] set volt --> 1105 mV success
0>--w&h rd rail:0, 1005, UNCORE_DVFS
0>--w&h rd rail:1, 800, UNCORE_DVFS
0>power domain[3] set volt -->  851 mV success
0>============volt post============
0>power domain[2] volt = 1105 mV
0>power domain[4] volt =  804 mV
0>power domain[3] volt =  851 mV
0>power domain[5] volt =  802 mV
0>power domain[1] volt =  767 mV
0>power domain[6] volt = 1105 mV
0>===============end===============
0>Hboot1 Info RAW Dump: [0x91][0x00][0x00][0x14][0x01][0x00][0x01]
0>PowerSensorSupport[1], Cali[5120], Loss[7200]
0>Power Sensor Calibration Value[5120]!
0>the power sensor : manu id = 2peak, die id = TPA626
0>power sensor[0] init success
0>Totem[1] Core Boot Vol [1105]mv
0>Totem[1] Core Current Vol [1100]mv
0>NA 1620V1b0
0>NB 1620V1b0
0>GetCoreBaseFreq [2600000KHZ]
0>GetCoreTurboFreq [2600000KHZ]
0>GetCustomClusterNum [10]
0>Ipu ACG Training Done!
0>AP Last Time:[0.00.01.394]
0>wait UEFI pll init...
0>done
0>acg trim start
0>core trim freq:2000, avs:0 volt:810mv
0>core trim freq:2050, avs:1 volt:810mv
0>core trim freq:2100, avs:2 volt:810mv
0>core trim freq:2150, avs:3 volt:810mv
0>core trim freq:2200, avs:4 volt:810mv
0>core trim freq:2250, avs:5 volt:821mv
0>core trim freq:2300, avs:6 volt:833mv
0>core trim freq:2350, avs:7 volt:846mv
0>core trim freq:2400, avs:8 volt:859mv
0>core trim freq:2450, avs:9 volt:872mv
0>core trim freq:2500, avs:10 volt:885mv
0>core trim freq:2550, avs:11 volt:898mv
0>core trim freq:2600, avs:12 volt:911mv
0>core trim freq:2650, avs:13 volt:923mv
0>core trim freq:2700, avs:14 volt:936mv
0>core trim freq:2750, avs:15 volt:948mv
0>core trim freq:2800, avs:16 volt:961mv
0>core trim freq:2850, avs:17 volt:973mv
0>core trim freq:2900, avs:18 volt:986mv
0>core trim freq:2950, avs:19 volt:997mv
0>core trim freq:3000, avs:20 volt:1009mv
0>core trim freq:3050, avs:21 volt:1020mv
0>core trim freq:3100, avs:22 volt:1032mv
0>acg trim end
0>LDO disabled
0>[TracePoint] type[  0] cmd[  2] data[  3]
0>Interrupt 423 register OK
0>Interrupt 430 register OK
0>[TracePoint] type[  0] cmd[  2] data[  4]
0>
0>cpu 0 entering scheduler
0>[TracePoint] type[  0] cmd[  3] data[  1]
0>add your ipu app init here!
0>IpuInterfaceTaskStart Entry ...
0>ipu interface task wait parameters from uefi...
0>thermal soc task enabled
0>AP Last Time:[0.00.14.701]
0>ThermalDimmStart Entry ...
0>wait ddr init done...
0>power task start...
0>[TracePoint] type[  0] cmd[  3] data[  2]
0>ufs task wait parameters from uefi...
0>AmuTaskStart Entry ... 
0>amu task wait parameters from uefi...
0>ThermalSiwStart Entry ...
0>ThermalSiwTask idle...
0>DemtTaskStart Entry ...
0>[TracePoint] type[  0] cmd[  3] data[  3]
0>demt task wait parameters from uefi...
0>HiBoostTaskStart Entry ...
0>HiBoost task enabled
0>Waiting for UEFI parameters...
0>[TracePoint] type[  0] cmd[  3] data[  4]
0>AgeTaskStart Entry ...
0>[TracePoint] type[  0] cmd[  3] data[  5]
0>age task wait parameters from uefi...
0>uefi parameters ready!
0>UFSProfile[0]
0>PowerPolicy[2] BenchMarkSelection[0]
0>ipu interface task wait ddr init done from uefi...
0>ufs task parameters from uefi ready
0>uncore domain[1] freq:2500
0>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
0>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
0>======sioe status======
0>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
0>thermal soc task restore underclocking_en=1
0>ppu alert temp div init done
0>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
0>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
0>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
0>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
0>==========end==========
0>sioe init done
0>ufs task enabled
0>--> UFS profile[0]
0>UEFI parameters ready
0>UncoreMaxFreq Set to [2500 MHZ]
0>get TDP from efuse success, value = 185000mw
0>target power set to [185000]mw, brd:[185000]
0>demt task parameters from uefi ready
0>age task parameters from uefi ready
0>age task enabled
0>uefi ddr init finish!
0>ipu interface task wait uefi end done from uefi...
0>ddr init done, start thermal dimm task
0>======dimm status======
0>  chl[0] dimm0 0, dimm1 0
0>  chl[1] dimm0 0, dimm1 0
0>  chl[2] dimm0 2, dimm1 0
0>  chl[3] dimm0 0, dimm1 0
0>  chl[4] dimm0 0, dimm1 0
0>  chl[5] dimm0 0, dimm1 0
0>  chl[6] dimm0 0, dimm1 0
0>  chl[7] dimm0 0, dimm1 0
0>==========end==========
0>chl[2] registered, dimm mask = 0x1
0>=====dimm temp params=====
0>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
0>  is_thermal_thro_en  : 1
0>  is_aref_rate_auto   : 1
0>===========end============
0>chl[2] max_temp 33'C, aref_rate 0x5 --> 0x4
0>uefi end finish!
0>ipu interface task exit!
0>amu task parameters from uefi ready
0>amu task activated
0>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
1>[TracePoint] type[  0] cmd[  1] data[  4]
1>
Board Info:
1>  chip version        : 0
1>  efuse pg cluster TB : 0x0
1>  ak mode             : 0
1>
1>[TracePoint] type[  0] cmd[  1] data[  5]
1>Voltage Type[3]
1>Core Vmin Formula:
1>Totem[1] Core 400MHZ Vol Changed From [790] mv to [810] mv
1>Totem[1] Core 400MHZ -> Vol[790] mv
1>Totem[1] Core 2000MHZ Vol Changed From [763] mv to [810] mv
1>Totem[1] Core 2000MHZ -> Vol[763] mv
1>Totem[1] Core 2300MHZ -> Vol[832] mv
1>Totem[1] Core 2600MHZ -> Vol[910] mv
1>Totem[1] Core 2900MHZ -> Vol[985] mv
1>Totem[1] Core 3100MHZ -> Vol[1031] mv
1>Uncore Vmin Formula:
1>Totem Uncore 400MHZ -> Vol[830] mv
1>Totem[1] Uncore 2000MHZ Vol Changed From [764] mv to [830] mv
1>Totem Uncore 2000MHZ -> Vol[764] mv
1>Totem[2] Uncore 2300MHZ Vol Changed From [814] mv to [830] mv
1>Totem Uncore 2300MHZ -> Vol[814] mv
1>Totem Uncore 2500MHZ -> Vol[846] mv
1>Totem Uncore 2700MHZ -> Vol[889] mv
1>Totem Uncore 2900MHZ -> Vol[930] mv
1>Core VF curve:
1>[ 400]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[ 450]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[ 500]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[ 550]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[ 600]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[ 650]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[ 700]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[ 750]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[ 800]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[ 850]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[ 900]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[ 950]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1000]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1050]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1100]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1150]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1200]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1250]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1300]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1350]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1400]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1450]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1500]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1550]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1600]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1650]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1700]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1750]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1800]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1850]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1900]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1950]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[2000]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[2050]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[2100]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[2150]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[2200]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[2250]MHZ -> Vol TA[ 810]mv TB[ 820]mv
1>[2300]MHZ -> Vol TA[ 810]mv TB[ 832]mv
1>[2350]MHZ -> Vol TA[ 810]mv TB[ 845]mv
1>[2400]MHZ -> Vol TA[ 810]mv TB[ 858]mv
1>[2450]MHZ -> Vol TA[ 810]mv TB[ 871]mv
1>[2500]MHZ -> Vol TA[ 810]mv TB[ 884]mv
1>[2550]MHZ -> Vol TA[ 810]mv TB[ 897]mv
1>[2600]MHZ -> Vol TA[ 810]mv TB[ 910]mv
1>[2650]MHZ -> Vol TA[ 810]mv TB[ 922]mv
1>[2700]MHZ -> Vol TA[ 810]mv TB[ 935]mv
1>[2750]MHZ -> Vol TA[ 810]mv TB[ 947]mv
1>[2800]MHZ -> Vol TA[ 810]mv TB[ 960]mv
1>[2850]MHZ -> Vol TA[ 810]mv TB[ 972]mv
1>[2900]MHZ -> Vol TA[ 810]mv TB[ 985]mv
1>[2950]MHZ -> Vol TA[ 810]mv TB[ 996]mv
1>[3000]MHZ -> Vol TA[ 810]mv TB[1008]mv
1>[3050]MHZ -> Vol TA[ 810]mv TB[1019]mv
1>[3100]MHZ -> Vol TA[ 810]mv TB[1031]mv
1>Uncore VF curve:
1>Uncore [   0]MHZ -> Vol [ 830]mv
1>Uncore [ 100]MHZ -> Vol [ 830]mv
1>Uncore [ 200]MHZ -> Vol [ 830]mv
1>Uncore [ 300]MHZ -> Vol [ 830]mv
1>Uncore [ 400]MHZ -> Vol [ 830]mv
1>Uncore [ 500]MHZ -> Vol [ 830]mv
1>Uncore [ 600]MHZ -> Vol [ 830]mv
1>Uncore [ 700]MHZ -> Vol [ 830]mv
1>Uncore [ 800]MHZ -> Vol [ 830]mv
1>Uncore [ 900]MHZ -> Vol [ 830]mv
1>Uncore [1000]MHZ -> Vol [ 830]mv
1>Uncore [1100]MHZ -> Vol [ 830]mv
1>Uncore [1200]MHZ -> Vol [ 830]mv
1>Uncore [1300]MHZ -> Vol [ 830]mv
1>Uncore [1400]MHZ -> Vol [ 830]mv
1>Uncore [1500]MHZ -> Vol [ 830]mv
1>Uncore [1600]MHZ -> Vol [ 830]mv
1>Uncore [1700]MHZ -> Vol [ 830]mv
1>Uncore [1800]MHZ -> Vol [ 830]mv
1>Uncore [1900]MHZ -> Vol [ 830]mv
1>Uncore [2000]MHZ -> Vol [ 830]mv
1>Uncore [2100]MHZ -> Vol [ 830]mv
1>Uncore [2200]MHZ -> Vol [ 830]mv
1>Uncore [2300]MHZ -> Vol [ 830]mv
1>Uncore [2400]MHZ -> Vol [ 830]mv
1>Uncore [2500]MHZ -> Vol [ 846]mv
1>Uncore [2600]MHZ -> Vol [ 867]mv
1>Uncore [2700]MHZ -> Vol [ 889]mv
1>Uncore [2800]MHZ -> Vol [ 909]mv
1>Uncore [2900]MHZ -> Vol [ 930]mv
1>Uncore [3000]MHZ -> Vol [1100]mv
1>[TracePoint] type[  0] cmd[  1] data[  6]
1>[TracePoint] type[  0] cmd[  1] data[  7]
1>
********Hello Huawei LiteOS********

KpxxxxIPU Firmware Version : VX.X.X
LiteOS Kernel Version : 5.7.0
1>Run on ChipVersion[0] Node[1] Die[0]
1>build time : Oct 27 2025 20:30:00

1>**********************************
1>
main core booting up...
1>start set affinity
1>
mpidr = 0x81040000
1>sram ecc state: 0x0, sram ecc cnt: 0x0
1>[TracePoint] type[  0] cmd[  2] data[  1]
1>[TracePoint] type[  0] cmd[  2] data[  2]
1>LRDXSD_LOCK_OFFSET = 0x0
1>LRDXSD_ERRIMSK_OFFSET = 0x0
1>LRDXSD_DBG_OTIMSK_OFFSET = 0x0
1>LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
1>LRDXSD_DBG_EN_OFFSET = 0x1
1>======tsensor params======
1>  is_trimmed       : 1
1>  underclocking_en : 1
1>===========end============
1>soc tsensor init done
1>========vrd info from cpld========
1>vrd_id | u64                | pmbus_en | avsbus_en | loop | pmbus_id | pmbus_addr | avs_sw | pmbus_sw | addr_9545 | domain_type | die_mask | reserved
1>  00   | 0x0003000300002b15 | 0x1      | 0x0       | 0x1  | 0x1      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x3         | 0x0300   | 0x0
1>  01   | 0x000001050000201b | 0x1      | 0x1       | 0x2  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0001   | 0x0
1>  02   | 0x0002000100002017 | 0x1      | 0x1       | 0x1  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0200   | 0x0
1>  03   | 0x0003000200002027 | 0x1      | 0x1       | 0x1  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x2         | 0x0300   | 0x0
1>  04   | 0x000002050000202b | 0x1      | 0x1       | 0x2  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0002   | 0x0
1>  05   | 0x0003000400002b19 | 0x1      | 0x0       | 0x2  | 0x1      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x4         | 0x0300   | 0x0
1>  06   | 0x0000000000000000 | 0x0      | 0x0       | 0x0  | 0x0      | 0x00       | 0x0    | 0x0      | 0x0       | 0x0         | 0x0000   | 0x0
1>================end===============
1>[ERR]1>vrd[6] info invalid, vrd_info = 0x0
1>default power domain data used
1>=============vrd info=============
1>power domain num: 6
1>power domain[00] id:2 | CORE_DVFS_TB       | PMBus NA | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
1>power domain[01] id:4 | IO_DVDD_NA         | PMBus NA | cap:0x3 | rail:1 | addr:0x20 | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
1>power domain[02] id:3 | UNCORE_DVFS        | PMBus NB | cap:0x3 | rail:0 | addr:0x20 | def_volt: 846 mV | min_volt: 750 mV | max_volt:1100 mV
1>power domain[03] id:5 | IO_DVDD_NB         | PMBus NB | cap:0x3 | rail:1 | addr:0x20 | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
1>power domain[04] id:1 | DDR_VDD            | PMBus NA | cap:0x1 | rail:0 | addr:0x2b | def_volt: 765 mV | min_volt: 650 mV | max_volt: 850 mV
1>power domain[05] id:6 | DDR_VDDQ           | PMBus NA | cap:0x1 | rail:1 | addr:0x2b | def_volt:1100 mV | min_volt:1000 mV | max_volt:1200 mV
1>================end===============
1>pmbus[0] init done
1>pmbus[1] init done
1>power domain[2] CORE_DVFS_TB       | NA PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
1>power domain[4] IO_DVDD_NA         | NA PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 800 mV | pmu:MP2882
1>power domain[3] UNCORE_DVFS        | NB PMBus/AVSBus | rail:0 | addr:0x20 | def_volt: 846 mV | pmu:MP2882
1>power domain[5] IO_DVDD_NB         | NB PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 800 mV | pmu:MP2882
1>power domain[1] DDR_VDD            | NA PMBus        | rail:0 | addr:0x2b | def_volt: 765 mV | pmu:MP2882
1>power domain[6] DDR_VDDQ           | NA PMBus        | rail:1 | addr:0x2b | def_volt:1100 mV | pmu:MP2882
1>power domain[2] CORE_DVFS_TB       is transferred to AVSBus mode
1>power domain[4] IO_DVDD_NA         is transferred to AVSBus mode
1>power domain[3] UNCORE_DVFS        is transferred to AVSBus mode
1>power domain[5] IO_DVDD_NB         is transferred to AVSBus mode
1>avsbus resync success
1>avsbus[0] init done
1>avsbus resync success
1>avsbus[1] init done
1>============volt boot============
1>power domain[2] volt = 1101 mV
1>power domain[4] volt =  806 mV
1>power domain[3] volt = 1007 mV
1>power domain[5] volt =  802 mV
1>power domain[1] volt =  769 mV
1>power domain[6] volt = 1103 mV
1>===============end===============
1>power domain[0] not exist
1>--w&h rd rail:0, 1099, CORE_DVFS_TB
1>--w&h rd rail:1, 800, CORE_DVFS_TB
1>power domain[2] set volt --> 1101 mV success
1>--w&h rd rail:0, 1007, UNCORE_DVFS
1>--w&h rd rail:1, 800, UNCORE_DVFS
1>power domain[3] set volt -->  851 mV success
1>============volt post============
1>power domain[2] volt = 1099 mV
1>power domain[4] volt =  802 mV
1>power domain[3] volt =  851 mV
1>power domain[5] volt =  800 mV
1>power domain[1] volt =  769 mV
1>power domain[6] volt = 1103 mV
1>===============end===============
1>Hboot1 Info RAW Dump: [0x01][0x00][0x00][0x14][0x01][0x00][0x01]
1>PowerSensorSupport[1], Cali[5120], Loss[0]
1>Power Sensor Calibration Value[5120]!
1>the power sensor : manu id = 2peak, die id = TPA626
1>power sensor[0] init success
1>Totem[1] Core Boot Vol [1101]mv
1>Totem[1] Core Current Vol [1100]mv
1>NA 1620V1b0
1>NB 1620V1b0
1>GetCoreBaseFreq [2600000KHZ]
1>GetCoreTurboFreq [2600000KHZ]
1>GetCustomClusterNum [10]
1>Ipu ACG Training Done!
1>AP Last Time:[0.00.01.395]
1>wait UEFI pll init...
1>done
1>acg trim start
1>core trim freq:2000, avs:0 volt:810mv
1>core trim freq:2050, avs:1 volt:810mv
1>core trim freq:2100, avs:2 volt:810mv
1>core trim freq:2150, avs:3 volt:810mv
1>core trim freq:2200, avs:4 volt:810mv
1>core trim freq:2250, avs:5 volt:820mv
1>core trim freq:2300, avs:6 volt:832mv
1>core trim freq:2350, avs:7 volt:845mv
1>core trim freq:2400, avs:8 volt:858mv
1>core trim freq:2450, avs:9 volt:871mv
1>core trim freq:2500, avs:10 volt:884mv
1>core trim freq:2550, avs:11 volt:897mv
1>core trim freq:2600, avs:12 volt:910mv
1>core trim freq:2650, avs:13 volt:922mv
1>core trim freq:2700, avs:14 volt:935mv
1>core trim freq:2750, avs:15 volt:947mv
1>core trim freq:2800, avs:16 volt:960mv
1>core trim freq:2850, avs:17 volt:972mv
1>core trim freq:2900, avs:18 volt:985mv
1>core trim freq:2950, avs:19 volt:996mv
1>core trim freq:3000, avs:20 volt:1008mv
1>core trim freq:3050, avs:21 volt:1019mv
1>core trim freq:3100, avs:22 volt:1031mv
1>acg trim end
1>LDO disabled
1>[TracePoint] type[  0] cmd[  2] data[  3]
1>Interrupt 423 register OK
1>Interrupt 430 register OK
1>[TracePoint] type[  0] cmd[  2] data[  4]
1>
1>cpu 0 entering scheduler
1>[TracePoint] type[  0] cmd[  3] data[  1]
1>add your ipu app init here!
1>IpuInterfaceTaskStart Entry ...
1>ipu interface task wait parameters from uefi...
1>thermal soc task enabled
1>AP Last Time:[0.00.14.856]
1>ThermalDimmStart Entry ...
1>wait ddr init done...
1>power task start...
1>[TracePoint] type[  0] cmd[  3] data[  2]
1>ufs task wait parameters from uefi...
1>AmuTaskStart Entry ... 
1>amu task wait parameters from uefi...
1>ThermalSiwStart Entry ...
1>ThermalSiwTask idle...
1>DemtTaskStart Entry ...
1>[TracePoint] type[  0] cmd[  3] data[  3]
1>demt task wait parameters from uefi...
1>HiBoostTaskStart Entry ...
1>HiBoost task enabled
1>Waiting for UEFI parameters...
1>[TracePoint] type[  0] cmd[  3] data[  4]
1>AgeTaskStart Entry ...
1>[TracePoint] type[  0] cmd[  3] data[  5]
1>age task wait parameters from uefi...
1>uefi parameters ready!
1>UFSProfile[0]
1>PowerPolicy[2] BenchMarkSelection[0]
1>ipu interface task wait ddr init done from uefi...
1>ufs task parameters from uefi ready
1>uncore domain[1] freq:2500
1>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
1>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
1>======sioe status======
1>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
1>thermal soc task restore underclocking_en=1
1>ppu alert temp div init done
1>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
1>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
1>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
1>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
1>==========end==========
1>sioe init done
1>ufs task enabled
1>--> UFS profile[0]
1>UEFI parameters ready
1>UncoreMaxFreq Set to [2500 MHZ]
1>get TDP from efuse success, value = 185000mw
1>target power set to [185000]mw, brd:[185000]
1>demt task parameters from uefi ready
1>age task parameters from uefi ready
1>age task enabled
1>uefi ddr init finish!
1>ipu interface task wait uefi end done from uefi...
1>ddr init done, start thermal dimm task
1>======dimm status======
1>  chl[0] dimm0 0, dimm1 0
1>  chl[1] dimm0 0, dimm1 0
1>  chl[2] dimm0 2, dimm1 0
1>  chl[3] dimm0 0, dimm1 0
1>  chl[4] dimm0 0, dimm1 0
1>  chl[5] dimm0 0, dimm1 0
1>  chl[6] dimm0 0, dimm1 0
1>  chl[7] dimm0 0, dimm1 0
1>==========end==========
1>chl[2] registered, dimm mask = 0x1
1>=====dimm temp params=====
1>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
1>  is_thermal_thro_en  : 1
1>  is_aref_rate_auto   : 1
1>===========end============
1>chl[2] max_temp 34'C, aref_rate 0x5 --> 0x4
1>uefi end finish!
1>ipu interface task exit!
1>amu task parameters from uefi ready
1>amu task activated
1>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!


HSM_LOG:
[00:00:00.010][info] os_mem_system_init default pool done
[00:00:00.016][info] succeed to do thirdparty otpc_pabuk init
[00:00



HSM_LOG:
:00.017][info] succeed to do thirdparty boot_profile_driver init
[00:00:00.017][info] succeed to do thirdparty measure_value_ma



HSM_LOG:
nage_driver init
[00:00:00.018][info] succeed to do thirdparty period_driver init
[00:00:00.018][info]  start loading internal



HSM_LOG:
 task ...
[00:00:00.018][info]  task name is ccm_task
[00:00:00.019][info]  hm_dynamic_loadelf successfully!
[00:00:00.019][i



HSM_LOG:
nfo] internal task[1] task_name=ccm_task load successfully
[00:00:00.020][info]  task name is upgrade_task
[00:00:00.020][info



HSM_LOG:
]  hm_dynamic_loadelf successfully!
[00:00:00.021][info] internal task[2] task_name=upgrade_task load successfully
[00:00:00.0



HSM_LOG:
22][info]  task name is hes_task
[00:00:00.022][info]  hm_dynamic_loadelf successfully!
[00:00:00.023][info] internal task[3] 



HSM_LOG:
task_name=hes_task load successfully
[00:00:00.024][info] created task ccm_task success!
[00:00:00.025][info] created task upg



HSM_LOG:
rade_task success!
[00:00:00.026][info] created task hes_task success!
[00:00:00.026][info] Init start.
[1970-01-01 00:00:00.



HSM_LOG:
027][HSM][INFO][54] Platform init 0x20250523 0x4e.

[1970-01-01 00:00:00.027][HSM][INFO][197] ccm start.

[1970-01-01 00:00:00



HSM_LOG:
.028][HSM][INFO][86] upgrade task init success.

[1970-01-01 00:00:00.028][HSM][INFO][95] upgrade recv cmd, 0x181.

[1970-01-0



HSM_LOG:
1 00:00:00.029][HSM][INFO][103] upgrade res, 0x3a5aa5a3.

[1970-01-01 00:00:00.030][HSM][INFO][75] hes tee_task_entry.

[1970-



HSM_LOG:
01-01 00:00:00.556][HSM][INFO][44] hes init success.

[00:00:00.556][info] Init over.


[0.06.27.554]IpmiCmdReportPcieMMIO start
[0.06.38.283]IpmiCmdReportPcieMMIO end
pool addr          pool size    used size     free size    max free node size   used node num     free node num      UsageWaterLine
---------------    --------     -------       --------     --------------       -------------      ------------      ------------
0x8409090488       0x1e740      0x19dd0       0x4700       0x30b0               0x90               0x3                0x1b690        

********Hello Huawei LiteOS********

KpxxxxIMU Firmware Version : VX.X.X
LiteOS Kernel Version : 5.7.0
Run on ChipVersion[0] Node[0] Die[2]
build time : Oct 27 2025 20:30:00

**********************************

main core booting up...
start set affinity

mpidr = 0x81020000
sram ecc state: 0x0, sram ecc cnt: 0x0
[0.00.00.032]node 0 begins init all serdes.
BoardInfo->NodeNum 2.
BoardInfo->NodeId 0.
BoardInfo->InfoVersion 5.
BoardInfo->NASerdesSceneMode 3.
BoardInfo->NBSerdesSceneMode 3.
BoardInfo->HccsTopologyType 0.
BoardInfo->BoardId 0.
ChipVersionIsPro: 0.
BoardInfo Node 0, SerdesUseMode: 1 2 1 1 1 1 1  1 1 1 4 4 1 12 
BoardInfo Node 1, SerdesUseMode: 1 1 1 1 1 1 1  12 13 1 4 4 1 1 
BoardInfo Node 0, SerdesRxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 1, SerdesRxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 0, SerdesTxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 1, SerdesTxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
serdessdk version: 2.0_5.0_20241203_imu
node_id 0, die 0, ind 0, usemode 1 begin serdes-init.
node_id 0, die 0, ind 1, usemode 2 begin serdes-init.
node_id 0, die 2, ind 0, usemode 1 begin serdes-init.
node_id 0, die 2, ind 1, usemode 1 begin serdes-init.
node_id 0, die 2, ind 6, usemode 12 begin serdes-init.
chip_id 0, die 2, ind 6, usemode 12 don't support, power down macro!
NodeId 0, DieId 2, Macro 6, power-down DS succeed.
NodeId 0, DieId 2, Macro 6, power-down DS succeed.
NodeId 0, DieId 2, Macro 6, power-down DS succeed.
NodeId 0, DieId 2, Macro 6, power-down DS succeed.
NodeId 0, DieId 2, Macro 6, power-down DS succeed.
NodeId 0, DieId 2, Macro 6, power-down DS succeed.
NodeId 0, DieId 2, Macro 6, power-down DS succeed.
NodeId 0, DieId 2, Macro 6, power-down DS succeed.
chip serdes init status:0x0.
[0.00.00.432]node 0 ends init all serdes.
link[4] freq_type:1 | peer_chip_type:1 | peer_node_id:1 | peer_link_id:5
link[5] freq_type:1 | peer_chip_type:1 | peer_node_id:1 | peer_link_id:4
register hccs done
IsFfeAdapt = 0.Use Default HCCS FFE Paras.
nodeId 0, dieId 1, linkId 0, FFE info: fir_pre1 -8, fir_main 55, fir_post1 0
node_id 0, die 2, ind 4, usemode 4 begin serdes-init.
IsFfeAdapt = 0.Use Default HCCS FFE Paras.
nodeId 0, dieId 1, linkId 1, FFE info: fir_pre1 -8, fir_main 55, fir_post1 0
node_id 0, die 2, ind 3, usemode 4 begin serdes-init.
hccs init start...
pa ring link down success
reset pa success
link[4] pcs init success
link[5] pcs init success
release reset pa success
link[4] macro adapt done (lane_mask=0xff) (0ms)
link[5] macro adapt done (lane_mask=0xff) (0ms)
link[4] pcs training success (10ms)
link[5] pcs training success (10ms)
link[4] training success (20ms)
link[5] training success (20ms)
link[4]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link[5]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link training success
pa[0] linkEn = 0x0
pa[0] allNodeLink0 = 0x0
pa[0] allNodeLink1 = 0x0
pa[1] linkEn = 0x3
pa[1] allNodeLink0 = 0x30
pa[1] allNodeLink1 = 0x0
pa init success
COM_PAID_INTLV_REG = 0x2
paid decode init success
pa[0] PA_PM_BASE_INFO = 0x0
pa[0] PA_PM_MAP_LINK_NUM = 0x0
pa[1] PA_PM_BASE_INFO = 0x330021
pa[1] PA_PM_MAP_LINK_NUM = 0x12
hccs performace config success
pa ring link up success
hccs init done
hccs access test start
node[0] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[1] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[1] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
hccs access test success
======hccs status======
  node[0] mask: expected = 0x30, link up = 0x30, width reduction = 0x0, link down = 0x0
  node[1] mask: expected = 0x30, link up = 0x30, width reduction = 0x0, link down = 0x0
==========end==========
report hccs status success
node[0] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
LRDXSD_LOCK_OFFSET = 0x0
LRDXSD_ERRIMSK_OFFSET = 0x0
LRDXSD_DBG_OTIMSK_OFFSET = 0x0
LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
LRDXSD_DBG_EN_OFFSET = 0x1
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
ID[0x1a67c8]!
[ERR]Don't support the flash, CS[0] ID[0x1a67c8]!!
ID[0x0]!
[ERR]Don't support the flash, CS[1] ID[0x0]!!
[ERR]Warnning, Select Default flash 
sfdp detect, try to get dummy data from hboot1 first.
ID[0x1a67c8]!
flash 0 support sfdp.
Interrupt 423 register OK
Interrupt 425 register OK
Interrupt 427 register OK
Interrupt 429 register OK
Interrupt 430 register OK
Interrupt 431 register OK
Interrupt 436 register OK

cpu 0 entering scheduler
[IMU] Watchdog Initialization done!
ScmiTaskEntry start.
Interrupt 456 register OK
Interrupt 469 register OK
Interrupt 482 register OK
Interrupt 495 register OK
starting Fpc Isolation Task end
starting fdm Err Info Task end
starting Roce recovery Task end
starting Ce_Storm Contrl Task end
starting Ras_Data_Update Task end
power register ubios call id
print register ubios call id
Interrupt 459 register OK
Interrupt 472 register OK
Interrupt 485 register OK
Interrupt 498 register OK
[0.00.13.272]Real time now 2026.3.17 08:20:07
NIC CARD[0][0]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[0][1]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[1][0]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[1][1]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
Init heart-beat-task end
Init SeamlessUpdateTask end
Init alarm-report-task end
pool addr          pool size    used size     free size    max free node size   used node num     free node num      UsageWaterLine
---------------    --------     -------       --------     --------------       -------------      ------------      ------------
0x8409090488       0x1e740      0x1b420       0x30b0       0x30b0               0x6c               0x1                0x1b690        
Get Setup Config.
pwr cap[0]: 0, 63
Node 0, Die 0 ImpState is 0 skip exec.
Node 0, Die 2 ImpState is 0 skip exec.
Node 1, Die 0 ImpState is 0 skip exec.
Node 1, Die 2 ImpState is 0 skip exec.
pwr cap[1]: f, 27
pwr cap[2]: 1, 3
[0.00.36.295]DDR Rreserved for IMU: len = 3e00000
[LOG]head = 0x0, tail = 0x1a1f, logSize = 0x1a1f
copy registry.json file success
Set component all release version to sram end.
ipcMsgSend success
[0.00.36.394]starting ras Init
nodeId = 0, dieId = 0, isSasExist = 0.
nodeId = 0, dieId = 2, isSasExist = 0.
nodeId = 1, dieId = 0, isSasExist = 0.
nodeId = 1, dieId = 2, isSasExist = 0.
Mce Table head exist!
RasIntRegister init 452 
RasIntRegister init 453 
RasIntRegister init 465 
RasIntRegister init 466 
RasIntRegister init 86 
RasIntRegister init 87 
RasIntRegister init 478 
RasIntRegister init 479 
RasIntRegister init 491 
RasIntRegister init 492 
RasIntRegister init 130 
RasIntRegister init 131 
RasIntRegister init 98 
RasIntRegister init 142 
[0.00.36.440]starting ras end
[0.00.43.790][ERR]cmd not support! cmd = 0xd
[0.00.58.096]PCIE INIT DONE.
Interrupt 454 register OK
Interrupt 467 register OK
Interrupt 480 register OK
Interrupt 493 register OK
data = 0x0
pmt Init done

Add ep: bdf=300 eid=9 epCnt=1 eid_alloc=a
mctp task ok.
[0.01.28.076]BIOS POST END.
Create SetReportPcieMmioToBmc ok.
Start SetReportPcieMmioToBmc ok.
slotNum = 0x18
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[0] port:4  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[1] port:6  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[2] port:12  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[3] port:14  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[4] port:16  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[5] port:18  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[6] port:20  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[7] port:22  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[8] port:24  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[9] port:26  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[10] port:32  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[11] port:34  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[12] port:0  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[13] port:2  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[14] port:12  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[15] port:14  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[16] port:16  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[17] port:18  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[18] port:24  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[19] port:26  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[20] port:32  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[21] port:34  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[22] port:36  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[23] port:38  pcieSlotCtrl.data (after)0x7c0.

Enter current value process


HSM_LOG:
[00:00:00.000][info] succeed to do thirdparty dfx_pabuk init
[00:00:00.000][info] succeed to do thirdparty crypto_driver init


0>[TracePoint] type[  0] cmd[  1] data[  4]
0>
Board Info:
0>  chip version        : 0
0>  efuse pg cluster TB : 0x0
0>  ak mode             : 0
0>
0>[TracePoint] type[  0] cmd[  1] data[  5]
0>Voltage Type[3]
0>Core Vmin Formula:
0>Totem[1] Core 400MHZ Vol Changed From [790] mv to [810] mv
0>Totem[1] Core 400MHZ -> Vol[790] mv
0>Totem[1] Core 2000MHZ Vol Changed From [763] mv to [810] mv
0>Totem[1] Core 2000MHZ -> Vol[763] mv
0>Totem[1] Core 2300MHZ -> Vol[833] mv
0>Totem[1] Core 2600MHZ -> Vol[911] mv
0>Totem[1] Core 2900MHZ -> Vol[986] mv
0>Totem[1] Core 3100MHZ -> Vol[1032] mv
0>Uncore Vmin Formula:
0>Totem Uncore 400MHZ -> Vol[830] mv
0>Totem[1] Uncore 2000MHZ Vol Changed From [766] mv to [830] mv
0>Totem Uncore 2000MHZ -> Vol[766] mv
0>Totem[2] Uncore 2300MHZ Vol Changed From [816] mv to [830] mv
0>Totem Uncore 2300MHZ -> Vol[816] mv
0>Totem Uncore 2500MHZ -> Vol[848] mv
0>Totem Uncore 2700MHZ -> Vol[891] mv
0>Totem Uncore 2900MHZ -> Vol[933] mv
0>Core VF curve:
0>[ 400]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[ 450]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[ 500]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[ 550]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[ 600]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[ 650]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[ 700]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[ 750]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[ 800]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[ 850]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[ 900]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[ 950]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1000]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1050]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1100]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1150]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1200]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1250]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1300]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1350]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1400]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1450]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1500]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1550]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1600]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1650]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1700]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1750]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1800]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1850]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1900]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1950]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[2000]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[2050]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[2100]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[2150]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[2200]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[2250]MHZ -> Vol TA[ 810]mv TB[ 821]mv
0>[2300]MHZ -> Vol TA[ 810]mv TB[ 833]mv
0>[2350]MHZ -> Vol TA[ 810]mv TB[ 846]mv
0>[2400]MHZ -> Vol TA[ 810]mv TB[ 859]mv
0>[2450]MHZ -> Vol TA[ 810]mv TB[ 872]mv
0>[2500]MHZ -> Vol TA[ 810]mv TB[ 885]mv
0>[2550]MHZ -> Vol TA[ 810]mv TB[ 898]mv
0>[2600]MHZ -> Vol TA[ 810]mv TB[ 911]mv
0>[2650]MHZ -> Vol TA[ 810]mv TB[ 923]mv
0>[2700]MHZ -> Vol TA[ 810]mv TB[ 936]mv
0>[2750]MHZ -> Vol TA[ 810]mv TB[ 948]mv
0>[2800]MHZ -> Vol TA[ 810]mv TB[ 961]mv
0>[2850]MHZ -> Vol TA[ 810]mv TB[ 973]mv
0>[2900]MHZ -> Vol TA[ 810]mv TB[ 986]mv
0>[2950]MHZ -> Vol TA[ 810]mv TB[ 997]mv
0>[3000]MHZ -> Vol TA[ 810]mv TB[1009]mv
0>[3050]MHZ -> Vol TA[ 810]mv TB[1020]mv
0>[3100]MHZ -> Vol TA[ 810]mv TB[1032]mv
0>Uncore VF curve:
0>Uncore [   0]MHZ -> Vol [ 830]mv
0>Uncore [ 100]MHZ -> Vol [ 830]mv
0>Uncore [ 200]MHZ -> Vol [ 830]mv
0>Uncore [ 300]MHZ -> Vol [ 830]mv
0>Uncore [ 400]MHZ -> Vol [ 830]mv
0>Uncore [ 500]MHZ -> Vol [ 830]mv
0>Uncore [ 600]MHZ -> Vol [ 830]mv
0>Uncore [ 700]MHZ -> Vol [ 830]mv
0>Uncore [ 800]MHZ -> Vol [ 830]mv
0>Uncore [ 900]MHZ -> Vol [ 830]mv
0>Uncore [1000]MHZ -> Vol [ 830]mv
0>Uncore [1100]MHZ -> Vol [ 830]mv
0>Uncore [1200]MHZ -> Vol [ 830]mv
0>Uncore [1300]MHZ -> Vol [ 830]mv
0>Uncore [1400]MHZ -> Vol [ 830]mv
0>Uncore [1500]MHZ -> Vol [ 830]mv
0>Uncore [1600]MHZ -> Vol [ 830]mv
0>Uncore [1700]MHZ -> Vol [ 830]mv
0>Uncore [1800]MHZ -> Vol [ 830]mv
0>Uncore [1900]MHZ -> Vol [ 830]mv
0>Uncore [2000]MHZ -> Vol [ 830]mv
0>Uncore [2100]MHZ -> Vol [ 830]mv
0>Uncore [2200]MHZ -> Vol [ 830]mv
0>Uncore [2300]MHZ -> Vol [ 830]mv
0>Uncore [2400]MHZ -> Vol [ 832]mv
0>Uncore [2500]MHZ -> Vol [ 848]mv
0>Uncore [2600]MHZ -> Vol [ 869]mv
0>Uncore [2700]MHZ -> Vol [ 891]mv
0>Uncore [2800]MHZ -> Vol [ 912]mv
0>Uncore [2900]MHZ -> Vol [ 933]mv
0>Uncore [3000]MHZ -> Vol [1100]mv
0>[TracePoint] type[  0] cmd[  1] data[  6]
0>[TracePoint] type[  0] cmd[  1] data[  7]
0>
********Hello Huawei LiteOS********

KpxxxxIPU Firmware Version : VX.X.X
LiteOS Kernel Version : 5.7.0
0>Run on ChipVersion[0] Node[0] Die[0]
0>build time : Oct 27 2025 20:30:00

0>**********************************
0>
main core booting up...
0>start set affinity
0>
mpidr = 0x81000000
0>sram ecc state: 0x0, sram ecc cnt: 0x0
0>[TracePoint] type[  0] cmd[  2] data[  1]
0>[TracePoint] type[  0] cmd[  2] data[  2]
0>LRDXSD_LOCK_OFFSET = 0x0
0>LRDXSD_ERRIMSK_OFFSET = 0x0
0>LRDXSD_DBG_OTIMSK_OFFSET = 0x0
0>LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
0>LRDXSD_DBG_EN_OFFSET = 0x1
0>======tsensor params======
0>  is_trimmed       : 1
0>  underclocking_en : 1
0>===========end============
0>soc tsensor init done
0>========vrd info from cpld========
0>vrd_id | u64                | pmbus_en | avsbus_en | loop | pmbus_id | pmbus_addr | avs_sw | pmbus_sw | addr_9545 | domain_type | die_mask | reserved
0>  00   | 0x0003000300002b15 | 0x1      | 0x0       | 0x1  | 0x1      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x3         | 0x0300   | 0x0
0>  01   | 0x000001050000201b | 0x1      | 0x1       | 0x2  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0001   | 0x0
0>  02   | 0x0002000100002017 | 0x1      | 0x1       | 0x1  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0200   | 0x0
0>  03   | 0x0003000200002027 | 0x1      | 0x1       | 0x1  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x2         | 0x0300   | 0x0
0>  04   | 0x000002050000202b | 0x1      | 0x1       | 0x2  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0002   | 0x0
0>  05   | 0x0003000400002b19 | 0x1      | 0x0       | 0x2  | 0x1      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x4         | 0x0300   | 0x0
0>  06   | 0x0000000000000000 | 0x0      | 0x0       | 0x0  | 0x0      | 0x00       | 0x0    | 0x0      | 0x0       | 0x0         | 0x0000   | 0x0
0>================end===============
0>[ERR]0>vrd[6] info invalid, vrd_info = 0x0
0>default power domain data used
0>=============vrd info=============
0>power domain num: 6
0>power domain[00] id:2 | CORE_DVFS_TB       | PMBus NA | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
0>power domain[01] id:4 | IO_DVDD_NA         | PMBus NA | cap:0x3 | rail:1 | addr:0x20 | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
0>power domain[02] id:3 | UNCORE_DVFS        | PMBus NB | cap:0x3 | rail:0 | addr:0x20 | def_volt: 848 mV | min_volt: 750 mV | max_volt:1100 mV
0>power domain[03] id:5 | IO_DVDD_NB         | PMBus NB | cap:0x3 | rail:1 | addr:0x20 | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
0>power domain[04] id:1 | DDR_VDD            | PMBus NA | cap:0x1 | rail:0 | addr:0x2b | def_volt: 765 mV | min_volt: 650 mV | max_volt: 850 mV
0>power domain[05] id:6 | DDR_VDDQ           | PMBus NA | cap:0x1 | rail:1 | addr:0x2b | def_volt:1100 mV | min_volt:1000 mV | max_volt:1200 mV
0>================end===============
0>pmbus[0] init done
0>pmbus[1] init done
0>power domain[2] CORE_DVFS_TB       | NA PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
0>power domain[4] IO_DVDD_NA         | NA PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 800 mV | pmu:MP2882
0>power domain[3] UNCORE_DVFS        | NB PMBus/AVSBus | rail:0 | addr:0x20 | def_volt: 848 mV | pmu:MP2882
0>power domain[5] IO_DVDD_NB         | NB PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 800 mV | pmu:MP2882
0>power domain[1] DDR_VDD            | NA PMBus        | rail:0 | addr:0x2b | def_volt: 765 mV | pmu:MP2882
0>power domain[6] DDR_VDDQ           | NA PMBus        | rail:1 | addr:0x2b | def_volt:1100 mV | pmu:MP2882
0>power domain[2] CORE_DVFS_TB       is transferred to AVSBus mode
0>power domain[4] IO_DVDD_NA         is transferred to AVSBus mode
0>power domain[3] UNCORE_DVFS        is transferred to AVSBus mode
0>power domain[5] IO_DVDD_NB         is transferred to AVSBus mode
0>avsbus resync success
0>avsbus[0] init done
0>avsbus resync success
0>avsbus[1] init done
0>============volt boot============
0>power domain[2] volt = 1105 mV
0>power domain[4] volt =  808 mV
0>power domain[3] volt = 1005 mV
0>power domain[5] volt =  806 mV
0>power domain[1] volt =  767 mV
0>power domain[6] volt = 1105 mV
0>===============end===============
0>power domain[0] not exist
0>--w&h rd rail:0, 1105, CORE_DVFS_TB
0>--w&h rd rail:1, 800, CORE_DVFS_TB
0>power domain[2] set volt --> 1105 mV success
0>--w&h rd rail:0, 1005, UNCORE_DVFS
0>--w&h rd rail:1, 800, UNCORE_DVFS
0>power domain[3] set volt -->  851 mV success
0>============volt post============
0>power domain[2] volt = 1105 mV
0>power domain[4] volt =  804 mV
0>power domain[3] volt =  851 mV
0>power domain[5] volt =  804 mV
0>power domain[1] volt =  769 mV
0>power domain[6] volt = 1103 mV
0>===============end===============
0>Hboot1 Info RAW Dump: [0x91][0x00][0x00][0x14][0x01][0x00][0x01]
0>PowerSensorSupport[1], Cali[5120], Loss[7200]
0>Power Sensor Calibration Value[5120]!
0>the power sensor : manu id = 2peak, die id = TPA626
0>power sensor[0] init success
0>Totem[1] Core Boot Vol [1107]mv
0>Totem[1] Core Current Vol [1100]mv
0>NA 1620V1b0
0>NB 1620V1b0
0>GetCoreBaseFreq [2600000KHZ]
0>GetCoreTurboFreq [2600000KHZ]
0>GetCustomClusterNum [10]
0>Ipu ACG Training Done!
0>AP Last Time:[0.00.01.394]
0>wait UEFI pll init...
0>done
0>acg trim start
0>core trim freq:2000, avs:0 volt:810mv
0>core trim freq:2050, avs:1 volt:810mv
0>core trim freq:2100, avs:2 volt:810mv
0>core trim freq:2150, avs:3 volt:810mv
0>core trim freq:2200, avs:4 volt:810mv
0>core trim freq:2250, avs:5 volt:821mv
0>core trim freq:2300, avs:6 volt:833mv
0>core trim freq:2350, avs:7 volt:846mv
0>core trim freq:2400, avs:8 volt:859mv
0>core trim freq:2450, avs:9 volt:872mv
0>core trim freq:2500, avs:10 volt:885mv
0>core trim freq:2550, avs:11 volt:898mv
0>core trim freq:2600, avs:12 volt:911mv
0>core trim freq:2650, avs:13 volt:923mv
0>core trim freq:2700, avs:14 volt:936mv
0>core trim freq:2750, avs:15 volt:948mv
0>core trim freq:2800, avs:16 volt:961mv
0>core trim freq:2850, avs:17 volt:973mv
0>core trim freq:2900, avs:18 volt:986mv
0>core trim freq:2950, avs:19 volt:997mv
0>core trim freq:3000, avs:20 volt:1009mv
0>core trim freq:3050, avs:21 volt:1020mv
0>core trim freq:3100, avs:22 volt:1032mv
0>acg trim end
0>LDO disabled
0>[TracePoint] type[  0] cmd[  2] data[  3]
0>Interrupt 423 register OK
0>Interrupt 430 register OK
0>[TracePoint] type[  0] cmd[  2] data[  4]
0>
0>cpu 0 entering scheduler
0>[TracePoint] type[  0] cmd[  3] data[  1]
0>add your ipu app init here!
0>IpuInterfaceTaskStart Entry ...
0>ipu interface task wait parameters from uefi...
0>thermal soc task enabled
0>AP Last Time:[0.00.14.696]
0>ThermalDimmStart Entry ...
0>wait ddr init done...
0>power task start...
0>[TracePoint] type[  0] cmd[  3] data[  2]
0>ufs task wait parameters from uefi...
0>AmuTaskStart Entry ... 
0>amu task wait parameters from uefi...
0>ThermalSiwStart Entry ...
0>ThermalSiwTask idle...
0>DemtTaskStart Entry ...
0>[TracePoint] type[  0] cmd[  3] data[  3]
0>demt task wait parameters from uefi...
0>HiBoostTaskStart Entry ...
0>HiBoost task enabled
0>Waiting for UEFI parameters...
0>[TracePoint] type[  0] cmd[  3] data[  4]
0>AgeTaskStart Entry ...
0>[TracePoint] type[  0] cmd[  3] data[  5]
0>age task wait parameters from uefi...
0>uefi parameters ready!
0>UFSProfile[0]
0>PowerPolicy[2] BenchMarkSelection[0]
0>ipu interface task wait ddr init done from uefi...
0>ufs task parameters from uefi ready
0>uncore domain[1] freq:2500
0>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
0>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
0>======sioe status======
0>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
0>thermal soc task restore underclocking_en=1
0>ppu alert temp div init done
0>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
0>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
0>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
0>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
0>==========end==========
0>sioe init done
0>ufs task enabled
0>--> UFS profile[0]
0>UEFI parameters ready
0>UncoreMaxFreq Set to [2500 MHZ]
0>get TDP from efuse success, value = 185000mw
0>target power set to [185000]mw, brd:[185000]
0>demt task parameters from uefi ready
0>age task parameters from uefi ready
0>age task enabled
0>uefi ddr init finish!
0>ipu interface task wait uefi end done from uefi...
0>ddr init done, start thermal dimm task
0>======dimm status======
0>  chl[0] dimm0 0, dimm1 0
0>  chl[1] dimm0 0, dimm1 0
0>  chl[2] dimm0 2, dimm1 0
0>  chl[3] dimm0 0, dimm1 0
0>  chl[4] dimm0 0, dimm1 0
0>  chl[5] dimm0 0, dimm1 0
0>  chl[6] dimm0 0, dimm1 0
0>  chl[7] dimm0 0, dimm1 0
0>==========end==========
0>chl[2] registered, dimm mask = 0x1
0>=====dimm temp params=====
0>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
0>  is_thermal_thro_en  : 1
0>  is_aref_rate_auto   : 1
0>===========end============
0>chl[2] max_temp 39'C, aref_rate 0x5 --> 0x4
0>uefi end finish!
0>ipu interface task exit!
0>amu task parameters from uefi ready
0>amu task activated
0>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
1>[TracePoint] type[  0] cmd[  1] data[  4]
1>
Board Info:
1>  chip version        : 0
1>  efuse pg cluster TB : 0x0
1>  ak mode             : 0
1>
1>[TracePoint] type[  0] cmd[  1] data[  5]
1>Voltage Type[3]
1>Core Vmin Formula:
1>Totem[1] Core 400MHZ Vol Changed From [790] mv to [810] mv
1>Totem[1] Core 400MHZ -> Vol[790] mv
1>Totem[1] Core 2000MHZ Vol Changed From [763] mv to [810] mv
1>Totem[1] Core 2000MHZ -> Vol[763] mv
1>Totem[1] Core 2300MHZ -> Vol[832] mv
1>Totem[1] Core 2600MHZ -> Vol[910] mv
1>Totem[1] Core 2900MHZ -> Vol[985] mv
1>Totem[1] Core 3100MHZ -> Vol[1031] mv
1>Uncore Vmin Formula:
1>Totem Uncore 400MHZ -> Vol[830] mv
1>Totem[1] Uncore 2000MHZ Vol Changed From [764] mv to [830] mv
1>Totem Uncore 2000MHZ -> Vol[764] mv
1>Totem[2] Uncore 2300MHZ Vol Changed From [814] mv to [830] mv
1>Totem Uncore 2300MHZ -> Vol[814] mv
1>Totem Uncore 2500MHZ -> Vol[846] mv
1>Totem Uncore 2700MHZ -> Vol[889] mv
1>Totem Uncore 2900MHZ -> Vol[930] mv
1>Core VF curve:
1>[ 400]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[ 450]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[ 500]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[ 550]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[ 600]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[ 650]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[ 700]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[ 750]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[ 800]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[ 850]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[ 900]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[ 950]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1000]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1050]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1100]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1150]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1200]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1250]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1300]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1350]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1400]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1450]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1500]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1550]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1600]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1650]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1700]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1750]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1800]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1850]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1900]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1950]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[2000]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[2050]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[2100]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[2150]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[2200]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[2250]MHZ -> Vol TA[ 810]mv TB[ 820]mv
1>[2300]MHZ -> Vol TA[ 810]mv TB[ 832]mv
1>[2350]MHZ -> Vol TA[ 810]mv TB[ 845]mv
1>[2400]MHZ -> Vol TA[ 810]mv TB[ 858]mv
1>[2450]MHZ -> Vol TA[ 810]mv TB[ 871]mv
1>[2500]MHZ -> Vol TA[ 810]mv TB[ 884]mv
1>[2550]MHZ -> Vol TA[ 810]mv TB[ 897]mv
1>[2600]MHZ -> Vol TA[ 810]mv TB[ 910]mv
1>[2650]MHZ -> Vol TA[ 810]mv TB[ 922]mv
1>[2700]MHZ -> Vol TA[ 810]mv TB[ 935]mv
1>[2750]MHZ -> Vol TA[ 810]mv TB[ 947]mv
1>[2800]MHZ -> Vol TA[ 810]mv TB[ 960]mv
1>[2850]MHZ -> Vol TA[ 810]mv TB[ 972]mv
1>[2900]MHZ -> Vol TA[ 810]mv TB[ 985]mv
1>[2950]MHZ -> Vol TA[ 810]mv TB[ 996]mv
1>[3000]MHZ -> Vol TA[ 810]mv TB[1008]mv
1>[3050]MHZ -> Vol TA[ 810]mv TB[1019]mv
1>[3100]MHZ -> Vol TA[ 810]mv TB[1031]mv
1>Uncore VF curve:
1>Uncore [   0]MHZ -> Vol [ 830]mv
1>Uncore [ 100]MHZ -> Vol [ 830]mv
1>Uncore [ 200]MHZ -> Vol [ 830]mv
1>Uncore [ 300]MHZ -> Vol [ 830]mv
1>Uncore [ 400]MHZ -> Vol [ 830]mv
1>Uncore [ 500]MHZ -> Vol [ 830]mv
1>Uncore [ 600]MHZ -> Vol [ 830]mv
1>Uncore [ 700]MHZ -> Vol [ 830]mv
1>Uncore [ 800]MHZ -> Vol [ 830]mv
1>Uncore [ 900]MHZ -> Vol [ 830]mv
1>Uncore [1000]MHZ -> Vol [ 830]mv
1>Uncore [1100]MHZ -> Vol [ 830]mv
1>Uncore [1200]MHZ -> Vol [ 830]mv
1>Uncore [1300]MHZ -> Vol [ 830]mv
1>Uncore [1400]MHZ -> Vol [ 830]mv
1>Uncore [1500]MHZ -> Vol [ 830]mv
1>Uncore [1600]MHZ -> Vol [ 830]mv
1>Uncore [1700]MHZ -> Vol [ 830]mv
1>Uncore [1800]MHZ -> Vol [ 830]mv
1>Uncore [1900]MHZ -> Vol [ 830]mv
1>Uncore [2000]MHZ -> Vol [ 830]mv
1>Uncore [2100]MHZ -> Vol [ 830]mv
1>Uncore [2200]MHZ -> Vol [ 830]mv
1>Uncore [2300]MHZ -> Vol [ 830]mv
1>Uncore [2400]MHZ -> Vol [ 830]mv
1>Uncore [2500]MHZ -> Vol [ 846]mv
1>Uncore [2600]MHZ -> Vol [ 867]mv
1>Uncore [2700]MHZ -> Vol [ 889]mv
1>Uncore [2800]MHZ -> Vol [ 909]mv
1>Uncore [2900]MHZ -> Vol [ 930]mv
1>Uncore [3000]MHZ -> Vol [1100]mv
1>[TracePoint] type[  0] cmd[  1] data[  6]
1>[TracePoint] type[  0] cmd[  1] data[  7]
1>
********Hello Huawei LiteOS********

KpxxxxIPU Firmware Version : VX.X.X
LiteOS Kernel Version : 5.7.0
1>Run on ChipVersion[0] Node[1] Die[0]
1>build time : Oct 27 2025 20:30:00

1>**********************************
1>
main core booting up...
1>start set affinity
1>
mpidr = 0x81040000
1>sram ecc state: 0x0, sram ecc cnt: 0x0
1>[TracePoint] type[  0] cmd[  2] data[  1]
1>[TracePoint] type[  0] cmd[  2] data[  2]
1>LRDXSD_LOCK_OFFSET = 0x0
1>LRDXSD_ERRIMSK_OFFSET = 0x0
1>LRDXSD_DBG_OTIMSK_OFFSET = 0x0
1>LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
1>LRDXSD_DBG_EN_OFFSET = 0x1
1>======tsensor params======
1>  is_trimmed       : 1
1>  underclocking_en : 1
1>===========end============
1>soc tsensor init done
1>========vrd info from cpld========
1>vrd_id | u64                | pmbus_en | avsbus_en | loop | pmbus_id | pmbus_addr | avs_sw | pmbus_sw | addr_9545 | domain_type | die_mask | reserved
1>  00   | 0x0003000300002b15 | 0x1      | 0x0       | 0x1  | 0x1      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x3         | 0x0300   | 0x0
1>  01   | 0x000001050000201b | 0x1      | 0x1       | 0x2  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0001   | 0x0
1>  02   | 0x0002000100002017 | 0x1      | 0x1       | 0x1  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0200   | 0x0
1>  03   | 0x0003000200002027 | 0x1      | 0x1       | 0x1  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x2         | 0x0300   | 0x0
1>  04   | 0x000002050000202b | 0x1      | 0x1       | 0x2  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0002   | 0x0
1>  05   | 0x0003000400002b19 | 0x1      | 0x0       | 0x2  | 0x1      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x4         | 0x0300   | 0x0
1>  06   | 0x0000000000000000 | 0x0      | 0x0       | 0x0  | 0x0      | 0x00       | 0x0    | 0x0      | 0x0       | 0x0         | 0x0000   | 0x0
1>================end===============
1>[ERR]1>vrd[6] info invalid, vrd_info = 0x0
1>default power domain data used
1>=============vrd info=============
1>power domain num: 6
1>power domain[00] id:2 | CORE_DVFS_TB       | PMBus NA | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
1>power domain[01] id:4 | IO_DVDD_NA         | PMBus NA | cap:0x3 | rail:1 | addr:0x20 | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
1>power domain[02] id:3 | UNCORE_DVFS        | PMBus NB | cap:0x3 | rail:0 | addr:0x20 | def_volt: 846 mV | min_volt: 750 mV | max_volt:1100 mV
1>power domain[03] id:5 | IO_DVDD_NB         | PMBus NB | cap:0x3 | rail:1 | addr:0x20 | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
1>power domain[04] id:1 | DDR_VDD            | PMBus NA | cap:0x1 | rail:0 | addr:0x2b | def_volt: 765 mV | min_volt: 650 mV | max_volt: 850 mV
1>power domain[05] id:6 | DDR_VDDQ           | PMBus NA | cap:0x1 | rail:1 | addr:0x2b | def_volt:1100 mV | min_volt:1000 mV | max_volt:1200 mV
1>================end===============
1>pmbus[0] init done
1>pmbus[1] init done
1>power domain[2] CORE_DVFS_TB       | NA PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
1>power domain[4] IO_DVDD_NA         | NA PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 800 mV | pmu:MP2882
1>power domain[3] UNCORE_DVFS        | NB PMBus/AVSBus | rail:0 | addr:0x20 | def_volt: 846 mV | pmu:MP2882
1>power domain[5] IO_DVDD_NB         | NB PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 800 mV | pmu:MP2882
1>power domain[1] DDR_VDD            | NA PMBus        | rail:0 | addr:0x2b | def_volt: 765 mV | pmu:MP2882
1>power domain[6] DDR_VDDQ           | NA PMBus        | rail:1 | addr:0x2b | def_volt:1100 mV | pmu:MP2882
1>power domain[2] CORE_DVFS_TB       is transferred to AVSBus mode
1>power domain[4] IO_DVDD_NA         is transferred to AVSBus mode
1>power domain[3] UNCORE_DVFS        is transferred to AVSBus mode
1>power domain[5] IO_DVDD_NB         is transferred to AVSBus mode
1>avsbus resync success
1>avsbus[0] init done
1>avsbus resync success
1>avsbus[1] init done
1>============volt boot============
1>power domain[2] volt = 1101 mV
1>power domain[4] volt =  806 mV
1>power domain[3] volt = 1007 mV
1>power domain[5] volt =  802 mV
1>power domain[1] volt =  769 mV
1>power domain[6] volt = 1103 mV
1>===============end===============
1>power domain[0] not exist
1>--w&h rd rail:0, 1101, CORE_DVFS_TB
1>--w&h rd rail:1, 800, CORE_DVFS_TB
1>power domain[2] set volt --> 1101 mV success
1>--w&h rd rail:0, 1007, UNCORE_DVFS
1>--w&h rd rail:1, 800, UNCORE_DVFS
1>power domain[3] set volt -->  851 mV success
1>============volt post============
1>power domain[2] volt = 1101 mV
1>power domain[4] volt =  802 mV
1>power domain[3] volt =  851 mV
1>power domain[5] volt =  800 mV
1>power domain[1] volt =  769 mV
1>power domain[6] volt = 1103 mV
1>===============end===============
1>Hboot1 Info RAW Dump: [0x01][0x00][0x00][0x14][0x01][0x00][0x01]
1>PowerSensorSupport[1], Cali[5120], Loss[0]
1>Power Sensor Calibration Value[5120]!
1>the power sensor : manu id = 2peak, die id = TPA626
1>power sensor[0] init success
1>Totem[1] Core Boot Vol [1101]mv
1>Totem[1] Core Current Vol [1100]mv
1>NA 1620V1b0
1>NB 1620V1b0
1>GetCoreBaseFreq [2600000KHZ]
1>GetCoreTurboFreq [2600000KHZ]
1>GetCustomClusterNum [10]
1>Ipu ACG Training Done!
1>AP Last Time:[0.00.01.400]
1>wait UEFI pll init...
1>done
1>acg trim start
1>core trim freq:2000, avs:0 volt:810mv
1>core trim freq:2050, avs:1 volt:810mv
1>core trim freq:2100, avs:2 volt:810mv
1>core trim freq:2150, avs:3 volt:810mv
1>core trim freq:2200, avs:4 volt:810mv
1>core trim freq:2250, avs:5 volt:820mv
1>core trim freq:2300, avs:6 volt:832mv
1>core trim freq:2350, avs:7 volt:845mv
1>core trim freq:2400, avs:8 volt:858mv
1>core trim freq:2450, avs:9 volt:871mv
1>core trim freq:2500, avs:10 volt:884mv
1>core trim freq:2550, avs:11 volt:897mv
1>core trim freq:2600, avs:12 volt:910mv
1>core trim freq:2650, avs:13 volt:922mv
1>core trim freq:2700, avs:14 volt:935mv
1>core trim freq:2750, avs:15 volt:947mv
1>core trim freq:2800, avs:16 volt:960mv
1>core trim freq:2850, avs:17 volt:972mv
1>core trim freq:2900, avs:18 volt:985mv
1>core trim freq:2950, avs:19 volt:996mv
1>core trim freq:3000, avs:20 volt:1008mv
1>core trim freq:3050, avs:21 volt:1019mv
1>core trim freq:3100, avs:22 volt:1031mv
1>acg trim end
1>LDO disabled
1>[TracePoint] type[  0] cmd[  2] data[  3]
1>Interrupt 423 register OK
1>Interrupt 430 register OK
1>[TracePoint] type[  0] cmd[  2] data[  4]
1>
1>cpu 0 entering scheduler
1>[TracePoint] type[  0] cmd[  3] data[  1]
1>add your ipu app init here!
1>IpuInterfaceTaskStart Entry ...
1>ipu interface task wait parameters from uefi...
1>thermal soc task enabled
1>AP Last Time:[0.00.14.849]
1>ThermalDimmStart Entry ...
1>wait ddr init done...
1>power task start...
1>[TracePoint] type[  0] cmd[  3] data[  2]
1>ufs task wait parameters from uefi...
1>AmuTaskStart Entry ... 
1>amu task wait parameters from uefi...
1>ThermalSiwStart Entry ...
1>ThermalSiwTask idle...
1>DemtTaskStart Entry ...
1>[TracePoint] type[  0] cmd[  3] data[  3]
1>demt task wait parameters from uefi...
1>HiBoostTaskStart Entry ...
1>HiBoost task enabled
1>Waiting for UEFI parameters...
1>[TracePoint] type[  0] cmd[  3] data[  4]
1>AgeTaskStart Entry ...
1>[TracePoint] type[  0] cmd[  3] data[  5]
1>age task wait parameters from uefi...
1>uefi parameters ready!
1>UFSProfile[0]
1>PowerPolicy[2] BenchMarkSelection[0]
1>ipu interface task wait ddr init done from uefi...
1>ufs task parameters from uefi ready
1>uncore domain[1] freq:2500
1>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
1>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
1>======sioe status======
1>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
1>thermal soc task restore underclocking_en=1
1>ppu alert temp div init done
1>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
1>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
1>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
1>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
1>==========end==========
1>sioe init done
1>ufs task enabled
1>--> UFS profile[0]
1>UEFI parameters ready
1>UncoreMaxFreq Set to [2500 MHZ]
1>get TDP from efuse success, value = 185000mw
1>target power set to [185000]mw, brd:[185000]
1>demt task parameters from uefi ready
1>age task parameters from uefi ready
1>age task enabled
1>uefi ddr init finish!
1>ipu interface task wait uefi end done from uefi...
1>ddr init done, start thermal dimm task
1>======dimm status======
1>  chl[0] dimm0 0, dimm1 0
1>  chl[1] dimm0 0, dimm1 0
1>  chl[2] dimm0 2, dimm1 0
1>  chl[3] dimm0 0, dimm1 0
1>  chl[4] dimm0 0, dimm1 0
1>  chl[5] dimm0 0, dimm1 0
1>  chl[6] dimm0 0, dimm1 0
1>  chl[7] dimm0 0, dimm1 0
1>==========end==========
1>chl[2] registered, dimm mask = 0x1
1>=====dimm temp params=====
1>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
1>  is_thermal_thro_en  : 1
1>  is_aref_rate_auto   : 1
1>===========end============
1>chl[2] max_temp 39'C, aref_rate 0x5 --> 0x4
1>uefi end finish!
1>ipu interface task exit!
1>amu task parameters from uefi ready
1>amu task activated
1>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!


HSM_LOG:
[00:00:00.010][info] os_mem_system_init default pool done
[00:00:00.016][info] succeed to do thirdparty otpc_pabuk init
[00:00



HSM_LOG:
:00.017][info] succeed to do thirdparty boot_profile_driver init
[00:00:00.017][info] succeed to do thirdparty measure_value_ma



HSM_LOG:
nage_driver init
[00:00:00.018][info] succeed to do thirdparty period_driver init
[00:00:00.018][info]  start loading internal



HSM_LOG:
 task ...
[00:00:00.018][info]  task name is ccm_task
[00:00:00.019][info]  hm_dynamic_loadelf successfully!
[00:00:00.019][i



HSM_LOG:
nfo] internal task[1] task_name=ccm_task load successfully
[00:00:00.020][info]  task name is upgrade_task
[00:00:00.020][info



HSM_LOG:
]  hm_dynamic_loadelf successfully!
[00:00:00.021][info] internal task[2] task_name=upgrade_task load successfully
[00:00:00.0



HSM_LOG:
22][info]  task name is hes_task
[00:00:00.022][info]  hm_dynamic_loadelf successfully!
[00:00:00.023][info] internal task[3] 



HSM_LOG:
task_name=hes_task load successfully
[00:00:00.024][info] created task ccm_task success!
[00:00:00.025][info] created task upg



HSM_LOG:
rade_task success!
[00:00:00.026][info] created task hes_task success!
[00:00:00.026][info] Init start.
[1970-01-01 00:00:00.



HSM_LOG:
027][HSM][INFO][54] Platform init 0x20250523 0x4e.

[1970-01-01 00:00:00.027][HSM][INFO][197] ccm start.

[1970-01-01 00:00:00



HSM_LOG:
.028][HSM][INFO][86] upgrade task init success.

[1970-01-01 00:00:00.028][HSM][INFO][95] upgrade recv cmd, 0x181.

[1970-01-0



HSM_LOG:
1 00:00:00.029][HSM][INFO][103] upgrade res, 0x3a5aa5a3.

[1970-01-01 00:00:00.030][HSM][INFO][75] hes tee_task_entry.

[1970-



HSM_LOG:
01-01 00:00:00.550][HSM][INFO][44] hes init success.

[00:00:00.551][info] Init over.


[0.06.28.076]IpmiCmdReportPcieMMIO start
[0.06.38.806]IpmiCmdReportPcieMMIO end
pool addr          pool size    used size     free size    max free node size   used node num     free node num      UsageWaterLine
---------------    --------     -------       --------     --------------       -------------      ------------      ------------
0x8409090488       0x1e740      0x19dd0       0x4700       0x30b0               0x90               0x3                0x1b690        

********Hello Huawei LiteOS********

KpxxxxIMU Firmware Version : VX.X.X
LiteOS Kernel Version : 5.7.0
Run on ChipVersion[0] Node[0] Die[2]
build time : Oct 27 2025 20:30:00

**********************************

main core booting up...
start set affinity

mpidr = 0x81020000
sram ecc state: 0x0, sram ecc cnt: 0x0
[0.00.00.032]node 0 begins init all serdes.
BoardInfo->NodeNum 2.
BoardInfo->NodeId 0.
BoardInfo->InfoVersion 5.
BoardInfo->NASerdesSceneMode 3.
BoardInfo->NBSerdesSceneMode 3.
BoardInfo->HccsTopologyType 0.
BoardInfo->BoardId 0.
ChipVersionIsPro: 0.
BoardInfo Node 0, SerdesUseMode: 1 2 1 1 1 1 1  1 1 1 4 4 1 12 
BoardInfo Node 1, SerdesUseMode: 1 1 1 1 1 1 1  12 13 1 4 4 1 1 
BoardInfo Node 0, SerdesRxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 1, SerdesRxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 0, SerdesTxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 1, SerdesTxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
serdessdk version: 2.0_5.0_20241203_imu
node_id 0, die 0, ind 0, usemode 1 begin serdes-init.
node_id 0, die 0, ind 1, usemode 2 begin serdes-init.
node_id 0, die 2, ind 0, usemode 1 begin serdes-init.
node_id 0, die 2, ind 1, usemode 1 begin serdes-init.
node_id 0, die 2, ind 6, usemode 12 begin serdes-init.
chip_id 0, die 2, ind 6, usemode 12 don't support, power down macro!
NodeId 0, DieId 2, Macro 6, power-down DS succeed.
NodeId 0, DieId 2, Macro 6, power-down DS succeed.
NodeId 0, DieId 2, Macro 6, power-down DS succeed.
NodeId 0, DieId 2, Macro 6, power-down DS succeed.
NodeId 0, DieId 2, Macro 6, power-down DS succeed.
NodeId 0, DieId 2, Macro 6, power-down DS succeed.
NodeId 0, DieId 2, Macro 6, power-down DS succeed.
NodeId 0, DieId 2, Macro 6, power-down DS succeed.
chip serdes init status:0x0.
[0.00.00.433]node 0 ends init all serdes.
link[4] freq_type:1 | peer_chip_type:1 | peer_node_id:1 | peer_link_id:5
link[5] freq_type:1 | peer_chip_type:1 | peer_node_id:1 | peer_link_id:4
register hccs done
IsFfeAdapt = 0.Use Default HCCS FFE Paras.
nodeId 0, dieId 1, linkId 0, FFE info: fir_pre1 -8, fir_main 55, fir_post1 0
node_id 0, die 2, ind 4, usemode 4 begin serdes-init.
IsFfeAdapt = 0.Use Default HCCS FFE Paras.
nodeId 0, dieId 1, linkId 1, FFE info: fir_pre1 -8, fir_main 55, fir_post1 0
node_id 0, die 2, ind 3, usemode 4 begin serdes-init.
hccs init start...
pa ring link down success
reset pa success
link[4] pcs init success
link[5] pcs init success
release reset pa success
link[4] macro adapt done (lane_mask=0xff) (0ms)
link[5] macro adapt done (lane_mask=0xff) (0ms)
link[4] pcs training success (10ms)
link[5] pcs training success (10ms)
link[4] training success (20ms)
link[5] training success (20ms)
link[4]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link[5]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link training success
pa[0] linkEn = 0x0
pa[0] allNodeLink0 = 0x0
pa[0] allNodeLink1 = 0x0
pa[1] linkEn = 0x3
pa[1] allNodeLink0 = 0x30
pa[1] allNodeLink1 = 0x0
pa init success
COM_PAID_INTLV_REG = 0x2
paid decode init success
pa[0] PA_PM_BASE_INFO = 0x0
pa[0] PA_PM_MAP_LINK_NUM = 0x0
pa[1] PA_PM_BASE_INFO = 0x330021
pa[1] PA_PM_MAP_LINK_NUM = 0x12
hccs performace config success
pa ring link up success
hccs init done
hccs access test start
node[0] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[1] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[1] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
hccs access test success
======hccs status======
  node[0] mask: expected = 0x30, link up = 0x30, width reduction = 0x0, link down = 0x0
  node[1] mask: expected = 0x30, link up = 0x30, width reduction = 0x0, link down = 0x0
==========end==========
report hccs status success
node[0] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
LRDXSD_LOCK_OFFSET = 0x0
LRDXSD_ERRIMSK_OFFSET = 0x0
LRDXSD_DBG_OTIMSK_OFFSET = 0x0
LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
LRDXSD_DBG_EN_OFFSET = 0x1
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
ID[0x1a67c8]!
[ERR]Don't support the flash, CS[0] ID[0x1a67c8]!!
ID[0x0]!
[ERR]Don't support the flash, CS[1] ID[0x0]!!
[ERR]Warnning, Select Default flash 
sfdp detect, try to get dummy data from hboot1 first.
ID[0x1a67c8]!
flash 0 support sfdp.
Interrupt 423 register OK
Interrupt 425 register OK
Interrupt 427 register OK
Interrupt 429 register OK
Interrupt 430 register OK
Interrupt 431 register OK
Interrupt 436 register OK

cpu 0 entering scheduler
[IMU] Watchdog Initialization done!
ScmiTaskEntry start.
Interrupt 456 register OK
Interrupt 469 register OK
Interrupt 482 register OK
Interrupt 495 register OK
starting Fpc Isolation Task end
starting fdm Err Info Task end
starting Roce recovery Task end
starting Ce_Storm Contrl Task end
starting Ras_Data_Update Task end
power register ubios call id
print register ubios call id
Interrupt 459 register OK
Interrupt 472 register OK
Interrupt 485 register OK
Interrupt 498 register OK
[0.00.13.276]Real time now 2026.3.18 06:33:20
NIC CARD[0][0]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[0][1]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[1][0]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[1][1]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
Init heart-beat-task end
Init SeamlessUpdateTask end
Init alarm-report-task end
pool addr          pool size    used size     free size    max free node size   used node num     free node num      UsageWaterLine
---------------    --------     -------       --------     --------------       -------------      ------------      ------------
0x8409090488       0x1e740      0x1b420       0x30b0       0x30b0               0x6c               0x1                0x1b690        
Get Setup Config.
pwr cap[0]: 0, 63
pwr cap[1]: f, 27
Node 0, Die 0 ImpState is 0 skip exec.
Node 0, Die 2 ImpState is 0 skip exec.
Node 1, Die 0 ImpState is 0 skip exec.
Node 1, Die 2 ImpState is 0 skip exec.
pwr cap[2]: 1, 3
[0.00.56.962]DDR Rreserved for IMU: len = 3e00000
[LOG]head = 0x0, tail = 0x1a1f, logSize = 0x1a1f
copy registry.json file success
Set component all release version to sram end.
ipcMsgSend success
[0.00.56.999]starting ras Init
nodeId = 0, dieId = 0, isSasExist = 0.
nodeId = 0, dieId = 2, isSasExist = 0.
nodeId = 1, dieId = 0, isSasExist = 0.
nodeId = 1, dieId = 2, isSasExist = 0.
Mce Table head exist!
RasIntRegister init 452 
RasIntRegister init 453 
RasIntRegister init 465 
RasIntRegister init 466 
RasIntRegister init 86 
RasIntRegister init 87 
RasIntRegister init 478 
RasIntRegister init 479 
RasIntRegister init 491 
RasIntRegister init 492 
RasIntRegister init 130 
RasIntRegister init 131 
RasIntRegister init 98 
RasIntRegister init 142 
[0.00.57.050]starting ras end
[0.01.04.775][ERR]cmd not support! cmd = 0xd
[0.01.18.888]PCIE INIT DONE.
Interrupt 454 register OK
Interrupt 467 register OK
Interrupt 480 register OK
Interrupt 493 register OK
data = 0x0
pmt Init done

Add ep: bdf=d900 eid=9 epCnt=1 eid_alloc=a
Add ep: bdf=300 eid=a epCnt=1 eid_alloc=b
mctp task ok.


HSM_LOG:
[00:00:00.000][info] succeed to do thirdparty dfx_pabuk init
[00:00:00.000][info] succeed to do thirdparty crypto_driver init


0>[TracePoint] type[  0] cmd[  1] data[  4]
0>
Board Info:
0>  chip version        : 0
0>  efuse pg cluster TB : 0x0
0>  ak mode             : 0
0>
0>[TracePoint] type[  0] cmd[  1] data[  5]
0>Voltage Type[3]
0>Core Vmin Formula:
0>Totem[1] Core 400MHZ Vol Changed From [790] mv to [810] mv
0>Totem[1] Core 400MHZ -> Vol[790] mv
0>Totem[1] Core 2000MHZ Vol Changed From [763] mv to [810] mv
0>Totem[1] Core 2000MHZ -> Vol[763] mv
0>Totem[1] Core 2300MHZ -> Vol[833] mv
0>Totem[1] Core 2600MHZ -> Vol[911] mv
0>Totem[1] Core 2900MHZ -> Vol[986] mv
0>Totem[1] Core 3100MHZ -> Vol[1032] mv
0>Uncore Vmin Formula:
0>Totem Uncore 400MHZ -> Vol[830] mv
0>Totem[1] Uncore 2000MHZ Vol Changed From [766] mv to [830] mv
0>Totem Uncore 2000MHZ -> Vol[766] mv
0>Totem[2] Uncore 2300MHZ Vol Changed From [816] mv to [830] mv
0>Totem Uncore 2300MHZ -> Vol[816] mv
0>Totem Uncore 2500MHZ -> Vol[848] mv
0>Totem Uncore 2700MHZ -> Vol[891] mv
0>Totem Uncore 2900MHZ -> Vol[933] mv
0>Core VF curve:
0>[ 400]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[ 450]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[ 500]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[ 550]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[ 600]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[ 650]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[ 700]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[ 750]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[ 800]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[ 850]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[ 900]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[ 950]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1000]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1050]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1100]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1150]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1200]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1250]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1300]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1350]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1400]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1450]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1500]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1550]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1600]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1650]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1700]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1750]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1800]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1850]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1900]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1950]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[2000]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[2050]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[2100]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[2150]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[2200]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[2250]MHZ -> Vol TA[ 810]mv TB[ 821]mv
0>[2300]MHZ -> Vol TA[ 810]mv TB[ 833]mv
0>[2350]MHZ -> Vol TA[ 810]mv TB[ 846]mv
0>[2400]MHZ -> Vol TA[ 810]mv TB[ 859]mv
0>[2450]MHZ -> Vol TA[ 810]mv TB[ 872]mv
0>[2500]MHZ -> Vol TA[ 810]mv TB[ 885]mv
0>[2550]MHZ -> Vol TA[ 810]mv TB[ 898]mv
0>[2600]MHZ -> Vol TA[ 810]mv TB[ 911]mv
0>[2650]MHZ -> Vol TA[ 810]mv TB[ 923]mv
0>[2700]MHZ -> Vol TA[ 810]mv TB[ 936]mv
0>[2750]MHZ -> Vol TA[ 810]mv TB[ 948]mv
0>[2800]MHZ -> Vol TA[ 810]mv TB[ 961]mv
0>[2850]MHZ -> Vol TA[ 810]mv TB[ 973]mv
0>[2900]MHZ -> Vol TA[ 810]mv TB[ 986]mv
0>[2950]MHZ -> Vol TA[ 810]mv TB[ 997]mv
0>[3000]MHZ -> Vol TA[ 810]mv TB[1009]mv
0>[3050]MHZ -> Vol TA[ 810]mv TB[1020]mv
0>[3100]MHZ -> Vol TA[ 810]mv TB[1032]mv
0>Uncore VF curve:
0>Uncore [   0]MHZ -> Vol [ 830]mv
0>Uncore [ 100]MHZ -> Vol [ 830]mv
0>Uncore [ 200]MHZ -> Vol [ 830]mv
0>Uncore [ 300]MHZ -> Vol [ 830]mv
0>Uncore [ 400]MHZ -> Vol [ 830]mv
0>Uncore [ 500]MHZ -> Vol [ 830]mv
0>Uncore [ 600]MHZ -> Vol [ 830]mv
0>Uncore [ 700]MHZ -> Vol [ 830]mv
0>Uncore [ 800]MHZ -> Vol [ 830]mv
0>Uncore [ 900]MHZ -> Vol [ 830]mv
0>Uncore [1000]MHZ -> Vol [ 830]mv
0>Uncore [1100]MHZ -> Vol [ 830]mv
0>Uncore [1200]MHZ -> Vol [ 830]mv
0>Uncore [1300]MHZ -> Vol [ 830]mv
0>Uncore [1400]MHZ -> Vol [ 830]mv
0>Uncore [1500]MHZ -> Vol [ 830]mv
0>Uncore [1600]MHZ -> Vol [ 830]mv
0>Uncore [1700]MHZ -> Vol [ 830]mv
0>Uncore [1800]MHZ -> Vol [ 830]mv
0>Uncore [1900]MHZ -> Vol [ 830]mv
0>Uncore [2000]MHZ -> Vol [ 830]mv
0>Uncore [2100]MHZ -> Vol [ 830]mv
0>Uncore [2200]MHZ -> Vol [ 830]mv
0>Uncore [2300]MHZ -> Vol [ 830]mv
0>Uncore [2400]MHZ -> Vol [ 832]mv
0>Uncore [2500]MHZ -> Vol [ 848]mv
0>Uncore [2600]MHZ -> Vol [ 869]mv
0>Uncore [2700]MHZ -> Vol [ 891]mv
0>Uncore [2800]MHZ -> Vol [ 912]mv
0>Uncore [2900]MHZ -> Vol [ 933]mv
0>Uncore [3000]MHZ -> Vol [1100]mv
0>[TracePoint] type[  0] cmd[  1] data[  6]
0>[TracePoint] type[  0] cmd[  1] data[  7]
0>
********Hello Huawei LiteOS********

KpxxxxIPU Firmware Version : VX.X.X
LiteOS Kernel Version : 5.7.0
0>Run on ChipVersion[0] Node[0] Die[0]
0>build time : Oct 27 2025 20:30:00

0>**********************************
0>
main core booting up...
0>start set affinity
0>
mpidr = 0x81000000
0>sram ecc state: 0x0, sram ecc cnt: 0x0
0>[TracePoint] type[  0] cmd[  2] data[  1]
0>[TracePoint] type[  0] cmd[  2] data[  2]
0>LRDXSD_LOCK_OFFSET = 0x0
0>LRDXSD_ERRIMSK_OFFSET = 0x0
0>LRDXSD_DBG_OTIMSK_OFFSET = 0x0
0>LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
0>LRDXSD_DBG_EN_OFFSET = 0x1
0>======tsensor params======
0>  is_trimmed       : 1
0>  underclocking_en : 1
0>===========end============
0>soc tsensor init done
0>========vrd info from cpld========
0>vrd_id | u64                | pmbus_en | avsbus_en | loop | pmbus_id | pmbus_addr | avs_sw | pmbus_sw | addr_9545 | domain_type | die_mask | reserved
0>  00   | 0x0003000300002b15 | 0x1      | 0x0       | 0x1  | 0x1      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x3         | 0x0300   | 0x0
0>  01   | 0x000001050000201b | 0x1      | 0x1       | 0x2  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0001   | 0x0
0>  02   | 0x0002000100002017 | 0x1      | 0x1       | 0x1  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0200   | 0x0
0>  03   | 0x0003000200002027 | 0x1      | 0x1       | 0x1  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x2         | 0x0300   | 0x0
0>  04   | 0x000002050000202b | 0x1      | 0x1       | 0x2  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0002   | 0x0
0>  05   | 0x0003000400002b19 | 0x1      | 0x0       | 0x2  | 0x1      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x4         | 0x0300   | 0x0
0>  06   | 0x0000000000000000 | 0x0      | 0x0       | 0x0  | 0x0      | 0x00       | 0x0    | 0x0      | 0x0       | 0x0         | 0x0000   | 0x0
0>================end===============
0>[ERR]0>vrd[6] info invalid, vrd_info = 0x0
0>default power domain data used
0>=============vrd info=============
0>power domain num: 6
0>power domain[00] id:2 | CORE_DVFS_TB       | PMBus NA | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
0>power domain[01] id:4 | IO_DVDD_NA         | PMBus NA | cap:0x3 | rail:1 | addr:0x20 | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
0>power domain[02] id:3 | UNCORE_DVFS        | PMBus NB | cap:0x3 | rail:0 | addr:0x20 | def_volt: 848 mV | min_volt: 750 mV | max_volt:1100 mV
0>power domain[03] id:5 | IO_DVDD_NB         | PMBus NB | cap:0x3 | rail:1 | addr:0x20 | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
0>power domain[04] id:1 | DDR_VDD            | PMBus NA | cap:0x1 | rail:0 | addr:0x2b | def_volt: 765 mV | min_volt: 650 mV | max_volt: 850 mV
0>power domain[05] id:6 | DDR_VDDQ           | PMBus NA | cap:0x1 | rail:1 | addr:0x2b | def_volt:1100 mV | min_volt:1000 mV | max_volt:1200 mV
0>================end===============
0>pmbus[0] init done
0>pmbus[1] init done
0>power domain[2] CORE_DVFS_TB       | NA PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
0>power domain[4] IO_DVDD_NA         | NA PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 800 mV | pmu:MP2882
0>power domain[3] UNCORE_DVFS        | NB PMBus/AVSBus | rail:0 | addr:0x20 | def_volt: 848 mV | pmu:MP2882
0>power domain[5] IO_DVDD_NB         | NB PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 800 mV | pmu:MP2882
0>power domain[1] DDR_VDD            | NA PMBus        | rail:0 | addr:0x2b | def_volt: 765 mV | pmu:MP2882
0>power domain[6] DDR_VDDQ           | NA PMBus        | rail:1 | addr:0x2b | def_volt:1100 mV | pmu:MP2882
0>power domain[2] CORE_DVFS_TB       is transferred to AVSBus mode
0>power domain[4] IO_DVDD_NA         is transferred to AVSBus mode
0>power domain[3] UNCORE_DVFS        is transferred to AVSBus mode
0>power domain[5] IO_DVDD_NB         is transferred to AVSBus mode
0>avsbus resync success
0>avsbus[0] init done
0>avsbus resync success
0>avsbus[1] init done
0>============volt boot============
0>power domain[2] volt = 1105 mV
0>power domain[4] volt =  804 mV
0>power domain[3] volt = 1005 mV
0>power domain[5] volt =  804 mV
0>power domain[1] volt =  767 mV
0>power domain[6] volt = 1103 mV
0>===============end===============
0>power domain[0] not exist
0>--w&h rd rail:0, 1105, CORE_DVFS_TB
0>--w&h rd rail:1, 800, CORE_DVFS_TB
0>power domain[2] set volt --> 1105 mV success
0>--w&h rd rail:0, 1005, UNCORE_DVFS
0>--w&h rd rail:1, 800, UNCORE_DVFS
0>power domain[3] set volt -->  851 mV success
0>============volt post============
0>power domain[2] volt = 1105 mV
0>power domain[4] volt =  802 mV
0>power domain[3] volt =  849 mV
0>power domain[5] volt =  802 mV
0>power domain[1] volt =  767 mV
0>power domain[6] volt = 1103 mV
0>===============end===============
0>Hboot1 Info RAW Dump: [0x91][0x00][0x00][0x14][0x01][0x00][0x01]
0>PowerSensorSupport[1], Cali[5120], Loss[7200]
0>Power Sensor Calibration Value[5120]!
0>the power sensor : manu id = 2peak, die id = TPA626
0>power sensor[0] init success
0>Totem[1] Core Boot Vol [1105]mv
0>Totem[1] Core Current Vol [1100]mv
0>NA 1620V1b0
0>NB 1620V1b0
0>GetCoreBaseFreq [2600000KHZ]
0>GetCoreTurboFreq [2600000KHZ]
0>GetCustomClusterNum [10]
0>Ipu ACG Training Done!
0>AP Last Time:[0.00.01.394]
0>wait UEFI pll init...
0>done
0>acg trim start
0>core trim freq:2000, avs:0 volt:810mv
0>core trim freq:2050, avs:1 volt:810mv
0>core trim freq:2100, avs:2 volt:810mv
0>core trim freq:2150, avs:3 volt:810mv
0>core trim freq:2200, avs:4 volt:810mv
0>core trim freq:2250, avs:5 volt:821mv
0>core trim freq:2300, avs:6 volt:833mv
0>core trim freq:2350, avs:7 volt:846mv
0>core trim freq:2400, avs:8 volt:859mv
0>core trim freq:2450, avs:9 volt:872mv
0>core trim freq:2500, avs:10 volt:885mv
0>core trim freq:2550, avs:11 volt:898mv
0>core trim freq:2600, avs:12 volt:911mv
0>core trim freq:2650, avs:13 volt:923mv
0>core trim freq:2700, avs:14 volt:936mv
0>core trim freq:2750, avs:15 volt:948mv
0>core trim freq:2800, avs:16 volt:961mv
0>core trim freq:2850, avs:17 volt:973mv
0>core trim freq:2900, avs:18 volt:986mv
0>core trim freq:2950, avs:19 volt:997mv
0>core trim freq:3000, avs:20 volt:1009mv
0>core trim freq:3050, avs:21 volt:1020mv
0>core trim freq:3100, avs:22 volt:1032mv
0>acg trim end
0>LDO disabled
0>[TracePoint] type[  0] cmd[  2] data[  3]
0>Interrupt 423 register OK
0>Interrupt 430 register OK
0>[TracePoint] type[  0] cmd[  2] data[  4]
0>
0>cpu 0 entering scheduler
0>[TracePoint] type[  0] cmd[  3] data[  1]
0>add your ipu app init here!
0>IpuInterfaceTaskStart Entry ...
0>ipu interface task wait parameters from uefi...
0>thermal soc task enabled
0>AP Last Time:[0.00.14.704]
0>ThermalDimmStart Entry ...
0>wait ddr init done...
0>power task start...
0>[TracePoint] type[  0] cmd[  3] data[  2]
0>ufs task wait parameters from uefi...
0>AmuTaskStart Entry ... 
0>amu task wait parameters from uefi...
0>ThermalSiwStart Entry ...
0>ThermalSiwTask idle...
0>DemtTaskStart Entry ...
0>[TracePoint] type[  0] cmd[  3] data[  3]
0>demt task wait parameters from uefi...
0>HiBoostTaskStart Entry ...
0>HiBoost task enabled
0>Waiting for UEFI parameters...
0>[TracePoint] type[  0] cmd[  3] data[  4]
0>AgeTaskStart Entry ...
0>[TracePoint] type[  0] cmd[  3] data[  5]
0>age task wait parameters from uefi...
0>uefi parameters ready!
0>UFSProfile[0]
0>PowerPolicy[2] BenchMarkSelection[0]
0>ipu interface task wait ddr init done from uefi...
0>ufs task parameters from uefi ready
0>uncore domain[1] freq:2500
0>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
0>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
0>======sioe status======
0>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
0>thermal soc task restore underclocking_en=1
0>ppu alert temp div init done
0>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
0>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
0>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
0>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
0>==========end==========
0>sioe init done
0>ufs task enabled
0>--> UFS profile[0]
0>UEFI parameters ready
0>UncoreMaxFreq Set to [2500 MHZ]
0>get TDP from efuse success, value = 185000mw
0>target power set to [185000]mw, brd:[185000]
0>demt task parameters from uefi ready
0>age task parameters from uefi ready
0>age task enabled
0>uefi ddr init finish!
0>ipu interface task wait uefi end done from uefi...
0>ddr init done, start thermal dimm task
0>======dimm status======
0>  chl[0] dimm0 0, dimm1 0
0>  chl[1] dimm0 0, dimm1 0
0>  chl[2] dimm0 2, dimm1 0
0>  chl[3] dimm0 0, dimm1 0
0>  chl[4] dimm0 0, dimm1 0
0>  chl[5] dimm0 0, dimm1 0
0>  chl[6] dimm0 0, dimm1 0
0>  chl[7] dimm0 0, dimm1 0
0>==========end==========
0>chl[2] registered, dimm mask = 0x1
0>=====dimm temp params=====
0>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
0>  is_thermal_thro_en  : 1
0>  is_aref_rate_auto   : 1
0>===========end============
0>chl[2] max_temp 30'C, aref_rate 0x5 --> 0x4
1>[TracePoint] type[  0] cmd[  1] data[  4]
1>
Board Info:
1>  chip version        : 0
1>  efuse pg cluster TB : 0x0
1>  ak mode             : 0
1>
1>[TracePoint] type[  0] cmd[  1] data[  5]
1>Voltage Type[3]
1>Core Vmin Formula:
1>Totem[1] Core 400MHZ Vol Changed From [790] mv to [810] mv
1>Totem[1] Core 400MHZ -> Vol[790] mv
1>Totem[1] Core 2000MHZ Vol Changed From [763] mv to [810] mv
1>Totem[1] Core 2000MHZ -> Vol[763] mv
1>Totem[1] Core 2300MHZ -> Vol[832] mv
1>Totem[1] Core 2600MHZ -> Vol[910] mv
1>Totem[1] Core 2900MHZ -> Vol[985] mv
1>Totem[1] Core 3100MHZ -> Vol[1031] mv
1>Uncore Vmin Formula:
1>Totem Uncore 400MHZ -> Vol[830] mv
1>Totem[1] Uncore 2000MHZ Vol Changed From [764] mv to [830] mv
1>Totem Uncore 2000MHZ -> Vol[764] mv
1>Totem[2] Uncore 2300MHZ Vol Changed From [814] mv to [830] mv
1>Totem Uncore 2300MHZ -> Vol[814] mv
1>Totem Uncore 2500MHZ -> Vol[846] mv
1>Totem Uncore 2700MHZ -> Vol[889] mv
1>Totem Uncore 2900MHZ -> Vol[930] mv
1>Core VF curve:
1>[ 400]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[ 450]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[ 500]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[ 550]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[ 600]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[ 650]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[ 700]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[ 750]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[ 800]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[ 850]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[ 900]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[ 950]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1000]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1050]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1100]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1150]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1200]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1250]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1300]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1350]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1400]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1450]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1500]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1550]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1600]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1650]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1700]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1750]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1800]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1850]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1900]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1950]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[2000]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[2050]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[2100]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[2150]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[2200]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[2250]MHZ -> Vol TA[ 810]mv TB[ 820]mv
1>[2300]MHZ -> Vol TA[ 810]mv TB[ 832]mv
1>[2350]MHZ -> Vol TA[ 810]mv TB[ 845]mv
1>[2400]MHZ -> Vol TA[ 810]mv TB[ 858]mv
1>[2450]MHZ -> Vol TA[ 810]mv TB[ 871]mv
1>[2500]MHZ -> Vol TA[ 810]mv TB[ 884]mv
1>[2550]MHZ -> Vol TA[ 810]mv TB[ 897]mv
1>[2600]MHZ -> Vol TA[ 810]mv TB[ 910]mv
1>[2650]MHZ -> Vol TA[ 810]mv TB[ 922]mv
1>[2700]MHZ -> Vol TA[ 810]mv TB[ 935]mv
1>[2750]MHZ -> Vol TA[ 810]mv TB[ 947]mv
1>[2800]MHZ -> Vol TA[ 810]mv TB[ 960]mv
1>[2850]MHZ -> Vol TA[ 810]mv TB[ 972]mv
1>[2900]MHZ -> Vol TA[ 810]mv TB[ 985]mv
1>[2950]MHZ -> Vol TA[ 810]mv TB[ 996]mv
1>[3000]MHZ -> Vol TA[ 810]mv TB[1008]mv
1>[3050]MHZ -> Vol TA[ 810]mv TB[1019]mv
1>[3100]MHZ -> Vol TA[ 810]mv TB[1031]mv
1>Uncore VF curve:
1>Uncore [   0]MHZ -> Vol [ 830]mv
1>Uncore [ 100]MHZ -> Vol [ 830]mv
1>Uncore [ 200]MHZ -> Vol [ 830]mv
1>Uncore [ 300]MHZ -> Vol [ 830]mv
1>Uncore [ 400]MHZ -> Vol [ 830]mv
1>Uncore [ 500]MHZ -> Vol [ 830]mv
1>Uncore [ 600]MHZ -> Vol [ 830]mv
1>Uncore [ 700]MHZ -> Vol [ 830]mv
1>Uncore [ 800]MHZ -> Vol [ 830]mv
1>Uncore [ 900]MHZ -> Vol [ 830]mv
1>Uncore [1000]MHZ -> Vol [ 830]mv
1>Uncore [1100]MHZ -> Vol [ 830]mv
1>Uncore [1200]MHZ -> Vol [ 830]mv
1>Uncore [1300]MHZ -> Vol [ 830]mv
1>Uncore [1400]MHZ -> Vol [ 830]mv
1>Uncore [1500]MHZ -> Vol [ 830]mv
1>Uncore [1600]MHZ -> Vol [ 830]mv
1>Uncore [1700]MHZ -> Vol [ 830]mv
1>Uncore [1800]MHZ -> Vol [ 830]mv
1>Uncore [1900]MHZ -> Vol [ 830]mv
1>Uncore [2000]MHZ -> Vol [ 830]mv
1>Uncore [2100]MHZ -> Vol [ 830]mv
1>Uncore [2200]MHZ -> Vol [ 830]mv
1>Uncore [2300]MHZ -> Vol [ 830]mv
1>Uncore [2400]MHZ -> Vol [ 830]mv
1>Uncore [2500]MHZ -> Vol [ 846]mv
1>Uncore [2600]MHZ -> Vol [ 867]mv
1>Uncore [2700]MHZ -> Vol [ 889]mv
1>Uncore [2800]MHZ -> Vol [ 909]mv
1>Uncore [2900]MHZ -> Vol [ 930]mv
1>Uncore [3000]MHZ -> Vol [1100]mv
1>[TracePoint] type[  0] cmd[  1] data[  6]
1>[TracePoint] type[  0] cmd[  1] data[  7]
1>
********Hello Huawei LiteOS********

KpxxxxIPU Firmware Version : VX.X.X
LiteOS Kernel Version : 5.7.0
1>Run on ChipVersion[0] Node[1] Die[0]
1>build time : Oct 27 2025 20:30:00

1>**********************************
1>
main core booting up...
1>start set affinity
1>
mpidr = 0x81040000
1>sram ecc state: 0x0, sram ecc cnt: 0x0
1>[TracePoint] type[  0] cmd[  2] data[  1]
1>[TracePoint] type[  0] cmd[  2] data[  2]
1>LRDXSD_LOCK_OFFSET = 0x0
1>LRDXSD_ERRIMSK_OFFSET = 0x0
1>LRDXSD_DBG_OTIMSK_OFFSET = 0x0
1>LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
1>LRDXSD_DBG_EN_OFFSET = 0x1
1>======tsensor params======
1>  is_trimmed       : 1
1>  underclocking_en : 1
1>===========end============
1>soc tsensor init done
1>========vrd info from cpld========
1>vrd_id | u64                | pmbus_en | avsbus_en | loop | pmbus_id | pmbus_addr | avs_sw | pmbus_sw | addr_9545 | domain_type | die_mask | reserved
1>  00   | 0x0003000300002b15 | 0x1      | 0x0       | 0x1  | 0x1      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x3         | 0x0300   | 0x0
1>  01   | 0x000001050000201b | 0x1      | 0x1       | 0x2  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0001   | 0x0
1>  02   | 0x0002000100002017 | 0x1      | 0x1       | 0x1  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0200   | 0x0
1>  03   | 0x0003000200002027 | 0x1      | 0x1       | 0x1  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x2         | 0x0300   | 0x0
1>  04   | 0x000002050000202b | 0x1      | 0x1       | 0x2  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0002   | 0x0
1>  05   | 0x0003000400002b19 | 0x1      | 0x0       | 0x2  | 0x1      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x4         | 0x0300   | 0x0
1>  06   | 0x0000000000000000 | 0x0      | 0x0       | 0x0  | 0x0      | 0x00       | 0x0    | 0x0      | 0x0       | 0x0         | 0x0000   | 0x0
1>================end===============
1>[ERR]1>vrd[6] info invalid, vrd_info = 0x0
1>default power domain data used
1>=============vrd info=============
1>power domain num: 6
1>power domain[00] id:2 | CORE_DVFS_TB       | PMBus NA | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
1>power domain[01] id:4 | IO_DVDD_NA         | PMBus NA | cap:0x3 | rail:1 | addr:0x20 | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
1>power domain[02] id:3 | UNCORE_DVFS        | PMBus NB | cap:0x3 | rail:0 | addr:0x20 | def_volt: 846 mV | min_volt: 750 mV | max_volt:1100 mV
1>power domain[03] id:5 | IO_DVDD_NB         | PMBus NB | cap:0x3 | rail:1 | addr:0x20 | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
1>power domain[04] id:1 | DDR_VDD            | PMBus NA | cap:0x1 | rail:0 | addr:0x2b | def_volt: 765 mV | min_volt: 650 mV | max_volt: 850 mV
1>power domain[05] id:6 | DDR_VDDQ           | PMBus NA | cap:0x1 | rail:1 | addr:0x2b | def_volt:1100 mV | min_volt:1000 mV | max_volt:1200 mV
1>================end===============
1>pmbus[0] init done
1>pmbus[1] init done
1>power domain[2] CORE_DVFS_TB       | NA PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
1>power domain[4] IO_DVDD_NA         | NA PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 800 mV | pmu:MP2882
1>power domain[3] UNCORE_DVFS        | NB PMBus/AVSBus | rail:0 | addr:0x20 | def_volt: 846 mV | pmu:MP2882
1>power domain[5] IO_DVDD_NB         | NB PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 800 mV | pmu:MP2882
1>power domain[1] DDR_VDD            | NA PMBus        | rail:0 | addr:0x2b | def_volt: 765 mV | pmu:MP2882
1>power domain[6] DDR_VDDQ           | NA PMBus        | rail:1 | addr:0x2b | def_volt:1100 mV | pmu:MP2882
1>power domain[2] CORE_DVFS_TB       is transferred to AVSBus mode
1>power domain[4] IO_DVDD_NA         is transferred to AVSBus mode
1>power domain[3] UNCORE_DVFS        is transferred to AVSBus mode
1>power domain[5] IO_DVDD_NB         is transferred to AVSBus mode
1>avsbus resync success
1>avsbus[0] init done
1>avsbus resync success
1>avsbus[1] init done
1>============volt boot============
1>power domain[2] volt = 1101 mV
1>power domain[4] volt =  806 mV
1>power domain[3] volt = 1005 mV
1>power domain[5] volt =  804 mV
1>power domain[1] volt =  769 mV
1>power domain[6] volt = 1101 mV
1>===============end===============
1>power domain[0] not exist
1>--w&h rd rail:0, 1101, CORE_DVFS_TB
1>--w&h rd rail:1, 800, CORE_DVFS_TB
1>power domain[2] set volt --> 1101 mV success
1>--w&h rd rail:0, 1007, UNCORE_DVFS
1>--w&h rd rail:1, 800, UNCORE_DVFS
1>power domain[3] set volt -->  851 mV success
1>============volt post============
1>power domain[2] volt = 1101 mV
1>power domain[4] volt =  804 mV
1>power domain[3] volt =  851 mV
1>power domain[5] volt =  800 mV
1>power domain[1] volt =  769 mV
1>power domain[6] volt = 1103 mV
1>===============end===============
1>Hboot1 Info RAW Dump: [0x01][0x00][0x00][0x14][0x01][0x00][0x01]
1>PowerSensorSupport[1], Cali[5120], Loss[0]
1>Power Sensor Calibration Value[5120]!
1>the power sensor : manu id = 2peak, die id = TPA626
1>power sensor[0] init success
1>Totem[1] Core Boot Vol [1101]mv
1>Totem[1] Core Current Vol [1100]mv
1>NA 1620V1b0
1>NB 1620V1b0
1>GetCoreBaseFreq [2600000KHZ]
1>GetCoreTurboFreq [2600000KHZ]
1>GetCustomClusterNum [10]
1>Ipu ACG Training Done!
1>AP Last Time:[0.00.01.391]
1>wait UEFI pll init...
1>done
1>acg trim start
1>core trim freq:2000, avs:0 volt:810mv
1>core trim freq:2050, avs:1 volt:810mv
1>core trim freq:2100, avs:2 volt:810mv
1>core trim freq:2150, avs:3 volt:810mv
1>core trim freq:2200, avs:4 volt:810mv
1>core trim freq:2250, avs:5 volt:820mv
1>core trim freq:2300, avs:6 volt:832mv
1>core trim freq:2350, avs:7 volt:845mv
1>core trim freq:2400, avs:8 volt:858mv
1>core trim freq:2450, avs:9 volt:871mv
1>core trim freq:2500, avs:10 volt:884mv
1>core trim freq:2550, avs:11 volt:897mv
1>core trim freq:2600, avs:12 volt:910mv
1>core trim freq:2650, avs:13 volt:922mv
1>core trim freq:2700, avs:14 volt:935mv
1>core trim freq:2750, avs:15 volt:947mv
1>core trim freq:2800, avs:16 volt:960mv
1>core trim freq:2850, avs:17 volt:972mv
1>core trim freq:2900, avs:18 volt:985mv
1>core trim freq:2950, avs:19 volt:996mv
1>core trim freq:3000, avs:20 volt:1008mv
1>core trim freq:3050, avs:21 volt:1019mv
1>core trim freq:3100, avs:22 volt:1031mv
1>acg trim end
1>LDO disabled
1>[TracePoint] type[  0] cmd[  2] data[  3]
1>Interrupt 423 register OK
1>Interrupt 430 register OK
1>[TracePoint] type[  0] cmd[  2] data[  4]
1>
1>cpu 0 entering scheduler
1>[TracePoint] type[  0] cmd[  3] data[  1]
1>add your ipu app init here!
1>IpuInterfaceTaskStart Entry ...
1>ipu interface task wait parameters from uefi...
1>thermal soc task enabled
1>AP Last Time:[0.00.14.859]
1>ThermalDimmStart Entry ...
1>wait ddr init done...
1>power task start...
1>[TracePoint] type[  0] cmd[  3] data[  2]
1>ufs task wait parameters from uefi...
1>AmuTaskStart Entry ... 
1>amu task wait parameters from uefi...
1>ThermalSiwStart Entry ...
1>ThermalSiwTask idle...
1>DemtTaskStart Entry ...
1>[TracePoint] type[  0] cmd[  3] data[  3]
1>demt task wait parameters from uefi...
1>HiBoostTaskStart Entry ...
1>HiBoost task enabled
1>Waiting for UEFI parameters...
1>[TracePoint] type[  0] cmd[  3] data[  4]
1>AgeTaskStart Entry ...
1>[TracePoint] type[  0] cmd[  3] data[  5]
1>age task wait parameters from uefi...
1>uefi parameters ready!
1>UFSProfile[0]
1>PowerPolicy[2] BenchMarkSelection[0]
1>ipu interface task wait ddr init done from uefi...
1>ufs task parameters from uefi ready
1>uncore domain[1] freq:2500
1>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
1>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
1>======sioe status======
1>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
1>thermal soc task restore underclocking_en=1
1>ppu alert temp div init done
1>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
1>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
1>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
1>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
1>==========end==========
1>sioe init done
1>ufs task enabled
1>--> UFS profile[0]
1>UEFI parameters ready
1>UncoreMaxFreq Set to [2500 MHZ]
1>get TDP from efuse success, value = 185000mw
1>target power set to [185000]mw, brd:[185000]
1>demt task parameters from uefi ready
1>age task parameters from uefi ready
1>age task enabled
1>uefi ddr init finish!
1>ipu interface task wait uefi end done from uefi...
1>ddr init done, start thermal dimm task
1>======dimm status======
1>  chl[0] dimm0 0, dimm1 0
1>  chl[1] dimm0 0, dimm1 0
1>  chl[2] dimm0 2, dimm1 0
1>  chl[3] dimm0 0, dimm1 0
1>  chl[4] dimm0 0, dimm1 0
1>  chl[5] dimm0 0, dimm1 0
1>  chl[6] dimm0 0, dimm1 0
1>  chl[7] dimm0 0, dimm1 0
1>==========end==========
1>chl[2] registered, dimm mask = 0x1
1>=====dimm temp params=====
1>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
1>  is_thermal_thro_en  : 1
1>  is_aref_rate_auto   : 1
1>===========end============
1>chl[2] max_temp 30'C, aref_rate 0x5 --> 0x4


HSM_LOG:
[00:00:00.010][info] os_mem_system_init default pool done
[00:00:00.016][info] succeed to do thirdparty otpc_pabuk init
[00:00



HSM_LOG:
:00.017][info] succeed to do thirdparty boot_profile_driver init
[00:00:00.017][info] succeed to do thirdparty measure_value_ma



HSM_LOG:
nage_driver init
[00:00:00.018][info] succeed to do thirdparty period_driver init
[00:00:00.018][info]  start loading internal

[0.01.50.994]BIOS POST END.
Create SetReportPcieMmioToBmc ok.
Start SetReportPcieMmioToBmc ok.
slotNum = 0x18
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[0] port:4  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[1] port:6  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[2] port:12  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[3] port:14  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[4] port:16  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[5] port:18  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[6] port:20  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[7] port:22  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[8] port:24  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[9] port:26  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[10] port:32  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[11] port:34  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[12] port:0  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[13] port:2  pcieSlotCtrl.data (after)0x7c0.



HSM_LOG:
 task ...
[00:00:00.018][info]  task name is ccm_task
[00:00:00.019][info]  hm_dynamic_loadelf successfully!
[00:00:00.019][i

0>uefi end finish!
0>ipu interface task exit!
0>amu task parameters from uefi ready
1>uefi end finish!
1>ipu interface task exit!
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[14] port:12  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[15] port:14  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[16] port:16  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[17] port:18  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[18] port:24  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[19] port:26  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[20] port:32  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[21] port:34  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[22] port:36  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[23] port:38  pcieSlotCtrl.data (after)0x14801c0.



HSM_LOG:
nfo] internal task[1] task_name=ccm_task load successfully
[00:00:00.020][info]  task name is upgrade_task
[00:00:00.020][info

1>amu task parameters from uefi ready
Enter current value process


HSM_LOG:
]  hm_dynamic_loadelf successfully!
[00:00:00.021][info] internal task[2] task_name=upgrade_task load successfully
[00:00:00.0



HSM_LOG:
22][info]  task name is hes_task
[00:00:00.022][info]  hm_dynamic_loadelf successfully!
[00:00:00.023][info] internal task[3] 



HSM_LOG:
task_name=hes_task load successfully
[00:00:00.024][info] created task ccm_task success!
[00:00:00.025][info] created task upg



HSM_LOG:
rade_task success!
[00:00:00.026][info] created task hes_task success!
[00:00:00.026][info] Init start.
[1970-01-01 00:00:00.



HSM_LOG:
027][HSM][INFO][54] Platform init 0x20250523 0x4e.

[1970-01-01 00:00:00.027][HSM][INFO][197] ccm start.

[1970-01-01 00:00:00



HSM_LOG:
.028][HSM][INFO][86] upgrade task init success.

[1970-01-01 00:00:00.028][HSM][INFO][95] upgrade recv cmd, 0x181.

[1970-01-0



HSM_LOG:
1 00:00:00.029][HSM][INFO][103] upgrade res, 0x3a5aa5a3.

[1970-01-01 00:00:00.030][HSM][INFO][75] hes tee_task_entry.

[1970-



HSM_LOG:
01-01 00:00:00.554][HSM][INFO][44] hes init success.

[00:00:00.554][info] Init over.


0>amu task activated
0>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
1>amu task activated
1>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
[0.06.50.993]IpmiCmdReportPcieMMIO start
[0.07.01.825]IpmiCmdReportPcieMMIO end
pool addr          pool size    used size     free size    max free node size   used node num     free node num      UsageWaterLine
---------------    --------     -------       --------     --------------       -------------      ------------      ------------
0x8409090488       0x1e740      0x19dd0       0x4700       0x30b0               0x90               0x3                0x1b690        
[0.31.24.031]ext0 int trigger
[0.31.24.209]slot: 23, slotCtrl = 0x815f8
[0.31.24.287]slot[23] port:38 begin to power OFF.
[0.31.37.528]ext0 int trigger
[0.31.37.603]slot: 12, slotCtrl = 0x4817f8
[0.31.37.632]slot[12] port:0 begin to power ON.
Add ep: bdf=8100 eid=b epCnt=1 eid_alloc=c
[0.40.56.127]ext0 int trigger
[0.40.56.202]slot: 12, slotCtrl = 0x811f8
[0.40.56.290]ext0 int trigger
[0.40.56.427]slot[12] port:0 begin to power OFF.
[0.41.04.327]ext0 int trigger
[0.41.04.409]slot: 13, slotCtrl = 0x4817f8
[0.41.04.502]slot[13] port:2 begin to power ON.
Add ep: bdf=8200 eid=c epCnt=2 eid_alloc=d
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     
********Hello Huawei LiteOS********

KpxxxxIMU Firmware Version : VX.X.X
LiteOS Kernel Version : 5.7.0
Run on ChipVersion[0] Node[0] Die[2]
build time : Oct 27 2025 20:30:00

**********************************

main core booting up...
start set affinity

mpidr = 0x81020000
sram ecc state: 0x0, sram ecc cnt: 0x0
[0.00.00.032]node 0 begins init all serdes.
BoardInfo->NodeNum 2.
BoardInfo->NodeId 0.
BoardInfo->InfoVersion 5.
BoardInfo->NASerdesSceneMode 3.
BoardInfo->NBSerdesSceneMode 3.
BoardInfo->HccsTopologyType 0.
BoardInfo->BoardId 0.
ChipVersionIsPro: 0.
BoardInfo Node 0, SerdesUseMode: 1 2 1 1 1 1 1  1 1 1 4 4 1 12 
BoardInfo Node 1, SerdesUseMode: 1 1 1 1 1 1 1  12 13 1 4 4 1 1 
BoardInfo Node 0, SerdesRxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 1, SerdesRxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 0, SerdesTxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 1, SerdesTxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
serdessdk version: 2.0_5.0_20241203_imu
node_id 0, die 0, ind 0, usemode 1 begin serdes-init.
node_id 0, die 0, ind 1, usemode 2 begin serdes-init.
node_id 0, die 2, ind 0, usemode 1 begin serdes-init.
node_id 0, die 2, ind 1, usemode 1 begin serdes-init.
node_id 0, die 2, ind 6, usemode 12 begin serdes-init.
chip_id 0, die 2, ind 6, usemode 12 don't support, power down macro!
NodeId 0, DieId 2, Macro 6, power-down DS succeed.
NodeId 0, DieId 2, Macro 6, power-down DS succeed.
NodeId 0, DieId 2, Macro 6, power-down DS succeed.
NodeId 0, DieId 2, Macro 6, power-down DS succeed.
NodeId 0, DieId 2, Macro 6, power-down DS succeed.
NodeId 0, DieId 2, Macro 6, power-down DS succeed.
NodeId 0, DieId 2, Macro 6, power-down DS succeed.
NodeId 0, DieId 2, Macro 6, power-down DS succeed.
chip serdes init status:0x0.
[0.00.00.434]node 0 ends init all serdes.
link[4] freq_type:1 | peer_chip_type:1 | peer_node_id:1 | peer_link_id:5
link[5] freq_type:1 | peer_chip_type:1 | peer_node_id:1 | peer_link_id:4
register hccs done
IsFfeAdapt = 0.Use Default HCCS FFE Paras.
nodeId 0, dieId 1, linkId 0, FFE info: fir_pre1 -8, fir_main 55, fir_post1 0
node_id 0, die 2, ind 4, usemode 4 begin serdes-init.
IsFfeAdapt = 0.Use Default HCCS FFE Paras.
nodeId 0, dieId 1, linkId 1, FFE info: fir_pre1 -8, fir_main 55, fir_post1 0
node_id 0, die 2, ind 3, usemode 4 begin serdes-init.
hccs init start...
pa ring link down success
reset pa success
link[4] pcs init success
link[5] pcs init success
release reset pa success
link[4] macro adapt done (lane_mask=0xff) (0ms)
link[5] macro adapt done (lane_mask=0xff) (0ms)
link[4] pcs training success (10ms)
link[5] pcs training success (10ms)
link[4] training success (20ms)
link[5] training success (20ms)
link[4]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link[5]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link training success
pa[0] linkEn = 0x0
pa[0] allNodeLink0 = 0x0
pa[0] allNodeLink1 = 0x0
pa[1] linkEn = 0x3
pa[1] allNodeLink0 = 0x30
pa[1] allNodeLink1 = 0x0
pa init success
COM_PAID_INTLV_REG = 0x2
paid decode init success
pa[0] PA_PM_BASE_INFO = 0x0
pa[0] PA_PM_MAP_LINK_NUM = 0x0
pa[1] PA_PM_BASE_INFO = 0x330021
pa[1] PA_PM_MAP_LINK_NUM = 0x12
hccs performace config success
pa ring link up success
hccs init done
hccs access test start
node[0] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[1] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[1] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
hccs access test success
======hccs status======
  node[0] mask: expected = 0x30, link up = 0x30, width reduction = 0x0, link down = 0x0
  node[1] mask: expected = 0x30, link up = 0x30, width reduction = 0x0, link down = 0x0
==========end==========
report hccs status success
node[0] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
LRDXSD_LOCK_OFFSET = 0x0
LRDXSD_ERRIMSK_OFFSET = 0x0
LRDXSD_DBG_OTIMSK_OFFSET = 0x0
LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
LRDXSD_DBG_EN_OFFSET = 0x1
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
ID[0x1a67c8]!
[ERR]Don't support the flash, CS[0] ID[0x1a67c8]!!
ID[0x0]!
[ERR]Don't support the flash, CS[1] ID[0x0]!!
[ERR]Warnning, Select Default flash 
sfdp detect, try to get dummy data from hboot1 first.
ID[0x1a67c8]!
flash 0 support sfdp.
Interrupt 423 register OK
Interrupt 425 register OK
Interrupt 427 register OK
Interrupt 429 register OK
Interrupt 430 register OK
Interrupt 431 register OK
Interrupt 436 register OK

cpu 0 entering scheduler
[IMU] Watchdog Initialization done!
ScmiTaskEntry start.
Interrupt 456 register OK
Interrupt 469 register OK
Interrupt 482 register OK
Interrupt 495 register OK
starting Fpc Isolation Task end
starting fdm Err Info Task end
starting Roce recovery Task end
starting Ce_Storm Contrl Task end
starting Ras_Data_Update Task end
power register ubios call id
print register ubios call id
Interrupt 459 register OK
Interrupt 472 register OK
Interrupt 485 register OK
Interrupt 498 register OK
[0.00.13.275]Real time now 2026.3.18 07:31:57
NIC CARD[0][0]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[0][1]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[1][0]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[1][1]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
Init heart-beat-task end
Init SeamlessUpdateTask end
Init alarm-report-task end
pool addr          pool size    used size     free size    max free node size   used node num     free node num      UsageWaterLine
---------------    --------     -------       --------     --------------       -------------      ------------      ------------
0x8409090488       0x1e740      0x1b420       0x30b0       0x30b0               0x6c               0x1                0x1b690        
Get Setup Config.
pwr cap[0]: 0, 63
pwr cap[1]: f, 27
Node 0, Die 0 ImpState is 0 skip exec.
Node 0, Die 2 ImpState is 0 skip exec.
Node 1, Die 0 ImpState is 0 skip exec.
Node 1, Die 2 ImpState is 0 skip exec.
pwr cap[2]: 1, 3
[0.00.52.192]DDR Rreserved for IMU: len = 3e00000
[LOG]head = 0x0, tail = 0x1a1f, logSize = 0x1a1f
copy registry.json file success
Set component all release version to sram end.
ipcMsgSend success
[0.00.52.229]starting ras Init
nodeId = 0, dieId = 0, isSasExist = 0.
nodeId = 0, dieId = 2, isSasExist = 0.
nodeId = 1, dieId = 0, isSasExist = 0.
nodeId = 1, dieId = 2, isSasExist = 0.
Mce Table head exist!
RasIntRegister init 452 
RasIntRegister init 453 
RasIntRegister init 465 
RasIntRegister init 466 
RasIntRegister init 86 
RasIntRegister init 87 
RasIntRegister init 478 
RasIntRegister init 479 
RasIntRegister init 491 
RasIntRegister init 492 
RasIntRegister init 130 
RasIntRegister init 131 
RasIntRegister init 98 
RasIntRegister init 142 
[0.00.52.277]starting ras end
[0.01.01.278][ERR]cmd not support! cmd = 0xd
[0.01.15.569]PCIE INIT DONE.
Interrupt 454 register OK
Interrupt 467 register OK
Interrupt 480 register OK
Interrupt 493 register OK
data = 0x0
pmt Init done

Add ep: bdf=5800 eid=9 epCnt=1 eid_alloc=a
Add ep: bdf=300 eid=a epCnt=1 eid_alloc=b
mctp task ok.
[0.01.48.424]BIOS POST END.
Create SetReportPcieMmioToBmc ok.
Start SetReportPcieMmioToBmc ok.
slotNum = 0x18
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[0] port:4  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[1] port:6  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[2] port:12  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[3] port:14  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[4] port:16  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[5] port:18  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[6] port:20  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[7] port:22  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[8] port:24  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[9] port:26  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[10] port:32  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[11] port:34  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[12] port:0  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[13] port:2  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[14] port:12  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[15] port:14  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[16] port:16  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[17] port:18  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[18] port:24  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[19] port:26  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[20] port:32  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[21] port:34  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[22] port:36  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[23] port:38  pcieSlotCtrl.data (after)0x7c0.



HSM_LOG:
[00:00:00.000][info] succeed to do thirdparty dfx_pabuk init
[00:00:00.000][info] succeed to do thirdparty crypto_driver init


0>[TracePoint] type[  0] cmd[  1] data[  4]
0>
Board Info:
0>  chip version        : 0
0>  efuse pg cluster TB : 0x0
0>  ak mode             : 0
0>
0>[TracePoint] type[  0] cmd[  1] data[  5]
0>Voltage Type[3]
0>Core Vmin Formula:
0>Totem[1] Core 400MHZ Vol Changed From [790] mv to [810] mv
0>Totem[1] Core 400MHZ -> Vol[790] mv
0>Totem[1] Core 2000MHZ Vol Changed From [763] mv to [810] mv
0>Totem[1] Core 2000MHZ -> Vol[763] mv
0>Totem[1] Core 2300MHZ -> Vol[833] mv
0>Totem[1] Core 2600MHZ -> Vol[911] mv
0>Totem[1] Core 2900MHZ -> Vol[986] mv
0>Totem[1] Core 3100MHZ -> Vol[1032] mv
0>Uncore Vmin Formula:
0>Totem Uncore 400MHZ -> Vol[830] mv
0>Totem[1] Uncore 2000MHZ Vol Changed From [766] mv to [830] mv
0>Totem Uncore 2000MHZ -> Vol[766] mv
0>Totem[2] Uncore 2300MHZ Vol Changed From [816] mv to [830] mv
0>Totem Uncore 2300MHZ -> Vol[816] mv
0>Totem Uncore 2500MHZ -> Vol[848] mv
0>Totem Uncore 2700MHZ -> Vol[891] mv
0>Totem Uncore 2900MHZ -> Vol[933] mv
0>Core VF curve:
0>[ 400]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[ 450]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[ 500]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[ 550]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[ 600]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[ 650]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[ 700]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[ 750]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[ 800]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[ 850]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[ 900]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[ 950]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1000]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1050]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1100]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1150]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1200]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1250]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1300]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1350]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1400]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1450]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1500]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1550]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1600]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1650]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1700]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1750]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1800]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1850]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1900]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[1950]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[2000]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[2050]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[2100]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[2150]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[2200]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[2250]MHZ -> Vol TA[ 810]mv TB[ 821]mv
0>[2300]MHZ -> Vol TA[ 810]mv TB[ 833]mv
0>[2350]MHZ -> Vol TA[ 810]mv TB[ 846]mv
0>[2400]MHZ -> Vol TA[ 810]mv TB[ 859]mv
0>[2450]MHZ -> Vol TA[ 810]mv TB[ 872]mv
0>[2500]MHZ -> Vol TA[ 810]mv TB[ 885]mv
0>[2550]MHZ -> Vol TA[ 810]mv TB[ 898]mv
0>[2600]MHZ -> Vol TA[ 810]mv TB[ 911]mv
0>[2650]MHZ -> Vol TA[ 810]mv TB[ 923]mv
0>[2700]MHZ -> Vol TA[ 810]mv TB[ 936]mv
0>[2750]MHZ -> Vol TA[ 810]mv TB[ 948]mv
0>[2800]MHZ -> Vol TA[ 810]mv TB[ 961]mv
0>[2850]MHZ -> Vol TA[ 810]mv TB[ 973]mv
0>[2900]MHZ -> Vol TA[ 810]mv TB[ 986]mv
0>[2950]MHZ -> Vol TA[ 810]mv TB[ 997]mv
0>[3000]MHZ -> Vol TA[ 810]mv TB[1009]mv
0>[3050]MHZ -> Vol TA[ 810]mv TB[1020]mv
0>[3100]MHZ -> Vol TA[ 810]mv TB[1032]mv
0>Uncore VF curve:
0>Uncore [   0]MHZ -> Vol [ 830]mv
0>Uncore [ 100]MHZ -> Vol [ 830]mv
0>Uncore [ 200]MHZ -> Vol [ 830]mv
0>Uncore [ 300]MHZ -> Vol [ 830]mv
0>Uncore [ 400]MHZ -> Vol [ 830]mv
0>Uncore [ 500]MHZ -> Vol [ 830]mv
0>Uncore [ 600]MHZ -> Vol [ 830]mv
0>Uncore [ 700]MHZ -> Vol [ 830]mv
0>Uncore [ 800]MHZ -> Vol [ 830]mv
0>Uncore [ 900]MHZ -> Vol [ 830]mv
0>Uncore [1000]MHZ -> Vol [ 830]mv
0>Uncore [1100]MHZ -> Vol [ 830]mv
0>Uncore [1200]MHZ -> Vol [ 830]mv
0>Uncore [1300]MHZ -> Vol [ 830]mv
0>Uncore [1400]MHZ -> Vol [ 830]mv
0>Uncore [1500]MHZ -> Vol [ 830]mv
0>Uncore [1600]MHZ -> Vol [ 830]mv
0>Uncore [1700]MHZ -> Vol [ 830]mv
0>Uncore [1800]MHZ -> Vol [ 830]mv
0>Uncore [1900]MHZ -> Vol [ 830]mv
0>Uncore [2000]MHZ -> Vol [ 830]mv
0>Uncore [2100]MHZ -> Vol [ 830]mv
0>Uncore [2200]MHZ -> Vol [ 830]mv
0>Uncore [2300]MHZ -> Vol [ 830]mv
0>Uncore [2400]MHZ -> Vol [ 832]mv
0>Uncore [2500]MHZ -> Vol [ 848]mv
0>Uncore [2600]MHZ -> Vol [ 869]mv
0>Uncore [2700]MHZ -> Vol [ 891]mv
0>Uncore [2800]MHZ -> Vol [ 912]mv
0>Uncore [2900]MHZ -> Vol [ 933]mv
0>Uncore [3000]MHZ -> Vol [1100]mv
0>[TracePoint] type[  0] cmd[  1] data[  6]
0>[TracePoint] type[  0] cmd[  1] data[  7]
0>
********Hello Huawei LiteOS********

KpxxxxIPU Firmware Version : VX.X.X
LiteOS Kernel Version : 5.7.0
0>Run on ChipVersion[0] Node[0] Die[0]
0>build time : Oct 27 2025 20:30:00

0>**********************************
0>
main core booting up...
0>start set affinity
0>
mpidr = 0x81000000
0>sram ecc state: 0x0, sram ecc cnt: 0x0
0>[TracePoint] type[  0] cmd[  2] data[  1]
0>[TracePoint] type[  0] cmd[  2] data[  2]
0>LRDXSD_LOCK_OFFSET = 0x0
0>LRDXSD_ERRIMSK_OFFSET = 0x0
0>LRDXSD_DBG_OTIMSK_OFFSET = 0x0
0>LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
0>LRDXSD_DBG_EN_OFFSET = 0x1
0>======tsensor params======
0>  is_trimmed       : 1
0>  underclocking_en : 1
0>===========end============
0>soc tsensor init done
0>========vrd info from cpld========
0>vrd_id | u64                | pmbus_en | avsbus_en | loop | pmbus_id | pmbus_addr | avs_sw | pmbus_sw | addr_9545 | domain_type | die_mask | reserved
0>  00   | 0x0003000300002b15 | 0x1      | 0x0       | 0x1  | 0x1      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x3         | 0x0300   | 0x0
0>  01   | 0x000001050000201b | 0x1      | 0x1       | 0x2  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0001   | 0x0
0>  02   | 0x0002000100002017 | 0x1      | 0x1       | 0x1  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0200   | 0x0
0>  03   | 0x0003000200002027 | 0x1      | 0x1       | 0x1  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x2         | 0x0300   | 0x0
0>  04   | 0x000002050000202b | 0x1      | 0x1       | 0x2  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0002   | 0x0
0>  05   | 0x0003000400002b19 | 0x1      | 0x0       | 0x2  | 0x1      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x4         | 0x0300   | 0x0
0>  06   | 0x0000000000000000 | 0x0      | 0x0       | 0x0  | 0x0      | 0x00       | 0x0    | 0x0      | 0x0       | 0x0         | 0x0000   | 0x0
0>================end===============
0>[ERR]0>vrd[6] info invalid, vrd_info = 0x0
0>default power domain data used
0>=============vrd info=============
0>power domain num: 6
0>power domain[00] id:2 | CORE_DVFS_TB       | PMBus NA | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
0>power domain[01] id:4 | IO_DVDD_NA         | PMBus NA | cap:0x3 | rail:1 | addr:0x20 | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
0>power domain[02] id:3 | UNCORE_DVFS        | PMBus NB | cap:0x3 | rail:0 | addr:0x20 | def_volt: 848 mV | min_volt: 750 mV | max_volt:1100 mV
0>power domain[03] id:5 | IO_DVDD_NB         | PMBus NB | cap:0x3 | rail:1 | addr:0x20 | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
0>power domain[04] id:1 | DDR_VDD            | PMBus NA | cap:0x1 | rail:0 | addr:0x2b | def_volt: 765 mV | min_volt: 650 mV | max_volt: 850 mV
0>power domain[05] id:6 | DDR_VDDQ           | PMBus NA | cap:0x1 | rail:1 | addr:0x2b | def_volt:1100 mV | min_volt:1000 mV | max_volt:1200 mV
0>================end===============
0>pmbus[0] init done
0>pmbus[1] init done
0>power domain[2] CORE_DVFS_TB       | NA PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
0>power domain[4] IO_DVDD_NA         | NA PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 800 mV | pmu:MP2882
0>power domain[3] UNCORE_DVFS        | NB PMBus/AVSBus | rail:0 | addr:0x20 | def_volt: 848 mV | pmu:MP2882
0>power domain[5] IO_DVDD_NB         | NB PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 800 mV | pmu:MP2882
0>power domain[1] DDR_VDD            | NA PMBus        | rail:0 | addr:0x2b | def_volt: 765 mV | pmu:MP2882
0>power domain[6] DDR_VDDQ           | NA PMBus        | rail:1 | addr:0x2b | def_volt:1100 mV | pmu:MP2882
0>power domain[2] CORE_DVFS_TB       is transferred to AVSBus mode
0>power domain[4] IO_DVDD_NA         is transferred to AVSBus mode
0>power domain[3] UNCORE_DVFS        is transferred to AVSBus mode
0>power domain[5] IO_DVDD_NB         is transferred to AVSBus mode
0>avsbus resync success
0>avsbus[0] init done
0>avsbus resync success
0>avsbus[1] init done
0>============volt boot============
0>power domain[2] volt = 1105 mV
0>power domain[4] volt =  806 mV
0>power domain[3] volt = 1003 mV
0>power domain[5] volt =  806 mV
0>power domain[1] volt =  767 mV
0>power domain[6] volt = 1103 mV
0>===============end===============
0>power domain[0] not exist
0>--w&h rd rail:0, 1105, CORE_DVFS_TB
0>--w&h rd rail:1, 800, CORE_DVFS_TB
0>power domain[2] set volt --> 1105 mV success
0>--w&h rd rail:0, 1005, UNCORE_DVFS
0>--w&h rd rail:1, 800, UNCORE_DVFS
0>power domain[3] set volt -->  851 mV success
0>============volt post============
0>power domain[2] volt = 1105 mV
0>power domain[4] volt =  802 mV
0>power domain[3] volt =  849 mV
0>power domain[5] volt =  802 mV
0>power domain[1] volt =  767 mV
0>power domain[6] volt = 1103 mV
0>===============end===============
0>Hboot1 Info RAW Dump: [0x91][0x00][0x00][0x14][0x01][0x00][0x01]
0>PowerSensorSupport[1], Cali[5120], Loss[7200]
0>Power Sensor Calibration Value[5120]!
0>the power sensor : manu id = 2peak, die id = TPA626
0>power sensor[0] init success
0>Totem[1] Core Boot Vol [1105]mv
0>Totem[1] Core Current Vol [1100]mv
0>NA 1620V1b0
0>NB 1620V1b0
0>GetCoreBaseFreq [2600000KHZ]
0>GetCoreTurboFreq [2600000KHZ]
0>GetCustomClusterNum [10]
0>Ipu ACG Training Done!
0>AP Last Time:[0.00.01.394]
0>wait UEFI pll init...
0>done
0>acg trim start
0>core trim freq:2000, avs:0 volt:810mv
0>core trim freq:2050, avs:1 volt:810mv
0>core trim freq:2100, avs:2 volt:810mv
0>core trim freq:2150, avs:3 volt:810mv
0>core trim freq:2200, avs:4 volt:810mv
0>core trim freq:2250, avs:5 volt:821mv
0>core trim freq:2300, avs:6 volt:833mv
0>core trim freq:2350, avs:7 volt:846mv
0>core trim freq:2400, avs:8 volt:859mv
0>core trim freq:2450, avs:9 volt:872mv
0>core trim freq:2500, avs:10 volt:885mv
0>core trim freq:2550, avs:11 volt:898mv
0>core trim freq:2600, avs:12 volt:911mv
0>core trim freq:2650, avs:13 volt:923mv
0>core trim freq:2700, avs:14 volt:936mv
0>core trim freq:2750, avs:15 volt:948mv
0>core trim freq:2800, avs:16 volt:961mv
0>core trim freq:2850, avs:17 volt:973mv
0>core trim freq:2900, avs:18 volt:986mv
0>core trim freq:2950, avs:19 volt:997mv
0>core trim freq:3000, avs:20 volt:1009mv
0>core trim freq:3050, avs:21 volt:1020mv
0>core trim freq:3100, avs:22 volt:1032mv
0>acg trim end
0>LDO disabled
0>[TracePoint] type[  0] cmd[  2] data[  3]
0>Interrupt 423 register OK
0>Interrupt 430 register OK
0>[TracePoint] type[  0] cmd[  2] data[  4]
0>
0>cpu 0 entering scheduler
0>[TracePoint] type[  0] cmd[  3] data[  1]
0>add your ipu app init here!
0>IpuInterfaceTaskStart Entry ...
0>ipu interface task wait parameters from uefi...
0>thermal soc task enabled
0>AP Last Time:[0.00.14.698]
0>ThermalDimmStart Entry ...
0>wait ddr init done...
0>power task start...
0>[TracePoint] type[  0] cmd[  3] data[  2]
0>ufs task wait parameters from uefi...
0>AmuTaskStart Entry ... 
0>amu task wait parameters from uefi...
0>ThermalSiwStart Entry ...
0>ThermalSiwTask idle...
0>DemtTaskStart Entry ...
0>[TracePoint] type[  0] cmd[  3] data[  3]
0>demt task wait parameters from uefi...
0>HiBoostTaskStart Entry ...
0>HiBoost task enabled
0>Waiting for UEFI parameters...
0>[TracePoint] type[  0] cmd[  3] data[  4]
0>AgeTaskStart Entry ...
0>[TracePoint] type[  0] cmd[  3] data[  5]
0>age task wait parameters from uefi...
0>uefi parameters ready!
0>UFSProfile[0]
0>PowerPolicy[2] BenchMarkSelection[0]
0>ipu interface task wait ddr init done from uefi...
0>ufs task parameters from uefi ready
0>uncore domain[1] freq:2500
0>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
0>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
0>======sioe status======
0>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
0>thermal soc task restore underclocking_en=1
0>ppu alert temp div init done
0>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
0>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
0>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
0>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
0>==========end==========
0>sioe init done
0>ufs task enabled
0>--> UFS profile[0]
0>UEFI parameters ready
0>UncoreMaxFreq Set to [2500 MHZ]
0>get TDP from efuse success, value = 185000mw
0>target power set to [185000]mw, brd:[185000]
0>demt task parameters from uefi ready
0>age task parameters from uefi ready
0>age task enabled
0>uefi ddr init finish!
0>ipu interface task wait uefi end done from uefi...
0>ddr init done, start thermal dimm task
0>======dimm status======
0>  chl[0] dimm0 0, dimm1 0
0>  chl[1] dimm0 0, dimm1 0
0>  chl[2] dimm0 2, dimm1 0
0>  chl[3] dimm0 0, dimm1 0
0>  chl[4] dimm0 0, dimm1 0
0>  chl[5] dimm0 0, dimm1 0
0>  chl[6] dimm0 0, dimm1 0
0>  chl[7] dimm0 0, dimm1 0
0>==========end==========
0>chl[2] registered, dimm mask = 0x1
0>=====dimm temp params=====
0>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
0>  is_thermal_thro_en  : 1
0>  is_aref_rate_auto   : 1
0>===========end============
0>chl[2] max_temp 33'C, aref_rate 0x5 --> 0x4
1>[TracePoint] type[  0] cmd[  1] data[  4]
1>
Board Info:
1>  chip version        : 0
1>  efuse pg cluster TB : 0x0
1>  ak mode             : 0
1>
1>[TracePoint] type[  0] cmd[  1] data[  5]
1>Voltage Type[3]
1>Core Vmin Formula:
1>Totem[1] Core 400MHZ Vol Changed From [790] mv to [810] mv
1>Totem[1] Core 400MHZ -> Vol[790] mv
1>Totem[1] Core 2000MHZ Vol Changed From [763] mv to [810] mv
1>Totem[1] Core 2000MHZ -> Vol[763] mv
1>Totem[1] Core 2300MHZ -> Vol[832] mv
1>Totem[1] Core 2600MHZ -> Vol[910] mv
1>Totem[1] Core 2900MHZ -> Vol[985] mv
1>Totem[1] Core 3100MHZ -> Vol[1031] mv
1>Uncore Vmin Formula:
1>Totem Uncore 400MHZ -> Vol[830] mv
1>Totem[1] Uncore 2000MHZ Vol Changed From [764] mv to [830] mv
1>Totem Uncore 2000MHZ -> Vol[764] mv
1>Totem[2] Uncore 2300MHZ Vol Changed From [814] mv to [830] mv
1>Totem Uncore 2300MHZ -> Vol[814] mv
1>Totem Uncore 2500MHZ -> Vol[846] mv
1>Totem Uncore 2700MHZ -> Vol[889] mv
1>Totem Uncore 2900MHZ -> Vol[930] mv
1>Core VF curve:
1>[ 400]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[ 450]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[ 500]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[ 550]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[ 600]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[ 650]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[ 700]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[ 750]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[ 800]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[ 850]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[ 900]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[ 950]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1000]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1050]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1100]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1150]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1200]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1250]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1300]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1350]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1400]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1450]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1500]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1550]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1600]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1650]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1700]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1750]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1800]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1850]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1900]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[1950]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[2000]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[2050]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[2100]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[2150]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[2200]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[2250]MHZ -> Vol TA[ 810]mv TB[ 820]mv
1>[2300]MHZ -> Vol TA[ 810]mv TB[ 832]mv
1>[2350]MHZ -> Vol TA[ 810]mv TB[ 845]mv
1>[2400]MHZ -> Vol TA[ 810]mv TB[ 858]mv
1>[2450]MHZ -> Vol TA[ 810]mv TB[ 871]mv
1>[2500]MHZ -> Vol TA[ 810]mv TB[ 884]mv
1>[2550]MHZ -> Vol TA[ 810]mv TB[ 897]mv
1>[2600]MHZ -> Vol TA[ 810]mv TB[ 910]mv
1>[2650]MHZ -> Vol TA[ 810]mv TB[ 922]mv
1>[2700]MHZ -> Vol TA[ 810]mv TB[ 935]mv
1>[2750]MHZ -> Vol TA[ 810]mv TB[ 947]mv
1>[2800]MHZ -> Vol TA[ 810]mv TB[ 960]mv
1>[2850]MHZ -> Vol TA[ 810]mv TB[ 972]mv
1>[2900]MHZ -> Vol TA[ 810]mv TB[ 985]mv
1>[2950]MHZ -> Vol TA[ 810]mv TB[ 996]mv
1>[3000]MHZ -> Vol TA[ 810]mv TB[1008]mv
1>[3050]MHZ -> Vol TA[ 810]mv TB[1019]mv
1>[3100]MHZ -> Vol TA[ 810]mv TB[1031]mv
1>Uncore VF curve:
1>Uncore [   0]MHZ -> Vol [ 830]mv
1>Uncore [ 100]MHZ -> Vol [ 830]mv
1>Uncore [ 200]MHZ -> Vol [ 830]mv
1>Uncore [ 300]MHZ -> Vol [ 830]mv
1>Uncore [ 400]MHZ -> Vol [ 830]mv
1>Uncore [ 500]MHZ -> Vol [ 830]mv
1>Uncore [ 600]MHZ -> Vol [ 830]mv
1>Uncore [ 700]MHZ -> Vol [ 830]mv
1>Uncore [ 800]MHZ -> Vol [ 830]mv
1>Uncore [ 900]MHZ -> Vol [ 830]mv
1>Uncore [1000]MHZ -> Vol [ 830]mv
1>Uncore [1100]MHZ -> Vol [ 830]mv
1>Uncore [1200]MHZ -> Vol [ 830]mv
1>Uncore [1300]MHZ -> Vol [ 830]mv
1>Uncore [1400]MHZ -> Vol [ 830]mv
1>Uncore [1500]MHZ -> Vol [ 830]mv
1>Uncore [1600]MHZ -> Vol [ 830]mv
1>Uncore [1700]MHZ -> Vol [ 830]mv
1>Uncore [1800]MHZ -> Vol [ 830]mv
1>Uncore [1900]MHZ -> Vol [ 830]mv
1>Uncore [2000]MHZ -> Vol [ 830]mv
1>Uncore [2100]MHZ -> Vol [ 830]mv
1>Uncore [2200]MHZ -> Vol [ 830]mv
1>Uncore [2300]MHZ -> Vol [ 830]mv
1>Uncore [2400]MHZ -> Vol [ 830]mv
1>Uncore [2500]MHZ -> Vol [ 846]mv
1>Uncore [2600]MHZ -> Vol [ 867]mv
1>Uncore [2700]MHZ -> Vol [ 889]mv
1>Uncore [2800]MHZ -> Vol [ 909]mv
1>Uncore [2900]MHZ -> Vol [ 930]mv
1>Uncore [3000]MHZ -> Vol [1100]mv
1>[TracePoint] type[  0] cmd[  1] data[  6]
1>[TracePoint] type[  0] cmd[  1] data[  7]
1>
********Hello Huawei LiteOS********

KpxxxxIPU Firmware Version : VX.X.X
LiteOS Kernel Version : 5.7.0
1>Run on ChipVersion[0] Node[1] Die[0]
1>build time : Oct 27 2025 20:30:00

1>**********************************
1>
main core booting up...
1>start set affinity
1>
mpidr = 0x81040000
1>sram ecc state: 0x0, sram ecc cnt: 0x0
1>[TracePoint] type[  0] cmd[  2] data[  1]
1>[TracePoint] type[  0] cmd[  2] data[  2]
1>LRDXSD_LOCK_OFFSET = 0x0
1>LRDXSD_ERRIMSK_OFFSET = 0x0
1>LRDXSD_DBG_OTIMSK_OFFSET = 0x0
1>LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
1>LRDXSD_DBG_EN_OFFSET = 0x1
1>======tsensor params======
1>  is_trimmed       : 1
1>  underclocking_en : 1
1>===========end============
1>soc tsensor init done
1>========vrd info from cpld========
1>vrd_id | u64                | pmbus_en | avsbus_en | loop | pmbus_id | pmbus_addr | avs_sw | pmbus_sw | addr_9545 | domain_type | die_mask | reserved
1>  00   | 0x0003000300002b15 | 0x1      | 0x0       | 0x1  | 0x1      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x3         | 0x0300   | 0x0
1>  01   | 0x000001050000201b | 0x1      | 0x1       | 0x2  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0001   | 0x0
1>  02   | 0x0002000100002017 | 0x1      | 0x1       | 0x1  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0200   | 0x0
1>  03   | 0x0003000200002027 | 0x1      | 0x1       | 0x1  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x2         | 0x0300   | 0x0
1>  04   | 0x000002050000202b | 0x1      | 0x1       | 0x2  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0002   | 0x0
1>  05   | 0x0003000400002b19 | 0x1      | 0x0       | 0x2  | 0x1      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x4         | 0x0300   | 0x0
1>  06   | 0x0000000000000000 | 0x0      | 0x0       | 0x0  | 0x0      | 0x00       | 0x0    | 0x0      | 0x0       | 0x0         | 0x0000   | 0x0
1>================end===============
1>[ERR]1>vrd[6] info invalid, vrd_info = 0x0
1>default power domain data used
1>=============vrd info=============
1>power domain num: 6
1>power domain[00] id:2 | CORE_DVFS_TB       | PMBus NA | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
1>power domain[01] id:4 | IO_DVDD_NA         | PMBus NA | cap:0x3 | rail:1 | addr:0x20 | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
1>power domain[02] id:3 | UNCORE_DVFS        | PMBus NB | cap:0x3 | rail:0 | addr:0x20 | def_volt: 846 mV | min_volt: 750 mV | max_volt:1100 mV
1>power domain[03] id:5 | IO_DVDD_NB         | PMBus NB | cap:0x3 | rail:1 | addr:0x20 | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
1>power domain[04] id:1 | DDR_VDD            | PMBus NA | cap:0x1 | rail:0 | addr:0x2b | def_volt: 765 mV | min_volt: 650 mV | max_volt: 850 mV
1>power domain[05] id:6 | DDR_VDDQ           | PMBus NA | cap:0x1 | rail:1 | addr:0x2b | def_volt:1100 mV | min_volt:1000 mV | max_volt:1200 mV
1>================end===============
1>pmbus[0] init done
1>pmbus[1] init done
1>power domain[2] CORE_DVFS_TB       | NA PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
1>power domain[4] IO_DVDD_NA         | NA PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 800 mV | pmu:MP2882
1>power domain[3] UNCORE_DVFS        | NB PMBus/AVSBus | rail:0 | addr:0x20 | def_volt: 846 mV | pmu:MP2882
1>power domain[5] IO_DVDD_NB         | NB PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 800 mV | pmu:MP2882
1>power domain[1] DDR_VDD            | NA PMBus        | rail:0 | addr:0x2b | def_volt: 765 mV | pmu:MP2882
1>power domain[6] DDR_VDDQ           | NA PMBus        | rail:1 | addr:0x2b | def_volt:1100 mV | pmu:MP2882
1>power domain[2] CORE_DVFS_TB       is transferred to AVSBus mode
1>power domain[4] IO_DVDD_NA         is transferred to AVSBus mode
1>power domain[3] UNCORE_DVFS        is transferred to AVSBus mode
1>power domain[5] IO_DVDD_NB         is transferred to AVSBus mode
1>avsbus resync success
1>avsbus[0] init done
1>avsbus resync success
1>avsbus[1] init done
1>============volt boot============
1>power domain[2] volt = 1099 mV
1>power domain[4] volt =  804 mV
1>power domain[3] volt = 1007 mV
1>power domain[5] volt =  804 mV
1>power domain[1] volt =  769 mV
1>power domain[6] volt = 1103 mV
1>===============end===============
1>power domain[0] not exist
1>--w&h rd rail:0, 1101, CORE_DVFS_TB
1>--w&h rd rail:1, 800, CORE_DVFS_TB
1>power domain[2] set volt --> 1101 mV success
1>--w&h rd rail:0, 1007, UNCORE_DVFS
1>--w&h rd rail:1, 800, UNCORE_DVFS
1>power domain[3] set volt -->  851 mV success
1>============volt post============
1>power domain[2] volt = 1101 mV
1>power domain[4] volt =  804 mV
1>power domain[3] volt =  851 mV
1>power domain[5] volt =  802 mV
1>power domain[1] volt =  769 mV
1>power domain[6] volt = 1103 mV
1>===============end===============
1>Hboot1 Info RAW Dump: [0x01][0x00][0x00][0x14][0x01][0x00][0x01]
1>PowerSensorSupport[1], Cali[5120], Loss[0]
1>Power Sensor Calibration Value[5120]!
1>the power sensor : manu id = 2peak, die id = TPA626
1>power sensor[0] init success
1>Totem[1] Core Boot Vol [1101]mv
1>Totem[1] Core Current Vol [1100]mv
1>NA 1620V1b0
1>NB 1620V1b0
1>GetCoreBaseFreq [2600000KHZ]
1>GetCoreTurboFreq [2600000KHZ]
1>GetCustomClusterNum [10]
1>Ipu ACG Training Done!
1>AP Last Time:[0.00.01.393]
1>wait UEFI pll init...
1>done
1>acg trim start
1>core trim freq:2000, avs:0 volt:810mv
1>core trim freq:2050, avs:1 volt:810mv
1>core trim freq:2100, avs:2 volt:810mv
1>core trim freq:2150, avs:3 volt:810mv
1>core trim freq:2200, avs:4 volt:810mv
1>core trim freq:2250, avs:5 volt:820mv
1>core trim freq:2300, avs:6 volt:832mv
1>core trim freq:2350, avs:7 volt:845mv
1>core trim freq:2400, avs:8 volt:858mv
1>core trim freq:2450, avs:9 volt:871mv
1>core trim freq:2500, avs:10 volt:884mv
1>core trim freq:2550, avs:11 volt:897mv
1>core trim freq:2600, avs:12 volt:910mv
1>core trim freq:2650, avs:13 volt:922mv
1>core trim freq:2700, avs:14 volt:935mv
1>core trim freq:2750, avs:15 volt:947mv
1>core trim freq:2800, avs:16 volt:960mv
1>core trim freq:2850, avs:17 volt:972mv
1>core trim freq:2900, avs:18 volt:985mv
1>core trim freq:2950, avs:19 volt:996mv
1>core trim freq:3000, avs:20 volt:1008mv
1>core trim freq:3050, avs:21 volt:1019mv
1>core trim freq:3100, avs:22 volt:1031mv
1>acg trim end
1>LDO disabled
1>[TracePoint] type[  0] cmd[  2] data[  3]
1>Interrupt 423 register OK
1>Interrupt 430 register OK
1>[TracePoint] type[  0] cmd[  2] data[  4]
1>
1>cpu 0 entering scheduler
1>[TracePoint] type[  0] cmd[  3] data[  1]
1>add your ipu app init here!
1>IpuInterfaceTaskStart Entry ...
1>ipu interface task wait parameters from uefi...
1>thermal soc task enabled
1>AP Last Time:[0.00.14.851]
1>ThermalDimmStart Entry ...
1>wait ddr init done...
1>power task start...
1>[TracePoint] type[  0] cmd[  3] data[  2]
1>ufs task wait parameters from uefi...
1>AmuTaskStart Entry ... 
1>amu task wait parameters from uefi...
1>ThermalSiwStart Entry ...
1>ThermalSiwTask idle...
1>DemtTaskStart Entry ...
1>[TracePoint] type[  0] cmd[  3] data[  3]
1>demt task wait parameters from uefi...
1>HiBoostTaskStart Entry ...
1>HiBoost task enabled
1>Waiting for UEFI parameters...
1>[TracePoint] type[  0] cmd[  3] data[  4]
1>AgeTaskStart Entry ...
1>[TracePoint] type[  0] cmd[  3] data[  5]
1>age task wait parameters from uefi...
1>uefi parameters ready!
1>UFSProfile[0]
1>PowerPolicy[2] BenchMarkSelection[0]
1>ipu interface task wait ddr init done from uefi...
1>ufs task parameters from uefi ready
1>uncore domain[1] freq:2500
1>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
1>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
1>======sioe status======
1>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
1>thermal soc task restore underclocking_en=1
1>ppu alert temp div init done
1>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
1>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
1>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
1>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
1>==========end==========
1>sioe init done
1>ufs task enabled
1>--> UFS profile[0]
1>UEFI parameters ready
1>UncoreMaxFreq Set to [2500 MHZ]
1>get TDP from efuse success, value = 185000mw
1>target power set to [185000]mw, brd:[185000]
1>demt task parameters from uefi ready
1>age task parameters from uefi ready
1>age task enabled
1>uefi ddr init finish!
1>ipu interface task wait uefi end done from uefi...
1>ddr init done, start thermal dimm task
1>======dimm status======
1>  chl[0] dimm0 0, dimm1 0
1>  chl[1] dimm0 0, dimm1 0
1>  chl[2] dimm0 2, dimm1 0
1>  chl[3] dimm0 0, dimm1 0
1>  chl[4] dimm0 0, dimm1 0
1>  chl[5] dimm0 0, dimm1 0
1>  chl[6] dimm0 0, dimm1 0
1>  chl[7] dimm0 0, dimm1 0
1>==========end==========
1>chl[2] registered, dimm mask = 0x1
1>=====dimm temp params=====
1>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
1>  is_thermal_thro_en  : 1
1>  is_aref_rate_auto   : 1
1>===========end============
1>chl[2] max_temp 34'C, aref_rate 0x5 --> 0x4


HSM_LOG:
[00:00:00.010][info] os_mem_system_init default pool done
[00:00:00.016][info] succeed to do thirdparty otpc_pabuk init
[00:00

0>uefi end finish!
0>ipu interface task exit!
0>amu task parameters from uefi ready
1>uefi end finish!
1>ipu interface task exit!
1>amu task parameters from uefi ready
Enter current value process


HSM_LOG:
:00.017][info] succeed to do thirdparty boot_profile_driver init
[00:00:00.017][info] succeed to do thirdparty measure_value_ma



HSM_LOG:
nage_driver init
[00:00:00.018][info] succeed to do thirdparty period_driver init
[00:00:00.018][info]  start loading internal



HSM_LOG:
 task ...
[00:00:00.018][info]  task name is ccm_task
[00:00:00.019][info]  hm_dynamic_loadelf successfully!
[00:00:00.019][i



HSM_LOG:
nfo] internal task[1] task_name=ccm_task load successfully
[00:00:00.020][info]  task name is upgrade_task
[00:00:00.020][info



HSM_LOG:
]  hm_dynamic_loadelf successfully!
[00:00:00.021][info] internal task[2] task_name=upgrade_task load successfully
[00:00:00.0



HSM_LOG:
22][info]  task name is hes_task
[00:00:00.022][info]  hm_dynamic_loadelf successfully!
[00:00:00.023][info] internal task[3] 



HSM_LOG:
task_name=hes_task load successfully
[00:00:00.024][info] created task ccm_task success!
[00:00:00.025][info] created task upg



HSM_LOG:
rade_task success!
[00:00:00.026][info] created task hes_task success!
[00:00:00.026][info] Init start.
[1970-01-01 00:00:00.



HSM_LOG:
027][HSM][INFO][54] Platform init 0x20250523 0x4e.

[1970-01-01 00:00:00.027][HSM][INFO][197] ccm start.

[1970-01-01 00:00:00



HSM_LOG:
.028][HSM][INFO][86] upgrade task init success.

[1970-01-01 00:00:00.028][HSM][INFO][95] upgrade recv cmd, 0x181.

[1970-01-0



HSM_LOG:
1 00:00:00.029][HSM][INFO][103] upgrade res, 0x3a5aa5a3.

[1970-01-01 00:00:00.030][HSM][INFO][75] hes tee_task_entry.

[1970-



HSM_LOG:
01-01 00:00:00.553][HSM][INFO][44] hes init success.

[00:00:00.553][info] Init over.


0>amu task activated
0>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
1>amu task activated
1>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
[0.06.48.423]IpmiCmdReportPcieMMIO start
[0.06.54.829]ext0 int trigger
[0.06.54.899]slot: 7, slotCtrl = 0x811f8
[0.06.55.076]ext0 int trigger
[0.06.59.261]IpmiCmdReportPcieMMIO end
pool addr          pool size    used size     free size    max free node size   used node num     free node num      UsageWaterLine
---------------    --------     -------       --------     --------------       -------------      ------------      ------------
0x8409090488       0x1e740      0x19dd0       0x4700       0x30b0               0x90               0x3                0x1b690        
[0.06.59.301]slot[7] port:22 begin to power OFF.
[0.13.42.427]ext0 int trigger
[0.13.42.469]slot: 6, slotCtrl = 0x4817f8
[0.13.42.619]slot[6] port:20 begin to power ON.
[0.13.44.427]ext0 int trigger
[0.13.44.469]slot: 6, slotCtrl = 0x812f8
[0.13.44.497]slot[6] port:20 begin to power OFF.
[0.13.44.591]ext0 int trigger
[0.13.45.827]ext0 int trigger
[0.13.45.869]slot: 6, slotCtrl = 0x481778
[0.13.45.942]slot[6] port:20 begin to power ON.
[0.13.46.685]Receive ras int[465]
First coalesce handler start
Type2 status = 0x0
Type1 status = 0x4000
Found error node[14]
Secondary coalesce handler start
Type2 status = 0x0
Type1 status = 0x4
Found error node[2]
-- RAS DUMP --
PCIE AER ERROR
Error severity is RECOVERABLE[8101000000]
PortType[4] PCIeInfo[56:00:00]
VendorId[0x19e5] DeviceId[0xa120]
AER_CAP_HEADER    = 0x0000000031020001
UNCR_ERR_STATUS   = 0x0000000000004000
UNCR_ERR_MASK     = 0x0000000004580000
UNCR_ERR_SEVERITY = 0x0000000000462030
COR_ERR_STATUS    = 0x0000000000000000
COR_ERR_MASK      = 0x000000000000e000
AER_CAP_HEADER    = 0x00000000000010ae
OemErrorLogReport
report to os
Type0 status = 0x0
Type0 status = 0x0
ras int[465] end

[0.13.46.748]slot[6] port:20 begin to power OFF.
[0.13.46.827]ext0 int trigger
[0.13.46.869]slot: 6, slotCtrl = 0x815f8
[0.13.49.427]ext0 int trigger
[0.13.49.469]slot: 6, slotCtrl = 0x4817f8
[0.13.49.592]slot[6] port:20 begin to power ON.
[0.13.51.464]slot[6] port:20 begin to power OFF.
[0.13.51.627]ext0 int trigger
[0.13.51.671]slot: 6, slotCtrl = 0x815f8
[0.13.51.793]ext0 int trigger
[0.18.38.628]ext0 int trigger
[0.18.38.749]slot: 20, slotCtrl = 0x4817f8
[0.18.38.792]ext0 int trigger
[0.18.38.861]slot[20] port:32 begin to power ON.
[0.18.40.187]Receive ras int[491]
First coalesce handler start
Type2 status = 0x0
Type1 status = 0x0
Type0 status = 0x2
Found error node[1]
OemErrorLogReport
DpcCap0X08 = 0x1f00
coreIndex = 0xb, dpcFlag = 0x0
not report to os
-- RAS DUMP --
Node[1] Nimbus[0] Module[PCIE] Submodule[3] Device[2] Port[0] ErrorType[0x3301] 
Error severity is CORRECTED[208303000000]
ERR_MISC_00 = 0x00041a08
ERR_MISC_01 = 0x00000000
ERR_MISC_02 = 0x00000000
ERR_MISC_03 = 0x00000000
ERR_MISC_04 = 0x02492494
ERR_MISC_05 = 0x00000000
ERR_MISC_06 = 0x00000000
ERR_MISC_07 = 0x00000000
ERR_MISC_08 = 0x00000000
ERR_MISC_09 = 0x00000000
ERR_MISC_10 = 0x00000000
ERR_MISC_11 = 0x00000011
ERR_MISC_12 = 0x00000000
ERR_MISC_13 = 0x00000000
ERR_MISC_14 = 0x00000001
ras int[491] end

[0.18.40.250]ext0 int trigger
[0.18.40.392]slot: 20, slotCtrl = 0x815f8
[0.18.40.424]slot[20] port:32 begin to power OFF.
[0.18.42.428]ext0 int trigger
[0.18.42.549]slot: 20, slotCtrl = 0x4817f8
[0.18.42.661]slot[20] port:32 begin to power ON.
Add ep: bdf=d600 eid=b epCnt=1 eid_alloc=c
[0.44.12.624]ext0 int trigger
[0.44.12.745]slot: 20, slotCtrl = 0x811f8
[0.44.12.788]ext0 int trigger
[0.44.12.800]slot[20] port:32 begin to power OFF.
[0.44.17.024]ext0 int trigger
[0.44.17.105]slot: 13, slotCtrl = 0x4817f8
[0.44.17.123]slot[13] port:2 begin to power ON.
[0.44.17.194]ext0 int trigger
Add ep: bdf=8200 eid=c epCnt=1 eid_alloc=d
[0.48.57.724]ext0 int trigger
[0.48.57.806]slot: 13, slotCtrl = 0x815f8
[0.48.57.808]slot[13] port:2 begin to power OFF.
[0.49.05.624]ext0 int trigger
[0.49.05.751]slot: 21, slotCtrl = 0x4817f8
[0.49.05.836]slot[21] port:34 begin to power ON.
Add ep: bdf=d700 eid=d epCnt=2 eid_alloc=e
[1.08.23.721]ext0 int trigger
[1.08.23.870]slot: 21, slotCtrl = 0x815f8
[1.08.24.017]slot[21] port:34 begin to power OFF.
[1.08.30.319]ext0 int trigger
[1.08.30.429]slot: 18, slotCtrl = 0x4817f8
[1.08.30.536]slot[18] port:24 begin to power ON.
Add ep: bdf=c100 eid=e epCnt=1 eid_alloc=f
[1.14.25.718]ext0 int trigger
[1.14.25.827]slot: 18, slotCtrl = 0x811f8
[1.14.25.881]ext0 int trigger
[1.14.25.955]slot[18] port:24 begin to power OFF.
[1.14.30.119]ext0 int trigger
[1.14.30.262]slot: 19, slotCtrl = 0x4817f8
[1.14.30.338]slot[19] port:26 begin to power ON.
Add ep: bdf=c200 eid=f epCnt=2 eid_alloc=10
[1.18.27.217]Receive ras int[491]
First coalesce handler start
Type2 status = 0x0
Type1 status = 0x0
Type0 status = 0x4000
Found error node[14]
Secondary coalesce handler start
Type2 status = 0x0
Type1 status = 0x0
Type0 status = 0x4
Found error node[2]
OemErrorLogReport
DpcCap0X08 = 0x1f00
coreIndex = 0x9, dpcFlag = 0x0
not report to os
-- RAS DUMP --
Node[1] Nimbus[0] Module[PCIE] Submodule[3] Device[0] Port[12] ErrorType[0x3301] 
Error severity is CORRECTED[208101000000]
ERR_MISC_00 = 0x00041a08
ERR_MISC_01 = 0x00000000
ERR_MISC_02 = 0x00000000
ERR_MISC_03 = 0x00000000
ERR_MISC_04 = 0x02492494
ERR_MISC_05 = 0x00000003
ERR_MISC_06 = 0x00000000
ERR_MISC_07 = 0x00000000
ERR_MISC_08 = 0x00000000
ERR_MISC_09 = 0x00000000
ERR_MISC_10 = 0x00000000
ERR_MISC_11 = 0x00000000
ERR_MISC_12 = 0x00000000
ERR_MISC_13 = 0x00000000
ERR_MISC_14 = 0x00000001
ras int[491] end

[1.18.27.319]ext0 int trigger
[1.18.27.434]slot[19] port:26 begin to power OFF.
[1.18.27.436]slot: 19, slotCtrl = 0x815f8
[1.18.27.488]ext0 int trigger
[1.18.30.821]ext0 int trigger
[1.18.30.919]slot: 16, slotCtrl = 0x4817f8
[1.18.31.009]slot[16] port:16 begin to power ON.
Add ep: bdf=ad00 eid=10 epCnt=1 eid_alloc=11
[1.31.47.119]ext0 int trigger
[1.31.47.217]slot: 16, slotCtrl = 0x815f8
[1.31.47.323]slot[16] port:16 begin to power OFF.
[1.31.52.820]ext0 int trigger
[1.31.52.924]slot: 17, slotCtrl = 0x4817f8
[1.31.52.984]ext0 int trigger
[1.31.53.089]slot[17] port:18 begin to power ON.
Add ep: bdf=ae00 eid=11 epCnt=2 eid_alloc=12
[1.36.40.619]ext0 int trigger
[1.36.40.724]slot: 17, slotCtrl = 0x815f8
[1.36.40.815]slot[17] port:18 begin to power OFF.
[1.36.45.717]ext0 int trigger
[1.36.45.804]slot: 14, slotCtrl = 0x4817f8
[1.36.45.882]ext0 int trigger
[1.36.45.927]slot[14] port:12 begin to power ON.
Add ep: bdf=ab00 eid=12 epCnt=3 eid_alloc=13
[1.41.31.951]Receive ras int[478]
First coalesce handler start
Type2 status = 0x0
Type1 status = 0x0
Type0 status = 0x2
Found error node[1]
OemErrorLogReport
DpcCap0X08 = 0x1f00
coreIndex = 0x8, dpcFlag = 0x0
not report to os
-- RAS DUMP --
Node[1] Nimbus[1] Module[PCIE] Submodule[3] Device[2] Port[0] ErrorType[0x3301] 
Error severity is CORRECTED[200303000000]
ERR_MISC_00 = 0x00061a08
ERR_MISC_01 = 0x00000000
ERR_MISC_02 = 0x00000000
ERR_MISC_03 = 0x00000000
ERR_MISC_04 = 0x02492490
ERR_MISC_05 = 0x00000001
ERR_MISC_06 = 0x00000000
ERR_MISC_07 = 0x00000000
ERR_MISC_08 = 0x00000000
ERR_MISC_09 = 0x00000000
ERR_MISC_10 = 0x00000000
ERR_MISC_11 = 0x00000011
ERR_MISC_12 = 0x00000000
ERR_MISC_13 = 0x00000000
ERR_MISC_14 = 0x00000001
ras int[478] end

[1.41.32.054]ext0 int trigger
[1.41.32.147]slot[14] port:12 begin to power OFF.
[1.41.32.153]slot: 14, slotCtrl = 0x815f8
[1.41.32.239]ext0 int trigger
[1.41.39.417]ext0 int trigger
[1.41.39.512]slot: 15, slotCtrl = 0x4817f8
[1.41.39.583]ext0 int trigger
[1.41.39.634]slot[15] port:14 begin to power ON.
Add ep: bdf=ac00 eid=13 epCnt=4 eid_alloc=14
[1.47.03.242]Receive ras int[478]
First coalesce handler start
Type2 status = 0x0
Type1 status = 0x0
Type0 status = 0x2
Found error node[1]
OemErrorLogReport
DpcCap0X08 = 0x1f00
coreIndex = 0x8, dpcFlag = 0x0
not report to os
-- RAS DUMP --
Node[1] Nimbus[1] Module[PCIE] Submodule[3] Device[2] Port[4] ErrorType[0x3301] 
Error severity is CORRECTED[200303000000]
ERR_MISC_00 = 0x00041a08
ERR_MISC_01 = 0x00000000
ERR_MISC_02 = 0x00000000
ERR_MISC_03 = 0x00000000
ERR_MISC_04 = 0x02492494
ERR_MISC_05 = 0x00000004
ERR_MISC_06 = 0x00000000
ERR_MISC_07 = 0x00000000
ERR_MISC_08 = 0x00000000
ERR_MISC_09 = 0x00000000
ERR_MISC_10 = 0x00000000
ERR_MISC_11 = 0x00000000
ERR_MISC_12 = 0x00000000
ERR_MISC_13 = 0x00000000
ERR_MISC_14 = 0x00000001
ce or nfe error happen, but interval time over 60 second, so recount again.
ras int[478] end

[1.47.03.316]ext0 int trigger
[1.47.03.411]slot: 15, slotCtrl = 0x811f8
[1.47.03.521]slot[15] port:14 begin to power OFF.
[1.47.10.214]ext0 int trigger
[1.47.10.234]slot: 2, slotCtrl = 0x4817f8
[1.47.10.344]slot[2] port:12 begin to power ON.
[1.47.10.392]ext0 int trigger
Add ep: bdf=4100 eid=14 epCnt=1 eid_alloc=15
[1.57.33.212]ext0 int trigger
[1.57.33.231]slot: 2, slotCtrl = 0x811f8
[1.57.33.388]ext0 int trigger
[1.57.33.420]slot[2] port:12 begin to power OFF.
[1.57.38.513]ext0 int trigger
[1.57.38.538]slot: 3, slotCtrl = 0x4817f8
[1.57.38.707]slot[3] port:14 begin to power ON.
Add ep: bdf=4200 eid=15 epCnt=2 eid_alloc=16
[2.10.21.411]ext0 int trigger
[2.10.21.436]slot: 3, slotCtrl = 0x811f8
[2.10.21.541]slot[3] port:14 begin to power OFF.
[2.10.26.812]ext0 int trigger
[2.10.26.842]slot: 4, slotCtrl = 0x4817f8
[2.10.26.932]slot[4] port:16 begin to power ON.
Add ep: bdf=4300 eid=16 epCnt=3 eid_alloc=17
[2.15.27.611]ext0 int trigger
[2.15.27.641]slot: 4, slotCtrl = 0x811f8
[2.15.27.765]slot[4] port:16 begin to power OFF.
[2.15.27.779]ext0 int trigger
[2.15.34.412]ext0 int trigger
[2.15.34.448]slot: 5, slotCtrl = 0x4817f8
[2.15.34.580]slot[5] port:18 begin to power ON.
Add ep: bdf=4400 eid=17 epCnt=4 eid_alloc=18
[2.32.04.010]ext0 int trigger
[2.32.04.046]slot: 5, slotCtrl = 0x811f8
[2.32.04.200]slot[5] port:18 begin to power OFF.
[2.32.10.407]ext0 int trigger
[2.32.10.415]slot: 0, slotCtrl = 0x4817f8
[2.32.10.466]slot[0] port:4 begin to power ON.
Add ep: bdf=600 eid=18 epCnt=2 eid_alloc=19
[2.38.24.506]ext0 int trigger
[2.38.24.514]slot: 0, slotCtrl = 0x811f8
[2.38.24.648]slot[0] port:4 begin to power OFF.
[2.38.24.674]ext0 int trigger
[2.38.30.907]ext0 int trigger
[2.38.30.920]slot: 1, slotCtrl = 0x4817f8
[2.38.31.057]slot[1] port:6 begin to power ON.
Add ep: bdf=700 eid=19 epCnt=3 eid_alloc=1a
[2.43.38.466]Receive ras int[452]
First coalesce handler start
Type2 status = 0x0
Type1 status = 0x0
Type0 status = 0x4000
Found error node[14]
Secondary coalesce handler start
Type2 status = 0x0
Type1 status = 0x0
Type0 status = 0x4
Found error node[2]
OemErrorLogReport
DpcCap0X08 = 0x1f00
coreIndex = 0x0, dpcFlag = 0x0
not report to os
-- RAS DUMP --
Node[0] Nimbus[1] Module[PCIE] Submodule[3] Device[0] Port[12] ErrorType[0x3301] 
Error severity is CORRECTED[101000000]
ERR_MISC_00 = 0x00041a08
ERR_MISC_01 = 0x00000000
ERR_MISC_02 = 0x00000000
ERR_MISC_03 = 0x00000000
ERR_MISC_04 = 0x02492494
ERR_MISC_05 = 0x00000001
ERR_MISC_06 = 0x00000000
ERR_MISC_07 = 0x00000000
ERR_MISC_08 = 0x00000000
ERR_MISC_09 = 0x00000000
ERR_MISC_10 = 0x00000000
ERR_MISC_11 = 0x00000000
ERR_MISC_12 = 0x00000000
ERR_MISC_13 = 0x00000000
ERR_MISC_14 = 0x00000001
ras int[452] end

[2.43.38.539]ext0 int trigger
[2.43.38.559]slot: 1, slotCtrl = 0x811f8
[2.43.38.664]slot[1] port:6 begin to power OFF.
[2.43.38.713]ext0 int trigger
[2.43.44.506]ext0 int trigger
[2.43.44.570]slot: 10, slotCtrl = 0x4817f8
[2.43.44.670]ext0 int trigger
[2.43.44.711]slot[10] port:32 begin to power ON.
Add ep: bdf=6000 eid=1a epCnt=1 eid_alloc=1b
[2.50.24.705]ext0 int trigger
[2.50.24.734]slot[10] port:32 begin to power OFF.
[2.50.24.771]slot: 10, slotCtrl = 0x815f8
[2.50.31.006]ext0 int trigger
[2.50.31.076]slot: 11, slotCtrl = 0x4817f8
[2.50.31.084]slot[11] port:34 begin to power ON.
[2.50.31.177]ext0 int trigger
Add ep: bdf=6100 eid=1b epCnt=2 eid_alloc=1c
[2.55.41.605]ext0 int trigger
[2.55.41.685]slot: 11, slotCtrl = 0x815f8
[2.55.41.778]slot[11] port:34 begin to power OFF.
[2.55.48.907]ext0 int trigger
[2.55.48.960]slot: 8, slotCtrl = 0x4817f8
[2.55.49.076]ext0 int trigger
[2.55.49.178]slot[8] port:24 begin to power ON.
Add ep: bdf=5900 eid=1c epCnt=2 eid_alloc=1d
[2.59.28.667]Receive ras int[465]
First coalesce handler start
Type2 status = 0x0
Type1 status = 0x0
Type0 status = 0x4000
Found error node[14]
Secondary coalesce handler start
Type2 status = 0x0
Type1 status = 0x0
Type0 status = 0x4
Found error node[2]
OemErrorLogReport
DpcCap0X08 = 0x1f00
coreIndex = 0x3, dpcFlag = 0x0
not report to os
-- RAS DUMP --
Node[0] Nimbus[0] Module[PCIE] Submodule[3] Device[0] Port[8] ErrorType[0x3301] 
Error severity is CORRECTED[8101000000]
ERR_MISC_00 = 0x00041a08
ERR_MISC_01 = 0x00000000
ERR_MISC_02 = 0x00000000
ERR_MISC_03 = 0x00000000
ERR_MISC_04 = 0x02492494
ERR_MISC_05 = 0x00000004
ERR_MISC_06 = 0x00000000
ERR_MISC_07 = 0x00000000
ERR_MISC_08 = 0x00000000
ERR_MISC_09 = 0x00000000
ERR_MISC_10 = 0x00000000
ERR_MISC_11 = 0x00000000
ERR_MISC_12 = 0x00000000
ERR_MISC_13 = 0x00000000
ERR_MISC_14 = 0x00000001
ras int[465] end

[2.59.28.741]ext0 int trigger
[2.59.28.804]slot: 8, slotCtrl = 0x811f8
[2.59.28.921]ext0 int trigger
[2.59.28.964]slot[8] port:24 begin to power OFF.
[2.59.33.807]ext0 int trigger
[2.59.33.867]slot: 9, slotCtrl = 0x4817f8
[2.59.33.881]slot[9] port:26 begin to power ON.
[2.59.33.978]ext0 int trigger
Add ep: bdf=5a00 eid=1d epCnt=3 eid_alloc=1e
[3.05.24.406]ext0 int trigger
[3.05.24.466]slot: 9, slotCtrl = 0x815f8
[3.05.24.560]slot[9] port:26 begin to power OFF.
[3.05.30.204]ext0 int trigger
[3.05.30.246]slot: 6, slotCtrl = 0x4817f8
[3.05.30.397]slot[6] port:20 begin to power ON.
Add ep: bdf=5700 eid=1e epCnt=4 eid_alloc=1f
