 | def_volt: 765 mV | pmu:MP2882
3>power domain[4] IO_DVDD_NA         | NA PMBus        | rail:0 | addr:0x2b | def_volt: 800 mV | pmu:MP2882
3>power domain[2] CORE_DVFS_TB       | NB PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
3>power domain[3] UNCORE_DVFS        | NB PMBus/AVSBus | rail:1 | addr:0x20 | def_volt:1012 mV | pmu:MP2882
3>power domain[5] IO_DVDD_NB         | NB PMBus        | rail:0 | addr:0x2b | def_volt: 800 mV | pmu:MP2882
3>power domain[6] DDR_VDDQ           | NB PMBus        | rail:1 | addr:0x2b | def_volt:1100 mV | pmu:MP2882
3>power domain[0] CORE_DVFS_TA       is transferred to AVSBus mode
3>power domain[1] DDR_VDD            is transferred to AVSBus mode
3>power domain[2] CORE_DVFS_TB       is transferred to AVSBus mode
3>power domain[3] UNCORE_DVFS        is transferred to AVSBus mode
3>avsbus resync success
3>avsbus[0] init done
3>avsbus resync success
3>avsbus[1] init done
3>============volt boot============
3>power domain[0] volt = 1101 mV
3>power domain[1] volt =  769 mV
3>power domain[4] volt =  800 mV
3>power domain[2] volt = 1105 mV
3>power domain[3] volt = 1005 mV
3>power domain[5] volt =  800 mV
3>power domain[6] volt = 1105 mV
3>===============end===============
3>--w&h rd rail:0, 1101, CORE_DVFS_TA
3>--w&h rd rail:1, 765, CORE_DVFS_TA
3>power domain[0] set volt --> 1101 mV success
3>--w&h rd rail:0, 1103, CORE_DVFS_TB
3>--w&h rd rail:1, 1005, CORE_DVFS_TB
3>power domain[2] set volt --> 1105 mV success
3>power domain[3] set volt --> 1017 mV success
3>============volt post============
3>power domain[0] volt = 1101 mV
3>power domain[1] volt =  767 mV
3>power domain[4] volt =  800 mV
3>power domain[2] volt = 1105 mV
3>power domain[3] volt = 1015 mV
3>power domain[5] volt =  800 mV
3>power domain[6] volt = 1103 mV
3>===============end===============
3>Hboot1 Info RAW Dump: [0x01][0x00][0x00][0x14][0x01][0x00][0x01]
3>PowerSensorSupport[1], Cali[5120], Loss[0]
3>Power Sensor Calibration Value[5120]!
3>the power sensor : manu id = 2peak, die id = TPA626
3>power sensor[0] init success
3>die[0] its[0] init done
3>die[0] its[1] init done
3>die[0] its[2] init done
3>die[0] its[3] init done
3>die[0] its[4] init done
3>die[0] its[5] init done
3>die[0] its[6] init done
3>die[0] its[7] init done
3>die[0] its[8] init done
3>die[0] its[9] init done
3>die[1] its[0] init done
3>die[1] its[1] init done
3>die[1] its[2] init done
3>die[1] its[3] init done
3>die[1] its[4] init done
3>die[1] its[5] init done
3>die[1] its[6] init done
3>die[1] its[7] init done
3>die[1] its[8] init done
3>die[1] its[9] init done
3>Totem[0] Core Boot Vol [1101]mv
3>Totem[0] Core Current Vol [1100]mv
3>Totem[1] Core Boot Vol [1105]mv
3>Totem[1] Core Current Vol [1100]mv
3>NA 1620V190
3>NB 1620V190
3>GetCoreBaseFreq [2900000KHZ]
3>GetCoreTurboFreq [2900000KHZ]
3>GetCustomClusterNum [10]
3>Ipu ACG Training Done!
3>AP Last Time:[0.00.01.520]
3>wait UEFI pll init...
3>done
3>acg trim start
3>core trim freq:2000, avs:0 volt:810mv
3>core trim freq:2000, avs:0 volt:810mv
3>core trim freq:2050, avs:1 volt:810mv
3>core trim freq:2050, avs:1 volt:810mv
3>core trim freq:2100, avs:2 volt:810mv
3>core trim freq:2100, avs:2 volt:810mv
3>core trim freq:2150, avs:3 volt:814mv
3>core trim freq:2150, avs:3 volt:817mv
3>core trim freq:2200, avs:4 volt:827mv
3>core trim freq:2200, avs:4 volt:830mv
3>core trim freq:2250, avs:5 volt:839mv
3>core trim freq:2250, avs:5 volt:842mv
3>core trim freq:2300, avs:6 volt:852mv
3>core trim freq:2300, avs:6 volt:855mv
3>core trim freq:2350, avs:7 volt:864mv
3>core trim freq:2350, avs:7 volt:868mv
3>core trim freq:2400, avs:8 volt:877mv
3>core trim freq:2400, avs:8 volt:880mv
3>core trim freq:2450, avs:9 volt:889mv
3>core trim freq:2450, avs:9 volt:893mv
3>core trim freq:2500, avs:10 volt:902mv
3>core trim freq:2500, avs:10 volt:905mv
3>core trim freq:2550, avs:11 volt:914mv
3>core trim freq:2550, avs:11 volt:918mv
3>core trim freq:2600, avs:12 volt:927mv
3>core trim freq:2600, avs:12 volt:930mv
3>core trim freq:2650, avs:13 volt:939mv
3>core trim freq:2650, avs:13 volt:943mv
3>core trim freq:2700, avs:14 volt:952mv
3>core trim freq:2700, avs:14 volt:956mv
3>core trim freq:2750, avs:15 volt:969mv
3>core trim freq:2750, avs:15 volt:974mv
3>core trim freq:2800, avs:16 volt:987mv
3>core trim freq:2800, avs:16 volt:992mv
3>core trim freq:2850, avs:17 volt:1005mv
3>core trim freq:2850, avs:17 volt:1010mv
3>core trim freq:2900, avs:18 volt:1023mv
3>core trim freq:2900, avs:18 volt:1028mv
3>core trim freq:2950, avs:19 volt:1040mv
3>core trim freq:2950, avs:19 volt:1045mv
3>core trim freq:3000, avs:20 volt:1057mv
3>core trim freq:3000, avs:20 volt:1063mv
3>core trim freq:3050, avs:21 volt:1071mv
3>core trim freq:3050, avs:21 volt:1
********Hello Huawei LiteOS********

KpxxxxIMU Firmware Version : V32.70.0
LiteOS Kernel Version : 5.7.0
Run on ChipVersion[0] Node[0] Die[2]
build time : Feb 05 2026 20:30:00

**********************************

main core booting up...
start set affinity

mpidr = 0x81020000
sram ecc state: 0x0, sram ecc cnt: 0x0
[0.00.00.033]node 0 begins init all serdes.
BoardInfo->NodeNum 4.
BoardInfo->NodeId 0.
BoardInfo->InfoVersion 5.
BoardInfo->NASerdesSceneMode 3.
BoardInfo->NBSerdesSceneMode 3.
BoardInfo->HccsTopologyType 12.
BoardInfo->BoardId 0.
ChipVersionIsPro: 0.
BoardInfo Node 0, SerdesUseMode: 1 1 12 4 4 4 4  1 1 1 4 4 4 4 
BoardInfo Node 1, SerdesUseMode: 12 13 12 4 4 4 4  1 1 12 4 4 4 4 
BoardInfo Node 2, SerdesUseMode: 1 1 1 4 4 4 4  1 1 1 4 4 4 4 
BoardInfo Node 3, SerdesUseMode: 1 1 1 4 4 4 4  1 1 1 4 4 4 4 
BoardInfo Node 0, SerdesRxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 1, SerdesRxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 2, SerdesRxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 3, SerdesRxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 0, SerdesTxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 1, SerdesTxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 2, SerdesTxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 3, SerdesTxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
serdessdk version: 2.0_5.0_20241203_imu
node_id 0, die 0, ind 0, usemode 1 begin serdes-init.
node_id 0, die 0, ind 1, usemode 1 begin serdes-init.
node_id 0, die 0, ind 2, usemode 12 begin serdes-init.
chip_id 0, die 0, ind 2, usemode 12 don't support, power down macro!
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
node_id 0, die 2, ind 0, usemode 1 begin serdes-init.
node_id 0, die 2, ind 1, usemode 1 begin serdes-init.
chip serdes init status:0x0.
[0.00.00.457]node 0 ends init all serdes.
link[0] freq_type:1 | peer_chip_type:2 | peer_node_id:0 | peer_link_id:0
link[1] freq_type:1 | peer_chip_type:2 | peer_node_id:0 | peer_link_id:0
link[2] freq_type:1 | peer_chip_type:2 | peer_node_id:0 | peer_link_id:0
link[3] freq_type:1 | peer_chip_type:2 | peer_node_id:0 | peer_link_id:0
link[4] freq_type:1 | peer_chip_type:2 | peer_node_id:0 | peer_link_id:0
link[5] freq_type:1 | peer_chip_type:1 | peer_node_id:1 | peer_link_id:4
link[6] freq_type:1 | peer_chip_type:1 | peer_node_id:2 | peer_link_id:7
link[7] freq_type:1 | peer_chip_type:1 | peer_node_id:3 | peer_link_id:5
register hccs done
nodeId 0, dieId 0, linkId 0, FFE info: fir_pre1 -5, fir_main 58, fir_post1 0
node_id 0, die 0, ind 4, usemode 4 begin serdes-init.
nodeId 0, dieId 0, linkId 1, FFE info: fir_pre1 -5, fir_main 58, fir_post1 0
node_id 0, die 0, ind 3, usemode 4 begin serdes-init.
nodeId 0, dieId 0, linkId 2, FFE info: fir_pre1 -5, fir_main 58, fir_post1 0
node_id 0, die 0, ind 5, usemode 4 begin serdes-init.
nodeId 0, dieId 0, linkId 3, FFE info: fir_pre1 -5, fir_main 58, fir_post1 0
node_id 0, die 0, ind 6, usemode 4 begin serdes-init.
nodeId 0, dieId 1, linkId 0, FFE info: fir_pre1 -5, fir_main 58, fir_post1 0
node_id 0, die 2, ind 4, usemode 4 begin serdes-init.
nodeId 0, dieId 1, linkId 1, FFE info: fir_pre1 -5, fir_main 58, fir_post1 0
node_id 0, die 2, ind 3, usemode 4 begin serdes-init.
nodeId 0, dieId 1, linkId 2, FFE info: fir_pre1 -6, fir_main 45, fir_post1 12
node_id 0, die 2, ind 5, usemode 4 begin serdes-init.
nodeId 0, dieId 1, linkId 3, FFE info: fir_pre1 -6, fir_main 45, fir_post1 12
node_id 0, die 2, ind 6, usemode 4 begin serdes-init.
hccs init start...
pa ring link down success
reset pa success
link[0] pcs init success
link[1] pcs init success
link[2] pcs init success
link[3] pcs init success
link[4] pcs init success
link[5] pcs init success
link[6] pcs init success
link[7] pcs init success
release reset pa success
link[0] macro adapt done (lane_mask=0xff) (0ms)
link[1] macro adapt done (lane_mask=0xff) (0ms)
link[2] macro adapt done (lane_mask=0xff) (0ms)
link[3] macro adapt done (lane_mask=0xff) (0ms)
link[4] macro adapt done (lane_mask=0xff) (0ms)
link[5] macro adapt done (lane_mask=0xff) (0ms)
link[6] macro adapt done (lane_mask=0xff) (0ms)
link[7] macro adapt done (lane_mask=0xff) (0ms)
link[6] pcs training success (10ms)
link[7] pcs training success (10ms)
link[6] training success (20ms)
link[7] training success (20ms)
link[5] pcs training success (690ms)
link[5] training success (700ms)
link[3] pcs training success (4690ms)
link[3] training success (4700ms)
link[4] pcs training success (4700ms)
link[4] training success (4710ms)
link[2] pcs training success (4920ms)
link[2] training success (4930ms)
link[1] pcs training success (5060ms)
link[1] training success (5070ms)
link[0] pcs training success (5410ms)
link[0] training success (5420ms)
link[0]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link[1]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link[2]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link[3]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link[4]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link[5]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link[6]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link[7]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link training success
pa[0] linkEn = 0xf
pa[0] allNodeLink0 = 0x0
pa[0] allNodeLink1 = 0xf000f
pa[0] connected with sw node
pa[1] linkEn = 0xf
pa[1] allNodeLink0 = 0x8420
pa[1] allNodeLink1 = 0x10001
pa[1] connected with sw node
pa init success
COM_PAID_INTLV_REG = 0xe
paid decode init success
pa[0] PA_PM_BASE_INFO = 0x0
pa[0] PA_PM_MAP_LINK_NUM = 0x1111
pa[1] PA_PM_BASE_INFO = 0xee0842
pa[1] PA_PM_MAP_LINK_NUM = 0x2811
hccs performace config success
pa ring link up success
hccs init done
hccs access test start
node[0] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[1] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[3] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[2] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[1] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
node[2] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
node[3] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
hccs access test success
======hccs status======
  node[0] mask: expected = 0xff, link up = 0xff, width reduction = 0x0, link down = 0x0
  node[1] mask: expected = 0xff, link up = 0xff, width reduction = 0x0, link down = 0x0
  node[2] mask: expected = 0xff, link up = 0xff, width reduction = 0x0, link down = 0x0
  node[3] mask: expected = 0xff, link up = 0xff, width reduction = 0x0, link down = 0x0
==========end==========
report hccs status success
node[0] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
LRDXSD_LOCK_OFFSET = 0x0
LRDXSD_ERRIMSK_OFFSET = 0x0
LRDXSD_DBG_OTIMSK_OFFSET = 0x0
LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
LRDXSD_DBG_EN_OFFSET = 0x1
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
ID[0x1967c8]!
[ERR]Don't support the flash, CS[0] ID[0x1967c8]!!
ID[0xffffff]!
[ERR]Don't support the flash, CS[1] ID[0xffffff]!!
[ERR]Warnning, Select Default flash 
sfdp detect, try to get dummy data from hboot1 first.
ID[0x1967c8]!
flash 0 support sfdp.
Interrupt 423 register OK
Interrupt 425 register OK
Interrupt 427 register OK
Interrupt 429 register OK
Interrupt 430 register OK
Interrupt 431 register OK
Interrupt 436 register OK

cpu 0 entering scheduler
[IMU] Watchdog Initialization done!
ScmiTaskEntry start.
Interrupt 456 register OK
Interrupt 469 register OK
Interrupt 482 register OK
Interrupt 495 register OK
Interrupt 508 register OK
Interrupt 521 register OK
Interrupt 534 register OK
Interrupt 547 register OK
starting Fpc Isolation Task end
starting fdm Err Info Task end
starting Roce recovery Task end
starting Ce_Storm Contrl Task end
starting Ras_Data_Update Task end
power register ubios call id
Interrupt 459 register OK
Interrupt 472 register OK
Interrupt 485 register OK
Interrupt 498 register OK
Interrupt 511 register OK
Interrupt 524 register OK
Interrupt 537 register OK
Interrupt 550 register OK
[0.00.46.427]Real time now 2026.5.14 06:40:02
NIC CARD[0][0]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[0][1]: nicPresent = 0x0, nicType =
********Hello Huawei LiteOS********

KpxxxxIMU Firmware Version : V32.70.0
LiteOS Kernel Version : 5.7.0
Run on ChipVersion[0] Node[0] Die[2]
build time : Feb 05 2026 20:30:00

**********************************

main core booting up...
start set affinity

mpidr = 0x81020000
sram ecc state: 0x0, sram ecc cnt: 0x0
[0.00.00.033]node 0 begins init all serdes.
BoardInfo->NodeNum 4.
BoardInfo->NodeId 0.
BoardInfo->InfoVersion 5.
BoardInfo->NASerdesSceneMode 3.
BoardInfo->NBSerdesSceneMode 3.
BoardInfo->HccsTopologyType 12.
BoardInfo->BoardId 0.
ChipVersionIsPro: 0.
BoardInfo Node 0, SerdesUseMode: 1 1 12 4 4 4 4  1 1 1 4 4 4 4 
BoardInfo Node 1, SerdesUseMode: 12 13 12 4 4 4 4  1 1 12 4 4 4 4 
BoardInfo Node 2, SerdesUseMode: 1 1 1 4 4 4 4  1 1 1 4 4 4 4 
BoardInfo Node 3, SerdesUseMode: 1 1 1 4 4 4 4  1 1 1 4 4 4 4 
BoardInfo Node 0, SerdesRxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 1, SerdesRxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 2, SerdesRxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 3, SerdesRxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 0, SerdesTxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 1, SerdesTxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 2, SerdesTxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 3, SerdesTxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
serdessdk version: 2.0_5.0_20241203_imu
node_id 0, die 0, ind 0, usemode 1 begin serdes-init.
node_id 0, die 0, ind 1, usemode 1 begin serdes-init.
node_id 0, die 0, ind 2, usemode 12 begin serdes-init.
chip_id 0, die 0, ind 2, usemode 12 don't support, power down macro!
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
node_id 0, die 2, ind 0, usemode 1 begin serdes-init.
node_id 0, die 2, ind 1, usemode 1 begin serdes-init.
chip serdes init status:0x0.
[0.00.00.457]node 0 ends init all serdes.
link[0] freq_type:1 | peer_chip_type:2 | peer_node_id:0 | peer_link_id:0
link[1] freq_type:1 | peer_chip_type:2 | peer_node_id:0 | peer_link_id:0
link[2] freq_type:1 | peer_chip_type:2 | peer_node_id:0 | peer_link_id:0
link[3] freq_type:1 | peer_chip_type:2 | peer_node_id:0 | peer_link_id:0
link[4] freq_type:1 | peer_chip_type:2 | peer_node_id:0 | peer_link_id:0
link[5] freq_type:1 | peer_chip_type:1 | peer_node_id:1 | peer_link_id:4
link[6] freq_type:1 | peer_chip_type:1 | peer_node_id:2 | peer_link_id:7
link[7] freq_type:1 | peer_chip_type:1 | peer_node_id:3 | peer_link_id:5
register hccs done
nodeId 0, dieId 0, linkId 0, FFE info: fir_pre1 -5, fir_main 58, fir_post1 0
node_id 0, die 0, ind 4, usemode 4 begin serdes-init.
nodeId 0, dieId 0, linkId 1, FFE info: fir_pre1 -5, fir_main 58, fir_post1 0
node_id 0, die 0, ind 3, usemode 4 begin serdes-init.
nodeId 0, dieId 0, linkId 2, FFE info: fir_pre1 -5, fir_main 58, fir_post1 0
node_id 0, die 0, ind 5, usemode 4 begin serdes-init.
nodeId 0, dieId 0, linkId 3, FFE info: fir_pre1 -5, fir_main 58, fir_post1 0
node_id 0, die 0, ind 6, usemode 4 begin serdes-init.
nodeId 0, dieId 1, linkId 0, FFE info: fir_pre1 -5, fir_main 58, fir_post1 0
node_id 0, die 2, ind 4, usemode 4 begin serdes-init.
nodeId 0, dieId 1, linkId 1, FFE info: fir_pre1 -5, fir_main 58, fir_post1 0
node_id 0, die 2, ind 3, usemode 4 begin serdes-init.
nodeId 0, dieId 1, linkId 2, FFE info: fir_pre1 -6, fir_main 45, fir_post1 12
node_id 0, die 2, ind 5, usemode 4 begin serdes-init.
nodeId 0, dieId 1, linkId 3, FFE info: fir_pre1 -6, fir_main 45, fir_post1 12
node_id 0, die 2, ind 6, usemode 4 begin serdes-init.
hccs init start...
pa ring link down success
reset pa success
link[0] pcs init success
link[1] pcs init success
link[2] pcs init success
link[3] pcs init success
link[4] pcs init success
link[5] pcs init success
link[6] pcs init success
link[7] pcs init success
release reset pa success
link[0] macro adapt done (lane_mask=0xff) (0ms)
link[1] macro adapt done (lane_mask=0xff) (0ms)
link[2] macro adapt done (lane_mask=0xff) (0ms)
link[3] macro adapt done (lane_mask=0xff) (0ms)
link[4] macro adapt done (lane_mask=0xff) (0ms)
link[5] macro adapt done (lane_mask=0xff) (0ms)
link[6] macro adapt done (lane_mask=0xff) (0ms)
link[7] macro adapt done (lane_mask=0xff) (0ms)
link[6] pcs training success (10ms)
link[7] pcs training success (10ms)
link[6] training success (20ms)
link[7] training success (20ms)
link[5] pcs training success (690ms)
link[5] training success (700ms)
link[1] pcs training success (4760ms)
link[1] training success (4770ms)
link[2] pcs training success (5460ms)
link[2] training success (5470ms)
link[3] pcs training success (5490ms)
link[3] training success (5500ms)
link[4] pcs training success (5730ms)
link[4] training success (5740ms)
link[0] pcs training success (5860ms)
link[0] training success (5870ms)
link[0]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link[1]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link[2]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link[3]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link[4]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link[5]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link[6]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link[7]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link training success
pa[0] linkEn = 0xf
pa[0] allNodeLink0 = 0x0
pa[0] allNodeLink1 = 0xf000f
pa[0] connected with sw node
pa[1] linkEn = 0xf
pa[1] allNodeLink0 = 0x8420
pa[1] allNodeLink1 = 0x10001
pa[1] connected with sw node
pa init success
COM_PAID_INTLV_REG = 0xe
paid decode init success
pa[0] PA_PM_BASE_INFO = 0x0
pa[0] PA_PM_MAP_LINK_NUM = 0x1111
pa[1] PA_PM_BASE_INFO = 0xee0842
pa[1] PA_PM_MAP_LINK_NUM = 0x2811
hccs performace config success
pa ring link up success
hccs init done
hccs access test start
node[0] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[1] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[2] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[3] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[1] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
node[2] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
node[3] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
hccs access test success
======hccs status======
  node[0] mask: expected = 0xff, link up = 0xff, width reduction = 0x0, link down = 0x0
  node[1] mask: expected = 0xff, link up = 0xff, width reduction = 0x0, link down = 0x0
  node[2] mask: expected = 0xff, link up = 0xff, width reduction = 0x0, link down = 0x0
  node[3] mask: expected = 0xff, link up = 0xff, width reduction = 0x0, link down = 0x0
==========end==========
report hccs status success
node[0] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
LRDXSD_LOCK_OFFSET = 0x0
LRDXSD_ERRIMSK_OFFSET = 0x0
LRDXSD_DBG_OTIMSK_OFFSET = 0x0
LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
LRDXSD_DBG_EN_OFFSET = 0x1
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
ID[0x1967c8]!
[ERR]Don't support the flash, CS[0] ID[0x1967c8]!!
ID[0xffffff]!
[ERR]Don't support the flash, CS[1] ID[0xffffff]!!
[ERR]Warnning, Select Default flash 
sfdp detect, try to get dummy data from hboot1 first.
ID[0x1967c8]!
flash 0 support sfdp.
Interrupt 423 register OK
Interrupt 425 register OK
Interrupt 427 register OK
Interrupt 429 register OK
Interrupt 430 register OK
Interrupt 431 register OK
Interrupt 436 register OK

cpu 0 entering scheduler
[IMU] Watchdog Initialization done!
ScmiTaskEntry start.
Interrupt 456 register OK
Interrupt 469 register OK
Interrupt 482 register OK
Interrupt 495 register OK
Interrupt 508 register OK
Interrupt 521 register OK
Interrupt 534 register OK
Interrupt 547 register OK
starting Fpc Isolation Task end
starting fdm Err Info Task end
starting Roce recovery Task end
starting Ce_Storm Contrl Task end
starting Ras_Data_Update Task end
power register ubios call id
Interrupt 459 register OK
Interrupt 472 register OK
Interrupt 485 register OK
Interrupt 498 register OK
Interrupt 511 register OK
Interrupt 524 register OK
Interrupt 537 register OK
Interrupt 550 register OK
[0.00.46.745]Real time now 2026.5.14 06:52:33
NIC CARD[0][0]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[0][1]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[1][0]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[1][1]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[2][0]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[2][1]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[3][0]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[3][1]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
Init heart-beat-task end
Init SeamlessUpdateTask end
pool addr          pool size    used size     free size    max free node size   used node num     free node num      UsageWaterLine
---------------    --------     -------       --------     --------------       -------------      ------------      ------------
0x840908e708       0x204c0      0x1a780       0x5ad0       0x5ad0               0x79               0x1                0x1a9f0        
Get Setup Config.
pwr cap[0]: 0, 63
pwr cap[1]: f, 27
pwr cap[2]: 1, 3
Node 0, Die 0 ImpState is 0 skip exec.
Node 0, Die 2 ImpState is 0 skip exec.
Node 1, Die 0 ImpState is 0 skip exec.
Node 1, Die 2 ImpState is 0 skip exec.
Node 2, Die 0 ImpState is 0 skip exec.
Node 2, Die 2 ImpState is 0 skip exec.
Node 3, Die 0 ImpState is 0 skip exec.
Node 3, Die 2 ImpState is 0 skip exec.
ACK Check Failed. Completion code = 0x80
IpmbWrite failed, Try Again Times:1 !!!!
ACK Check Failed. Completion code = 0x80
IpmbWrite failed, Try
2>power task start...
2>[TracePoint] type[  0] cmd[  3] data[  2]
2>ufs task wait parameters from uefi...
2>AmuTaskStart Entry ... 
2>amu task wait parameters from uefi...
2>ThermalSiwStart Entry ...
2>ThermalSiwTask idle...
2>DemtTaskStart Entry ...
2>[TracePoint] type[  0] cmd[  3] data[  3]
2>HiBoostTaskStart Entry ...
2>HiBoost task enabled
2>Waiting for UEFI parameters...
2>[TracePoint] type[  0] cmd[  3] data[  4]
2>AgeTaskStart Entry ...
2>demt task wait [1] Core 2700MHZ -> Vol[956] mv
3>Totem[1] Core 2900MHZ -> Vol[1028] mv
3>Totem[1] Core 3000MHZ -> Vol[1063] mv
3>Totem[1] Core 3100MHZ -> Vol[1090] mv
3>Uncore Vmin Formula:
3>Totem Uncore 400MHZ -> Vol[810] mv
3>Totem Uncore 2000MHZ -> Vol[906] mv
3>Totem Uncore 2500MHZ -> Vol[943] mv
3>Totem Uncore 2700MHZ -> Vol[978] mv
3>Totem Uncore 2900MHZ -> Vol[1012] mv
3>Totem Uncore 3000MHZ -> Vol[1026] mv
3>Core VF curve:
3>[ 400]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 450]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 500]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 550]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 600]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 650]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 700]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 750]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 800]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 850]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 900]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 950]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1000]MHZ -> Vol TA[ 810]mv TB[ 8 920]mv
3>Uncore [2300]MHZ -> Vol [ 928]mv
3>Uncore [2400]MHZ -> Vol [ 935]mv
3>Uncore [2500]MHZ -> Vol [ 943]mv
3>Uncore [2600]MHZ -> Vol [ 960]mv
3>Uncore [2700]MHZ -> Vol [ 978]mv
3>Uncore [2800]MHZ -> Vol [ 995]mv
3>Uncore [2900]MHZ -> Vol [1012]mv
3>Uncore [3000]MHZ -> Vol [1026]mv
3>[TracePoint] type[  0] cmd[  1] data[  6]
3>[TracePoint] type[  0] cmd[  1] data[  7]
3>
********Hello Huawei LiteOS********

KpxxxxIPU Firmware Version : V32.70.0
LiteOS Kernel Version : 5.7.0
3>Run on ChipVersion[0] Node[3] Die[0]
3>build time : Feb 05 2026 20:30:00

3>**********************************
3>
main core booting up...
3>start set affinity
3>
mpidr = 0x810c0000
3>sram ecc state: 0x0, sram ecc cnt: 0x0
3>[TracePoint] type[  0] cmd[  2] data[  1]
3>[TracePoint] type[  0] cmd[  2] data[  2]
3>LRDXSD_LOCK_OFFSET = 0x0
3>LRDXSD_ERRIMSK_OFFSET = 0x0
3>LRDXSD_DBG_OTIMSK_OFFSET = 0x0
3>LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
3>LRDXSD_DBG_EN_OFFSET = 0x1
3>======tsensor params======
3>  is_trimmed       : 1
3>  underclocking_en : 1
3>===========end============
3>soc tsensor init done
3>========vrd info from cpld========
3>vrd_id | u64                | pmbus_en | avsbus_en | loop | pmbus_id | pmbus_addr | avs_sw | pmbus_sw | addr_9545 | domain_type | die_mask | reserved
3>  00   | 0x0001000100002017 | 0x1      | 0x1       | 0x1  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0100   | 0x0
3>  01   | 0x000300030000201b | 0x1      | 0x1       | 0x2  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x3         | 0x0300   | 0x0
3>  02   | 0x0000010500002b15 | 0x1      | 0x0       | 0x1  | 0x1      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0001   | 0x0
3>  03   | 0x0002000100002027 | 0x1      | 0x1       | 0x1  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0200   | 0x0
3>  04   | 0x000300020000202b | 0x1      | 0x1       | 0x2  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x2         | 0x0300   | 0x0
3>  05   | 0x0000020500002b25 | 0x1      | 0x0       | 0x1  | 0x2      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0002   | 0x0
3>  06   | 0x0003000400002b29 | 0x1      | 0x0       | 0x2  | 0x2      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x4         | 0x0300   | 0x0
3>================end===============
3>=============vrd info=============
3>power domain num: 7
3>power domain[00] id:0 | CORE_DVFS_TA       | PMBus NA | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
3>power domain[01] id:1 | DDR_VDD            | PMBus NA | cap:0x3 | rail:1 | addr:0x20 | def_volt: 765 mV | min_volt: 650 mV | max_volt: 850 mV
3>power domain[02] id:4 | IO_DVDD_NA         | PMBus NA | cap:0x1 | rail:0 | addr:0x2b | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
3>power domain[03] id:2 | CORE_DVFS_TB       | PMBus NB | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
3>power domain[04] id:3 | UNCORE_DVFS        | PMBus NB | cap:0x3 | rail:1 | addr:0x20 | def_volt:1012 mV | min_volt: 750 mV | max_volt:1100 mV
3>power domain[05] id:5 | IO_DVDD_NB         | PMBus NB | cap:0x1 | rail:0 | addr:0x2b | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
3>power domain[06] id:6 | DDR_VDDQ           | PMBus NB | cap:0x1 | rail:1 | addr:0x2b | def_volt:1100 mV | min_volt:1000 mV | max_volt:1200 mV
3>================end===============
3>pmbus[0] init done
3>pmbus[1] init done
3>power domain[0] CORE_DVFS_TA       | NA PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
3>power domain[1] DDR_VDD            | NA PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 765 mV | pmu:MP2882
3>power domain[4] IO_DVDD_NA         | NA PMBus        | rail:0 | addr:0x2b | def_volt: 800 mV | pmu:MP2882
3>power domain[2] CORE_DVFS_TB       | NB PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
3>power domain[3] UNCORE_DVFS        | NB PMBus/AVSBus | rail:1 | addr:0x20 | def_volt:1012 mV | pmu:MP2882
3>power domain[5] IO_DVDD_NB         | NB PMBus        | rail:0 | addr:0x2b | def_volt: 800 mV | pmu:MP2882
3>power domain[6] DDR_VDDQ           | NB PMBus        | rail:1 | addr:0x2b | def_volt:1100 mV | pmu:MP2882
3>power domain[0] CORE_DVFS_TA       is transferred to AVSBus mode
3>power domain[1] DDR_VDD            is transferred to AVSBus mode
3>power domain[2] CORE_DVFS_TB       is transferred to AVSBus mode
3>power domain[3] UNCORE_DVFS        is transferred to AVSBus mode
3>avsbus resync success
3>avsbus[0] init done
3>avsbus resync success
3>avsbus[1] init done
3>============volt boot============
3>power domain[0] volt = 1101 mV
3>power domain[1] volt =  767 mV
3>power domain[4] volt =  800 mV
3>power domain[2] volt = 1105 mV
3>power domain[3] volt = 1007 mV
3>power domain[5] volt =  800 mV
3>power domain[6] volt = 1105 mV
3>===============end===============
3>--w&h rd rail:0, 1101, CORE_DVFS_TA
3>--w&h rd rail:1, 765, CORE_DVFS_TA
3>power domain[0] set volt --> 1101 mV success
3>--w&h rd rail:0, 1103, CORE_DVFS_TB
3>--w&h rd rail:1, 1005, CORE_DVFS_TB
3>power domain[2] set volt --> 1103 mV success
3>power domain[3] set volt --> 1015 mV success
3>============volt post============
3>power domain[0] volt = 1101 mV
3>power domain[1] volt =  767 mV
3>power domain[4] volt =  800 mV
3>power domain[2] volt = 1103 mV
3>power domain[3] volt = 1013 mV
3>power domain[5] volt =  800 mV
3>power domain[6] volt = 1103 mV
3>===============end===============
3>Hboot1 Info RAW Dump: [0x01][0x00][0x00][0x14][0x01][0x00][0x01]
3>PowerSensorSupport[1], Cali[5120], Loss[0]
3>Power Sensor Calibration Value[5120]!
3>the power sensor : manu id = 2peak, die id = TPA626
3>power sensor[0] init success
3>die[0] its[0] init done
3>die[0] its[1] init done
3>die[0] its[2] init done
3>die[0] its[3] init done
3>die[0] its[4] init done
3>die[0] its[5] init done
3>die[0] its[6] init done
3>die[0] its[7] init done
3>die[0] its[8] init done
3>die[0] its[9] init done
3>die[1] its[0] init done
3>die[1] its[1] init done
3>die[1] its[2] init done
3>die[1] its[3] init done
3>die[1] its[4] init done
3>die[1] its[5] init done
3>die[1] its[6] init done
3>die[1] its[7] init done
3>die[1] its[8] init done
3>die[1] its[9] init done
3>Totem[0] Core Boot Vol [1101]mv
3>Totem[0] Core Current Vol [1100]mv
3>Totem[1] Core Boot Vol [1103]mv
3>Totem[1] Core Current Vol [1100]mv
3>NA 1620V190
3>NB 1620V190
3>GetCoreBaseFreq [2900000KHZ]
3>GetCoreTurboFreq [2900000KHZ]
3>GetCustomClusterNum [10]
3>Ipu ACG Training Done!
3>AP Last Time:[0.00.01.519]
3>wait UEFI pll init...
3>done
3>acg trim start
3>core trim freq:2000, avs:0 volt:810mv
3>core trim freq:2000, avs:0 volt:810mv
3>core trim freq:2050, avs:1 volt:810mv
3>core trim freq:2050, avs:1 volt:810mv
3>core trim freq:2100, avs:2 volt:810mv
3>core trim freq:2100, avs:2 volt:810mv
3>core trim freq:2150, avs:3 volt:814mv
3>core trim freq:2150, avs:3 volt:817mv
3>core trim freq:2200, avs:4 volt:827mv
3>core trim freq:2200, avs:4 volt:830mv
3>core trim freq:2250, avs:5 volt:839mv
3>core trim freq:2250, avs:5 volt:842mv
3>core trim freq:2300, avs:6 volt:852mv
3>core trim freq:2300, avs:6 volt:855mv
3>core trim freq:2350, avs:7 volt:864mv
3>core trim freq:2350, avs:7 volt:868mv
3>core trim freq:2400, avs:8 volt:877mv
3>core trim freq:2400, avs:8 volt:880mv
3>core trim freq:2450, avs:9 volt:889mv
3>core trim freq:2450, avs:9 volt:893mv
3>core trim freq:2500, avs:10 volt:902mv
3>core trim freq:2500, avs:10 volt:905mv
3>core trim freq:2550, avs:11 volt:914mv
3>core trim freq:2550, avs:11 volt:918mv
3>core trim freq:2600, avs:12 volt:927mv
3>core trim freq:2600, avs:12 volt:930mv
3>core trim freq:2650, avs:13 volt:939mv
3>core trim freq:2650, avs:13 volt:943mv
3>core trim freq:2700, avs:14 volt:952mv
3>core trim freq:2700, avs:14 volt:956mv
3>core trim freq:2750, avs:15 volt:969mv
3>core trim freq:2750, avs:15 volt:974mv
3>core trim freq:2800, avs:16 volt:987mv
3>core trim freq:2800, avs:16 volt:992mv
3>core trim freq:2850, avs:17 volt:1005mv
3>core trim freq:2850, avs:17 volt:1010mv
3>core trim freq:2900, avs:18 volt:1023mv
3>core trim freq:2900, avs:18 volt:1028mv
3>core trim freq:2950, avs:19 volt:1040mv
3>core trim freq:2950, avs:19 volt:1045mv
3>core trim freq:3000, avs:20 volt:1057mv
3>core trim freq:3000, avs:20 volt:1063mv
3>core trim freq:3050, avs:21 volt:1071mv
3>core trim freq:3050, avs:21 volt:1076mv
3>core trim freq:3100, avs:22 volt:1085mv
3>core trim freq:3100, avs:22 volt:1090mv
3>acg trim end
3>LDO disabled
3>[TracePoint] type[  0] cmd[  2] data[  3]
3>Interrupt 423 register OK
3>Interrupt 430 register OK
3>[TracePoint] type[  0] cmd[  2] data[  4]
3>
3>cpu 0 entering scheduler
3>[TracePoint] type[  0] cmd[  3] data[  1]
3>add your ipu app init here!
3>IpuInterfaceTaskStart Entry ...
3>ipu interface task wait parameters from uefi...
3>thermal soc task enabled
3>AP Last Time:[0.00.44.000]
3>ThermalDimmStart Entry ...
3>wait ddr init done...
3>power task start...
3>[TracePoint] type[  0] cmd[  3] data[  2]
3>ufs task wait parameters from uefi...
3>AmuTaskStart Entry ... 
3>amu task wait parameters from uefi...
3>ThermalSiwStart Entry ...
3>ThermalSiwTask idle...
3>DemtTaskStart Entry ...
3>[TracePoint] type[  0] cmd[  3] data[  3]
3>HiBoostTaskStart Entry ...
3>HiBoost task enabled
3>Waiting for UEFI parameters...
3>[TracePoint] type[  0] cmd[  3] data[  4]
3>AgeTaskStart Entry ...
3>demt task wait parameters from uefi...
3>age task wait parameters from uefi...
3>[TracePoint] type[  0] cmd[  3] data[  5]
Get Setup Config.
pwr cap[0]: 0, 63
pwr cap[1]: f, 27
pwr cap[2]: 1, 3
0>uefi parameters ready!
0>UFSProfile[0]
0>PowerPolicy[0] BenchMarkSelection[0]
0>ipu interface task wait ddr init done from uefi...
0>thermal soc task restore underclocking_en=1
0>ppu alert temp div init done
0>ufs task parameters from uefi ready
0>uncore domain[0] freq:2900
0>uncore domain[1] freq:2900
0>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
0>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
0>======sioe status======
0>TA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TA_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TA_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TA_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
0>TA_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
0>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
0>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
0>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
0>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
0>==========end==========
0>sioe init done
0>ufs task disabled
0>UEFI parameters ready
0>UncoreMaxFreq Set to [2900 MHZ]
0>get TDP from efuse success, value = 357500mw
0>target power set to [357500]mw, brd:[357500]
0>demt task parameters from uefi ready
0>age task parameters from uefi ready
0>age task enabled
1>uefi parameters ready!
1>UFSProfile[0]
1>PowerPolicy[0] BenchMarkSelection[0]
1>ipu interface task wait ddr init done from uefi...
1>thermal soc task restore underclocking_en=1
1>ppu alert temp div init done
1>ufs task parameters from uefi ready
1>uncore domain[0] freq:2900
1>uncore domain[1] freq:2900
1>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
1>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
1>======sioe status======
1>TA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TA_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TA_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TA_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
1>TA_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
1>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
1>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
1>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
1>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
1>==========end==========
1>sioe init done
1>ufs task disabled
1>UEFI parameters ready
1>UncoreMaxFreq Set to [2900 MHZ]
1>get TDP from efuse success, value = 357500mw
1>target power set to [357500]mw, brd:[357500]
1>demt task parameters from uefi ready
1>age task parameters from uefi ready
1>age task enabled
2>uefi parameters ready!
2>UFSProfile[0]
2>PowerPolicy[0] BenchMarkSelection[0]
2>ipu interface task wait ddr init done from uefi...
2>thermal soc task restore underclocking_en=1
2>ppu alert temp div init done
2>ufs task parameters from uefi ready
2>uncore domain[0] freq:2900
2>uncore domain[1] freq:2900
2>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
2>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
2>======sioe status======
2>TA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
2>TA_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
2>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
2>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
2>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
2>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
2>==========end==========
2>sioe init done
2>ufs task disabled
2>UEFI parameters ready
2>UncoreMaxFreq Set to [2900 MHZ]
2>get TDP from efuse success, value = 357500mw
2>target power set to [357500]mw, brd:[357500]
2>demt task parameters from uefi ready
2>age task parameters from uefi ready
2>age task enabled
3>uefi parameters ready!
3>UFSProfile[0]
3>PowerPolicy[0] BenchMarkSelection[0]
3>ipu interface task wait ddr init done from uefi...
3>thermal soc task restore underclocking_en=1
3>ppu alert temp div init done
3>ufs task parameters from uefi ready
3>uncore domain[0] freq:2900
3>uncore domain[1] freq:2900
3>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
3>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
3>======sioe status======
3>TA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
3>TA_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
3>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
3>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
3>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
3>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
3>==========end==========
3>sioe init done
3>ufs task disabled
3>UEFI parameters ready
3>UncoreMaxFreq Set to [2900 MHZ]
3>get TDP from efuse success, value = 357500mw
3>target power set to [357500]mw, brd:[357500]
3>demt task parameters from uefi ready
3>age task parameters from uefi ready
3>age task enabled
Node 0, Die 0 ImpState is 0 skip exec.
Node 0, Die 2 ImpState is 0 skip exec.
Node 1, Die 0 ImpState is 0 skip exec.
Node 1, Die 2 ImpState is 0 skip exec.
Node 2, Die 0 ImpState is 0 skip exec.
Node 2, Die 2 ImpState is 0 skip exec.
Node 3, Die 0 ImpState is 0 skip exec.
Node 3, Die 2 ImpState is 0 skip exec.
ACK Check Failed. Completion code = 0x80
IpmbWrite failed, Try Again Times:1 !!!!
ACK Check Failed. Completion code = 0x80
IpmbWrite failed, Try Again Times:2 !!!!
ACK Check Failed. Completion code = 0x80
IpmbWrite failed, Try Again Times:3 !!!!
IPMB Send msg failed! Status:1
[ERR]IpmiSendRequest failed in task ipmis
ACK Check Failed. Completion code = 0x80
IpmbWrite failed, Try Again Times:1 !!!!
ACK Check Failed. Completion code = 0x80
IpmbWrite failed, Try Again Times:2 !!!!
ACK Check Failed. Completion code = 0x80
IpmbWrite failed, Try Again Times:3 !!!!
IPMB Send msg failed! Status:1
[ERR]IpmiSendRequest failed in task ipmis
ACK Check Failed. Completion code = 0x80
IpmbWrite failed, Try Again Times:1 !!!!
ACK Check Failed. Completion code = 0x80
IpmbWrite failed, Try Again Times:2 !!!!
ACK Check Failed. Completion code = 0x80
IpmbWrite failed, Try Again Times:3 !!!!
IPMB Send msg failed! Status:1
[ERR]IpmiSendRequest failed in task ipmis
0>uefi ddr init finish!
0>ipu interface task wait uefi end done from uefi...
0>ddr init done, start thermal dimm task
0>======dimm status======
0>  chl[0] dimm0 2, dimm1 0
0>  chl[1] dimm0 2, dimm1 0
0>  chl[2] dimm0 2, dimm1 0
0>  chl[3] dimm0 2, dimm1 0
0>  chl[4] dimm0 2, dimm1 0
0>  chl[5] dimm0 2, dimm1 0
0>  chl[6] dimm0 2, dimm1 0
0>  chl[7] dimm0 2, dimm1 0
0>==========end==========
0>chl[0] registered, dimm mask = 0x1
0>chl[1] registered, dimm mask = 0x1
0>chl[2] registered, dimm mask = 0x1
0>chl[3] registered, dimm mask = 0x1
0>chl[4] registered, dimm mask = 0x1
0>chl[5] registered, dimm mask = 0x1
0>chl[6] registered, dimm mask = 0x1
0>chl[7] registered, dimm mask = 0x1
0>=====dimm temp params=====
0>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
0>  is_thermal_thro_en  : 1
0>  is_aref_rate_auto   : 1
0>===========end============
1>uefi ddr init finish!
1>ipu interface task wait uefi end done from uefi...
1>ddr init done, start thermal dimm task
1>======dimm status======
1>  chl[0] dimm0 2, dimm1 0
1>  chl[1] dimm0 2, dimm1 0
1>  chl[2] dimm0 2, dimm1 0
1>  chl[3] dimm0 2, dimm1 0
1>  chl[4] dimm0 2, dimm1 0
1>  chl[5] dimm0 2, dimm1 0
1>  chl[6] dimm0 2, dimm1 0
1>  chl[7] dimm0 2, dimm1 0
1>==========end==========
1>chl[0] registered, dimm mask = 0x1
1>chl[1] registered, dimm mask = 0x1
1>chl[2] registered, dimm mask = 0x1
1>chl[3] registered, dimm mask = 0x1
1>chl[4] registered, dimm mask = 0x1
1>chl[5] registered, dimm mask = 0x1
1>chl[6] registered, dimm mask = 0x1
1>chl[7] registered, dimm mask = 0x1
1>=====dimm temp params=====
1>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
1>  is_thermal_thro_en  : 1
1>  is_aref_rate_auto   : 1
1>===========end============
2>uefi ddr init finish!
2>ipu interface task wait uefi end done from uefi...
2>ddr init done, start thermal dimm task
2>======dimm status======
2>  chl[0] dimm0 2, dimm1 0
2>  chl[1] dimm0 2, dimm1 0
2>  chl[2] dimm0 2, dimm1 0
2>  chl[3] dimm0 2, dimm1 0
2>  chl[4] dimm0 2, dimm1 0
2>  chl[5] dimm0 2, dimm1 0
2>  chl[6] dimm0 2, dimm1 0
2>  chl[7] dimm0 2, dimm1 0
2>==========end==========
2>chl[0] registered, dimm mask = 0x1
2>chl[1] registered, dimm mask = 0x1
2>chl[2] registered, dimm mask = 0x1
2>chl[3] registered, dimm mask = 0x1
2>chl[4] registered, dimm mask = 0x1
2>chl[5] registered, dimm mask = 0x1
2>chl[6] registered, dimm mask = 0x1
2>chl[7] registered, dimm mask = 0x1
2>=====dimm temp params=====
2>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
2>  is_thermal_thro_en  : 1
2>  is_aref_rate_auto   : 1
2>===========end============
3>uefi ddr init finish!
3>ipu interface task wait uefi end done from uefi...
3>ddr init done, start thermal dimm task
3>======dimm status======
3>  chl[0] dimm0 2, dimm1 0
3>  chl[1] dimm0 2, dimm1 0
3>  chl[2] dimm0 2, dimm1 0
3>  chl[3] dimm0 2, dimm1 0
3>  chl[4] dimm0 2, dimm1 0
3>  chl[5] dimm0 2, dimm1 0
3>  chl[6] dimm0 2, dimm1 0
3>  chl[7] dimm0 2, dimm1 0
3>==========end==========
3>chl[0] registered, dimm mask = 0x1
3>chl[1] registered, dimm mask = 0x1
3>chl[2] registered, dimm mask = 0x1
3>chl[3] registered, dimm mask = 0x1
3>chl[4] registered, dimm mask = 0x1
3>chl[5] registered, dimm mask = 0x1
3>chl[6] registered, dimm mask = 0x1
3>chl[7] registered, dimm mask = 0x1
3>=====dimm temp params=====
3>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
3>  is_thermal_thro_en  : 1
3>  is_aref_rate_auto   : 1
3>===========end============
[0.01.27.238]DDR Rreserved for IMU: len = 3e00000
[LOG]head = 0x0, tail = 0x4f35, logSize = 0x4f35
copy registry.json file success
Set component all release version to sram end.
ipcMsgSend success
[0.01.27.281]starting ras Init
nodeId = 0, dieId = 0, isSasExist = 0.
nodeId = 0, dieId = 2, isSasExist = 0.
nodeId = 1, dieId = 0, isSasExist = 0.
nodeId = 1, dieId = 2, isSasExist = 0.
nodeId = 2, dieId = 0, isSasExist = 0.
nodeId = 2, dieId = 2, isSasExist = 0.
nodeId = 3, dieId = 0, isSasExist = 0.
nodeId = 3, dieId = 2, isSasExist = 0.
Mce Table head exist!
RasIntRegister init 452 
RasIntRegister init 453 
RasIntRegister init 64 
RasIntRegister init 65 
RasIntRegister init 465 
RasIntRegister init 466 
RasIntRegister init 86 
RasIntRegister init 87 
RasIntRegister init 478 
RasIntRegister init 479 
RasIntRegister init 108 
RasIntRegister init 109 
RasIntRegister init 491 
RasIntRegister init 492 
RasIntRegister init 130 
RasIntRegister init 131 
RasIntRegister init 504 
RasIntRegister init 505 
RasIntRegister init 152 
RasIntRegister init 153 


HSM_LOG:
[00:00:00.000][info] succeed to do thirdparty dfx_pabuk init
[00:00:00.000][info] succeed to do thirdparty crypto_driver init


RasIntRegister init 517 
RasIntRegister init 518 
RasIntRegister init 174 
RasIntRegister init 175 
RasIntRegister init 530 
RasIntRegiste
********Hello Huawei LiteOS********

KpxxxxIMU Firmware Version : V32.70.0
LiteOS Kernel Version : 5.7.0
Run on ChipVersion[0] Node[0] Die[2]
build time : Feb 05 2026 20:30:00

**********************************

main core booting up...
start set affinity

mpidr = 0x81020000
sram ecc state: 0x0, sram ecc cnt: 0x0
[0.00.00.033]node 0 begins init all serdes.
BoardInfo->NodeNum 4.
BoardInfo->NodeId 0.
BoardInfo->InfoVersion 5.
BoardInfo->NASerdesSceneMode 3.
BoardInfo->NBSerdesSceneMode 3.
BoardInfo->HccsTopologyType 12.
BoardInfo->BoardId 0.
ChipVersionIsPro: 0.
BoardInfo Node 0, SerdesUseMode: 1 1 12 4 4 4 4  1 1 1 4 4 4 4 
BoardInfo Node 1, SerdesUseMode: 12 13 12 4 4 4 4  1 1 12 4 4 4 4 
BoardInfo Node 2, SerdesUseMode: 1 1 1 4 4 4 4  1 1 1 4 4 4 4 
BoardInfo Node 3, SerdesUseMode: 1 1 1 4 4 4 4  1 1 1 4 4 4 4 
BoardInfo Node 0, SerdesRxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 1, SerdesRxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 2, SerdesRxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 3, SerdesRxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 0, SerdesTxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 1, SerdesTxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 2, SerdesTxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 3, SerdesTxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
serdessdk version: 2.0_5.0_20241203_imu
node_id 0, die 0, ind 0, usemode 1 begin serdes-init.
node_id 0, die 0, ind 1, usemode 1 begin serdes-init.
node_id 0, die 0, ind 2, usemode 12 begin serdes-init.
chip_id 0, die 0, ind 2, usemode 12 don't support, power down macro!
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
node_id 0, die 2, ind 0, usemode 1 begin serdes-init.
node_id 0, die 2, ind 1, usemode 1 begin serdes-init.
chip serdes init status:0x0.
[0.00.00.457]node 0 ends init all serdes.
link[0] freq_type:1 | peer_chip_type:2 | peer_node_id:0 | peer_link_id:0
link[1] freq_type:1 | peer_chip_type:2 | peer_node_id:0 | peer_link_id:0
link[2] freq_type:1 | peer_chip_type:2 | peer_node_id:0 | peer_link_id:0
link[3] freq_type:1 | peer_chip_type:2 | peer_node_id:0 | peer_link_id:0
link[4] freq_type:1 | peer_chip_type:2 | peer_node_id:0 | peer_link_id:0
link[5] freq_type:1 | peer_chip_type:1 | peer_node_id:1 | peer_link_id:4
link[6] freq_type:1 | peer_chip_type:1 | peer_node_id:2 | peer_link_id:7
link[7] freq_type:1 | peer_chip_type:1 | peer_node_id:3 | peer_link_id:5
register hccs done
nodeId 0, dieId 0, linkId 0, FFE info: fir_pre1 -5, fir_main 58, fir_post1 0
node_id 0, die 0, ind 4, usemode 4 begin serdes-init.
nodeId 0, dieId 0, linkId 1, FFE info: fir_pre1 -5, fir_main 58, fir_post1 0
node_id 0, die 0, ind 3, usemode 4 begin serdes-init.
nodeId 0, dieId 0, linkId 2, FFE info: fir_pre1 -5, fir_main 58, fir_post1 0
node_id 0, die 0, ind 5, usemode 4 begin serdes-init.
nodeId 0, dieId 0, linkId 3, FFE info: fir_pre1 -5, fir_main 58, fir_post1 0
node_id 0, die 0, ind 6, usemode 4 begin serdes-init.
nodeId 0, dieId 1, linkId 0, FFE info: fir_pre1 -5, fir_main 58, fir_post1 0
node_id 0, die 2, ind 4, usemode 4 begin serdes-init.
nodeId 0, dieId 1, linkId 1, FFE info: fir_pre1 -5, fir_main 58, fir_post1 0
node_id 0, die 2, ind 3, usemode 4 begin serdes-init.
nodeId 0, dieId 1, linkId 2, FFE info: fir_pre1 -6, fir_main 45, fir_post1 12
node_id 0, die 2, ind 5, usemode 4 begin serdes-init.
nodeId 0, dieId 1, linkId 3, FFE info: fir_pre1 -6, fir_main 45, fir_post1 12
node_id 0, die 2, ind 6, usemode 4 begin serdes-init.
hccs init start...
pa ring link down success
reset pa success
link[0] pcs init success
link[1] pcs init success
link[2] pcs init success
link[3] pcs init success
link[4] pcs init success
link[5] pcs init success
link[6] pcs init success
link[7] pcs init success
release reset pa success
link[0] macro adapt done (lane_mask=0xff) (0ms)
link[1] macro adapt done (lane_mask=0xff) (0ms)
link[2] macro adapt done (lane_mask=0xff) (0ms)
link[3] macro adapt done (lane_mask=0xff) (0ms)
link[4] macro adapt done (lane_mask=0xff) (0ms)
link[5] macro adapt done (lane_mask=0xff) (0ms)
link[6] macro adapt done (lane_mask=0xff) (0ms)
link[7] macro adapt done (lane_mask=0xff) (0ms)
link[6] pcs training success (10ms)
link[7] pcs training success (10ms)
link[6] training success (20ms)
link[7] training success (20ms)
link[5] pcs training success (700ms)
link[5] training success (710ms)
link[2] pcs training success (5410ms)
link[2] training success (5420ms)
link[0] pcs training success (5590ms)
link[0] training success (5600ms)
link[1] pcs training success (5700ms)
link[1] training success (5710ms)
link[4] pcs training success (5710ms)
link[4] training success (5720ms)
link[3] pcs training success (5960ms)
link[3] training success (5970ms)
link[0]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link[1]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link[2]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link[3]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link[4]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link[5]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link[6]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link[7]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link training success
pa[0] linkEn = 0xf
pa[0] allNodeLink0 = 0x0
pa[0] allNodeLink1 = 0xf000f
pa[0] connected with sw node
pa[1] linkEn = 0xf
pa[1] allNodeLink0 = 0x8420
pa[1] allNodeLink1 = 0x10001
pa[1] connected with sw node
pa init success
COM_PAID_INTLV_REG = 0xe
paid decode init success
pa[0] PA_PM_BASE_INFO = 0x0
pa[0] PA_PM_MAP_LINK_NUM = 0x1111
pa[1] PA_PM_BASE_INFO = 0xee0842
pa[1] PA_PM_MAP_LINK_NUM = 0x2811
hccs performace config success
pa ring link up success
hccs init done
hccs access test start
node[0] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[1] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[2] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[3] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[1] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
node[2] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
node[3] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
hccs access test success
======hccs status======
  node[0] mask: expected = 0xff, link up = 0xff, width reduction = 0x0, link down = 0x0
  node[1] mask: expected = 0xff, link up = 0xff, width reduction = 0x0, link down = 0x0
  node[2] mask: expected = 0xff, link up = 0xff, width reduction = 0x0, link down = 0x0
  node[3] mask: expected = 0xff, link up = 0xff, width reduction = 0x0, link down = 0x0
==========end==========
report hccs status success
node[0] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
LRDXSD_LOCK_OFFSET = 0x0
LRDXSD_ERRIMSK_OFFSET = 0x0
LRDXSD_DBG_OTIMSK_OFFSET = 0x0
LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
LRDXSD_DBG_EN_OFFSET = 0x1
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
ID[0x1967c8]!
[ERR]Don't support the flash, CS[0] ID[0x1967c8]!!
ID[0xffffff]!
[ERR]Don't support the flash, CS[1] ID[0xffffff]!!
[ERR]Warnning, Select Default flash 
sfdp detect, try to get dummy data from hboot1 first.
ID[0x1967c8]!
flash 0 support sfdp.
Interrupt 423 register OK
Interrupt 425 register OK
Interrupt 427 register OK
Interrupt 429 register OK
Interrupt 430 register OK
Interrupt 431 register OK
Interrupt 436 register OK

cpu 0 entering scheduler
[IMU] Watchdog Initialization done!
ScmiTaskEntry start.
Interrupt 456 register OK
Interrupt 469 register OK
Interrupt 482 register OK
Interrupt 495 register OK
Interrupt 508 register OK
Interrupt 521 register OK
Interrupt 534 register OK
Interrupt 547 register OK
starting Fpc Isolation Task end
starting fdm Err Info Task end
starting Roce recovery Task end
starting Ce_Storm Contrl Task end
starting Ras_Data_Update Task end
power register ubios call id
Interrupt 459 register OK
Interrupt 472 register OK
Interrupt 485 register OK
Interrupt 498 register OK
Interrupt 511 register OK
Interrupt 524 register OK
Interrupt 537 register OK
Interrupt 550 register OK
[0.00.46.849]Real time now 2026.5.14 07:20:49
NIC CARD[0][0]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[0][1]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[1][0]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[1][1]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[2][0]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[2][1]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[3][0]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[3][1]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
Init heart-beat-task end
Init Seam