 Q      ExpBoard1 Q	    @                       Q9  ` p  d        i      1711 Core Temp Q  -      TS200-2280 Q P     BMCCard Q       BMC Q      FanBoard1 Q      PSU2	 Q      PSU1
 Q      NIC 2 (SF221Q) Q#  `c@o             SYS_Boot Q      M2TransferCard6
 Q      PCIe Riser1 Q 	     Zijin-DPU Q$  `c@#o         Watchdog2 Q(  `c@(o ! ! !         Mngmnt Health Q*  
`c!o            PS1 Temp Status Q4  
`h        p                   PSU1_POut Q:  
`h                             PSU1_Inlet_Temp Q&    c@	             Power_Fault Q2  	
`h                              PS1 IIn Q4  

`h                             PSU1_Temp Q3  
`h                              PS1 IOUT Q&  
`co O O O         PSU1_Supply Q3  
`h        p 4                  PSU1_PIn Q3  
`h                              PSU1_VIn Q4  
`h                              PSU1_VOut Q(  `c@            Redundant_PSU Q7  a                             SSD MAX Temp Q(  ac            PwrCap Status Q5  a                             Disks Temp  Q6  ah                             Total_Power! Q*   ~co            P1_CE_D0_Status" Q*   co            P1_CF_D0_Status# Q*   cco            P0_C3_D0_Status$ Q*   aco            P0_C1_D0_Status% Q*   oco            P0_CF_D0_Status& Q*   gco            P0_C7_D0_Status' Q*   ico            P0_C9_D0_Status( Q*   lco            P0_CC_D0_Status) Q*   fco            P0_C6_D0_Status* Q*   bco            P0_C2_D0_Status+ Q*   nco            P0_CE_D0_Status, Q*    tco            P1_C4_D0_Status- Q*  ! {co            P1_CB_D0_Status. Q*  " |co            P1_CC_D0_Status/ Q*  # wco            P1_C7_D0_Status0 Q*  $ xco            P1_C8_D0_Status1 Q*  % sco            P1_C3_D0_Status2 Q*  & `co            P0_C0_D0_Status3 Q*  ' kco            P0_CB_D0_Status4 Q*  ( hco            P0_C8_D0_Status5 Q*  ) jco            P0_CA_D0_Status6 Q*  * mco            P0_CD_D0_Status7 Q*  + pco            P1_C0_D0_Status8 Q*  , }co            P1_CD_D0_Status9 Q*  - qco            P1_C1_D0_Status: Q*  . zco            P1_CA_D0_Status; Q*  / vco            P1_C6_D0_Status< Q*  0 uco            P1_C5_D0_Status= Q*  1 dco            P0_C4_D0_Status> Q*  2 rco            P1_C2_D0_Status? Q*  3 yco            P1_C9_D0_Status@ Q*  4 eco            P0_C5_D0_StatusA Q$  5bc@o 4   $         Event_LogB Q'  6bc@            Op. Log FullC Q(  7bc@            Sec. Log FullD Q7  8c         ~     *              FAN4_F_SpeedE Q7  9c         ~     *              FAN4_R_SpeedF Q&  :3c
o            M2_1_StatusG Q&  ;2c
o            M2_0_StatusH Q2  <eh        d                 M2_TempI Q4  =
ah                              PSU2_VOutJ Q*  >
ac!o            PS2 Temp StatusK Q4  ?
ah        p u                  PSU2_POutL Q:  @
ah                             PSU2_Inlet_TempM Q&  A  c@	             Power_FaultN Q2  B
ah                              PS2 IInO Q4  C
ah                             PSU2_TempP Q3  D
ah                              PS2 IOUTQ Q&  E
aco O O O         PSU2_SupplyR Q3  F
ah        p                   PSU2_PInS Q3  G
ah                              PSU2_VInT Q7  H`         ~     *              FAN1_R_SpeedU Q7  I`         ~     *              FAN1_F_SpeedV Q'  Jac@
            FAN1_PresentW Q'  Kfc@
            FAN2_PresentX Q'  Lbc@
            FAN3_PresentY Q6  Me
              *              PUMP2 SpeedZ Q(  Nfc!o            FAN2_F_Status[ Q(  Odc!o            FAN4_R_Status\ Q4  Puh        d                  CLU1 Temp] Q(  Qbc!o            FAN3_R_Status^ Q(  Rfc!o            FAN2_R_Status_ Q(  Sac!o            FAN1_F_Status` Q(  Tbc!o            FAN3_F_Statusa Q(  Udc!o            FAN4_F_Statusb Q6  Vg
              *              PUMP1 Speedc Q(  Wac!o            FAN1_R_Statusd Q'  Xdc@
            FAN4_Presente Q&  Y  c@	             Power_Faultf Q6  Zah p  d         i      Riser1_Tempg Q:  [f        d                  DPU_FPGA_InTemph Q;  \f        d                  DPU_FPGA_OutTempi Q8  ]f p  d         d      DPU_FPGA_Tempj Q9  ^f         d                   DPU_DIMM_Powerk Q:  _f p  d         }      DPU_FPGA_VRTempl Q*  `fc@o
0
0
0         DPU_PCIE_Statusm Q9  af         d                   DPU_FPGA_Powern Q8  bf p  d         K      DPU_OPT0_Tempo Q:  cf         d                   DPU_Total_Powerp Q:  df        d                  DPU_CPU_OutTempq Q6  ef        d                  DPU_M2_Tempr Q8  ffh         d                   DPU_CPU_Powers Q%  gfc@o            DPU_PWR_Ont Q*  hfc@o         DPU_CPU0_Statusu Q)  ifc@o @   @         DPU_SOC_Statusv Q(  jfc@o         DPU_P0_G0_Hotw Q'  kfc@o            DPU_P0_C0_D0x Q'  lfc@o            DPU_P0_C1_D0y Q9  mf        d                 DPU_CPU_InTempz Q*  nfc@o 0 0 0         DPU_FPGA_Status{ Q8  of p  d         K      DPU_OPT1_Temp| Q8  pf        d                  DPU_DIMM_Temp} Q9  qf p  d         }      DPU_MEM_VRTemp~ Q9  rf p  d         }      DPU_CPU_VRTemp Q'  s  c@o
0
0
0         PCIe2_Status Q7  tf p  d         d      DPU_CPU_Temp Q'  ufc@o            DPU_PWR_Drop Q(  vfc@             DPU_ME_Status Q;  w`       n    y  c    CPU1 1V1_TBTA_VQ Q;  xah p  d          x      CPU2 0V9_N4 Temp Q&  ycc@	             Power_Fault Q$  zcc@+o             FW_Update Q;  {`h p  d          x      CPU1 0V9_N4 Temp Q;  |`       P    X  H    CPU1 0V8_N3_DVDD Q;  }a       x      l    CPU2 1V2_N2_AVDD Q;  ~`h p  d          x      CPU1 0V8_N3 Temp Q:  c       n    z  b    BCU1 3V3_RISER2 Q;  a       x      l    CPU2 1V2_N3_AVDD Q;  `       P    c  C    CPU1 0V9_N1_DVDD Q;  ah p  d          x      CPU2 TDCORE Temp Q;  `h p  d          x      CPU1 N3AVDD Temp Q;  `h p  d          x      CPU1 N4AVDD Temp Q;  a       P    X  H    CPU2 0V8_N1N4_DV Q;  `       x      l    CPU1 1V2_N4_AVDD Q;  `       P    c  D    CPU1 0V9_N2_DVDD Q;  `h p  d          x      CPU1 0V9_N3 Temp Q;  `h p  d          x      CPU1 TDTCVD Temp Q;  `h p  d          x      CPU1 N1N4DV Temp Q7  ah              x      CPU2_VR_Temp Q;  a       P    c  D    CPU2 0V7_TBTA_VD Q*  cc@+             BMC_Update_Fail Q;  a       P    c  D    CPU2 0V7_TDTC_VD Q:  
bh                        ((   BCU1 12V0_1 Pwr Q:  
bh         @              ((   BCU1 12V0_2 Pwr Q;  a       P    X  H    CPU2 0V8_N2_DVDD Q;  ah p  d          x      CPU2 0V8_N2 Temp Q:  
bh         @              ((   BCU1 12V0_3 Pwr Q;  a       P    X  H    CPU2 0V8_N3_DVDD Q5  c                 SYS_12V0_4 Q;  `       P      :    CPU1 0V9_TC_CORE Q5  c                 SYS_12V0_2 Q&  `c@o         CPU1_Status Q;  `       P    c  D    CPU1 0V7_TDTC_VD Q;  a       P    n  C    CPU2 0V9_TDTC_UC Q;  `       P    X  H    CPU1 0V8_N1N4_DV Q;  a       P      :    CPU2 0V9_TD_CORE Q;  a       n    y  c    CPU2 1V1_TBTA_VQ Q;  `       P    X  H    CPU1 0V8_N2_DVDD Q;  `h p  d          x      CPU1 0V8_N2 Temp Q4  arr  d       ni      CPU2_Temp Q;  `       n      l    CPU1 1V2_N3_AVDD Q'  cc@o             BIOS_Boot_Up Q4  `h                             MEM_Power Q;  `h p  d          x      CPU1 N1AVDD Temp Q;  `       x      l    CPU1 1V2_N1_AVDD Q;  ah p  d          x      CPU2 TACORE Temp Q;  `       n    y  c    CPU1 1V1_TDTC_VQ Q;  `       P      :    CPU1 0V9_TD_CORE Q;  ah p  d          x      CPU2 N4AVDD Temp Q;  ah p  d          x      CPU2 N3AVDD Temp Q;  a       P    c  D    CPU2 0V9_N3_DVDD Q;  `h p  d          x      CPU1 TBCORE Temp Q7  `h              x      CPU1_VR_Temp Q;  ah p  d          x      CPU2 N2AVDD Temp Q;  `       P    n  C    CPU1 0V9_TDTC_UC Q;  `       n      l    CPU1 1V2_N2_AVDD Q9  `h                             CPU1_MEM_Power Q;  `       P    c  D    CPU1 0V9_N3_DVDD Q;  `h p  d          x      CPU1 TDTCUC Temp Q(  cc@            System Notice Q;  a       P      :    CPU2 0V9_TC_CORE Q;  ah p  d          x      CPU2 TBTAUC Temp Q;  ah p  d          x      CPU2 TBTAVD Temp Q4  `rr  d       ni      CPU1_Temp Q:  
bh                        ((   BCU1 12V0_4 Pwr Q%  cco            Boot Error Q;  `h p  d          x      CPU1 TCCORE Temp Q"  cc@)o          P3V_BAT Q;  `h p  d          x      CPU1 TDCORE Temp Q;  `h p  d          x      CPU1 TDTCVQ Temp Q9  %a p           _      CPU2_DIMM_Temp Q;  `h p  d          x      CPU1 0V9_N1 Temp Q8  
bh                       ((   BCU1 stby Pwr Q;  a       P    c  C    CPU2 0V9_N1_DVDD Q;  ah p  d          x      CPU2 0V8_N3 Temp Q9  %` p           _      CPU1_DIMM_Temp Q;  `       P    c  D    CPU1 0V7_TBTA_VD Q;  `       P      :    CPU1 0V9_TA_CORE Q+  cc@+             BIOS_Update_Fail Q;  a       n      l    CPU2 1V2_N4_AVDD Q;  `       P    n  C    CPU1 0V9_TBTA_UC Q;  ah p  d          x      CPU2 N1AVDD Temp Q;  `       P      :    CPU1 0V9_TB_CORE Q;  a       P    c  D    CPU2 0V9_N2_DVDD Q;  ah p  d          x      CPU2 N1N4DV Temp Q;  `h p  d          x      CPU1 N2AVDD Temp Q;  ah p  d          x      CPU2 0V9_N3 Temp Q;  `h p  d          x      CPU1 TACORE Temp Q;  a       P    c  D    CPU2 0V9_N4_DVDD Q;  `h p  d          x      CPU1 TBTAVD Temp Q;  a       P      :    CPU2 0V9_TA_CORE Q;  `h p  d          x      CPU1 TBTAVQ Temp Q;  `h p  d          x      CPU1 0V9_N2 Temp Q&  ac@o         CPU2_Status Q#  cc@o             BMC_Boot Q9  ah                             CPU2_MEM_Power Q4  c                             CPU_Power Q3  c       n    z  b    SYS_3.3V Q5  c                 SYS_12V0_3 Q;  ah p  d          x      CPU2 TBCORE Temp Q9  c       B    H  <    BCU1 VCC_DRMOS Q;  `h p  d          x      CPU1 TBTAUC Temp Q'  cc@o            System Error Q"  cc@o             OS_Boot Q'  cco            SYS_Progress Q6  `h                             CPU1_VR_Pwr Q;  `       P    c  D    CPU1 0V9_N4_DVDD Q6  ah                             CPU2_VR_Pwr Q;  ah p  d          x      CPU2 0V9_N2 Temp Q;  a       n    y  c    CPU2 1V1_TDTC_VQ Q;  ah p  d          x      CPU2 TBTAVQ Temp Q;  ah p  d          x      CPU2 TCCORE Temp Q6  ch p           K      NIC OM Temp Q;  ah p  d          x      CPU2 TDTCUC Temp Q;  a       x      l    CPU2 1V2_N1_AVDD Q;  a       P    n  C    CPU2 0V9_TBTA_UC Q;  ah p  d          x      CPU2 TDTCVD Temp Q;  ah p  d          x      CPU2 0V9_N1 Temp Q;  ah p  d          x      CPU2 TDTCVQ Temp Q4  `h                         BCU1 Temp Q;  a       P      :    CPU2 0V9_TB_CORE Q7  h         ~     *              FAN2_F_Speed Q7  h         ~     *              FAN2_R_Speed  Q7  i         ~     *              FAN3_R_Speed Q7  i         ~     *              FAN3_F_Speed Q6  dh p  d        K      Outlet_Temp Q5  7`hrr  d       +)      Inlet_Temp Q:  d                  EXU1 VCC_12V0_1 Q:  d                  EXU1 VCC_12V0_3 Q7  d        d    n  Z    EXU1 VCC_5V0 Q8  d        d    n  Z    EXU1 STBY_5V0 Q'  dc@o             Power_Button	 Q8  dh                           EXU1 PSU Temp
 Q9  dh                           EXU1 NIC1 Temp Q9  dh                           EXU1 NIC2 Temp Q4 d                          FAN_Power
 Q& dc@	             Power_Fault Q% dc@"o a   a         ACPI_State Q: d                  EXU1 VCC_12V0_2 Q% dc@o             UID_Button Q8 d                  EXU1 STBY_3V3 Q* dc@o            PwrOk Sig. Drop Q( dc@o            PwrOn TimeOut Q4 	*`h p  d        s      NIC2 Temp Q      CpuBoard1