
IPU1log=ail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_volt:1122 mV | pmu:MP2882
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[0] volt =  904 mV
pwr domain
HSM0log=] succeed to do thirdparty boot_profile_driver init
[00:01:13.305][info] succeed to do thirdparty crypto_driver init
[00:01:13.311][info] succeed to do thirdparty period_driver init
[00:01:13.316][info]  start loading interna
IMU0log=eady.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait th
IPU0log=mu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pmbus:0x480c0000 ver:0x110
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
IPU1log=[9] volt = 1107 mV
=end=
w&h rd rail:0, 904
w&h rd rail:1, 1107
pwr domain[0] set volt  902 mV succ
pwr domain[9] set volt 1107 mV succ
volt post
pwr domain[0] volt =  902 mV
pwr domain[9] volt = 1107 mV
==end==
Totem[0] Core Bo
HSM0log=l task ...
[00:01:13.321][info]  task name is ccm_task
[00:01:13.325][info]  hm_dynamic_loadelf successfully!
[00:01:13.330][info] internal task[1] task_name=ccm_task load successfully
[00:01:13.337][info]  task name is upgr
IMU0log=e cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master I
IPU0log=
avsbus resync succ
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[2] volt =  904 mV
pwr domain[7] volt =  804 mV
pwr domain[4] volt =  804 mV
pwr domain[1] volt =  806 mV
=end=
w&h rd rail:
IPU1log=ot Vol [1044]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2,
HSM0log=ade_task
[00:01:13.341][info]  hm_dynamic_loadelf successfully!
[00:01:13.346][info] internal task[2] task_name=upgrade_task load successfully
[00:01:13.353][info] created task ccm_task success!
[00:01:13.357][info] created 
IMU0log=mu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
send IMU_INIT_END to cpld.
cpu 0 entering scheduler
|-------------
IPU0log=0, 904
w&h rd rail:1, 806
pwr domain[2] set volt  902 mV succ
pwr domain[7] set volt  804 mV succ
w&h rd rail:0, 802
w&h rd rail:1, 806
pwr domain[4] set volt  802 mV succ
pwr domain[1] set volt  804 mV succ
volt post
pwr domain
IPU1log= ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd8
HSM0log=task upgrade_task success!
[1970-01-01 00:01:13.362][HSM][INFO][54] Platform init 0x20250523 0x4e.
[1970-01-01 00:01:13.368][HSM][INFO][197] ccm start.
[1970-01-01 00:01:13.373][HSM][INFO][86] upgrade task init success.
[197
IMU0log=-------------------------------------|
AtsPrint
|idx|lockCount| srcAddr| destAddr| addrLen|
|--------------------------------------------------|
|  0|00000000|0x010500000|0x000110800000|0x00100000|
|  1|00000000|0x020000000|0x00
IPU0log=[2] volt =  902 mV
pwr domain[7] volt =  804 mV
pwr domain[4] volt =  802 mV
pwr domain[1] volt =  804 mV
==end==
Totem[0] Core Boot Vol [1051]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0,
IPU1log=00, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
opposite dieId: 0, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 
HSM0log=0-01-01 00:01:13.379][HSM][INFO][95] upgrade recv cmd, 0x181.
[1970-01-01 00:01:13.385][HSM][INFO][103] upgrade res, 0x3a5aa5a3.
.
IMU0log=001d000000|0x00800000|
|  2|00000000|0x020800000|0x000490000000|0x00100000|
|  3|00000000|0x020900000|0x000004000000|0x08000000|
|  4|00000000|0x028900000|0x000440580000|0x01000000|
|  5|00000000|0x029900000|0x000590000000|0x001
IPU0log= MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 
IPU1log=enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
hiboost task entry
boost wait SEF.
[INFO] mem used of task 'app_Task' is:0x2028, not zero when task being deleted
boost param OK.
Totem[0] Core[ 0] Freq Limit Low
HSM0log=
IMU0log=00000|
|  6|00000000|0x029a00000|0x002000150000|0x00100000|
|  7|00000000|0x000000000|0x000000000000|0x00000000|
|  8|00000000|0x040000000|0x000000000000|0x08000000|
|  9|00000000|0x048000000|0x000000000000|0x08000000|
| 10|0000
IPU0log=0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
tsensor type
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Fr
HSM0log=
IMU0log=0000|0x050000000|0x000000000000|0x08000000|
| 11|00000000|0x058000000|0x000000000000|0x08000000|
| 12|00000000|0x060000000|0x000000000000|0x08000000|
| 13|00000000|0x068000000|0x000000000000|0x08000000|
| 14|00000000|0x070000000
IPU0log=: 3, ppuFormatK: 0x4da6, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b4,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 3, mask: fffffff8
tsensor type: 4, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=|0x000000000000|0x08000000|
| 15|00000000|0x078000000|0x0028c8000000|0x08000000|
|--------------------------------------------------|
=~=~=~=~=~=~=~=~=~=~= IMU Log @ 2026.5.21 11:10:46 =~=~=~=~=~=~=~=~=~=~=
[IMU] Watchdog Initia
IPU0log=0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 4, mask: ffffffee
tsensor type: 5, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1

IPU1log= Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=lization done!
[RegisterInterruptSource]:[21] begin
Interrupt 32 register OK
Interrupt 34 register OK
Interrupt 40 register OK
Interrupt 44 register OK
sram cnt 0x0, id = 43
Interrupt 43 register OK
Interrupt 36 register OK
In
IPU0log=tsensor: 5, mask: ffffffda
tsensor type: 6, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 6, mask: ffffff80
tsensor type: 7, ppuFormatK: 0x437a,
IPU1log=KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=terrupt 57 register OK
sram cnt 0x0, id = 42
Interrupt 42 register OK
Interrupt 37 register OK
[RegisterInterruptSource]:[39] end
IPMB initialization Start...
IPMB clock set done, prer = 0x18.
IPMB Rx FIFO clear empty.
IPMB 
IPU0log= ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 7, mask: fffffffe
opposite dieId: 1, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
CPM max V[900]-
IPU1log= Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low
HSM0log=
IMU0log=initialization Done.
starting DFX Collect Task end
PowerTask Entry ...
Wait all vrd init done ...
All vrd init done, power task start
refresh domainId 0 Lsb 0x0
refresh domainId 9 Lsb 0x1
refresh domainId 2 Lsb 0x0
refresh dom
IPU0log=F:2800
CPM min V[750]-F:1600
freq:2350, idx:9
cpm trim freq: 2600, idx: 4
cpm trim finish
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
recount hours 
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Fr
HSM0log=
IMU0log=ainId 7 Lsb 0x1
refresh domainId 4 Lsb 0x0
refresh domainId 1 Lsb 0x1
power sensor[0] | calib:5120 | rshunt:1 | rshuntDiv:1000 | currLsb:1 | currLsbDiv:1000 | enableFlag:1
                | pwrLsb:25 | defPwr:25000 | minPwr:1000
IPU0log=0x4b0 
hiboost task entry
boost wait SEF.
boost param OK.
Totem[0] Core[ 0] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[26
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=0 | maxPwr:65000 | pwrFix:-3400
                | manufacturerId: 0x5549 | dieId: 0x2260
power sensor[0] init success
ScmiTaskEntry start.
[RegisterInterruptSource]:[21] begin
Interrupt 51 register OK
[RegisterInterruptSource]:
IPU0log=00000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[12000
IPU1log= Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 52 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 53 register OK
[RegisterInterruptSource]:[39] end
[0.01.32.116]startin
IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Lim
IPU1log=KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=g ras Init
RAS Setup Value get done!
INT_NUM_PER_SKT * HiGetSktNum() = 0x8
index = 0x0
RasIntRegister init 160 
index = 0x1
RasIntRegister init 172 
index = 0x2
RasIntRegister init 162 
index = 0x3
RasIntRegister init 174 
index
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IPU1log= Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low
HSM0log=
IMU0log= = 0x4
RasIntRegister init 184 
index = 0x5
RasIntRegister init 196 
index = 0x6
RasIntRegister init 186 
index = 0x7
RasIntRegister init 198 
RasIntRegister init 161 
RasIntRegister init 173 
RasIntRegister init 185 
RasIntRegi
IPU0log=14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
To
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[42] Fr
IMU0log=1T1N1U skt:0 CfgBusDfxPreConfig finish

********Hello Huawei LiteOS********

IMU Firmware Version : B173V01
LiteOS Kernel Version : 5.10.0
Run on Socket[0] Die[3]
Chip Version: 1
Max socket num: 2
*******************************
IPU0log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 0
cls: 6, core: 8
cpu 914 sram 1031 ddr 886
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  775|  841|  927|  980|
max  v
IPU1log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 1
cls: 6, core: 8
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  769|  835|  920|  973|
max  v: |  750|  750|  763|  790
HSM0log=[1970-01-01 00:01:12.538][HSM][INFO][30] init start
[1970-01-01 00:01:12.538][HSM][INFO][38] init over
[00:01:12.547][info] succeed to do thirdparty dfx_pabuk init
[00:01:12.553][info] os_mem_system_init default pool done
[0
IMU0log=***
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | rail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_vo
IPU0log=: |  750|  750|  761|  790|  863|  955| 1016|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:7
IPU1log=|  859|  950| 1009|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:750 F:1950
avs-uncore V:750
HSM0log=0:01:12.559][info] addr is already in region
[00:01:12.562][info] succeed to do thirdparty otpc_pabuk init
[1970-01-01 00:01:12.568][HSM][INFO][31] select_region: 0xc11cb55b
[1970-01-01 00:01:12.574][HSM][INFO][67] spi_nor de
IMU0log=lt:1122 mV | pmu:MP2882
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_v
IPU0log=50 F:1950
avs-uncore V:750 F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
av
IPU1log= F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
avs-uncore V:840 F:2450
avs-
HSM0log=vice_id 0xff1a67c8
[1970-01-01 00:01:12.580][HSM][INFO][50] std_cmd readback 0x30220d8
[1970-01-01 00:01:12.586][HSM][INFO][72] saf_cmd 0x0 readback 0x9f5a0604
[1970-01-01 00:01:12.592][HSM][INFO][72] saf_cmd 0x1 readback 0x5
IMU0log=olt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_
IPU0log=s-uncore V:840 F:2450
avs-uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain
IPU1log=uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | r
HSM0log=b7e938
[1970-01-01 00:01:12.598][HSM][INFO][72] saf_cmd 0x2 readback 0x1
[1970-01-01 00:01:12.604][HSM][INFO][72] saf_cmd 0x3 readback 0x0
[1970-01-01 00:01:12.610][HSM][INFO][72] saf_cmd 0x4 readback 0x0
[00:01:12.616][info
IMU0log=volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus r
IPU0log=[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | p
IPU1log=ail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_volt:1122 mV | pmu:MP2882
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[0] volt =  902 mV
pwr domain
HSM0log=] succeed to do thirdparty boot_profile_driver init
[00:01:12.622][info] succeed to do thirdparty crypto_driver init
[00:01:12.628][info] succeed to do thirdparty period_driver init
[00:01:12.634][info]  start loading interna
IMU0log=eady.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait th
IPU0log=mu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pmbus:0x480c0000 ver:0x110
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
IPU1log=[9] volt = 1107 mV
=end=
w&h rd rail:0, 904
w&h rd rail:1, 1107
pwr domain[0] set volt  902 mV succ
pwr domain[9] set volt 1107 mV succ
volt post
pwr domain[0] volt =  902 mV
pwr domain[9] volt = 1107 mV
==end==
Totem[0] Core Bo
HSM0log=l task ...
[00:01:12.638][info]  task name is ccm_task
[00:01:12.642][info]  hm_dynamic_loadelf successfully!
[00:01:12.647][info] internal task[1] task_name=ccm_task load successfully
[00:01:12.654][info]  task name is upgr
IMU0log=e cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master I
IPU0log=
avsbus resync succ
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[2] volt =  904 mV
pwr domain[7] volt =  804 mV
pwr domain[4] volt =  804 mV
pwr domain[1] volt =  806 mV
=end=
w&h rd rail:
IPU1log=ot Vol [1044]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2,
HSM0log=ade_task
[00:01:12.658][info]  hm_dynamic_loadelf successfully!
[00:01:12.663][info] internal task[2] task_name=upgrade_task load successfully
[00:01:12.670][info] created task ccm_task success!
[00:01:12.674][info] created 
IMU0log=mu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
send IMU_INIT_END to cpld.
cpu 0 entering scheduler
|-------------
IPU0log=0, 904
w&h rd rail:1, 804
pwr domain[2] set volt  902 mV succ
pwr domain[7] set volt  802 mV succ
w&h rd rail:0, 804
w&h rd rail:1, 806
pwr domain[4] set volt  802 mV succ
pwr domain[1] set volt  804 mV succ
volt post
pwr domain
IPU1log= ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd8
HSM0log=task upgrade_task success!
[1970-01-01 00:01:12.679][HSM][INFO][54] Platform init 0x20250523 0x4e.
[1970-01-01 00:01:12.686][HSM][INFO][197] ccm start.
[1970-01-01 00:01:12.690][HSM][INFO][86] upgrade task init success.
[197
IMU0log=-------------------------------------|
AtsPrint
|idx|lockCount| srcAddr| destAddr| addrLen|
|--------------------------------------------------|
|  0|00000000|0x010500000|0x000110800000|0x00100000|
|  1|00000000|0x020000000|0x00
IPU0log=[2] volt =  902 mV
pwr domain[7] volt =  802 mV
pwr domain[4] volt =  802 mV
pwr domain[1] volt =  804 mV
==end==
Totem[0] Core Boot Vol [1051]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0,
IPU1log=00, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
opposite dieId: 0, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 
HSM0log=0-01-01 00:01:12.696][HSM][INFO][95] upgrade recv cmd, 0x181.
[1970-01-01 00:01:12.702][HSM][INFO][103] upgrade res, 0x3a5aa5a3.
.
IMU0log=001d000000|0x00800000|
|  2|00000000|0x020800000|0x000490000000|0x00100000|
|  3|00000000|0x020900000|0x000004000000|0x08000000|
|  4|00000000|0x028900000|0x000440580000|0x01000000|
|  5|00000000|0x029900000|0x000590000000|0x001
IPU0log= MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 
IPU1log=enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
hiboost task entry
boost wait SEF.
[INFO] mem used of task 'app_Task' is:0x2028, not zero when task being deleted
boost param OK.
Totem[0] Core[ 0] Freq Limit Low
HSM0log=
IMU0log=00000|
|  6|00000000|0x029a00000|0x002000150000|0x00100000|
|  7|00000000|0x000000000|0x000000000000|0x00000000|
|  8|00000000|0x040000000|0x000000000000|0x08000000|
|  9|00000000|0x048000000|0x000000000000|0x08000000|
| 10|0000
IPU0log=0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
tsensor type
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Fr
HSM0log=
IMU0log=0000|0x050000000|0x000000000000|0x08000000|
| 11|00000000|0x058000000|0x000000000000|0x08000000|
| 12|00000000|0x060000000|0x000000000000|0x08000000|
| 13|00000000|0x068000000|0x000000000000|0x08000000|
| 14|00000000|0x070000000
IPU0log=: 3, ppuFormatK: 0x4da6, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b4,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 3, mask: fffffff8
tsensor type: 4, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=|0x000000000000|0x08000000|
| 15|00000000|0x078000000|0x0028c8000000|0x08000000|
|--------------------------------------------------|
=~=~=~=~=~=~=~=~=~=~= IMU Log @ 2026.5.21 11:19:8 =~=~=~=~=~=~=~=~=~=~=
[IMU] Watchdog Initial
IPU0log=0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 4, mask: ffffffee
tsensor type: 5, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1

IPU1log= Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=ization done!
[RegisterInterruptSource]:[21] begin
Interrupt 32 register OK
Interrupt 34 register OK
Interrupt 40 register OK
Interrupt 44 register OK
sram cnt 0x0, id = 43
Interrupt 43 register OK
Interrupt 36 register OK
Int
IPU0log=tsensor: 5, mask: ffffffda
tsensor type: 6, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 6, mask: ffffff80
tsensor type: 7, ppuFormatK: 0x437a,
IPU1log=KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=errupt 57 register OK
sram cnt 0x0, id = 42
Interrupt 42 register OK
Interrupt 37 register OK
[RegisterInterruptSource]:[39] end
IPMB initialization Start...
IPMB clock set done, prer = 0x18.
IPMB Rx FIFO clear empty.
IPMB i
IPU0log= ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 7, mask: fffffffe
opposite dieId: 1, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
CPM max V[900]-
IPU1log= Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low
HSM0log=
IMU0log=nitialization Done.
starting DFX Collect Task end
PowerTask Entry ...
Wait all vrd init done ...
All vrd init done, power task start
refresh domainId 0 Lsb 0x0
refresh domainId 9 Lsb 0x1
refresh domainId 2 Lsb 0x0
refresh doma
IPU0log=F:2800
CPM min V[750]-F:1600
freq:2350, idx:9
cpm trim freq: 2600, idx: 4
cpm trim finish
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
recount hours 
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Fr
HSM0log=
IMU0log=inId 7 Lsb 0x1
refresh domainId 4 Lsb 0x0
refresh domainId 1 Lsb 0x1
power sensor[0] | calib:5120 | rshunt:1 | rshuntDiv:1000 | currLsb:1 | currLsbDiv:1000 | enableFlag:1
                | pwrLsb:25 | defPwr:25000 | minPwr:10000
IPU0log=0x4b0 
hiboost task entry
boost wait SEF.
boost param OK.
Totem[0] Core[ 0] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[26
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log= | maxPwr:65000 | pwrFix:-3400
                | manufacturerId: 0x5549 | dieId: 0x2260
power sensor[0] init success
ScmiTaskEntry start.
[RegisterInterruptSource]:[21] begin
Interrupt 51 register OK
[RegisterInterruptSource]:[
IPU0log=00000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[12000
IPU1log= Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=39] end
[RegisterInterruptSource]:[21] begin
Interrupt 52 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 53 register OK
[RegisterInterruptSource]:[39] end
[0.01.31.462]starting
IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Lim
IPU1log=KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log= ras Init
RAS Setup Value get done!
INT_NUM_PER_SKT * HiGetSktNum() = 0x8
index = 0x0
RasIntRegister init 160 
index = 0x1
RasIntRegister init 172 
index = 0x2
RasIntRegister init 162 
index = 0x3
RasIntRegister init 174 
index 
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IPU1log= Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low
HSM0log=
IMU0log== 0x4
RasIntRegister init 184 
index = 0x5
RasIntRegister init 196 
index = 0x6
RasIntRegister init 186 
index = 0x7
RasIntRegister init 198 
RasIntRegister init 161 
RasIntRegister init 173 
RasIntRegister init 185 
RasIntRegis
IPU0log=14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
To
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[42] Fr
HSM0log=
IMU0log=ter init 197 
RasIntRegister init 284 
RasIntRegister init 314 
MceTableHeadInit start
starting Ce_Storm Contrl and Ras_Data_Update Task end
[0.01.31.544]starting ras end
[IMU][ERR] skt id 0
Ub init task start Entry ...
UbInitT
IPU0log=tem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[26
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[43] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[44] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[45] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=ask Entry ...
[RegisterInterruptSource]:[21] begin
Interrupt 167 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 191 register OK
[RegisterInterruptSource]:[39] end
[RegisterInte
IPU0log=00000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[12000
IPU1log= Core[46] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[47] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
get tdp value from Product! Tdp value per vdie : 220000 mW!
uncore max freq : 2600 MHz

HSM0log=
IMU0log=rruptSource]:[21] begin
Interrupt 171 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 183 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Int
IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Lim
IPU1log=
HSM0log=
IMU0log=errupt 195 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 207 register OK
[RegisterInterruptSource]:[39] end
Init heart-beat-task end
CS0 flash do not support sfdp!
Current flash
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IPU1log=
HSM0log=
IMU0log= device ID[0x61a67c8]!
System supported 1 Flash.
flash cs 0 Manufacture 0xc8, DeviceId 0x1a67, AddrMode[0-3B,1-4B] 0x1:
    size 0x4000000, pagesize 0x100
    read  cmd 0x13, dummy byte 0x8
    write cmd 0x12, dummy byte 0x0
   
IPU0log=33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
To
IPU1log=
HSM0log=
IMU0log= erase4k cmd 0x21, erase64k byte 0xdc
sfc init end
firstUnMskExt0Int
ThermalDimmStart Entry ...
wait ddr init done...
HacLowPowerStart Entry ...
Hello LiteOS...
pwr cap[0]: 0, 67
Init ReportPcieMmioToBmcTaskEntry end
startin
IPU0log=tem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[26
IPU1log=
HSM0log=
IMU0log=g Fpc Isolation Task end
pwr cap[1]: ea, 2
pwr cap[2]: 1, 3
BMC_COLLECTION: bmc req last log!
DDR initing...
BMC_COLLECTION: bmc req last log!
DDR initing...
[0.02.00.021]DDR init done
[LOG]head = 0x0, tail = 0x18c7, logSize =
IPU0log=00000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[42] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[43] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[44] Freq Limit Low[12000
IPU1log=
HSM0log=
IMU0log= 0x18c7
[IMU][ERR] HsmLogInit!
[IMU][ERR] HsmLogInit! TRUE
ddr init done, start thermal dimm task
======dimm status======
  chl[0] dimm0 0, dimm1 0
  chl[1] dimm0 1, dimm1 0
  chl[2] dimm0 0, dimm1 0
  chl[3] dimm0 0, dimm1 0
  
IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[45] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[46] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[47] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
get tdp value from Product
IPU1log=
HSM0log=
IMU0log=chl[4] dimm0 0, dimm1 0
  chl[5] dimm0 0, dimm1 0
  chl[6] dimm0 0, dimm1 0
  chl[7] dimm0 0, dimm1 0
  chl[8] dimm0 0, dimm1 0
  chl[9] dimm0 0, dimm1 0
  chl[10] dimm0 0, dimm1 0
  chl[11] dimm0 0, dimm1 0
==========end=======
IPU0log=! Tdp value per vdie : 220000 mW!
uncore max freq : 2600 MHz

IPU1log=
HSM0log=
IMU0log====
sktId[0] chl[1] registered, dimm mask = 0x1
======dimm status======
  chl[0] dimm0 0, dimm1 0
  chl[1] dimm0 0, dimm1 0
  chl[2] dimm0 0, dimm1 0
  chl[3] dimm0 0, dimm1 0
  chl[4] dimm0 0, dimm1 0
  chl[5] dimm0 0, dimm1 0

IPU0log=
IPU1log=
HSM0log=
IMU0log=  chl[6] dimm0 0, dimm1 0
  chl[7] dimm0 0, dimm1 0
  chl[8] dimm0 0, dimm1 0
  chl[9] dimm0 0, dimm1 0
  chl[10] dimm0 0, dimm1 0
  chl[11] dimm0 0, dimm1 0
==========end==========
=====dimm temp params=====
  temp_threshold   
IPU0log=
IPU1log=
HSM0log=
IMU0log=   : temp_mid:85,85 | temp_hi:95 | temp_cri:100
  is_thermal_thro_en  : 1
  is_aref_rate_auto   : 0
===========end============
set apei done!
UbConfigData size is 64
UbConfigData 0 : 0
UbConfigData 1 : 0
UbConfigData 2 : 0
UbCon
IPU0log=
IPU1log=
HSM0log=
IMU0log=figData 3 : 1
UbConfigData 4 : 31
UbConfigData 5 : 1
UbConfigData 6 : 0
UbConfigData 7 : 32
UbConfigData 8 : 0
UbConfigData 9 : 1
UbConfigData 10 : 2
UbConfigData 11 : 0
UbConfigData 12 : 0
UbConfigData 13 : 1
UbConfigData 14 : 
IPU0log=
IPU1log=
HSM0log=
IMU0log=0
UbConfigData 15 : 0
UbConfigData 16 : 0
UbConfigData 17 : 0
UbConfigData 18 : 0
UbConfigData 19 : 0
UbConfigData 20 : 0
UbConfigData 21 : 0
UbConfigData 22 : 11
UbConfigData 23 : 0
UbConfigData 24 : 0
UbConfigData 25 : 0
UbCon
IPU0log=
IPU1log=
HSM0log=
IMU0log=figData 26 : 0
UbConfigData 27 : 0
UbConfigData 28 : 0
UbConfigData 29 : 0
UbConfigData 30 : 0
UbConfigData 31 : 0
UbConfigData 32 : 0
UbConfigData 33 : 0
UbConfigData 34 : 0
UbConfigData 35 : 1
UbConfigData 36 : 0
UbConfigData 
IPU0log=
IPU1log=
HSM0log=
IMU0log=37 : 0
UbConfigData 38 : 0
UbConfigData 39 : 0
UbConfigData 40 : 0
UbConfigData 41 : 0
UbConfigData 42 : 0
UbConfigData 43 : 0
UbConfigData 44 : 0
UbConfigData 45 : 0
UbConfigData 46 : 0
UbConfigData 47 : 0
UbConfigData 48 : 0
U
IPU0log=
IPU1log=
HSM0log=
IMU0log=bConfigData 49 : 0
UbConfigData 50 : 0
UbConfigData 51 : 0
UbConfigData 52 : 0
UbConfigData 53 : 0
UbConfigData 54 : 0
UbConfigData 55 : 0
UbConfigData 56 : 0
UbConfigData 57 : 0
UbConfigData 58 : 0
UbConfigData 59 : 0
UbConfigD
IPU0log=
IPU1log=
HSM0log=
IMU0log=ata 60 : 0
UbConfigData 61 : 0
UbConfigData 62 : 0
UbConfigData 63 : 0
UbConfigData 64 : 0
ClusterSwitch: 0, 0
ClusterMode: 0, 0
ControlMode: 0, 0
EnumMode: 1, 1
BodyMask: 31, 31
CcCtxCount: 256, 256
RcCtxCount: 32, 32
UbMemEntr
IPU0log=
IPU1log=
HSM0log=
IMU0log=ySize: 128, 0
MctpSupport: 1, 1
SecureMode: 0, 0
PrimaryCna: 0, 0
Upi: 0, 0
EntityId: 0, 0
SlotId: 1, 1
SocketId: 2, 2
PortIndex: 0, 0
PortCna: 0, 0
CtrlCna: 11, 11
ImpBootFlag: 0, 0
ImuBootFlag: 1, 1
SktId: 0 DieId:2, HCCS_LINK
IPU0log=
IPU1log=
HSM0log=
IMU0log=:2 PaId:2
SktId: 1 DieId:2, HCCS_LINK:0 PaId:0
CIS register: ID[0xc00007ff], owner[0x1000003], function[0x1045df9c].
CIS register: ID[0xc0000002], owner[0x1000003], function[0x1045e03c].
odf: can not find od file[config]
Do not 
IPU0log=
IPU1log=
HSM0log=
IMU0log=get NII route table, disable NII Send function.
UbiosTaskStart Entry ...
UbiosCisTask Entry ...
UbiosTaskStart create task success
IMU ImpBootFlag: 0x0
skip IMP start config...
BMC_COLLECTION: bmc req last log!
[IMU][ERR] [
H
IPU0log=
IPU1log=
HSM0log=
IMU0log=SM0log= no log data error!]
[0.02.07.065]TF Heartbeat Start
[0.02.08.068]RECEIVE MEM SILK.
0: skt = 0 logic = 0 phy = 8 
1: skt = 0 logic = 9 phy = 11 
2: skt = 1 logic = 9 phy = 11 
3: skt = 1 logic = 7 phy = 1 
4: skt = 0 logi
IPU0log=
IPU1log=
HSM0log=
IMU0log=c = 10 phy = 3 
5: skt = 0 logic = 1 phy = 0 
6: skt = 1 logic = 4 phy = 2 
7: skt = 1 logic = 10 phy = 3 
8: skt = 1 logic = 2 phy = 4 
9: skt = 1 logic = 8 phy = 5 
10: skt = 1 logic = 5 phy = 6 
11: skt = 1 logic = 11 phy = 7
IPU0log=
IPU1log=
HSM0log=
IMU0log= 
12: skt = 1 logic = 0 phy = 8 
13: skt = 1 logic = 6 phy = 9 
14: skt = 1 logic = 3 phy = 10 
15: skt = 0 logic = 7 phy = 1 
16: skt = 1 logic = 1 phy = 0 
17: skt = 0 logic = 2 phy = 4 
18: skt = 0 logic = 8 phy = 5 
19: skt 
IPU0log=
IPU1log=
HSM0log=
IMU0log== 0 logic = 5 phy = 6 
20: skt = 0 logic = 3 phy = 10 
21: skt = 0 logic = 6 phy = 9 
22: skt = 0 logic = 4 phy = 2 
23: skt = 0 logic = 11 phy = 7 
get mem silk data length: 72
[0.02.13.377]PCIE INIT DONE.
[IMU][ERR] LOS_SemPen
IPU0log=
IPU1log=
HSM0log=
IMU0log=d(g_pcieSemaphore, LOS_WAIT_FOREVER)
[RegisterInterruptSource]:[21] begin
Interrupt 258 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 262 register OK
[RegisterInterruptSource]:[
IPU0log=
IPU1log=
HSM0log=
IMU0log=39] end
[RegisterInterruptSource]:[21] begin
Interrupt 266 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 270 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptS
IPU0log=
IPU1log=
HSM0log=
IMU0log=ource]:[21] begin
Interrupt 277 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 288 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt
IPU0log=
IPU1log=
HSM0log=
IMU0log= 292 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 296 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 300 register OK
[RegisterIn
IPU0log=
IPU1log=
HSM0log=
IMU0log=terruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 307 register OK
[RegisterInterruptSource]:[39] end
pmt Init done

-----------------ROUTE TABLE------------------
entryCount = 2
-------------------------
IPU0log=
IPU1log=
HSM0log=
IMU0log=---------------------
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2500
[No.1]:
eidRange = 1, startEid = 10, port = 0, isStatic =
IPU0log=
IPU1log=
HSM0log=
IMU0log= 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2100
----------------------------------------------
-----------------ROUTE TABLE------------------
entryCount = 2
---------------------------
IPU0log=
IPU1log=
HSM0log=
IMU0log=-------------------
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2500
[No.1]:
eidRange = 1, startEid = 10, port = 0, isStatic = 1
IPU0log=
IPU1log=
HSM0log=
IMU0log=, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2100
----------------------------------------------
-----------------ROUTE TABLE------------------
entryCount = 2
-----------------------------
IPU0log=
IPU1log=
HSM0log=
IMU0log=-----------------
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2500
[No.1]:
eidRange = 1, startEid = 10, port = 0, isStatic = 1, 
IPU0log=
IPU1log=
HSM0log=
IMU0log=entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2100
----------------------------------------------
HotPlug Open
slotNum = 42
portIdx = 0
portIdx = 1
portIdx = 2
portIdx = 3
portIdx = 4
p
IPU0log=
IPU1log=
HSM0log=
IMU0log=ortIdx = 5
portIdx = 6
portIdx = 7
portIdx = 8
portIdx = 9
portIdx = a
portIdx = b
portIdx = c
portIdx = d
portIdx = e
portIdx = f
portIdx = 10
portIdx = 11
portIdx = 12
portIdx = 13
portIdx = 14
portIdx = 15
po
IPU0log=
IPU1log=
HSM0log=
IMU0log=rtIdx = 16
portIdx = 17
portIdx = 18
portIdx = 19
portIdx = 1a
portIdx = 1b
portIdx = 1c
portIdx = 1d
portIdx = 1e
portIdx = 1f
portIdx = 20
portIdx = 40
portIdx = 41
portIdx = 42
portIdx = 43
portIdx = 44
portId
IPU0log=
IPU1log=
HSM0log=
IMU0log=x = 45
portIdx = 46
portIdx = 47
portIdx = 48
portIdx = 49
portIdx = 4a
portIdx = 4b
portIdx = 4c
portIdx = 4d
portIdx = 4e
portIdx = 4f
portIdx = 50
portIdx = 51
portIdx = 52
portIdx = 53
portIdx = 54
portIdx = 
IPU0log=
IPU1log=
HSM0log=
IMU0log=55
portIdx = 56
portIdx = 57
portIdx = 58
portIdx = 59
portIdx = 5a
portIdx = 5b
portIdx = 5c
portIdx = 5d
portIdx = 5e
portIdx = 5f
portIdx = 60
Pcie slot[0] port:0 base 0x2c01000000, pcieSlotCtrl.data (before)0x0.
IPU0log=
IPU1log=
HSM0log=
IMU0log=
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[0] port:0 base 0x2c01000000, pcieSlotCtrl.data (after)0x0.

Pcie slot[1] port:1 base 0x2c01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.prese
IPU0log=
IPU1log=
HSM0log=
IMU0log=ncd_det_st = 1
present:1, pwr_en:0.
Pcie slot[1] port:1 base 0x2c01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[2] port:2 base 0x2c01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
pre
IPU0log=
IPU1log=
HSM0log=
IMU0log=sent:1, pwr_en:0.
Pcie slot[2] port:2 base 0x2c01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[3] port:3 base 0x2c01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.

IPU0log=
IPU1log=
HSM0log=
IMU0log=Pcie slot[3] port:3 base 0x2c01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[4] port:4 base 0x2c01000000, pcieSlotCtrl.data (before)0x10003c0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[4] 
IPU0log=
IPU1log=
HSM0log=
IMU0log=port:4 base 0x2c01000000, pcieSlotCtrl.data (after)0x14801c0.

Pcie slot[5] port:5 base 0x2c01000000, pcieSlotCtrl.data (before)0x3c0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[5] port:5 base 0x2c
IPU0log=
IPU1log=
HSM0log=
IMU0log=01000000, pcieSlotCtrl.data (after)0x4801c0.

Pcie slot[6] port:6 base 0x2c01000000, pcieSlotCtrl.data (before)0x3c0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[6] port:6 base 0x2c01000000, pcieSlo
IPU0log=
IPU1log=
HSM0log=
IMU0log=tCtrl.data (after)0x4801c0.

Pcie slot[7] port:7 base 0x2c01000000, pcieSlotCtrl.data (before)0x3c0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[7] port:7 base 0x2c01000000, pcieSlotCtrl.data (after
IPU0log=
IPU1log=
HSM0log=
IMU0log=)0x4801c0.

Pcie slot[8] port:8 base 0x2c02000000, pcieSlotCtrl.data (before)0x10003c0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[8] port:8 base 0x2c02000000, pcieSlotCtrl.data (after)0x14801c0.

IPU0log=
IPU1log=
HSM0log=
IMU0log=
Pcie slot[9] port:9 base 0x2c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[9] port:9 base 0x2c02000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[10] por
IPU0log=
IPU1log=
HSM0log=
IMU0log=t:10 base 0x2c02000000, pcieSlotCtrl.data (before)0x10003c0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[10] port:10 base 0x2c02000000, pcieSlotCtrl.data (after)0x14801c0.

Pcie slot[11] port:11 bas
IPU0log=
IPU1log=
HSM0log=
IMU0log=e 0x2c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[11] port:11 base 0x2c02000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[12] port:12 base 0x2c02000000,
IPU0log=
IPU1log=
HSM0log=
IMU0log= pcieSlotCtrl.data (before)0x3c0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[12] port:12 base 0x2c02000000, pcieSlotCtrl.data (after)0x7c0.

Pcie slot[13] port:13 base 0x2c02000000, pcieSlotCtrl.da
IPU0log=
IPU1log=
HSM0log=
IMU0log=ta (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[13] port:13 base 0x2c02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[14] port:14 base 0x2c02000000, pcieSlotCtrl.data (before)0x3c0.
IPU0log=
IPU1log=
HSM0log=
IMU0log=
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[14] port:14 base 0x2c02000000, pcieSlotCtrl.data (after)0x7c0.

Pcie slot[15] port:15 base 0x2c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits
IPU0log=
IPU1log=
HSM0log=
IMU0log=.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[15] port:15 base 0x2c02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[16] port:16 base 0x2d01000000, pcieSlotCtrl.data (before)0x10003c0.
pcieSlotCtrl.bits.presencd_de
IPU0log=
IPU1log=
HSM0log=
IMU0log=t_st = 1
present:1, pwr_en:0.
Pcie slot[16] port:16 base 0x2d01000000, pcieSlotCtrl.data (after)0x14801c0.

Pcie slot[17] port:17 base 0x2d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
pres
IPU0log=
IPU1log=
HSM0log=
IMU0log=ent:1, pwr_en:0.
Pcie slot[17] port:17 base 0x2d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[18] port:18 base 0x2d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0
IPU0log=
IPU1log=
HSM0log=
IMU0log=.
Pcie slot[18] port:18 base 0x2d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[19] port:19 base 0x2d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[19
IPU0log=
IPU1log=
HSM0log=
IMU0log=] port:19 base 0x2d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[20] port:20 base 0x2d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[20] port:20 base 
IPU0log=
IPU1log=
HSM0log=
IMU0log=0x2d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[21] port:21 base 0x2d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[21] port:21 base 0x2d01000000, p
IPU0log=
IPU1log=
HSM0log=
IMU0log=cieSlotCtrl.data (after)0x480100.

Pcie slot[22] port:22 base 0x2d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[22] port:22 base 0x2d01000000, pcieSlotCtrl.dat
IPU0log=
IPU1log=
HSM0log=
IMU0log=a (after)0x480100.

Pcie slot[23] port:23 base 0x2d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[23] port:23 base 0x2d01000000, pcieSlotCtrl.data (after)0x4801
IPU0log=
IPU1log=
HSM0log=
IMU0log=00.

Pcie slot[24] port:24 base 0x2d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[24] port:24 base 0x2d02000000, pcieSlotCtrl.data (after)0x0.

Pcie slot[25]
IPU0log=
IPU1log=
HSM0log=
IMU0log= port:25 base 0x2d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[25] port:25 base 0x2d02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[26] port:26 base 0x2d
IPU0log=
IPU1log=
HSM0log=
IMU0log=02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[26] port:26 base 0x2d02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[27] port:27 base 0x2d02000000, pcieSlot
IPU0log=
IPU1log=
HSM0log=
IMU0log=Ctrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[27] port:27 base 0x2d02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[28] port:28 base 0x2d02000000, pcieSlotCtrl.data (before)
IPU0log=
IPU1log=
HSM0log=
IMU0log=0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[28] port:28 base 0x2d02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[29] port:29 base 0x2d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl
IPU0log=
IPU1log=
HSM0log=
IMU0log=.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[29] port:29 base 0x2d02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[30] port:30 base 0x2d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det
IPU0log=
IPU1log=
HSM0log=
IMU0log=_st = 0
present:0, pwr_en:1.
Pcie slot[30] port:30 base 0x2d02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[31] port:31 base 0x2d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0
IPU0log=
IPU1log=
HSM0log=
IMU0log=, pwr_en:1.
Pcie slot[31] port:31 base 0x2d02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[32] port:32 base 0x3210000000, pcieSlotCtrl.data (before)0xffffffff.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
IPU0log=
IPU1log=
HSM0log=
IMU0log=
Pcie slot[32] port:32 base 0x3210000000, pcieSlotCtrl.data (after)0xffffffff.

Pcie slot[33] port:0 base 0x6c01000000, pcieSlotCtrl.data (before)0x3c0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[
IPU0log=
IPU1log=
HSM0log=
IMU0log=33] port:0 base 0x6c01000000, pcieSlotCtrl.data (after)0x7c0.

Pcie slot[34] port:1 base 0x6c01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[34] port:1 base 0x6c
IPU0log=
IPU1log=
HSM0log=
IMU0log=01000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[35] port:2 base 0x6c01000000, pcieSlotCtrl.data (before)0x3c0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[35] port:2 base 0x6c01000000, pcieSlot
IPU0log=
IPU1log=
HSM0log=
IMU0log=Ctrl.data (after)0x7c0.

Pcie slot[36] port:3 base 0x6c01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[36] port:3 base 0x6c01000000, pcieSlotCtrl.data (after)0x7
IPU0log=
IPU1log=
HSM0log=
IMU0log=00.

Pcie slot[37] port:4 base 0x6c01000000, pcieSlotCtrl.data (before)0x3c0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[37] port:4 base 0x6c01000000, pcieSlotCtrl.data (after)0x7c0.

Pcie slot[3
IPU0log=
IPU1log=
HSM0log=
IMU0log=8] port:5 base 0x6c01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[38] port:5 base 0x6c01000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[39] port:6 base 0x6c0
IPU0log=
IPU1log=
HSM0log=
IMU0log=1000000, pcieSlotCtrl.data (before)0x3c0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[39] port:6 base 0x6c01000000, pcieSlotCtrl.data (after)0x7c0.

Pcie slot[40] port:7 base 0x6c01000000, pcieSlotC
IPU0log=
IPU1log=
HSM0log=
IMU0log=trl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[40] port:7 base 0x6c01000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[41] port:8 base 0x6c02000000, pcieSlotCtrl.data (before)0x0
IPU0log=
IPU1log=
HSM0log=
IMU0log=.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[41] port:8 base 0x6c02000000, pcieSlotCtrl.data (after)0x0.

Pcie slot[42] port:9 base 0x6c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.p
IPU0log=
IPU1log=
HSM0log=
IMU0log=resencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[42] port:9 base 0x6c02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[43] port:10 base 0x6c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
IPU0log=
IPU1log=
HSM0log=
IMU0log=
present:0, pwr_en:1.
Pcie slot[43] port:10 base 0x6c02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[44] port:11 base 0x6c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en
IPU0log=
IPU1log=
HSM0log=
IMU0log=:1.
Pcie slot[44] port:11 base 0x6c02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[45] port:12 base 0x6c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[45]
IPU0log=
IPU1log=
HSM0log=
IMU0log= port:12 base 0x6c02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[46] port:13 base 0x6c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[46] port:13 base 0x6c
IPU0log=
IPU1log=
HSM0log=
IMU0log=02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[47] port:14 base 0x6c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[47] port:14 base 0x6c02000000, pcieSlot
IPU0log=
IPU1log=
HSM0log=
IMU0log=Ctrl.data (after)0x700.

Pcie slot[48] port:15 base 0x6c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[48] port:15 base 0x6c02000000, pcieSlotCtrl.data (after)0
IPU0log=
IPU1log=
HSM0log=
IMU0log=x700.

Pcie slot[49] port:16 base 0x6d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[49] port:16 base 0x6d01000000, pcieSlotCtrl.data (after)0x0.

Pcie slot[5
IPU0log=
IPU1log=
HSM0log=
IMU0log=0] port:17 base 0x6d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[50] port:17 base 0x6d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[51] port:18 base
IPU0log=
IPU1log=
HSM0log=
IMU0log= 0x6d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[51] port:18 base 0x6d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[52] port:19 base 0x6d01000000, 
IPU0log=
IPU1log=
HSM0log=
IMU0log=pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[52] port:19 base 0x6d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[53] port:20 base 0x6d01000000, pcieSlotCtrl.da
IPU0log=
IPU1log=
HSM0log=
IMU0log=ta (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[53] port:20 base 0x6d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[54] port:21 base 0x6d01000000, pcieSlotCtrl.data (before)0x0.
IPU0log=
IPU1log=
HSM0log=
IMU0log=
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[54] port:21 base 0x6d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[55] port:22 base 0x6d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.
IPU0log=
IPU1log=
HSM0log=
IMU0log=bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[55] port:22 base 0x6d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[56] port:23 base 0x6d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_d
IPU0log=
IPU1log=
HSM0log=
IMU0log=et_st = 1
present:1, pwr_en:0.
Pcie slot[56] port:23 base 0x6d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[57] port:24 base 0x6d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
pres
IPU0log=
IPU1log=
HSM0log=
IMU0log=ent:1, pwr_en:0.
Pcie slot[57] port:24 base 0x6d02000000, pcieSlotCtrl.data (after)0x0.

Pcie slot[58] port:25 base 0x6d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pc
IPU0log=
IPU1log=
HSM0log=
IMU0log=ie slot[58] port:25 base 0x6d02000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[59] port:26 base 0x6d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[59] por
IPU0log=
IPU1log=
HSM0log=
IMU0log=t:26 base 0x6d02000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[60] port:27 base 0x6d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[60] port:27 base 0x6d0
IPU0log=
IPU1log=
HSM0log=
IMU0log=2000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[61] port:28 base 0x6d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[61] port:28 base 0x6d02000000, pcieSl
IPU0log=
IPU1log=
HSM0log=
IMU0log=otCtrl.data (after)0x480100.

Pcie slot[62] port:29 base 0x6d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[62] port:29 base 0x6d02000000, pcieSlotCtrl.data (af
IPU0log=
IPU1log=
HSM0log=
IMU0log=ter)0x480100.

Pcie slot[63] port:30 base 0x6d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[63] port:30 base 0x6d02000000, pcieSlotCtrl.data (after)0x480100.

IPU0log=
IPU1log=
HSM0log=
IMU0log=
Pcie slot[64] port:31 base 0x6d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[64] port:31 base 0x6d02000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[65]
IPU0log=
IPU1log=
HSM0log=
IMU0log= port:32 base 0x7210000000, pcieSlotCtrl.data (before)0xffffffff.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[65] port:32 base 0x7210000000, pcieSlotCtrl.data (after)0xffffffff.

[RegisterInterruptS
IPU0log=
IPU1log=
HSM0log=
IMU0log=ource]:[21] begin
Interrupt 61 register OK
[RegisterInterruptSource]:[39] end
fristMskExt0Int

Pcie Hotplug init done, with 66 port(s).
[0.02.44.205]BIOS POST END.
slot[0] port:0 begin to power ON.
slot[0] port:0 pwr_indica
IPU0log=
IPU1log=
HSM0log=
IMU0log=tor = 0, att_indicator = 0
ledStatus:0 invalid!
[HotPlugMonitorTask][248L]Pcie slot[0] port:0 base 0x2c01000000, pcieSlotCtrl.data (after)0x100000.
slot[1] port:1 begin to power ON.
slot[2] port:2 begin to power ON.
slot[3]
IPU0log=
IPU1log=
HSM0log=
IMU0log= port:3 begin to power ON.
slot[4] port:4 begin to power ON.
slot[5] port:5 begin to power ON.
slot[6] port:6 begin to power ON.
slot[7] port:7 begin to power ON.
slot[8] port:8 begin to power ON.
slot[9] port:9 begin to p
IPU0log=
IPU1log=
HSM0log=
IMU0log=ower ON.
slot[10] port:10 begin to power ON.
slot[11] port:11 begin to power ON.
slot[12] port:12 begin to power OFF.
slot[13] port:13 begin to power OFF.
slot[14] port:14 begin to power OFF.
slot[15] port:15 begin to powe
IPU0log=
IPU1log=
HSM0log=
IMU0log=r OFF.
slot[16] port:16 begin to power ON.
slot[17] port:17 begin to power ON.
slot[18] port:18 begin to power ON.
slot[19] port:19 begin to power ON.
slot[20] port:20 begin to power ON.
slot[21] port:21 begin to power ON.
IPU0log=
IPU1log=
HSM0log=
IMU0log=
slot[22] port:22 begin to power ON.
slot[23] port:23 begin to power ON.
slot[24] port:24 pwr_indicator = 0, att_indicator = 0
ledStatus:0 invalid!
[HotPlugMonitorTask][248L]Pcie slot[24] port:24 base 0x2d02000000, pcieSlot
IPU0log=
IPU1log=
HSM0log=
IMU0log=Ctrl.data (after)0x100000.
slot[25] port:25 begin to power OFF.
slot[26] port:26 begin to power OFF.
slot[27] port:27 begin to power OFF.
slot[28] port:28 begin to power OFF.
slot[29] port:29 begin to power OFF.
slot[30] p
IPU0log=
IPU1log=
HSM0log=
IMU0log=ort:30 begin to power OFF.
slot[31] port:31 begin to power OFF.
slot[32] port:32 begin to power OFF.
slot[33] port:0 begin to power OFF.
slot[34] port:1 begin to power OFF.
slot[35] port:2 begin to power OFF.
slot[36] port
IPU0log=
IPU1log=
HSM0log=
IMU0log=:3 begin to power OFF.
slot[37] port:4 begin to power OFF.
slot[38] port:5 begin to power OFF.
slot[39] port:6 begin to power OFF.
slot[40] port:7 begin to power OFF.
slot[41] port:8 pwr_indicator = 0, att_indicator = 0
le
IPU0log=
IPU1log=
HSM0log=
IMU0log=dStatus:0 invalid!
[HotPlugMonitorTask][248L]Pcie slot[41] port:8 base 0x6c02000000, pcieSlotCtrl.data (after)0x100000.
slot[42] port:9 begin to power OFF.
slot[43] port:10 begin to power OFF.
slot[44] port:11 begin to power
IPU0log=
IPU1log=
HSM0log=
IMU0log= OFF.
slot[45] port:12 begin to power OFF.
slot[46] port:13 begin to power OFF.
slot[47] port:14 begin to power OFF.
slot[48] port:15 begin to power OFF.
slot[49] port:16 begin to power ON.
slot[49] port:16 pwr_indicator =
IPU0log=
IPU1log=
HSM0log=
IMU0log= 0, att_indicator = 0
ledStatus:0 invalid!
[HotPlugMonitorTask][248L]Pcie slot[49] port:16 base 0x6d01000000, pcieSlotCtrl.data (after)0x100000.
slot[50] port:17 begin to power ON.
slot[51] port:18 begin to power ON.
slot[5
IPU0log=
IPU1log=
HSM0log=
IMU0log=2] port:19 begin to power ON.
slot[53] port:20 begin to power ON.
slot[54] port:21 begin to power ON.
slot[55] port:22 begin to power ON.
slot[56] port:23 begin to power ON.
slot[57] port:24 begin to power ON.
slot[57] por
IPU0log=
IPU1log=
HSM0log=
IMU0log=t:24 pwr_indicator = 0, att_indicator = 0
ledStatus:0 invalid!
[HotPlugMonitorTask][248L]Pcie slot[57] port:24 base 0x6d02000000, pcieSlotCtrl.data (after)0x100000.
slot[58] port:25 begin to power ON.
slot[59] port:26 begin 
IPU0log=
IPU1log=
HSM0log=
IMU0log=to power ON.
slot[60] port:27 begin to power ON.
slot[61] port:28 begin to power ON.
slot[62] port:29 begin to power ON.
slot[63] port:30 begin to power ON.
slot[64] port:31 begin to power ON.
slot[65] port:32 begin to pow
IPU0log=
IPU1log=
HSM0log=
IMU0log=er OFF.
[0.02.46.765]wait 5 mins to update pciemmio..
[0.07.46.764]IpmiCmdReportPcieMMIO start
[0.07.51.199]IpmiCmdReportPcieMMIO end

IPU0log=
IPU1log=
HSM0log=
IMU0log=1T1N1U skt:0 CfgBusDfxPreConfig finish

********Hello Huawei LiteOS********

IMU Firmware Version : B173V01
LiteOS Kernel Version : 5.10.0
Run on Socket[0] Die[3]
Chip Version: 1
Max socket num: 2
*******************************
IPU0log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 0
cls: 6, core: 8
cpu 914 sram 1031 ddr 886
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  775|  841|  927|  980|
max  v
IPU1log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 1
cls: 6, core: 8
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  769|  835|  920|  973|
max  v: |  750|  750|  763|  790
HSM0log=[1970-01-01 00:01:01.312][HSM][INFO][30] init start
[1970-01-01 00:01:01.312][HSM][INFO][38] init over
[00:01:01.322][info] succeed to do thirdparty dfx_pabuk init
[00:01:01.327][info] os_mem_system_init default pool done
[0
IMU0log=***
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | rail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_vo
IPU0log=: |  750|  750|  761|  790|  863|  955| 1016|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:7
IPU1log=|  859|  950| 1009|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:750 F:1950
avs-uncore V:750
HSM0log=0:01:01.334][info] addr is already in region
[00:01:01.336][info] succeed to do thirdparty otpc_pabuk init
[1970-01-01 00:01:01.342][HSM][INFO][31] select_region: 0xc11cb55b
[1970-01-01 00:01:01.348][HSM][INFO][67] spi_nor de
IMU0log=lt:1122 mV | pmu:MP2882
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_v
IPU0log=50 F:1950
avs-uncore V:750 F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
av
IPU1log= F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
avs-uncore V:840 F:2450
avs-
HSM0log=vice_id 0xff1a67c8
[1970-01-01 00:01:01.354][HSM][INFO][50] std_cmd readback 0x30220d8
[1970-01-01 00:01:01.360][HSM][INFO][72] saf_cmd 0x0 readback 0x9f5a0604
[1970-01-01 00:01:01.366][HSM][INFO][72] saf_cmd 0x1 readback 0x5
IMU0log=olt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_
IPU0log=s-uncore V:840 F:2450
avs-uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain
IPU1log=uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | r
HSM0log=b7e938
[1970-01-01 00:01:01.373][HSM][INFO][72] saf_cmd 0x2 readback 0x1
[1970-01-01 00:01:01.378][HSM][INFO][72] saf_cmd 0x3 readback 0x0
[1970-01-01 00:01:01.384][HSM][INFO][72] saf_cmd 0x4 readback 0x0
[00:01:01.391][info
IMU0log=volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus r
IPU0log=[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | p
IPU1log=ail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_volt:1122 mV | pmu:MP2882
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[0] volt =  916 mV
pwr domain
HSM0log=] succeed to do thirdparty boot_profile_driver init
[00:01:01.396][info] succeed to do thirdparty crypto_driver init
[00:01:01.402][info] succeed to do thirdparty period_driver init
[00:01:01.408][info]  start loading interna
IMU0log=eady.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
send IMU_INIT_END to cpld.
cpu 0 entering scheduler
|--------------------------------------------------|
AtsPrint
|idx|lockCount| srcAddr| destAddr| addrL
IPU0log=mu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pmbus:0x480c0000 ver:0x110
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
IPU1log=[9] volt = 1107 mV
=end=
w&h rd rail:0, 916
w&h rd rail:1, 1107
pwr domain[0] set volt  904 mV succ
pwr domain[9] set volt 1107 mV succ
volt post
pwr domain[0] volt =  902 mV
pwr domain[9] volt = 1107 mV
==end==
Totem[0] Core Bo
HSM0log=l task ...
[00:01:01.413][info]  task name is ccm_task
[00:01:01.416][info]  hm_dynamic_loadelf successfully!
[00:01:01.421][info] internal task[1] task_name=ccm_task load successfully
[00:01:01.428][info]  task name is upgr
IMU0log=en|
|--------------------------------------------------|
|  0|00000000|0x010500000|0x000110800000|0x00100000|
|  1|00000000|0x020000000|0x00001d000000|0x00800000|
|  2|00000000|0x020800000|0x000490000000|0x00100000|
|  3|0000000
IPU0log=
avsbus resync succ
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[2] volt =  921 mV
pwr domain[7] volt =  804 mV
pwr domain[4] volt =  822 mV
pwr domain[1] volt =  804 mV
=end=
w&h rd rail:
IPU1log=ot Vol [1044]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2,
HSM0log=ade_task
[00:01:01.432][info]  hm_dynamic_loadelf successfully!
[00:01:01.437][info] internal task[2] task_name=upgrade_task load successfully
[00:01:01.444][info] created task ccm_task success!
[00:01:01.449][info] created 
IMU0log=0|0x020900000|0x000004000000|0x08000000|
|  4|00000000|0x028900000|0x000440580000|0x01000000|
|  5|00000000|0x029900000|0x000590000000|0x00100000|
|  6|00000000|0x029a00000|0x002000150000|0x00100000|
|  7|00000000|0x000000000|0x
IPU0log=0, 921
w&h rd rail:1, 802
pwr domain[2] set volt  902 mV succ
pwr domain[7] set volt  804 mV succ
w&h rd rail:0, 822
w&h rd rail:1, 804
pwr domain[4] set volt  802 mV succ
pwr domain[1] set volt  804 mV succ
volt post
pwr domain
IPU1log= ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd8
HSM0log=task upgrade_task success!
[1970-01-01 00:01:01.454][HSM][INFO][54] Platform init 0x20250523 0x4e.
[1970-01-01 00:01:01.460][HSM][INFO][197] ccm start.
[1970-01-01 00:01:01.465][HSM][INFO][86] upgrade task init success.
[197
IMU0log=000000000000|0x00000000|
|  8|00000000|0x040000000|0x000000000000|0x08000000|
|  9|00000000|0x048000000|0x000000000000|0x08000000|
| 10|00000000|0x050000000|0x000000000000|0x08000000|
| 11|00000000|0x058000000|0x000000000000|0x0
IPU0log=[2] volt =  902 mV
pwr domain[7] volt =  804 mV
pwr domain[4] volt =  802 mV
pwr domain[1] volt =  804 mV
==end==
Totem[0] Core Boot Vol [1051]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0,
IPU1log=00, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
opposite dieId: 0, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 
HSM0log=0-01-01 00:01:01.471][HSM][INFO][95] upgrade recv cmd, 0x181.
[1970-01-01 00:01:01.476][HSM][INFO][103] upgrade res, 0x3a5aa5a3.
.
IMU0log=8000000|
| 12|00000000|0x060000000|0x000000000000|0x08000000|
| 13|00000000|0x068000000|0x000000000000|0x08000000|
| 14|00000000|0x070000000|0x000000000000|0x08000000|
| 15|00000000|0x078000000|0x0028c8000000|0x08000000|
|------
IPU0log= MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 
IPU1log=enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
hiboost task entry
boost wait SEF.
[INFO] mem used of task 'app_Task' is:0x2028, not zero when task being deleted
boost param OK.
Totem[0] Core[ 0] Freq Limit Low
HSM0log=
IMU0log=--------------------------------------------|
=~=~=~=~=~=~=~=~=~=~= IMU Log @ 2026.5.22 1:11:32 =~=~=~=~=~=~=~=~=~=~=
[IMU] Watchdog Initialization done!
[RegisterInterruptSource]:[21] begin
Interrupt 32 register OK
Interrupt 
IPU0log=0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
tsensor type
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Fr
HSM0log=
IMU0log=34 register OK
Interrupt 40 register OK
Interrupt 44 register OK
sram cnt 0x0, id = 43
Interrupt 43 register OK
Interrupt 36 register OK
Interrupt 57 register OK
sram cnt 0x0, id = 42
Interrupt 42 register OK
Interrupt 37 regist
IPU0log=: 3, ppuFormatK: 0x4da6, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b4,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 3, mask: fffffff8
tsensor type: 4, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=er OK
[RegisterInterruptSource]:[39] end
IPMB initialization Start...
IPMB clock set done, prer = 0x18.
IPMB Rx FIFO clear empty.
IPMB initialization Done.
starting DFX Collect Task end
PowerTask Entry ...
Wait all vrd ini
IPU0log=0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 4, mask: ffffffee
tsensor type: 5, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1

IPU1log= Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=t done ...
All vrd init done, power task start
refresh domainId 0 Lsb 0x0
refresh domainId 9 Lsb 0x1
refresh domainId 2 Lsb 0x0
refresh domainId 7 Lsb 0x1
refresh domainId 4 Lsb 0x0
refresh domainId 1 Lsb 0x1
power sensor[0] | c
IPU0log=tsensor: 5, mask: ffffffda
tsensor type: 6, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 6, mask: ffffff80
tsensor type: 7, ppuFormatK: 0x437a,
IPU1log=KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=alib:5120 | rshunt:1 | rshuntDiv:1000 | currLsb:1 | currLsbDiv:1000 | enableFlag:1
                | pwrLsb:25 | defPwr:25000 | minPwr:10000 | maxPwr:65000 | pwrFix:-3400
                | manufacturerId: 0x5549 | dieId: 0x2260

IPU0log= ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 7, mask: fffffffe
opposite dieId: 1, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
CPM max V[900]-
IPU1log= Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low
HSM0log=
IMU0log=power sensor[0] init success
ScmiTaskEntry start.
[RegisterInterruptSource]:[21] begin
Interrupt 51 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 52 register OK
[RegisterInterru
IPU0log=F:2800
CPM min V[750]-F:1600
freq:2350, idx:9
cpm trim freq: 2600, idx: 4
cpm trim finish
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
recount hours 
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Fr
HSM0log=
IMU0log=ptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 53 register OK
[RegisterInterruptSource]:[39] end
[0.01.03.687]starting ras Init
RAS Setup Value get done!
INT_NUM_PER_SKT * HiGetSktNum() = 0x8
index = 0x0
Ra
IPU0log=0x4bc 
hiboost task entry
boost wait SEF.
boost param OK.
Totem[0] Core[ 0] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[26
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=sIntRegister init 160 
index = 0x1
RasIntRegister init 172 
index = 0x2
RasIntRegister init 162 
index = 0x3
RasIntRegister init 174 
index = 0x4
RasIntRegister init 184 
index = 0x5
RasIntRegister init 196 
index = 0x6
RasIntRe
IPU0log=00000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[12000
IPU1log= Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=gister init 186 
index = 0x7
RasIntRegister init 198 
RasIntRegister init 161 
RasIntRegister init 173 
RasIntRegister init 185 
RasIntRegister init 197 
RasIntRegister init 284 
RasIntRegister init 314 
MceTableHeadInit start
s
IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Lim
IPU1log=KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=tarting Ce_Storm Contrl and Ras_Data_Update Task end
[0.01.03.768]starting ras end
[IMU][ERR] skt id 0
Ub init task start Entry ...
UbInitTask Entry ...
[RegisterInterruptSource]:[21] begin
Interrupt 167 register OK
[Register
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IPU1log= Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low
HSM0log=
IMU0log=InterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 191 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 171 register OK
[RegisterInterruptSource]:[39] end
[
IPU0log=14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
To
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[42] Fr
HSM0log=
IMU0log=RegisterInterruptSource]:[21] begin
Interrupt 183 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 195 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21
IPU0log=tem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[26
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[43] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[44] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[45] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=] begin
Interrupt 207 register OK
[RegisterInterruptSource]:[39] end
Init heart-beat-task end
CS0 flash do not support sfdp!
Current flash device ID[0x61a67c8]!
System supported 1 Flash.
flash cs 0 Manufacture 0xc8, DeviceId 0
IPU0log=00000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[12000
IPU1log= Core[46] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[47] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
get tdp value from Product! Tdp value per vdie : 220000 mW!
uncore max freq : 2600 MHz

HSM0log=
IMU0log=x1a67, AddrMode[0-3B,1-4B] 0x1:
    size 0x4000000, pagesize 0x100
    read  cmd 0x13, dummy byte 0x8
    write cmd 0x12, dummy byte 0x0
    erase4k cmd 0x21, erase64k byte 0xdc
sfc init end
firstUnMskExt0Int
ThermalDimmStart En
IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Lim
IPU1log=
HSM0log=
IMU0log=try ...
wait ddr init done...
HacLowPowerStart Entry ...
Hello LiteOS...
pwr cap[0]: 0, 67
Init ReportPcieMmioToBmcTaskEntry end
starting Fpc Isolation Task end
[0.01.06.368]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.06.
IMU0log=1T1N1U skt:0 CfgBusDfxPreConfig finish

********Hello Huawei LiteOS********

IMU Firmware Version : B173V01
LiteOS Kernel Version : 5.10.0
Run on Socket[0] Die[3]
Chip Version: 1
Max socket num: 2
*******************************
IPU0log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 0
cls: 6, core: 8
cpu 914 sram 1031 ddr 886
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  775|  841|  927|  980|
max  v
IPU1log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 1
cls: 6, core: 8
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  769|  835|  920|  973|
max  v: |  750|  750|  763|  790
HSM0log=[1970-01-01 00:01:12.597][HSM][INFO][30] init start
[1970-01-01 00:01:12.597][HSM][INFO][38] init over
[00:01:12.607][info] succeed to do thirdparty dfx_pabuk init
[00:01:12.612][info] os_mem_system_init default pool done
[0
IMU0log=***
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | rail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_vo
IPU0log=: |  750|  750|  761|  790|  863|  955| 1016|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:7
IPU1log=|  859|  950| 1009|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:750 F:1950
avs-uncore V:750
HSM0log=0:01:12.619][info] addr is already in region
[00:01:12.621][info] succeed to do thirdparty otpc_pabuk init
[1970-01-01 00:01:12.627][HSM][INFO][31] select_region: 0xc11cb55b
[1970-01-01 00:01:12.633][HSM][INFO][67] spi_nor de
IMU0log=lt:1122 mV | pmu:MP2882
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_v
IPU0log=50 F:1950
avs-uncore V:750 F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
av
IPU1log= F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
avs-uncore V:840 F:2450
avs-
HSM0log=vice_id 0xff1a67c8
[1970-01-01 00:01:12.639][HSM][INFO][50] std_cmd readback 0x30220d8
[1970-01-01 00:01:12.645][HSM][INFO][72] saf_cmd 0x0 readback 0x9f5a0604
[1970-01-01 00:01:12.651][HSM][INFO][72] saf_cmd 0x1 readback 0x5
IMU0log=olt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_
IPU0log=s-uncore V:840 F:2450
avs-uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain
IPU1log=uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | r
HSM0log=b7e938
[1970-01-01 00:01:12.658][HSM][INFO][72] saf_cmd 0x2 readback 0x1
[1970-01-01 00:01:12.664][HSM][INFO][72] saf_cmd 0x3 readback 0x0
[1970-01-01 00:01:12.669][HSM][INFO][72] saf_cmd 0x4 readback 0x0
[00:01:12.676][info
IMU0log=volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus r
IPU0log=[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | p
IPU1log=ail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_volt:1122 mV | pmu:MP2882
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[0] volt =  902 mV
pwr domain
HSM0log=] succeed to do thirdparty boot_profile_driver init
[00:01:12.681][info] succeed to do thirdparty crypto_driver init
[00:01:12.687][info] succeed to do thirdparty period_driver init
[00:01:12.693][info]  start loading interna
IMU0log=eady.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait th
IPU0log=mu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pmbus:0x480c0000 ver:0x110
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
IPU1log=[9] volt = 1107 mV
=end=
w&h rd rail:0, 904
w&h rd rail:1, 1107
pwr domain[0] set volt  902 mV succ
pwr domain[9] set volt 1107 mV succ
volt post
pwr domain[0] volt =  902 mV
pwr domain[9] volt = 1107 mV
==end==
Totem[0] Core Bo
HSM0log=l task ...
[00:01:12.698][info]  task name is ccm_task
[00:01:12.702][info]  hm_dynamic_loadelf successfully!
[00:01:12.706][info] internal task[1] task_name=ccm_task load successfully
[00:01:12.713][info]  task name is upgr
IMU0log=e cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master I
IPU0log=
avsbus resync succ
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[2] volt =  904 mV
pwr domain[7] volt =  806 mV
pwr domain[4] volt =  804 mV
pwr domain[1] volt =  806 mV
=end=
w&h rd rail:
IPU1log=ot Vol [1044]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2,
HSM0log=ade_task
[00:01:12.717][info]  hm_dynamic_loadelf successfully!
[00:01:12.722][info] internal task[2] task_name=upgrade_task load successfully
[00:01:12.729][info] created task ccm_task success!
[00:01:12.734][info] created 
IMU0log=mu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
send IMU_INIT_END to cpld.
cpu 0 entering scheduler
|-------------
IPU0log=0, 904
w&h rd rail:1, 804
pwr domain[2] set volt  902 mV succ
pwr domain[7] set volt  804 mV succ
w&h rd rail:0, 804
w&h rd rail:1, 806
pwr domain[4] set volt  802 mV succ
pwr domain[1] set volt  806 mV succ
volt post
pwr domain
IPU1log= ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd8
HSM0log=task upgrade_task success!
[1970-01-01 00:01:12.739][HSM][INFO][54] Platform init 0x20250523 0x4e.
[1970-01-01 00:01:12.745][HSM][INFO][197] ccm start.
[1970-01-01 00:01:12.750][HSM][INFO][86] upgrade task init success.
[197
IMU0log=-------------------------------------|
AtsPrint
|idx|lockCount| srcAddr| destAddr| addrLen|
|--------------------------------------------------|
|  0|00000000|0x010500000|0x000110800000|0x00100000|
|  1|00000000|0x020000000|0x00
IPU0log=[2] volt =  902 mV
pwr domain[7] volt =  802 mV
pwr domain[4] volt =  802 mV
pwr domain[1] volt =  804 mV
==end==
Totem[0] Core Boot Vol [1051]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0,
IPU1log=00, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
opposite dieId: 0, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 
HSM0log=0-01-01 00:01:12.756][HSM][INFO][95] upgrade recv cmd, 0x181.
[1970-01-01 00:01:12.761][HSM][INFO][103] upgrade res, 0x3a5aa5a3.
.
IMU0log=001d000000|0x00800000|
|  2|00000000|0x020800000|0x000490000000|0x00100000|
|  3|00000000|0x020900000|0x000004000000|0x08000000|
|  4|00000000|0x028900000|0x000440580000|0x01000000|
|  5|00000000|0x029900000|0x000590000000|0x001
IPU0log= MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 
IPU1log=enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
hiboost task entry
boost wait SEF.
[INFO] mem used of task 'app_Task' is:0x2028, not zero when task being deleted
boost param OK.
Totem[0] Core[ 0] Freq Limit Low
HSM0log=
IMU0log=00000|
|  6|00000000|0x029a00000|0x002000150000|0x00100000|
|  7|00000000|0x000000000|0x000000000000|0x00000000|
|  8|00000000|0x040000000|0x000000000000|0x08000000|
|  9|00000000|0x048000000|0x000000000000|0x08000000|
| 10|0000
IPU0log=0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
tsensor type
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Fr
HSM0log=
IMU0log=0000|0x050000000|0x000000000000|0x08000000|
| 11|00000000|0x058000000|0x000000000000|0x08000000|
| 12|00000000|0x060000000|0x000000000000|0x08000000|
| 13|00000000|0x068000000|0x000000000000|0x08000000|
| 14|00000000|0x070000000
IPU0log=: 3, ppuFormatK: 0x4da6, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b4,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 3, mask: fffffff8
tsensor type: 4, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=|0x000000000000|0x08000000|
| 15|00000000|0x078000000|0x0028c8000000|0x08000000|
|--------------------------------------------------|
=~=~=~=~=~=~=~=~=~=~= IMU Log @ 2026.5.22 1:19:41 =~=~=~=~=~=~=~=~=~=~=
[IMU] Watchdog Initial
IPU0log=0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 4, mask: ffffffee
tsensor type: 5, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1

IPU1log= Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=ization done!
[RegisterInterruptSource]:[21] begin
Interrupt 32 register OK
Interrupt 34 register OK
Interrupt 40 register OK
Interrupt 44 register OK
sram cnt 0x0, id = 43
Interrupt 43 register OK
Interrupt 36 register OK
Int
IPU0log=tsensor: 5, mask: ffffffda
tsensor type: 6, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 6, mask: ffffff80
tsensor type: 7, ppuFormatK: 0x437a,
IPU1log=KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=errupt 57 register OK
sram cnt 0x0, id = 42
Interrupt 42 register OK
Interrupt 37 register OK
[RegisterInterruptSource]:[39] end
IPMB initialization Start...
IPMB clock set done, prer = 0x18.
IPMB Rx FIFO clear empty.
IPMB i
IPU0log= ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 7, mask: fffffffe
opposite dieId: 1, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
CPM max V[900]-
IPU1log= Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low
HSM0log=
IMU0log=nitialization Done.
starting DFX Collect Task end
PowerTask Entry ...
Wait all vrd init done ...
All vrd init done, power task start
refresh domainId 0 Lsb 0x0
refresh domainId 9 Lsb 0x1
refresh domainId 2 Lsb 0x0
refresh doma
IPU0log=F:2800
CPM min V[750]-F:1600
freq:2350, idx:9
cpm trim freq: 2600, idx: 4
cpm trim finish
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
recount hours 
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Fr
HSM0log=
IMU0log=inId 7 Lsb 0x1
refresh domainId 4 Lsb 0x0
refresh domainId 1 Lsb 0x1
power sensor[0] | calib:5120 | rshunt:1 | rshuntDiv:1000 | currLsb:1 | currLsbDiv:1000 | enableFlag:1
                | pwrLsb:25 | defPwr:25000 | minPwr:10000
IPU0log=0x4bc 
hiboost task entry
boost wait SEF.
boost param OK.
Totem[0] Core[ 0] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[26
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log= | maxPwr:65000 | pwrFix:-3400
                | manufacturerId: 0x5549 | dieId: 0x2260
power sensor[0] init success
ScmiTaskEntry start.
[RegisterInterruptSource]:[21] begin
Interrupt 51 register OK
[RegisterInterruptSource]:[
IPU0log=00000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[12000
IPU1log= Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=39] end
[RegisterInterruptSource]:[21] begin
Interrupt 52 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 53 register OK
[RegisterInterruptSource]:[39] end
[0.01.31.496]starting
IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Lim
IPU1log=KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log= ras Init
RAS Setup Value get done!
INT_NUM_PER_SKT * HiGetSktNum() = 0x8
index = 0x0
RasIntRegister init 160 
index = 0x1
RasIntRegister init 172 
index = 0x2
RasIntRegister init 162 
index = 0x3
RasIntRegister init 174 
index 
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IPU1log= Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low
HSM0log=
IMU0log== 0x4
RasIntRegister init 184 
index = 0x5
RasIntRegister init 196 
index = 0x6
RasIntRegister init 186 
index = 0x7
RasIntRegister init 198 
RasIntRegister init 161 
RasIntRegister init 173 
RasIntRegister init 185 
RasIntRegis
IPU0log=14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
To
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[42] Fr
HSM0log=
IMU0log=ter init 197 
RasIntRegister init 284 
RasIntRegister init 314 
MceTableHeadInit start
starting Ce_Storm Contrl and Ras_Data_Update Task end
[0.01.31.577]starting ras end
[IMU][ERR] skt id 0
Ub init task start Entry ...
UbInitT
IPU0log=tem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[26
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[43] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[44] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[45] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=ask Entry ...
[RegisterInterruptSource]:[21] begin
Interrupt 167 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 191 register OK
[RegisterInterruptSource]:[39] end
[RegisterInte
IPU0log=00000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[12000
IPU1log= Core[46] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[47] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
get tdp value from Product! Tdp value per vdie : 220000 mW!
uncore max freq : 2600 MHz

HSM0log=
IMU0log=rruptSource]:[21] begin
Interrupt 171 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 183 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Int
IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Lim
IPU1log=
HSM0log=
IMU0log=errupt 195 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 207 register OK
[RegisterInterruptSource]:[39] end
Init heart-beat-task end
CS0 flash do not support sfdp!
Current flash
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IPU1log=
HSM0log=
IMU0log= device ID[0x61a67c8]!
System supported 1 Flash.
flash cs 0 Manufacture 0xc8, DeviceId 0x1a67, AddrMode[0-3B,1-4B] 0x1:
    size 0x4000000, pagesize 0x100
    read  cmd 0x13, dummy byte 0x8
    write cmd 0x12, dummy byte 0x0
   
IPU0log=33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
To
IPU1log=
HSM0log=
IMU0log= erase4k cmd 0x21, erase64k byte 0xdc
sfc init end
firstUnMskExt0Int
ThermalDimmStart Entry ...
wait ddr init done...
HacLowPowerStart Entry ...
Hello LiteOS...
pwr cap[0]: 0, 67
Init ReportPcieMmioToBmcTaskEntry end
startin
IPU0log=tem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[26
IPU1log=
HSM0log=
IMU0log=g Fpc Isolation Task end
[0.01.34.160]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.34.172]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.34.215]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.34.238]Get PCIE Info CMD INVALID, P
IPU0log=00000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[42] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[43] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[44] Freq Limit Low[12000
IPU1log=
HSM0log=
IMU0log=CIE No Init!
[0.01.34.355]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.34.363]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.34.394]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.34.487]Get PCIE Info CMD INVALID, PCIE No Init!
IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[45] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[46] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[47] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
get tdp value from Product
IPU1log=
HSM0log=
IMU0log=
[0.01.34.511]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.34.525]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.34.639]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.34.665]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.34.67
IPU0log=! Tdp value per vdie : 220000 mW!
uncore max freq : 2600 MHz

IPU1log=
HSM0log=
IMU0log=4]Get PCIE Info CMD INVALID, PCIE No Init!
pwr cap[1]: ea, 2
[0.01.34.785]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.34.800]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.34.821]Get PCIE Info CMD INVALID, PCIE No Init!
[0.0
IPU0log=
IPU1log=
HSM0log=
IMU0log=1.34.916]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.34.938]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.34.953]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.35.058]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.35.063]Get
IPU0log=
IPU1log=
HSM0log=
IMU0log= PCIE Info CMD INVALID, PCIE No Init!
[0.01.35.074]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.35.180]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.35.185]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.35.211]Get PCIE Info C
IPU0log=
IPU1log=
HSM0log=
IMU0log=MD INVALID, PCIE No Init!
[0.01.35.328]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.35.336]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.35.347]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.35.445]Get PCIE Info CMD INVALID, 
IPU0log=
IPU1log=
HSM0log=
IMU0log=PCIE No Init!
[0.01.35.459]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.35.484]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.35.601]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.35.612]Get PCIE Info CMD INVALID, PCIE No Init
IPU0log=
IPU1log=
HSM0log=
IMU0log=!
[0.01.35.640]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.35.757]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.35.764]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.35.775]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.35.8
IPU0log=
IPU1log=
HSM0log=
IMU0log=83]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.35.913]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.35.925]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.36.030]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.36.039]Get PCIE 
IPU0log=
IPU1log=
HSM0log=
IMU0log=Info CMD INVALID, PCIE No Init!
[0.01.36.049]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.36.159]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.36.186]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.36.200]Get PCIE Info CMD INV
IPU0log=
IPU1log=
HSM0log=
IMU0log=ALID, PCIE No Init!
[0.01.36.310]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.36.321]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.36.342]Get PCIE Info CMD INVALID, PCIE No Init!
pwr cap[2]: 1, 3
[0.01.38.448]Get PCIE Info C
IPU0log=
IPU1log=
HSM0log=
IMU0log=MD INVALID, PCIE No Init!
[0.01.38.487]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.38.501]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.38.613]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.38.623]Get PCIE Info CMD INVALID, 
IPU0log=
IPU1log=
HSM0log=
IMU0log=PCIE No Init!
[0.01.38.643]Get PCIE Info CMD INVALID, PCIE No Init!
BMC_COLLECTION: bmc req last log!
DDR initing...
[0.01.44.220]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.44.228]Get PCIE Info CMD INVALID, PCIE No Init!
[0.
IPU0log=
IPU1log=
HSM0log=
IMU0log=01.44.237]Get PCIE Info CMD INVALID, PCIE No Init!
BMC_COLLECTION: bmc req last log!
DDR initing...
[0.01.54.243]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.54.250]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.54.259]Get PCI
IPU0log=
IPU1log=
HSM0log=
IMU0log=E Info CMD INVALID, PCIE No Init!
[0.01.59.399]DDR init done
[LOG]head = 0x0, tail = 0x25a5, logSize = 0x25a5
[IMU][ERR] HsmLogInit!
[IMU][ERR] HsmLogInit! TRUE
ddr init done, start thermal dimm task
======dimm status======
  ch
IPU0log=
IPU1log=
HSM0log=
IMU0log=l[0] dimm0 0, dimm1 0
  chl[1] dimm0 1, dimm1 0
  chl[2] dimm0 0, dimm1 0
  chl[3] dimm0 0, dimm1 0
  chl[4] dimm0 0, dimm1 0
  chl[5] dimm0 0, dimm1 0
  chl[6] dimm0 0, dimm1 0
  chl[7] dimm0 0, dimm1 0
  chl[8] dimm0 0, dimm1 
IPU0log=
IPU1log=
HSM0log=
IMU0log=0
  chl[9] dimm0 0, dimm1 0
  chl[10] dimm0 0, dimm1 0
  chl[11] dimm0 0, dimm1 0
==========end==========
sktId[0] chl[1] registered, dimm mask = 0x1
======dimm status======
  chl[0] dimm0 0, dimm1 0
  chl[1] dimm0 0, dimm1 0
  
IPU0log=
IPU1log=
HSM0log=
IMU0log=chl[2] dimm0 0, dimm1 0
  chl[3] dimm0 0, dimm1 0
  chl[4] dimm0 0, dimm1 0
  chl[5] dimm0 0, dimm1 0
  chl[6] dimm0 0, dimm1 0
  chl[7] dimm0 0, dimm1 0
  chl[8] dimm0 0, dimm1 0
  chl[9] dimm0 0, dimm1 0
  chl[10] dimm0 0, dim
IPU0log=
IPU1log=
HSM0log=
IMU0log=m1 0
  chl[11] dimm0 0, dimm1 0
==========end==========
=====dimm temp params=====
  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
  is_thermal_thro_en  : 1
  is_aref_rate_auto   : 0
===========end============
IPU0log=
IPU1log=
HSM0log=
IMU0log=
set apei done!
UbConfigData size is 64
UbConfigData 0 : 0
UbConfigData 1 : 0
UbConfigData 2 : 0
UbConfigData 3 : 1
UbConfigData 4 : 31
UbConfigData 5 : 1
UbConfigData 6 : 0
UbConfigData 7 : 32
UbConfigData 8 : 0
UbConfigData 9 
IPU0log=
IPU1log=
HSM0log=
IMU0log=1T1N1U skt:0 CfgBusDfxPreConfig finish

********Hello Huawei LiteOS********

IMU Firmware Version : B173V01
LiteOS Kernel Version : 5.10.0
Run on Socket[0] Die[3]
Chip Version: 1
Max socket num: 2
*******************************
IPU0log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 0
cls: 6, core: 8
cpu 914 sram 1031 ddr 886
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  775|  841|  927|  980|
max  v
IPU1log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 1
cls: 6, core: 8
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  769|  835|  920|  973|
max  v: |  750|  750|  763|  790
HSM0log=[1970-01-01 00:01:01.205][HSM][INFO][30] init start
[1970-01-01 00:01:01.205][HSM][INFO][38] init over
[00:01:01.215][info] succeed to do thirdparty dfx_pabuk init
[00:01:01.220][info] os_mem_system_init default pool done
[0
IMU0log=***
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | rail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_vo
IPU0log=: |  750|  750|  761|  790|  863|  955| 1016|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:7
IPU1log=|  859|  950| 1009|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:750 F:1950
avs-uncore V:750
HSM0log=0:01:01.226][info] addr is already in region
[00:01:01.229][info] succeed to do thirdparty otpc_pabuk init
[1970-01-01 00:01:01.235][HSM][INFO][31] select_region: 0xc11cb55b
[1970-01-01 00:01:01.241][HSM][INFO][67] spi_nor de
IMU0log=lt:1122 mV | pmu:MP2882
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_v
IPU0log=50 F:1950
avs-uncore V:750 F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
av
IPU1log= F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
avs-uncore V:840 F:2450
avs-
HSM0log=vice_id 0xff1a67c8
[1970-01-01 00:01:01.247][HSM][INFO][50] std_cmd readback 0x30220d8
[1970-01-01 00:01:01.253][HSM][INFO][72] saf_cmd 0x0 readback 0x9f5a0604
[1970-01-01 00:01:01.259][HSM][INFO][72] saf_cmd 0x1 readback 0x5
IMU0log=olt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_
IPU0log=s-uncore V:840 F:2450
avs-uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain
IPU1log=uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | r
HSM0log=b7e938
[1970-01-01 00:01:01.266][HSM][INFO][72] saf_cmd 0x2 readback 0x1
[1970-01-01 00:01:01.271][HSM][INFO][72] saf_cmd 0x3 readback 0x0
[1970-01-01 00:01:01.277][HSM][INFO][72] saf_cmd 0x4 readback 0x0
[00:01:01.284][info
IMU0log=volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus r
IPU0log=[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | p
IPU1log=ail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_volt:1122 mV | pmu:MP2882
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[0] volt = 1046 mV
pwr domain
HSM0log=] succeed to do thirdparty boot_profile_driver init
[00:01:01.289][info] succeed to do thirdparty crypto_driver init
[00:01:01.295][info] succeed to do thirdparty period_driver init
[00:01:01.301][info]  start loading interna
IMU0log=eady.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
send IMU_INIT_END to cpld.
cpu 0 entering scheduler
|--------------------------------------------------|
AtsPrint
|idx|lockCount| srcAddr| destAddr| addrL
IPU0log=mu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pmbus:0x480c0000 ver:0x110
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
IPU1log=[9] volt = 1107 mV
=end=
w&h rd rail:0, 1048
w&h rd rail:1, 1107
pwr domain[0] set volt  904 mV succ
pwr domain[9] set volt 1107 mV succ
volt post
pwr domain[0] volt =  902 mV
pwr domain[9] volt = 1107 mV
==end==
Totem[0] Core B
HSM0log=l task ...
[00:01:01.305][info]  task name is ccm_task
[00:01:01.309][info]  hm_dynamic_loadelf successfully!
[00:01:01.314][info] internal task[1] task_name=ccm_task load successfully
[00:01:01.321][info]  task name is upgr
IMU0log=en|
|--------------------------------------------------|
|  0|00000000|0x010500000|0x000110800000|0x00100000|
|  1|00000000|0x020000000|0x00001d000000|0x00800000|
|  2|00000000|0x020800000|0x000490000000|0x00100000|
|  3|0000000
IPU0log=
avsbus resync succ
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[2] volt = 1058 mV
pwr domain[7] volt =  804 mV
pwr domain[4] volt =  822 mV
pwr domain[1] volt =  804 mV
=end=
w&h rd rail:
IPU1log=oot Vol [1044]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2
HSM0log=ade_task
[00:01:01.325][info]  hm_dynamic_loadelf successfully!
[00:01:01.330][info] internal task[2] task_name=upgrade_task load successfully
[00:01:01.337][info] created task ccm_task success!
[00:01:01.342][info] created 
IMU0log=0|0x020900000|0x000004000000|0x08000000|
|  4|00000000|0x028900000|0x000440580000|0x01000000|
|  5|00000000|0x029900000|0x000590000000|0x00100000|
|  6|00000000|0x029a00000|0x002000150000|0x00100000|
|  7|00000000|0x000000000|0x
IPU0log=0, 1056
w&h rd rail:1, 804
pwr domain[2] set volt  904 mV succ
pwr domain[7] set volt  802 mV succ
w&h rd rail:0, 822
w&h rd rail:1, 804
pwr domain[4] set volt  800 mV succ
pwr domain[1] set volt  804 mV succ
volt post
pwr domai
IPU1log=, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd
HSM0log=task upgrade_task success!
[1970-01-01 00:01:01.346][HSM][INFO][54] Platform init 0x20250523 0x4e.
[1970-01-01 00:01:01.353][HSM][INFO][197] ccm start.
[1970-01-01 00:01:01.358][HSM][INFO][86] upgrade task init success.
[197
IMU0log=000000000000|0x00000000|
|  8|00000000|0x040000000|0x000000000000|0x08000000|
|  9|00000000|0x048000000|0x000000000000|0x08000000|
| 10|00000000|0x050000000|0x000000000000|0x08000000|
| 11|00000000|0x058000000|0x000000000000|0x0
IPU0log=n[2] volt =  902 mV
pwr domain[7] volt =  804 mV
pwr domain[4] volt =  802 mV
pwr domain[1] volt =  804 mV
==end==
Totem[0] Core Boot Vol [1051]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0
IPU1log=800, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
opposite dieId: 0, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89
HSM0log=0-01-01 00:01:01.363][HSM][INFO][95] upgrade recv cmd, 0x181.
[1970-01-01 00:01:01.369][HSM][INFO][103] upgrade res, 0x3a5aa5a3.
.
IMU0log=8000000|
| 12|00000000|0x060000000|0x000000000000|0x08000000|
| 13|00000000|0x068000000|0x000000000000|0x08000000|
| 14|00000000|0x070000000|0x000000000000|0x08000000|
| 15|00000000|0x078000000|0x0028c8000000|0x08000000|
|------
IPU0log=, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor:
IPU1log= enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
hiboost task entry
boost wait SEF.
[INFO] mem used of task 'app_Task' is:0x2028, not zero when task being deleted
boost param OK.
Totem[0] Core[ 0] Freq Limit Lo
HSM0log=
IMU0log=--------------------------------------------|
=~=~=~=~=~=~=~=~=~=~= IMU Log @ 2026.5.22 1:29:55 =~=~=~=~=~=~=~=~=~=~=
[IMU] Watchdog Initialization done!
[RegisterInterruptSource]:[21] begin
Interrupt 32 register OK
Interrupt 
IPU0log= 0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
tsensor typ
IPU1log=w[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] F
HSM0log=
IMU0log=34 register OK
Interrupt 40 register OK
Interrupt 44 register OK
sram cnt 0x0, id = 43
Interrupt 43 register OK
Interrupt 36 register OK
Interrupt 57 register OK
sram cnt 0x0, id = 42
Interrupt 42 register OK
Interrupt 37 regist
IPU0log=e: 3, ppuFormatK: 0x4da6, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b4,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 3, mask: fffffff8
tsensor type: 4, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB:
IPU1log=req Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0
HSM0log=
IMU0log=er OK
[RegisterInterruptSource]:[39] end
IPMB initialization Start...
IPMB clock set done, prer = 0x18.
IPMB Rx FIFO clear empty.
IPMB initialization Done.
starting DFX Collect Task end
PowerTask Entry ...
Wait all vrd ini
IPU0log= 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 4, mask: ffffffee
tsensor type: 5, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
IPU1log=] Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000
HSM0log=
IMU0log=t done ...
All vrd init done, power task start
refresh domainId 0 Lsb 0x0
refresh domainId 9 Lsb 0x1
refresh domainId 2 Lsb 0x0
refresh domainId 7 Lsb 0x1
refresh domainId 4 Lsb 0x0
refresh domainId 1 Lsb 0x1
power sensor[0] | c
IPU0log=
tsensor: 5, mask: ffffffda
tsensor type: 6, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 6, mask: ffffff80
tsensor type: 7, ppuFormatK: 0x437a
IPU1log=]KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KH
HSM0log=
IMU0log=alib:5120 | rshunt:1 | rshuntDiv:1000 | currLsb:1 | currLsbDiv:1000 | enableFlag:1
                | pwrLsb:25 | defPwr:25000 | minPwr:10000 | maxPwr:65000 | pwrFix:-3400
                | manufacturerId: 0x5549 | dieId: 0x2260

IPU0log=, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 7, mask: fffffffe
opposite dieId: 1, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
CPM max V[900]
IPU1log=Z Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Lo
HSM0log=
IMU0log=power sensor[0] init success
ScmiTaskEntry start.
[RegisterInterruptSource]:[21] begin
Interrupt 51 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 52 register OK
[RegisterInterru
IPU0log=-F:2800
CPM min V[750]-F:1600
freq:2350, idx:9
cpm trim freq: 2600, idx: 4
cpm trim finish
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
recount hours
IPU1log=w[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] F
HSM0log=
IMU0log=ptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 53 register OK
[RegisterInterruptSource]:[39] end
[0.01.03.576]starting ras Init
RAS Setup Value get done!
INT_NUM_PER_SKT * HiGetSktNum() = 0x8
index = 0x0
Ra
IPU0log= 0x4bc 
hiboost task entry
boost wait SEF.
boost param OK.
Totem[0] Core[ 0] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[2
IPU1log=req Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0
HSM0log=
IMU0log=sIntRegister init 160 
index = 0x1
BMC_COLLECTION: bmc req last log!
DDR initing...
RasIntRegister init 172 
index = 0x2
RasIntRegister init 162 
index = 0x3
RasIntRegister init 174 
index = 0x4
RasIntRegister init 184 
index = 
IPU0log=600000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[1200
IPU1log=] Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000
HSM0log=
IMU0log=0x5
RasIntRegister init 196 
index = 0x6
RasIntRegister init 186 
index = 0x7
RasIntRegister init 198 
RasIntRegister init 161 
RasIntRegister init 173 
RasIntRegister init 185 
RasIntRegister init 197 
RasIntRegister init 284 

IPU0log=000]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Li
IPU1log=]KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KH
HSM0log=
IMU0log=RasIntRegister init 314 
starting Ce_Storm Contrl and Ras_Data_Update Task end
[0.01.03.656]starting ras end
MceTableHeadInit start
[IMU][ERR] skt id 0
Ub init task start Entry ...
UbInitTask Entry ...
[RegisterInterruptSource
IPU0log=mit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core
IPU1log=Z Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Lo
HSM0log=
IMU0log=]:[21] begin
Interrupt 167 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 191 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 171 
IPU0log=[14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
T
IPU1log=w[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[42] F
HSM0log=
IMU0log=register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 183 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 195 register OK
[RegisterInterru
IPU0log=otem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[2
IPU1log=req Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[43] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[44] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[45] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0
HSM0log=
IMU0log=ptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 207 register OK
[RegisterInterruptSource]:[39] end
Init heart-beat-task end
CS0 flash do not support sfdp!
Current flash device ID[0x61a67c8]!
System supported
IPU0log=600000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[1200
IPU1log=] Core[46] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[47] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
get tdp value from Product! Tdp value per vdie : 220000 mW!
uncore max freq : 2600 MHz

HSM0log=
IMU0log= 1 Flash.
flash cs 0 Manufacture 0xc8, DeviceId 0x1a67, AddrMode[0-3B,1-4B] 0x1:
    size 0x4000000, pagesize 0x100
    read  cmd 0x13, dummy byte 0x8
    write cmd 0x12, dummy byte 0x0
    erase4k cmd 0x21, erase64k byte 0xdc
s
IPU0log=000]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Li
IPU1log=
HSM0log=
IMU0log=fc init end
firstUnMskExt0Int
ThermalDimmStart Entry ...
wait ddr init done...
HacLowPowerStart Entry ...
Hello LiteOS...
Init ReportPcieMmioToBmcTaskEntry end
starting Fpc Isolation Task end
pwr cap[0]: 0, 67
[0.01.05.612]G
IPU0log=mit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core
IPU1log=
HSM0log=
IMU0log=et PCIE Info CMD INVALID, PCIE No Init!
[0.01.05.690]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.05.728]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.05.767]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.05.780]Get PCIE Info
IPU0log=[33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
T
IPU1log=
HSM0log=
IMU0log= CMD INVALID, PCIE No Init!
[0.01.05.820]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.05.845]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.05.851]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.05.962]Get PCIE Info CMD INVALID
IPU0log=otem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[2
IPU1log=
HSM0log=
IMU0log=, PCIE No Init!
[0.01.05.969]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.06.001]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.06.118]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.06.130]Get PCIE Info CMD INVALID, PCIE No In
IPU0log=600000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[42] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[43] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[44] Freq Limit Low[1200
IPU1log=
HSM0log=
IMU0log=it!
[0.01.06.157]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.06.274]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.06.284]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.06.289]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.06
IPU0log=000]KHZ Up[2600000]KHZ
Totem[0] Core[45] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[46] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[47] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
get tdp value from Produc
IPU1log=
HSM0log=
IMU0log=.399]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.06.430]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.06.436]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.06.547]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.06.560]Get PCI
IPU0log=t! Tdp value per vdie : 220000 mW!
uncore max freq : 2600 MHz

IPU1log=
HSM0log=
IMU0log=E Info CMD INVALID, PCIE No Init!
pwr cap[1]: ea, 2
[0.01.07.560]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.07.578]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.07.680]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.07.690]
IPU0log=
IPU1log=
HSM0log=
IMU0log=Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.07.716]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.07.833]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.07.844]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.07.872]Get PCIE Inf
IPU0log=
IPU1log=
HSM0log=
IMU0log=o CMD INVALID, PCIE No Init!
[0.01.07.989]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.07.994]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.08.028]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.08.145]Get PCIE Info CMD INVALI
IPU0log=
IPU1log=
HSM0log=
IMU0log=D, PCIE No Init!
[0.01.08.158]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.08.184]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.08.301]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.08.310]Get PCIE Info CMD INVALID, PCIE No I
IPU0log=
IPU1log=
HSM0log=
IMU0log=nit!
[0.01.08.319]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.08.418]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.08.431]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.08.457]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.0
IPU0log=
IPU1log=
HSM0log=
IMU0log=8.574]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.08.591]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.08.613]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.08.735]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.08.746]Get PC
IPU0log=
IPU1log=
HSM0log=
IMU0log=IE Info CMD INVALID, PCIE No Init!
[0.01.08.769]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.08.886]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.08.900]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.08.925]Get PCIE Info CMD 
IPU0log=
IPU1log=
HSM0log=
IMU0log=INVALID, PCIE No Init!
[0.01.09.042]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.09.052]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.09.081]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.09.198]Get PCIE Info CMD INVALID, PCI
IPU0log=
IPU1log=
HSM0log=
IMU0log=E No Init!
[0.01.09.203]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.09.213]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.09.320]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.09.327]Get PCIE Info CMD INVALID, PCIE No Init!
[
IPU0log=
IPU1log=
HSM0log=
IMU0log=0.01.09.354]Get PCIE Info CMD INVALID, PCIE No Init!
pwr cap[2]: 1, 3
BMC_COLLECTION: bmc req last log!
DDR initing...
[0.01.15.789]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.15.798]Get PCIE Info CMD INVALID, PCIE No Init!

IPU0log=
IPU1log=
HSM0log=
IMU0log=[0.01.15.828]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.25.851]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.25.856]Get PCIE Info CMD INVALID, PCIE No Init!
[0.01.25.862]Get PCIE Info CMD INVALID, PCIE No Init!
BMC_COLLECTI
IPU0log=
IPU1log=
HSM0log=
IMU0log=ON: bmc req last log!
DDR initing...
[0.01.31.394]DDR init done
[LOG]head = 0x0, tail = 0x24c4, logSize = 0x24c4
[IMU][ERR] HsmLogInit!
[IMU][ERR] HsmLogInit! TRUE
ddr init done, start thermal dimm task
======dimm status======
 
IPU0log=
IPU1log=
HSM0log=
IMU0log= chl[0] dimm0 0, dimm1 0
  chl[1] dimm0 1, dimm1 0
  chl[2] dimm0 0, dimm1 0
  chl[3] dimm0 0, dimm1 0
  chl[4] dimm0 0, dimm1 0
  chl[5] dimm0 0, dimm1 0
  chl[6] dimm0 0, dimm1 0
  chl[7] dimm0 0, dimm1 0
  chl[8] dimm0 0, dim
IPU0log=
IPU1log=
HSM0log=
IMU0log=m1 0
  chl[9] dimm0 0, dimm1 0
  chl[10] dimm0 0, dimm1 0
  chl[11] dimm0 0, dimm1 0
==========end==========
sktId[0] chl[1] registered, dimm mask = 0x1
======dimm status======
  chl[0] dimm0 0, dimm1 0
  chl[1] dimm0 0, dimm1 0
IMU0log=skt = 1 logic = 6 phy = 9 
14: skt = 1 logic = 3 phy = 10 
15: skt = 0 logic = 7 phy = 1 
16: skt = 1 logic = 1 phy = 0 
17: skt = 0 logic = 2 phy = 4 
18: skt = 0 logic = 8 phy = 5 
19: skt = 0 logic = 5 phy = 6 
20: skt = 0 lo
IPU0log=
IPU1log=
HSM0log=
IMU0log=gic = 3 phy = 10 
21: skt = 0 logic = 6 phy = 9 
22: skt = 0 logic = 4 phy = 2 
23: skt = 0 logic = 11 phy = 7 
get mem silk data length: 72
BMC_COLLECTION: bmc req last log!
[IMU][ERR] [
HSM0log= no log data error!]
[0.01.44.39
IPU0log=
IPU1log=
HSM0log=
IMU0log=4]PCIE INIT DONE.
[IMU][ERR] LOS_SemPend(g_pcieSemaphore, LOS_WAIT_FOREVER)
[RegisterInterruptSource]:[21] begin
Interrupt 258 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 262 
IPU0log=
IPU1log=
HSM0log=
IMU0log=register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 266 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 270 register OK
[RegisterInterru
IPU0log=
IPU1log=
HSM0log=
IMU0log=ptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 277 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 288 register OK
[RegisterInterruptSource]:[39] end
[Registe
IPU0log=
IPU1log=
HSM0log=
IMU0log=rInterruptSource]:[21] begin
Interrupt 292 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 296 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
IPU0log=
IPU1log=
HSM0log=
IMU0log=
Interrupt 300 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 307 register OK
[RegisterInterruptSource]:[39] end
pmt Init done

-----------------ROUTE TABLE------------------
e
IPU0log=
IPU1log=
HSM0log=
IMU0log=ntryCount = 2
----------------------------------------------
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2500
[No.1]:
eidRange =
IPU0log=
IPU1log=
HSM0log=
IMU0log= 1, startEid = 10, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2100
----------------------------------------------
-----------------ROUTE TABLE------------------
ent
IPU0log=
IPU1log=
HSM0log=
IMU0log=ryCount = 2
----------------------------------------------
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2500
[No.1]:
eidRange = 1
IPU0log=
IPU1log=
HSM0log=
IMU0log=, startEid = 10, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2100
----------------------------------------------
-----------------ROUTE TABLE------------------
entry
IPU0log=
IPU1log=
HSM0log=
IMU0log=Count = 2
----------------------------------------------
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2500
[No.1]:
eidRange = 1, 
IPU0log=
IPU1log=
HSM0log=
IMU0log=startEid = 10, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2100
----------------------------------------------
HotPlug Open
slotNum = 42
portIdx = 0
portIdx = 1
p
IPU0log=
IPU1log=
HSM0log=
IMU0log=ortIdx = 2
portIdx = 3
portIdx = 4
portIdx = 5
portIdx = 6
portIdx = 7
portIdx = 8
portIdx = 9
portIdx = a
portIdx = b
portIdx = c
portIdx = d
portIdx = e
portIdx = f
portIdx = 10
portIdx = 11
portIdx = 12
portI
IPU0log=
IPU1log=
HSM0log=
IMU0log=dx = 13
portIdx = 14
portIdx = 15
portIdx = 16
portIdx = 17
portIdx = 18
portIdx = 19
portIdx = 1a
portIdx = 1b
portIdx = 1c
portIdx = 1d
portIdx = 1e
portIdx = 1f
portIdx = 20
portIdx = 40
portIdx = 41
portIdx =
IPU0log=
IPU1log=
HSM0log=
IMU0log= 42
portIdx = 43
portIdx = 44
portIdx = 45
portIdx = 46
portIdx = 47
portIdx = 48
portIdx = 49
portIdx = 4a
portIdx = 4b
portIdx = 4c
portIdx = 4d
portIdx = 4e
portIdx = 4f
portIdx = 50
portIdx = 51
portIdx = 52
IPU0log=
IPU1log=
HSM0log=
IMU0log=
portIdx = 53
portIdx = 54
portIdx = 55
portIdx = 56
portIdx = 57
portIdx = 58
portIdx = 59
portIdx = 5a
portIdx = 5b
portIdx = 5c
portIdx = 5d
portIdx = 5e
portIdx = 5f
portIdx = 60
Pcie slot[0] port:0 base 0x2c01
IPU0log=
IPU1log=
HSM0log=
IMU0log=000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[0] port:0 base 0x2c01000000, pcieSlotCtrl.data (after)0x0.

Pcie slot[1] port:1 base 0x2c01000000, pcieSlotCtrl.dat
IPU0log=
IPU1log=
HSM0log=
IMU0log=a (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[1] port:1 base 0x2c01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[2] port:2 base 0x2c01000000, pcieSlotCtrl.data (before)0x0.
pci
IPU0log=
IPU1log=
HSM0log=
IMU0log=eSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[2] port:2 base 0x2c01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[3] port:3 base 0x2c01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.pres
IPU0log=
IPU1log=
HSM0log=
IMU0log=encd_det_st = 1
present:1, pwr_en:0.
Pcie slot[3] port:3 base 0x2c01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[4] port:4 base 0x2c01000000, pcieSlotCtrl.data (before)0x10003c0.
pcieSlotCtrl.bits.presencd_det_st =
IPU0log=
IPU1log=
HSM0log=
IMU0log= 1
present:1, pwr_en:0.
Pcie slot[4] port:4 base 0x2c01000000, pcieSlotCtrl.data (after)0x14801c0.

Pcie slot[5] port:5 base 0x2c01000000, pcieSlotCtrl.data (before)0x3c0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, p
IPU0log=
IPU1log=
HSM0log=
IMU0log=wr_en:0.
Pcie slot[5] port:5 base 0x2c01000000, pcieSlotCtrl.data (after)0x4801c0.

Pcie slot[6] port:6 base 0x2c01000000, pcieSlotCtrl.data (before)0x3c0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie sl
IPU0log=
IPU1log=
HSM0log=
IMU0log=ot[6] port:6 base 0x2c01000000, pcieSlotCtrl.data (after)0x4801c0.

Pcie slot[7] port:7 base 0x2c01000000, pcieSlotCtrl.data (before)0x3c0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[7] port:7 base
IPU0log=
IPU1log=
HSM0log=
IMU0log= 0x2c01000000, pcieSlotCtrl.data (after)0x4801c0.

Pcie slot[8] port:8 base 0x2c02000000, pcieSlotCtrl.data (before)0x3c0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[8] port:8 base 0x2c02000000, pc
IPU0log=
IPU1log=
HSM0log=
IMU0log=ieSlotCtrl.data (after)0x7c0.

Pcie slot[9] port:9 base 0x2c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[9] port:9 base 0x2c02000000, pcieSlotCtrl.data (after
IPU0log=
IPU1log=
HSM0log=
IMU0log=)0x700.

Pcie slot[10] port:10 base 0x2c02000000, pcieSlotCtrl.data (before)0x10003c0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[10] port:10 base 0x2c02000000, pcieSlotCtrl.data (after)0x14801c0.
IPU0log=
IPU1log=
HSM0log=
IMU0log=

Pcie slot[11] port:11 base 0x2c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[11] port:11 base 0x2c02000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[12
IPU0log=
IPU1log=
HSM0log=
IMU0log=] port:12 base 0x2c02000000, pcieSlotCtrl.data (before)0x3c0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[12] port:12 base 0x2c02000000, pcieSlotCtrl.data (after)0x7c0.

Pcie slot[13] port:13 base 0
IPU0log=
IPU1log=
HSM0log=
IMU0log=x2c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[13] port:13 base 0x2c02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[14] port:14 base 0x2c02000000, pcieS
IPU0log=
IPU1log=
HSM0log=
IMU0log=lotCtrl.data (before)0x3c0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[14] port:14 base 0x2c02000000, pcieSlotCtrl.data (after)0x7c0.

Pcie slot[15] port:15 base 0x2c02000000, pcieSlotCtrl.data (be
IPU0log=
IPU1log=
HSM0log=
IMU0log=fore)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[15] port:15 base 0x2c02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[16] port:16 base 0x2d01000000, pcieSlotCtrl.data (before)0x10003c0.
p
IPU0log=
IPU1log=
HSM0log=
IMU0log=cieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[16] port:16 base 0x2d01000000, pcieSlotCtrl.data (after)0x14801c0.

Pcie slot[17] port:17 base 0x2d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bi
IPU0log=
IPU1log=
HSM0log=
IMU0log=ts.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[17] port:17 base 0x2d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[18] port:18 base 0x2d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det
IPU0log=
IPU1log=
HSM0log=
IMU0log=_st = 1
present:1, pwr_en:0.
Pcie slot[18] port:18 base 0x2d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[19] port:19 base 0x2d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
presen
IPU0log=
IPU1log=
HSM0log=
IMU0log=t:1, pwr_en:0.
Pcie slot[19] port:19 base 0x2d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[20] port:20 base 0x2d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
IPU0log=
IPU1log=
HSM0log=
IMU0log=
Pcie slot[20] port:20 base 0x2d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[21] port:21 base 0x2d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[21] 
IPU0log=
IPU1log=
HSM0log=
IMU0log=port:21 base 0x2d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[22] port:22 base 0x2d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[22] port:22 base 0x
IPU0log=
IPU1log=
HSM0log=
IMU0log=2d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[23] port:23 base 0x2d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[23] port:23 base 0x2d01000000, pci
IPU0log=
IPU1log=
HSM0log=
IMU0log=eSlotCtrl.data (after)0x480100.

Pcie slot[24] port:24 base 0x2d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[24] port:24 base 0x2d02000000, pcieSlotCtrl.data 
IPU0log=
IPU1log=
HSM0log=
IMU0log=(after)0x0.

Pcie slot[25] port:25 base 0x2d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[25] port:25 base 0x2d02000000, pcieSlotCtrl.data (after)0x700.

Pci
IPU0log=
IPU1log=
HSM0log=
IMU0log=e slot[26] port:26 base 0x2d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[26] port:26 base 0x2d02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[27] port:27
IPU0log=
IPU1log=
HSM0log=
IMU0log= base 0x2d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[27] port:27 base 0x2d02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[28] port:28 base 0x2d02000000
IPU0log=
IPU1log=
HSM0log=
IMU0log=, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[28] port:28 base 0x2d02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[29] port:29 base 0x2d02000000, pcieSlotCtrl.dat
IPU0log=
IPU1log=
HSM0log=
IMU0log=a (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[29] port:29 base 0x2d02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[30] port:30 base 0x2d02000000, pcieSlotCtrl.data (before)0x0.
pc
IPU0log=
IPU1log=
HSM0log=
IMU0log=ieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[30] port:30 base 0x2d02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[31] port:31 base 0x2d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.pr
IPU0log=
IPU1log=
HSM0log=
IMU0log=esencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[31] port:31 base 0x2d02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[32] port:32 base 0x3210000000, pcieSlotCtrl.data (before)0xffffffff.
pcieSlotCtrl.bits.presencd_det_
IPU0log=
IPU1log=
HSM0log=
IMU0log=st = 0
present:0, pwr_en:1.
Pcie slot[32] port:32 base 0x3210000000, pcieSlotCtrl.data (after)0xffffffff.

Pcie slot[33] port:0 base 0x6c01000000, pcieSlotCtrl.data (before)0x3c0.
pcieSlotCtrl.bits.presencd_det_st = 0
pres
IPU0log=
IPU1log=
HSM0log=
IMU0log=ent:0, pwr_en:1.
Pcie slot[33] port:0 base 0x6c01000000, pcieSlotCtrl.data (after)0x7c0.

Pcie slot[34] port:1 base 0x6c01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pc
IPU0log=
IPU1log=
HSM0log=
IMU0log=ie slot[34] port:1 base 0x6c01000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[35] port:2 base 0x6c01000000, pcieSlotCtrl.data (before)0x3c0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[35] port:2
IPU0log=
IPU1log=
HSM0log=
IMU0log= base 0x6c01000000, pcieSlotCtrl.data (after)0x7c0.

Pcie slot[36] port:3 base 0x6c01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[36] port:3 base 0x6c01000000, 
IPU0log=
IPU1log=
HSM0log=
IMU0log=pcieSlotCtrl.data (after)0x700.

Pcie slot[37] port:4 base 0x6c01000000, pcieSlotCtrl.data (before)0x3c0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[37] port:4 base 0x6c01000000, pcieSlotCtrl.data 
IPU0log=
IPU1log=
HSM0log=
IMU0log=(after)0x7c0.

Pcie slot[38] port:5 base 0x6c01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[38] port:5 base 0x6c01000000, pcieSlotCtrl.data (after)0x700.

Pci
IPU0log=
IPU1log=
HSM0log=
IMU0log=e slot[39] port:6 base 0x6c01000000, pcieSlotCtrl.data (before)0x3c0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[39] port:6 base 0x6c01000000, pcieSlotCtrl.data (after)0x7c0.

Pcie slot[40] port:7 
IPU0log=
IPU1log=
HSM0log=
IMU0log=base 0x6c01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[40] port:7 base 0x6c01000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[41] port:8 base 0x6c02000000, p
IPU0log=
IPU1log=
HSM0log=
IMU0log=cieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[41] port:8 base 0x6c02000000, pcieSlotCtrl.data (after)0x0.

Pcie slot[42] port:9 base 0x6c02000000, pcieSlotCtrl.data (befo
IPU0log=
IPU1log=
HSM0log=
IMU0log=re)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[42] port:9 base 0x6c02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[43] port:10 base 0x6c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCt
IPU0log=
IPU1log=
HSM0log=
IMU0log=rl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[43] port:10 base 0x6c02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[44] port:11 base 0x6c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_d
IPU0log=
IPU1log=
HSM0log=
IMU0log=et_st = 0
present:0, pwr_en:1.
Pcie slot[44] port:11 base 0x6c02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[45] port:12 base 0x6c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present
IPU0log=
IPU1log=
HSM0log=
IMU0log=:0, pwr_en:1.
Pcie slot[45] port:12 base 0x6c02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[46] port:13 base 0x6c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pci
IPU0log=
IPU1log=
HSM0log=
IMU0log=e slot[46] port:13 base 0x6c02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[47] port:14 base 0x6c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[47] port:14
IPU0log=
IPU1log=
HSM0log=
IMU0log= base 0x6c02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[48] port:15 base 0x6c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[48] port:15 base 0x6c02000000
IPU0log=
IPU1log=
HSM0log=
IMU0log=, pcieSlotCtrl.data (after)0x700.

Pcie slot[49] port:16 base 0x6d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[49] port:16 base 0x6d01000000, pcieSlotCtrl.dat
IPU0log=
IPU1log=
HSM0log=
IMU0log=a (after)0x0.

Pcie slot[50] port:17 base 0x6d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[50] port:17 base 0x6d01000000, pcieSlotCtrl.data (after)0x480100.

IPU0log=
IPU1log=
HSM0log=
IMU0log=
Pcie slot[51] port:18 base 0x6d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[51] port:18 base 0x6d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[52]
IPU0log=
IPU1log=
HSM0log=
IMU0log= port:19 base 0x6d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[52] port:19 base 0x6d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[53] port:20 base 0
IPU0log=
IPU1log=
HSM0log=
IMU0log=x6d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[53] port:20 base 0x6d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[54] port:21 base 0x6d01000000, pc
IPU0log=
IPU1log=
HSM0log=
IMU0log=ieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[54] port:21 base 0x6d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[55] port:22 base 0x6d01000000, pcieSlotCtrl.data
IPU0log=
IPU1log=
HSM0log=
IMU0log= (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[55] port:22 base 0x6d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[56] port:23 base 0x6d01000000, pcieSlotCtrl.data (before)0x0.

IPU0log=
IPU1log=
HSM0log=
IMU0log=pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[56] port:23 base 0x6d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[57] port:24 base 0x6d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bi
IPU0log=
IPU1log=
HSM0log=
IMU0log=ts.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[57] port:24 base 0x6d02000000, pcieSlotCtrl.data (after)0x0.

Pcie slot[58] port:25 base 0x6d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st =
IPU0log=
IPU1log=
HSM0log=
IMU0log= 1
present:1, pwr_en:0.
Pcie slot[58] port:25 base 0x6d02000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[59] port:26 base 0x6d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, 
IPU0log=
IPU1log=
HSM0log=
IMU0log=pwr_en:0.
Pcie slot[59] port:26 base 0x6d02000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[60] port:27 base 0x6d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie
IPU0log=
IPU1log=
HSM0log=
IMU0log= slot[60] port:27 base 0x6d02000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[61] port:28 base 0x6d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[61] port:
IPU0log=
IPU1log=
HSM0log=
IMU0log=28 base 0x6d02000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[62] port:29 base 0x6d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[62] port:29 base 0x6d020
IPU0log=
IPU1log=
HSM0log=
IMU0log=00000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[63] port:30 base 0x6d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[63] port:30 base 0x6d02000000, pcieSlot
IPU0log=
IPU1log=
HSM0log=
IMU0log=Ctrl.data (after)0x480100.

Pcie slot[64] port:31 base 0x6d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[64] port:31 base 0x6d02000000, pcieSlotCtrl.data (afte
IPU0log=
IPU1log=
HSM0log=
IMU0log=r)0x480100.

Pcie slot[65] port:32 base 0x7210000000, pcieSlotCtrl.data (before)0xffffffff.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[65] port:32 base 0x7210000000, pcieSlotCtrl.data (after)0xffff
IPU0log=
IPU1log=
HSM0log=
IMU0log=ffff.

[RegisterInterruptSource]:[21] begin
Interrupt 61 register OK
[RegisterInterruptSource]:[39] end
fristMskExt0Int

Pcie Hotplug init done, with 66 port(s).
[0.07.20.539]BIOS POST END.
slot[0] port:0 begin to power ON
IPU0log=
IPU1log=
HSM0log=
IMU0log=.
slot[0] port:0 pwr_indicator = 0, att_indicator = 0
ledStatus:0 invalid!
[HotPlugMonitorTask][248L]Pcie slot[0] port:0 base 0x2c01000000, pcieSlotCtrl.data (after)0x100000.
slot[1] port:1 begin to power ON.
slot[2] port:2
IPU0log=
IPU1log=
HSM0log=
IMU0log= begin to power ON.
slot[3] port:3 begin to power ON.
slot[4] port:4 begin to power ON.
slot[5] port:5 begin to power ON.
slot[6] port:6 begin to power ON.
slot[7] port:7 begin to power ON.
slot[8] port:8 begin to power OF
IPU0log=
IPU1log=
HSM0log=
IMU0log=F.
slot[9] port:9 begin to power OFF.
slot[10] port:10 begin to power ON.
slot[11] port:11 begin to power ON.
slot[12] port:12 begin to power OFF.
slot[13] port:13 begin to power OFF.
slot[14] port:14 begin to power OFF.

IPU0log=
IPU1log=
HSM0log=
IMU0log=slot[15] port:15 begin to power OFF.
slot[16] port:16 begin to power ON.
slot[17] port:17 begin to power ON.
slot[18] port:18 begin to power ON.
slot[19] port:19 begin to power ON.
slot[20] port:20 begin to power ON.
slot[
IPU0log=
IPU1log=
HSM0log=
IMU0log=21] port:21 begin to power ON.
slot[22] port:22 begin to power ON.
slot[23] port:23 begin to power ON.
slot[24] port:24 pwr_indicator = 0, att_indicator = 0
ledStatus:0 invalid!
[HotPlugMonitorTask][248L]Pcie slot[24] port:
IPU0log=
IPU1log=
HSM0log=
IMU0log=24 base 0x2d02000000, pcieSlotCtrl.data (after)0x100000.
slot[25] port:25 begin to power OFF.
slot[26] port:26 begin to power OFF.
slot[27] port:27 begin to power OFF.
slot[28] port:28 begin to power OFF.
slot[29] port:29 b
IPU0log=
IPU1log=
HSM0log=
IMU0log=egin to power OFF.
slot[30] port:30 begin to power OFF.
slot[31] port:31 begin to power OFF.
slot[32] port:32 begin to power OFF.
slot[33] port:0 begin to power OFF.
slot[34] port:1 begin to power OFF.
slot[35] port:2 begi
IPU0log=
IPU1log=
HSM0log=
IMU0log=n to power OFF.
slot[36] port:3 begin to power OFF.
slot[37] port:4 begin to power OFF.
slot[38] port:5 begin to power OFF.
slot[39] port:6 begin to power OFF.
slot[40] port:7 begin to power OFF.
slot[41] port:8 pwr_indica
IPU0log=
IPU1log=
HSM0log=
IMU0log=tor = 0, att_indicator = 0
ledStatus:0 invalid!
[HotPlugMonitorTask][248L]Pcie slot[41] port:8 base 0x6c02000000, pcieSlotCtrl.data (after)0x100000.
slot[42] port:9 begin to power OFF.
slot[43] port:10 begin to power OFF.
s
IPU0log=
IPU1log=
HSM0log=
IMU0log=lot[44] port:11 begin to power OFF.
slot[45] port:12 begin to power OFF.
slot[46] port:13 begin to power OFF.
slot[47] port:14 begin to power OFF.
slot[48] port:15 begin to power OFF.
slot[49] port:16 begin to power ON.
sl
IPU0log=
IPU1log=
HSM0log=
IMU0log=ot[49] port:16 pwr_indicator = 0, att_indicator = 0
ledStatus:0 invalid!
[HotPlugMonitorTask][248L]Pcie slot[49] port:16 base 0x6d01000000, pcieSlotCtrl.data (after)0x100000.
slot[50] port:17 begin to power ON.
slot[51] port
IPU0log=
IPU1log=
HSM0log=
IMU0log=:18 begin to power ON.
slot[52] port:19 begin to power ON.
slot[53] port:20 begin to power ON.
slot[54] port:21 begin to power ON.
slot[55] port:22 begin to power ON.
slot[56] port:23 begin to power ON.
slot[57] port:24 be
IPU0log=
IPU1log=
HSM0log=
IMU0log=gin to power ON.
slot[57] port:24 pwr_indicator = 0, att_indicator = 0
ledStatus:0 invalid!
[HotPlugMonitorTask][248L]Pcie slot[57] port:24 base 0x6d02000000, pcieSlotCtrl.data (after)0x100000.
slot[58] port:25 begin to powe
IPU0log=
IPU1log=
HSM0log=
IMU0log=r ON.
slot[59] port:26 begin to power ON.
slot[60] port:27 begin to power ON.
slot[61] port:28 begin to power ON.
slot[62] port:29 begin to power ON.
slot[63] port:30 begin to power ON.
slot[64] port:31 begin to power ON.
IPU0log=
IPU1log=
HSM0log=
IMU0log=
slot[65] port:32 begin to power OFF.
[0.07.24.216]wait 5 mins to update pciemmio..
[0.12.24.215]IpmiCmdReportPcieMMIO start
[0.12.28.533]IpmiCmdReportPcieMMIO end

IPU0log=
IPU1log=
HSM0log=