 Q      ExpBoard1 Q	    @                       Q$  `c@#o         Watchdog2 Q  -      TS200-2280 Q P     BMCCard Q       BMC Q      FanBoard1 Q      NIC 2 (SF221Q)	 Q      PSU2
 Q      PSU1 Q      M2TransferCard6 Q 
     PCIe Riser1
 Q      Zijin-DPU Q#  `c@o             SYS_Boot Q9  ` p  d        i      1711 Core Temp Q(  `c@(o ! ! !         Mngmnt Health Q7  c         ~     *              FAN4_F_Speed Q7  c         ~     *              FAN4_R_Speed Q4  
`h        p ^                  PSU2_POut Q&  
`co O O O         PSU2_Supply Q:  	
`h                             PSU2_Inlet_Temp Q3  

`h                              PSU2_VIn Q&    c@	             Power_Fault Q4  
`h                             PSU2_Temp Q2  
`h                              PS2 IIn Q3  
`h        p z                  PSU2_PIn Q4  
`h                              PSU2_VOut Q*  
`c!o            PS2 Temp Status Q3  
`h                              PS2 IOUT Q2  
ah                              PS1 IIn Q3  
ah        p o                  PSU1_PIn  Q4  
ah                              PSU1_VOut! Q*  
ac!o            PS1 Temp Status" Q3  
ah                              PS1 IOUT# Q4  
ah        p N                  PSU1_POut$ Q&  
aco O O O         PSU1_Supply% Q:  
ah                             PSU1_Inlet_Temp& Q3  
ah                              PSU1_VIn' Q&    c@	             Power_Fault( Q4  
ah                             PSU1_Temp) Q5  7`hrr  d       +)      Inlet_Temp* Q9  ah                           EXU1 NIC1 Temp+ Q9  ah                           EXU1 NIC2 Temp, Q4   a                          FAN_Power- Q:  !a                  EXU1 VCC_12V0_3. Q8  "a        d    n  Z    EXU1 STBY_5V0/ Q(  #ac@o            PwrOn TimeOut0 Q7  $a        d    n  Z    EXU1 VCC_5V01 Q*  %ac@o            PwrOk Sig. Drop2 Q%  &ac@"o a   a         ACPI_State3 Q6  'ah p  d        K      Outlet_Temp4 Q:  (a                  EXU1 VCC_12V0_25 Q:  )a                  EXU1 VCC_12V0_16 Q8  *a                  EXU1 STBY_3V37 Q8  +ah                           EXU1 PSU Temp8 Q%  ,ac@o             UID_Button9 Q&  -ac@	             Power_Fault: Q'  .ac@o             Power_Button; Q&  /3c
o            M2_1_Status< Q2  0eh        d                 M2_Temp= Q&  12c
o            M2_0_Status> Q'  2ac@
            FAN2_Present? Q'  3dc@
            FAN4_Present@ Q(  4dc!o            FAN4_F_StatusA Q6  5e
              *              PUMP2 SpeedB Q4  6uh        d                  CLU1 TempC Q(  7`c!o            FAN1_F_StatusD Q(  8ac!o            FAN2_R_StatusE Q(  9`c!o            FAN1_R_StatusF Q(  :bc!o            FAN3_R_StatusG Q(  ;dc!o            FAN4_R_StatusH Q'  <`c@
            FAN1_PresentI Q(  =bc!o            FAN3_F_StatusJ Q6  >f
              *              PUMP1 SpeedK Q'  ?bc@
            FAN3_PresentL Q(  @ac!o            FAN2_F_StatusM Q7  Ag         ~     *              FAN2_F_SpeedN Q7  Bg         ~     *              FAN2_R_SpeedO Q4  C*`h p  d        s      NIC2 TempP Q&  D  c@	             Power_FaultQ Q6  E`h p  d         i      Riser1_TempR Q9  Ff        d                 DPU_CPU_InTempS Q:  Gf p  d         }      DPU_FPGA_VRTempT Q'  Hfc@o            DPU_P0_C1_D0U Q9  If         d                   DPU_DIMM_PowerV Q7  Jf p  d         d      DPU_CPU_TempW Q'  K  c@o
0
0
0         PCIe2_StatusX Q8  Lf        d                  DPU_DIMM_TempY Q9  Mf p  d         }      DPU_MEM_VRTempZ Q9  Nf p  d         }      DPU_CPU_VRTemp[ Q*  Ofc@o
0
0
0         DPU_PCIE_Status\ Q8  Pfh         d                   DPU_CPU_Power] Q9  Qf         d                   DPU_FPGA_Power^ Q*  Rfc@o         DPU_CPU0_Status_ Q:  Sf         d                   DPU_Total_Power` Q(  Tfc@o         DPU_P0_G0_Hota Q8  Uf p  d         K      DPU_OPT0_Tempb Q%  Vfc@o            DPU_PWR_Onc Q'  Wfc@o            DPU_P0_C0_D0d Q8  Xf p  d         K      DPU_OPT1_Tempe Q'  Yfc@o            DPU_PWR_Dropf Q*  Zfc@o 0 0 0         DPU_FPGA_Statusg Q)  [fc@o @   @         DPU_SOC_Statush Q:  \f        d                  DPU_CPU_OutTempi Q6  ]f        d                  DPU_M2_Tempj Q(  ^fc@             DPU_ME_Statusk Q:  _f        d                  DPU_FPGA_InTempl Q8  `f p  d         d      DPU_FPGA_Tempm Q;  af        d                  DPU_FPGA_OutTempn Q*  b lco            P0_CC_D0_Statuso Q*  c kco            P0_CB_D0_Statusp Q*  d aco            P0_C1_D0_Statusq Q*  e bco            P0_C2_D0_Statusr Q*  f cco            P0_C3_D0_Statuss Q*  g dco            P0_C4_D0_Statust Q*  h eco            P0_C5_D0_Statusu Q*  i hco            P0_C8_D0_Statusv Q*  j ico            P0_C9_D0_Statusw Q*  k co            P1_CF_D0_Statusx Q*  l jco            P0_CA_D0_Statusy Q*  m pco            P1_C0_D0_Statusz Q*  n qco            P1_C1_D0_Status{ Q*  o rco            P1_C2_D0_Status| Q*  p sco            P1_C3_D0_Status} Q*  q tco            P1_C4_D0_Status~ Q*  r wco            P1_C7_D0_Status Q*  s xco            P1_C8_D0_Status Q*  t vco            P1_C6_D0_Status Q*  u {co            P1_CB_D0_Status Q*  v |co            P1_CC_D0_Status Q*  w ~co            P1_CE_D0_Status Q*  x mco            P0_CD_D0_Status Q*  y zco            P1_CA_D0_Status Q*  z yco            P1_C9_D0_Status Q*  { `co            P0_C0_D0_Status Q*  | nco            P0_CE_D0_Status Q*  } uco            P1_C5_D0_Status Q*  ~ fco            P0_C6_D0_Status Q*   oco            P0_CF_D0_Status Q*   }co            P1_CD_D0_Status Q*   gco            P0_C7_D0_Status Q7  h         ~     *              FAN3_F_Speed Q7  h         ~     *              FAN3_R_Speed Q'  bc@            Op. Log Full Q$  bc@o 4   $         Event_Log Q(  bc@            Sec. Log Full Q6  ch                             Total_Power Q(  cc            PwrCap Status Q(  ac@            Redundant_PSU Q7  c                             SSD MAX Temp Q5  c                             Disks Temp Q;  ah p  d          x      CPU2 N4AVDD Temp Q&  ac@o         CPU2_Status Q;  `       P    c  D    CPU1 0V9_N3_DVDD Q;  `h p  d          x      CPU1 0V9_N3 Temp Q;  `h p  d          x      CPU1 TDTCUC Temp Q;  `h p  d          x      CPU1 TCCORE Temp Q;  `h p  d          x      CPU1 0V9_N4 Temp Q;  `h p  d          x      CPU1 TDTCVQ Temp Q;  `       P      :    CPU1 0V9_TA_CORE Q&  `c@o         CPU1_Status Q;  ah p  d          x      CPU2 TACORE Temp Q#  dc@o             BMC_Boot Q;  ah p  d          x      CPU2 0V8_N3 Temp Q;  a       P    c  D    CPU2 0V7_TDTC_VD Q;  a       P    X  H    CPU2 0V8_N2_DVDD Q;  a       n      l    CPU2 1V2_N4_AVDD Q:  
bh                        ((   BCU1 12V0_1 Pwr Q;  `       P    c  D    CPU1 0V7_TDTC_VD Q;  a       P    X  H    CPU2 0V8_N3_DVDD Q;  ah p  d          x      CPU2 N1N4DV Temp Q;  ah p  d          x      CPU2 N2AVDD Temp Q;  a       P      :    CPU2 0V9_TD_CORE Q'  dco            SYS_Progress Q;  a       n    y  c    CPU2 1V1_TBTA_VQ Q;  ah p  d          x      CPU2 TBTAUC Temp Q:  d       n    z  b    BCU1 3V3_RISER2 Q9  d       B    H  <    BCU1 VCC_DRMOS Q5  d                 SYS_12V0_4 Q;  a       x      l    CPU2 1V2_N1_AVDD Q5  d                 SYS_12V0_2 Q;  a       x      l    CPU2 1V2_N2_AVDD Q;  ah p  d          x      CPU2 TBTAVQ Temp Q5  d                 SYS_12V0_3 Q;  a       x      l    CPU2 1V2_N3_AVDD Q;  ah p  d          x      CPU2 TCCORE Temp Q;  `       P    X  H    CPU1 0V8_N1N4_DV Q9  %a p           _      CPU2_DIMM_Temp Q7  `h              x      CPU1_VR_Temp Q;  `       n    y  c    CPU1 1V1_TBTA_VQ Q7  ah              x      CPU2_VR_Temp Q;  `h p  d          x      CPU1 0V9_N2 Temp Q;  ah p  d          x      CPU2 0V9_N1 Temp Q;  ah p  d          x      CPU2 0V8_N2 Temp Q;  a       n    y  c    CPU2 1V1_TDTC_VQ Q4  `h                             MEM_Power Q9  ah                             CPU2_MEM_Power Q6  `h                             CPU1_VR_Pwr Q4  d                             CPU_Power Q;  `       n    y  c    CPU1 1V1_TDTC_VQ Q6  ah                             CPU2_VR_Pwr Q;  a       P    c  D    CPU2 0V9_N3_DVDD Q;  a       P    X  H    CPU2 0V8_N1N4_DV Q;  a       P    c  D    CPU2 0V7_TBTA_VD Q;  a       P    c  D    CPU2 0V9_N4_DVDD Q3  d       n    z  b    SYS_3.3V Q;  ah p  d          x      CPU2 0V9_N2 Temp Q;  `h p  d          x      CPU1 N3AVDD Temp Q;  ah p  d          x      CPU2 TBCORE Temp Q;  `h p  d          x      CPU1 TDTCVD Temp Q;  `h p  d          x      CPU1 TACORE Temp Q;  a       P      :    CPU2 0V9_TB_CORE Q%  dco            Boot Error Q8  
bh                       ((   BCU1 stby Pwr Q"  dc@)o          P3V_BAT Q4  arr  d       ni      CPU2_Temp Q'  dc@o            System Error Q;  `       P    c  D    CPU1 0V7_TBTA_VD Q(  dc@            System Notice Q;  ah p  d          x      CPU2 N3AVDD Temp Q:  
bh         @              ((   BCU1 12V0_2 Pwr Q:  
bh         @              ((   BCU1 12V0_3 Pwr Q;  `       P    c  D    CPU1 0V9_N4_DVDD Q;  ah p  d          x      CPU2 TDTCUC Temp Q;  a       P    c  D    CPU2 0V9_N2_DVDD Q;  ah p  d          x      CPU2 TDTCVD Temp Q;  `       P      :    CPU1 0V9_TB_CORE Q;  ah p  d          x      CPU2 TDCORE Temp Q"  dc@o             OS_Boot Q;  `h p  d          x      CPU1 TBTAVQ Temp Q;  a       P      :    CPU2 0V9_TC_CORE Q4  `rr  d       ni      CPU1_Temp Q;  ah p  d          x      CPU2 TDTCVQ Temp Q9  %` p           _      CPU1_DIMM_Temp Q;  a       P    c  C    CPU2 0V9_N1_DVDD Q;  ah p  d          x      CPU2 N1AVDD Temp Q;  `h p  d          x      CPU1 TBCORE Temp Q;  a       P    n  C    CPU2 0V9_TBTA_UC Q*  dc@+             BMC_Update_Fail Q;  `h p  d          x      CPU1 TDCORE Temp Q;  a       P    n  C    CPU2 0V9_TDTC_UC Q;  `       P      :    CPU1 0V9_TD_CORE Q;  `       P    c  D    CPU1 0V9_N2_DVDD Q;  `h p  d          x      CPU1 0V9_N1 Temp Q;  `h p  d          x      CPU1 TBTAVD Temp Q;  `       P    c  C    CPU1 0V9_N1_DVDD Q&  dc@	             Power_Fault Q;  `h p  d          x      CPU1 TBTAUC Temp Q'  dc@o             BIOS_Boot_Up Q;  `h p  d          x      CPU1 0V8_N3 Temp Q;  `       P    X  H    CPU1 0V8_N3_DVDD Q:  
bh                        ((   BCU1 12V0_4 Pwr Q9  `h                             CPU1_MEM_Power Q6  dh p           K      NIC OM Temp Q;  `       P      :    CPU1 0V9_TC_CORE  Q;  `       x      l    CPU1 1V2_N1_AVDD Q;  `       n      l    CPU1 1V2_N2_AVDD Q;  `       n      l    CPU1 1V2_N3_AVDD Q;  `       x      l    CPU1 1V2_N4_AVDD Q;  ah p  d          x      CPU2 TBTAVD Temp Q;  `h p  d          x      CPU1 N1AVDD Temp Q;  `h p  d          x      CPU1 N1N4DV Temp Q;  ah p  d          x      CPU2 0V9_N3 Temp Q;  `h p  d          x      CPU1 N2AVDD Temp	 Q;  `h p  d          x      CPU1 N4AVDD Temp
 Q;  ah p  d          x      CPU2 0V9_N4 Temp Q;  `       P    X  H    CPU1 0V8_N2_DVDD Q; `h p  d          x      CPU1 0V8_N2 Temp
 Q; a       P      :    CPU2 0V9_TA_CORE Q$ dc@+o             FW_Update Q; `       P    n  C    CPU1 0V9_TBTA_UC Q4 `h                         BCU1 Temp Q; `       P    n  C    CPU1 0V9_TDTC_UC Q+ dc@+             BIOS_Update_Fail Q7 i         ~     *              FAN1_F_Speed Q7 	i         ~     *              FAN1_R_Speed Q      CpuBoard1