
IMU0log=1T1N1U skt:0 CfgBusDfxPreConfig finish

********Hello Huawei LiteOS********

IMU Firmware Version : B173V01
LiteOS Kernel Version : 5.10.0
Run on Socket[0] Die[3]
Chip Version: 1
Max socket num: 2
*******************************
IPU0log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 0
cls: 6, core: 7
cpu 933 sram 1010 ddr 983
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  750|  802|  885|  933|
max  v
IPU1log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 1
cls: 6, core: 7
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  759|  821|  909|  961|
max  v: |  750|  750|  753|  781
HSM0log=[1970-01-01 00:01:12.167][HSM][INFO][30] init start
[1970-01-01 00:01:12.167][HSM][INFO][38] init over
[00:01:12.177][info] succeed to do thirdparty dfx_pabuk init
[00:01:12.183][info] os_mem_system_init default pool done
[0
IMU0log=***
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | rail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_vo
IPU0log=: |  750|  750|  754|  775|  836|  922|  980|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:7
IPU1log=|  846|  938|  994|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:750 F:1950
avs-uncore V:750
HSM0log=0:01:12.189][info] addr is already in region
[00:01:12.192][info] succeed to do thirdparty otpc_pabuk init
[1970-01-01 00:01:12.197][HSM][INFO][31] select_region: 0xc11cb55b
[1970-01-01 00:01:12.203][HSM][INFO][67] spi_nor de
IMU0log=lt:1122 mV | pmu:MP2882
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_v
IPU0log=50 F:1950
avs-uncore V:750 F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
av
IPU1log= F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
avs-uncore V:840 F:2450
avs-
HSM0log=vice_id 0xff1a67c8
[1970-01-01 00:01:12.209][HSM][INFO][50] std_cmd readback 0x30220d8
[1970-01-01 00:01:12.215][HSM][INFO][72] saf_cmd 0x0 readback 0x9f5a0604
[1970-01-01 00:01:12.222][HSM][INFO][72] saf_cmd 0x1 readback 0x5
IMU0log=olt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_
IPU0log=s-uncore V:840 F:2450
avs-uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain
IPU1log=uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | r
HSM0log=b7e938
[1970-01-01 00:01:12.228][HSM][INFO][72] saf_cmd 0x2 readback 0x1
[1970-01-01 00:01:12.234][HSM][INFO][72] saf_cmd 0x3 readback 0x0
[1970-01-01 00:01:12.240][HSM][INFO][72] saf_cmd 0x4 readback 0x0
[00:01:12.246][info
IMU0log=volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus r
IPU0log=[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | p
IPU1log=ail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_volt:1122 mV | pmu:MP2882
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[0] volt =  906 mV
pwr domain
HSM0log=] succeed to do thirdparty boot_profile_driver init
[00:01:12.252][info] succeed to do thirdparty crypto_driver init
[00:01:12.257][info] succeed to do thirdparty period_driver init
[00:01:12.263][info]  start loading interna
IMU0log=eady.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait th
IPU0log=mu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pmbus:0x480c0000 ver:0x110
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
IPU1log=[9] volt = 1103 mV
=end=
w&h rd rail:0, 906
w&h rd rail:1, 1103
pwr domain[0] set volt  904 mV succ
pwr domain[9] set volt 1103 mV succ
volt post
pwr domain[0] volt =  904 mV
pwr domain[9] volt = 1103 mV
==end==
Totem[0] Core Bo
HSM0log=l task ...
[00:01:12.268][info]  task name is ccm_task
[00:01:12.272][info]  hm_dynamic_loadelf successfully!
[00:01:12.277][info] internal task[1] task_name=ccm_task load successfully
[00:01:12.283][info]  task name is upgr
IMU0log=e cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master I
IPU0log=
avsbus resync succ
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[2] volt =  904 mV
pwr domain[7] volt =  802 mV
pwr domain[4] volt =  806 mV
pwr domain[1] volt =  804 mV
=end=
w&h rd rail:
IPU1log=ot Vol [1029]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2,
HSM0log=ade_task
[00:01:12.288][info]  hm_dynamic_loadelf successfully!
[00:01:12.292][info] internal task[2] task_name=upgrade_task load successfully
[00:01:12.299][info] created task ccm_task success!
[00:01:12.304][info] created 
IMU0log=mu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
cpu 0 entering scheduler
|--------------------------------------------------|
AtsPrint
|idx|lockCount| srcAddr| destAddr| addrLen|
|--
IPU0log=0, 904
w&h rd rail:1, 802
pwr domain[2] set volt  902 mV succ
pwr domain[7] set volt  802 mV succ
w&h rd rail:0, 806
w&h rd rail:1, 804
pwr domain[4] set volt  804 mV succ
pwr domain[1] set volt  802 mV succ
volt post
pwr domain
IPU1log= ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd8
HSM0log=task upgrade_task success!
[1970-01-01 00:01:12.309][HSM][INFO][54] Platform init 0x20250523 0x4e.
[1970-01-01 00:01:12.315][HSM][INFO][197] ccm start.
[1970-01-01 00:01:12.320][HSM][INFO][86] upgrade task init success.
[197
IMU0log=------------------------------------------------|
|  0|00000000|0x010500000|0x000110800000|0x00100000|
|  1|00000000|0x020000000|0x00001d000000|0x00800000|
|  2|00000000|0x020800000|0x000490000000|0x00100000|
|  3|00000000|0x020
IPU0log=[2] volt =  904 mV
pwr domain[7] volt =  802 mV
pwr domain[4] volt =  802 mV
pwr domain[1] volt =  802 mV
==end==
Totem[0] Core Boot Vol [1015]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0,
IPU1log=00, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
opposite dieId: 0, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 
HSM0log=0-01-01 00:01:12.326][HSM][INFO][95] upgrade recv cmd, 0x181.
[1970-01-01 00:01:12.332][HSM][INFO][103] upgrade res, 0x3a5aa5a3.
.
IMU0log=900000|0x000004000000|0x08000000|
|  4|00000000|0x028900000|0x000440580000|0x01000000|
|  5|00000000|0x029900000|0x000590000000|0x00100000|
|  6|00000000|0x029a00000|0x002000150000|0x00100000|
|  7|00000000|0x000000000|0x0000000
IPU0log= MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 
IPU1log=enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
hiboost task entry
boost wait SEF.
[INFO] mem used of task 'app_Task' is:0x2028, not zero when task being deleted
boost param OK.
Totem[0] Core[ 0] Freq Limit Low
HSM0log=
IMU0log=00000|0x00000000|
|  8|00000000|0x040000000|0x000000000000|0x08000000|
|  9|00000000|0x048000000|0x000000000000|0x08000000|
| 10|00000000|0x050000000|0x000000000000|0x08000000|
| 11|00000000|0x058000000|0x000000000000|0x08000000
IPU0log=0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
tsensor type
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Fr
HSM0log=
IMU0log=|
| 12|00000000|0x060000000|0x000000000000|0x08000000|
| 13|00000000|0x068000000|0x000000000000|0x08000000|
| 14|00000000|0x070000000|0x000000000000|0x08000000|
| 15|00000000|0x078000000|0x000490000000|0x08000000|
|-------------
IPU0log=: 3, ppuFormatK: 0x4da6, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b4,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 3, mask: fffffff8
tsensor type: 4, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=-------------------------------------|
=~=~=~=~=~=~=~=~=~=~= IMU Log @ 2026.4.10 3:27:37 =~=~=~=~=~=~=~=~=~=~=
[IMU] Watchdog Initialization done!
[RegisterInterruptSource]:[21] begin
Interrupt 32 register OK
Interrupt 34 regi
IPU0log=0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 4, mask: ffffffee
tsensor type: 5, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1

IPU1log= Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=ster OK
Interrupt 40 register OK
Interrupt 44 register OK
sram cnt 0x0, id = 43
Interrupt 43 register OK
Interrupt 36 register OK
Interrupt 57 register OK
sram cnt 0x0, id = 42
Interrupt 42 register OK
Interrupt 37 register OK
[
IPU0log=tsensor: 5, mask: ffffffda
tsensor type: 6, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 6, mask: ffffff80
tsensor type: 7, ppuFormatK: 0x437a,
IPU1log=KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=RegisterInterruptSource]:[39] end
IPMB initialization Start...
IPMB clock set done, prer = 0x18.
IPMB Rx FIFO clear empty.
IPMB initialization Done.
starting DFX Collect Task end
PowerTask Entry ...
Wait all vrd init done 
IPU0log= ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 7, mask: fffffffe
opposite dieId: 1, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
CPM max V[900]-
IPU1log= Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low
HSM0log=
IMU0log=...
All vrd init done, power task start
refresh domainId 0 Lsb 0x0
refresh domainId 9 Lsb 0x1
refresh domainId 2 Lsb 0x0
refresh domainId 7 Lsb 0x1
refresh domainId 4 Lsb 0x0
refresh domainId 1 Lsb 0x1
power sensor[0] | calib:51
IPU0log=F:2800
CPM min V[750]-F:1600
freq:2350, idx:9
cpm trim freq: 2600, idx: 4
cpm trim finish
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
recount hours 
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Fr
HSM0log=
IMU0log=20 | rshunt:1 | rshuntDiv:1000 | currLsb:1 | currLsbDiv:1000 | enableFlag:1
                | pwrLsb:25 | defPwr:25000 | minPwr:10000 | maxPwr:65000 | pwrFix:3400
                | manufacturerId: 0x5549 | dieId: 0x2260
power se
IPU0log=0x69c 
hiboost task entry
boost wait SEF.
boost param OK.
Totem[0] Core[ 0] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[26
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=nsor[0] init success
ScmiTaskEntry start.
[RegisterInterruptSource]:[21] begin
Interrupt 51 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 52 register OK
[RegisterInterruptSource
IPU0log=00000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[12000
IPU1log= Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 53 register OK
[RegisterInterruptSource]:[39] end
[0.01.28.865]starting ras Init
RAS Setup Value get done!
INT_NUM_PER_SKT * HiGetSktNum() = 0x8
index = 0x0
RasIntRegi
IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Lim
IPU1log=KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=ster init 160 
index = 0x1
RasIntRegister init 172 
index = 0x2
RasIntRegister init 162 
index = 0x3
RasIntRegister init 174 
index = 0x4
RasIntRegister init 184 
index = 0x5
RasIntRegister init 196 
index = 0x6
RasIntRegister i
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IPU1log= Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low
HSM0log=
IMU0log=nit 186 
index = 0x7
RasIntRegister init 198 
RasIntRegister init 161 
RasIntRegister init 173 
RasIntRegister init 185 
RasIntRegister init 197 
RasIntRegister init 284 
RasIntRegister init 314 
MceTableHeadInit start
starting 
IPU0log=14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
To
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
uncore max freq : 23
HSM0log=
IMU0log=Ce_Storm Contrl and Ras_Data_Update Task end
[0.01.28.947]starting ras end
[IMU][ERR] skt id 0
Ub init task start Entry ...
UbInitTask Entry ...
[RegisterInterruptSource]:[21] begin
Interrupt 167 register OK
[RegisterInterrup
IPU0log=tem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[26
IPU1log=50 MHz

HSM0log=
IMU0log=tSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 191 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 171 register OK
[RegisterInterruptSource]:[39] end
[Register
IPU0log=00000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[12000
IPU1log=
HSM0log=
IMU0log=InterruptSource]:[21] begin
Interrupt 183 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 195 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Lim
IPU1log=
HSM0log=
IMU0log=
Interrupt 207 register OK
[RegisterInterruptSource]:[39] end
Init heart-beat-task end
CS0 flash do not support sfdp!
Current flash device ID[0x61a67c8]!
System supported 1 Flash.
flash cs 0 Manufacture 0xc8, DeviceId 0x1a67, A
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IPU1log=
HSM0log=
IMU0log=ddrMode[0-3B,1-4B] 0x1:
    size 0x4000000, pagesize 0x100
    read  cmd 0x13, dummy byte 0x8
    write cmd 0x12, dummy byte 0x0
    erase4k cmd 0x21, erase64k byte 0xdc
sfc init end
firstUnMskExt0Int
ThermalDimmStart Entry ...
IPU0log=33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
To
IPU1log=
HSM0log=
IMU0log=
wait ddr init done...
HacLowPowerStart Entry ...
Hello LiteOS...
pwr cap[0]: 0, 67
Init ReportPcieMmioToBmcTaskEntry end
starting Fpc Isolation Task end
BMC_COLLECTION: bmc req last log!
[IMU][ERR] [
IPU3log= no log data err
IPU0log=tem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[26
IPU1log=
HSM0log=
IMU0log=or!]
pwr cap[1]: f, 27
pwr cap[2]: 1, 3
[IMU][ERR] IMP log not ready, DDR initing...
[IMU][ERR] IMP log not ready, DDR initing...
[IMU][ERR] IMP log not ready, DDR initing...
[0.03.53.215]DDR init done
[LOG]head = 0x0, tail = 
IPU0log=00000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
uncore max freq : 2350 MHz

IPU1log=
HSM0log=
IMU0log=0x18d8, logSize = 0x18d8
[IMU][ERR] HsmLogInit!
[IMU][ERR] HsmLogInit! TRUE
set apei done!
UbConfigData size is 64
UbConfigData 0 : 0
UbConfigData 1 : 0
UbConfigData 2 : 0
UbConfigData 3 : 1
UbConfigData 4 : 31
UbConfigData 5 : 
IPU0log=
IPU1log=
HSM0log=
IMU0log=1
UbConfigData 6 : 0
UbConfigData 7 : 32
UbConfigData 8 : 0
UbConfigData 9 : 1
UbConfigData 10 : 2
UbConfigData 11 : 0
UbConfigData 12 : 0
UbConfigData 13 : 1
UbConfigData 14 : 0
UbConfigData 15 : 0
UbConfigData 16 : 0
UbConfigD
IPU0log=
IPU1log=
HSM0log=
IMU0log=ata 17 : 0
UbConfigData 18 : 0
UbConfigData 19 : 0
UbConfigData 20 : 0
UbConfigData 21 : 0
UbConfigData 22 : 11
UbConfigData 23 : 0
UbConfigData 24 : 0
UbConfigData 25 : 0
UbConfigData 26 : 0
UbConfigData 27 : 0
UbConfigData 28 
IPU0log=
IPU1log=
HSM0log=
IMU0log=: 0
UbConfigData 29 : 0
UbConfigData 30 : 0
UbConfigData 31 : 0
UbConfigData 32 : 0
UbConfigData 33 : 0
UbConfigData 34 : 2
UbConfigData 35 : 1
UbConfigData 36 : 0
UbConfigData 37 : 0
UbConfigData 38 : 0
UbConfigData 39 : 0
UbCo
IPU0log=
IPU1log=
HSM0log=
IMU0log=nfigData 40 : 0
UbConfigData 41 : 0
UbConfigData 42 : 0
UbConfigData 43 : 0
UbConfigData 44 : 0
UbConfigData 45 : 0
UbConfigData 46 : 0
UbConfigData 47 : 0
UbConfigData 48 : 0
UbConfigData 49 : 0
UbConfigData 50 : 0
UbConfigData
IPU0log=
IPU1log=
HSM0log=
IMU0log= 51 : 0
UbConfigData 52 : 0
ddr init done, start thermal dimm task
======dimm status======
  chl[0] dimm0 1, dimm1 0
  chl[1] dimm0 0, dimm1 0
  chl[2] dimm0 0, dimm1 0
  chl[3] dimm0 0, dimm1 0
  chl[4] dimm0 0, dimm1 0
  chl[5
IPU0log=
IPU1log=
HSM0log=
IMU0log=] dimm0 0, dimm1 0
  chl[6] dimm0 0, dimm1 0
  chl[7] dimm0 0, dimm1 0
  chl[8] dimm0 0, dimm1 0
  chl[9] dimm0 0, dimm1 0
  chl[10] dimm0 0, dimm1 0
  chl[11] dimm0 0, dimm1 0
==========end==========
sktId[0] chl[0] registered,
IPU0log=
IPU1log=
HSM0log=
IMU0log= dimm mask = 0x1
======dimm status======
  chl[0] dimm0 1, dimm1 0
  chl[1] dimm0 0, dimm1 0
  chl[2] dimm0 0, dimm1 0
  chl[3] dimm0 0, dimm1 0
  chl[4] dimm0 0, dimm1 0
  chl[5] dimm0 0, dimm1 0
  chl[6] dimm0 0, dimm1 0
  chl
IPU0log=
IPU1log=
HSM0log=
IMU0log=[7] dimm0 0, dimm1 0
  chl[8] dimm0 0, dimm1 0
  chl[9] dimm0 0, dimm1 0
  chl[10] dimm0 0, dimm1 0
  chl[11] dimm0 0, dimm1 0
==========end==========
sktId[1] chl[0] registered, dimm mask = 0x1
=====dimm temp params=====
  temp
IPU0log=
IPU1log=
HSM0log=
IMU0log=_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
  is_thermal_thro_en  : 1
  is_aref_rate_auto   : 0
===========end============
UbConfigData 53 : 0
UbConfigData 54 : 0
UbConfigData 55 : 0
UbConfigData 56 : 0
UbConfig
IPU0log=
IPU1log=
HSM0log=
IMU0log=Data 57 : 0
UbConfigData 58 : 0
UbConfigData 59 : 0
UbConfigData 60 : 0
UbConfigData 61 : 0
UbConfigData 62 : 0
UbConfigData 63 : 0
UbConfigData 64 : 0
ClusterSwitch: 0, 0
ClusterMode: 0, 0
ControlMode: 0, 0
EnumMode: 1, 1
BodyM
IPU0log=
IPU1log=
HSM0log=
IMU0log=ask: 31, 31
CcCtxCount: 256, 256
RcCtxCount: 32, 32
UbMemEntrySize: 128, 0
MctpSupport: 1, 1
SecureMode: 0, 0
PrimaryCna: 0, 0
Upi: 0, 0
EntityId: 0, 0
SlotId: 1, 1
SocketId: 2, 2
PortIndex: 0, 0
PortCna: 0, 0
CtrlCna: 11, 11
Im
IPU0log=
IPU1log=
HSM0log=
IMU0log=pBootFlag: 2, 2
ImuBootFlag: 1, 1
SktId: 0 DieId:2, HCCS_LINK:2 PaId:2
SktId: 1 DieId:2, HCCS_LINK:0 PaId:0
CIS register: ID[0xc00007ff], owner[0x1000003], function[0x1045dc5c].
CIS register: ID[0xc0000002], owner[0x1000003], fu
IPU0log=
IPU1log=
HSM0log=
IMU0log=nction[0x1045dcfc].
odf: can not find od file[config]
Do not get NII route table, disable NII Send function.
UbiosTaskStart Entry ...
UbiosTaskStart create task success
IMU ImpBootFlag: 0x2
UbiosCisTask Entry ...
skip IMP sta
IPU0log=
IPU1log=
HSM0log=
IMU0log=rt config...
[0.04.00.447]TF Heartbeat Start
[0.04.02.006]RECEIVE MEM SILK.
0: skt = 0 logic = 5 phy = 6 
1: skt = 0 logic = 6 phy = 9 
2: skt = 0 logic = 3 phy = 10 
3: skt = 0 logic = 9 phy = 11 
4: skt = 1 logic = 1 phy = 0 

IPU0log=
IPU1log=
HSM0log=
IMU0log=5: skt = 1 logic = 7 phy = 1 
6: skt = 1 logic = 4 phy = 2 
7: skt = 1 logic = 10 phy = 3 
8: skt = 1 logic = 2 phy = 4 
9: skt = 1 logic = 8 phy = 5 
10: skt = 1 logic = 11 phy = 7 
11: skt = 1 logic = 0 phy = 8 
12: skt = 1 lo
IPU0log=
IPU1log=
HSM0log=
IMU0log=gic = 6 phy = 9 
13: skt = 1 logic = 3 phy = 10 
14: skt = 1 logic = 9 phy = 11 
15: skt = 0 logic = 4 phy = 2 
16: skt = 0 logic = 10 phy = 3 
17: skt = 0 logic = 2 phy = 4 
18: skt = 0 logic = 8 phy = 5 
19: skt = 0 logic = 11
IPU0log=
IPU1log=
HSM0log=
IMU0log= phy = 7 
20: skt = 1 logic = 5 phy = 6 
21: skt = 0 logic = 7 phy = 1 
22: skt = 0 logic = 1 phy = 0 
23: skt = 0 logic = 0 phy = 8 
get mem silk data length: 72
[IMU][ERR] [
IMP0log= no log data error!]
[0.04.04.979]PCIE INIT 
IPU0log=
IPU1log=
HSM0log=
IMU0log=DONE.
[IMU][ERR] LOS_SemPend(g_pcieSemaphore, LOS_WAIT_FOREVER)
[RegisterInterruptSource]:[21] begin
Interrupt 258 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 262 register OK

HSM0log=
IMU0log=1T1N1U skt:0 CfgBusDfxPreConfig finish

********Hello Huawei LiteOS********

IMU Firmware Version : B173V01
LiteOS Kernel Version : 5.10.0
Run on Socket[0] Die[3]
Chip Version: 1
Max socket num: 2
*******************************
IPU0log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 0
cls: 6, core: 7
cpu 933 sram 1010 ddr 983
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  750|  802|  885|  933|
max  v
IPU1log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 1
cls: 6, core: 7
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  759|  821|  909|  961|
max  v: |  750|  750|  753|  781
HSM0log=[1970-01-01 00:01:12.298][HSM][INFO][30] init start
[1970-01-01 00:01:12.298][HSM][INFO][38] init over
[00:01:12.308][info] succeed to do thirdparty dfx_pabuk init
[00:01:12.313][info] os_mem_system_init default pool done
[0
IMU0log=***
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | rail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_vo
IPU0log=: |  750|  750|  754|  775|  836|  922|  980|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:7
IPU1log=|  846|  938|  994|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:750 F:1950
avs-uncore V:750
HSM0log=0:01:12.320][info] addr is already in region
[00:01:12.323][info] succeed to do thirdparty otpc_pabuk init
[1970-01-01 00:01:12.328][HSM][INFO][31] select_region: 0xc11cb55b
[1970-01-01 00:01:12.334][HSM][INFO][67] spi_nor de
IMU0log=lt:1122 mV | pmu:MP2882
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_v
IPU0log=50 F:1950
avs-uncore V:750 F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
av
IPU1log= F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
avs-uncore V:840 F:2450
avs-
HSM0log=vice_id 0xff1a67c8
[1970-01-01 00:01:12.340][HSM][INFO][50] std_cmd readback 0x30220d8
[1970-01-01 00:01:12.346][HSM][INFO][72] saf_cmd 0x0 readback 0x9f5a0604
[1970-01-01 00:01:12.352][HSM][INFO][72] saf_cmd 0x1 readback 0x5
IMU0log=olt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_
IPU0log=s-uncore V:840 F:2450
avs-uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain
IPU1log=uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | r
HSM0log=b7e938
[1970-01-01 00:01:12.359][HSM][INFO][72] saf_cmd 0x2 readback 0x1
[1970-01-01 00:01:12.365][HSM][INFO][72] saf_cmd 0x3 readback 0x0
[1970-01-01 00:01:12.370][HSM][INFO][72] saf_cmd 0x4 readback 0x0
[00:01:12.377][info
IMU0log=volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus r
IPU0log=[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | p
IPU1log=ail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_volt:1122 mV | pmu:MP2882
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[0] volt =  906 mV
pwr domain
HSM0log=] succeed to do thirdparty boot_profile_driver init
[00:01:12.382][info] succeed to do thirdparty crypto_driver init
[00:01:12.388][info] succeed to do thirdparty period_driver init
[00:01:12.394][info]  start loading interna
IMU0log=eady.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait th
IPU0log=mu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pmbus:0x480c0000 ver:0x110
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
IPU1log=[9] volt = 1105 mV
=end=
w&h rd rail:0, 906
w&h rd rail:1, 1103
pwr domain[0] set volt  904 mV succ
pwr domain[9] set volt 1103 mV succ
volt post
pwr domain[0] volt =  904 mV
pwr domain[9] volt = 1103 mV
==end==
Totem[0] Core Bo
HSM0log=l task ...
[00:01:12.399][info]  task name is ccm_task
[00:01:12.403][info]  hm_dynamic_loadelf successfully!
[00:01:12.407][info] internal task[1] task_name=ccm_task load successfully
[00:01:12.414][info]  task name is upgr
IMU0log=e cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master I
IPU0log=
avsbus resync succ
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[2] volt =  904 mV
pwr domain[7] volt =  804 mV
pwr domain[4] volt =  806 mV
pwr domain[1] volt =  804 mV
=end=
w&h rd rail:
IPU1log=ot Vol [1029]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2,
HSM0log=ade_task
[00:01:12.418][info]  hm_dynamic_loadelf successfully!
[00:01:12.423][info] internal task[2] task_name=upgrade_task load successfully
[00:01:12.430][info] created task ccm_task success!
[00:01:12.435][info] created 
IMU0log=mu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
cpu 0 entering scheduler
|--------------------------------------------------|
AtsPrint
|idx|lockCount| srcAddr| destAddr| addrLen|
|--
IPU0log=0, 904
w&h rd rail:1, 802
pwr domain[2] set volt  902 mV succ
pwr domain[7] set volt  800 mV succ
w&h rd rail:0, 806
w&h rd rail:1, 804
pwr domain[4] set volt  802 mV succ
pwr domain[1] set volt  802 mV succ
volt post
pwr domain
IPU1log= ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd8
HSM0log=task upgrade_task success!
[1970-01-01 00:01:12.440][HSM][INFO][54] Platform init 0x20250523 0x4e.
[1970-01-01 00:01:12.446][HSM][INFO][197] ccm start.
[1970-01-01 00:01:12.451][HSM][INFO][86] upgrade task init success.
[197
IMU0log=------------------------------------------------|
|  0|00000000|0x010500000|0x000110800000|0x00100000|
|  1|00000000|0x020000000|0x00001d000000|0x00800000|
|  2|00000000|0x020800000|0x000490000000|0x00100000|
|  3|00000000|0x020
IPU0log=[2] volt =  902 mV
pwr domain[7] volt =  800 mV
pwr domain[4] volt =  804 mV
pwr domain[1] volt =  802 mV
==end==
Totem[0] Core Boot Vol [1015]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0,
IPU1log=00, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
opposite dieId: 0, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 
HSM0log=0-01-01 00:01:12.457][HSM][INFO][95] upgrade recv cmd, 0x181.
[1970-01-01 00:01:12.462][HSM][INFO][103] upgrade res, 0x3a5aa5a3.
.
IMU0log=900000|0x000004000000|0x08000000|
|  4|00000000|0x028900000|0x000440580000|0x01000000|
|  5|00000000|0x029900000|0x000590000000|0x00100000|
|  6|00000000|0x029a00000|0x002000150000|0x00100000|
|  7|00000000|0x000000000|0x0000000
IPU0log= MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 
IPU1log=enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
hiboost task entry
boost wait SEF.
[INFO] mem used of task 'app_Task' is:0x2028, not zero when task being deleted
boost param OK.
Totem[0] Core[ 0] Freq Limit Low
HSM0log=
IMU0log=00000|0x00000000|
|  8|00000000|0x040000000|0x000000000000|0x08000000|
|  9|00000000|0x048000000|0x000000000000|0x08000000|
| 10|00000000|0x050000000|0x000000000000|0x08000000|
| 11|00000000|0x058000000|0x000000000000|0x08000000
IPU0log=0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
tsensor type
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Fr
HSM0log=
IMU0log=|
| 12|00000000|0x060000000|0x000000000000|0x08000000|
| 13|00000000|0x068000000|0x000000000000|0x08000000|
| 14|00000000|0x070000000|0x000000000000|0x08000000|
| 15|00000000|0x078000000|0x000490000000|0x08000000|
|-------------
IPU0log=: 3, ppuFormatK: 0x4da6, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b4,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 3, mask: fffffff8
tsensor type: 4, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=-------------------------------------|
=~=~=~=~=~=~=~=~=~=~= IMU Log @ 2026.4.17 5:54:54 =~=~=~=~=~=~=~=~=~=~=
[IMU] Watchdog Initialization done!
[RegisterInterruptSource]:[21] begin
Interrupt 32 register OK
Interrupt 34 regi
IPU0log=0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 4, mask: ffffffee
tsensor type: 5, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1

IPU1log= Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=ster OK
Interrupt 40 register OK
Interrupt 44 register OK
sram cnt 0x0, id = 43
Interrupt 43 register OK
Interrupt 36 register OK
Interrupt 57 register OK
sram cnt 0x0, id = 42
Interrupt 42 register OK
Interrupt 37 register OK
[
IPU0log=tsensor: 5, mask: ffffffda
tsensor type: 6, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 6, mask: ffffff80
tsensor type: 7, ppuFormatK: 0x437a,
IPU1log=KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=RegisterInterruptSource]:[39] end
IPMB initialization Start...
IPMB clock set done, prer = 0x18.
IPMB Rx FIFO clear empty.
IPMB initialization Done.
starting DFX Collect Task end
PowerTask Entry ...
Wait all vrd init done 
IPU0log= ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 7, mask: fffffffe
opposite dieId: 1, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
CPM max V[900]-
IPU1log= Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low
HSM0log=
IMU0log=...
All vrd init done, power task start
refresh domainId 0 Lsb 0x0
refresh domainId 9 Lsb 0x1
refresh domainId 2 Lsb 0x0
refresh domainId 7 Lsb 0x1
refresh domainId 4 Lsb 0x0
refresh domainId 1 Lsb 0x1
power sensor[0] | calib:51
IPU0log=F:2800
CPM min V[750]-F:1600
freq:2350, idx:9
cpm trim freq: 2600, idx: 4
cpm trim finish
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
recount hours 
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Fr
HSM0log=
IMU0log=20 | rshunt:1 | rshuntDiv:1000 | currLsb:1 | currLsbDiv:1000 | enableFlag:1
                | pwrLsb:25 | defPwr:25000 | minPwr:10000 | maxPwr:65000 | pwrFix:3400
                | manufacturerId: 0x5549 | dieId: 0x2260
power se
IPU0log=0x744 
hiboost task entry
boost wait SEF.
boost param OK.
Totem[0] Core[ 0] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[26
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=nsor[0] init success
ScmiTaskEntry start.
[RegisterInterruptSource]:[21] begin
Interrupt 51 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 52 register OK
[RegisterInterruptSource
IPU0log=00000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[12000
IPU1log= Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 53 register OK
[RegisterInterruptSource]:[39] end
[0.01.29.017]starting ras Init
RAS Setup Value get done!
INT_NUM_PER_SKT * HiGetSktNum() = 0x8
index = 0x0
RasIntRegi
IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Lim
IPU1log=KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=ster init 160 
index = 0x1
RasIntRegister init 172 
index = 0x2
RasIntRegister init 162 
index = 0x3
RasIntRegister init 174 
index = 0x4
RasIntRegister init 184 
index = 0x5
RasIntRegister init 196 
index = 0x6
RasIntRegister i
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IPU1log= Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low
HSM0log=
IMU0log=nit 186 
index = 0x7
RasIntRegister init 198 
RasIntRegister init 161 
RasIntRegister init 173 
RasIntRegister init 185 
RasIntRegister init 197 
RasIntRegister init 284 
RasIntRegister init 314 
MceTableHeadInit start
starting 
IPU0log=14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
To
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
uncore max freq : 23
HSM0log=
IMU0log=Ce_Storm Contrl and Ras_Data_Update Task end
[0.01.29.099]starting ras end
[IMU][ERR] skt id 0
Ub init task start Entry ...
UbInitTask Entry ...
[RegisterInterruptSource]:[21] begin
Interrupt 167 register OK
[RegisterInterrup
IPU0log=tem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[26
IPU1log=50 MHz

HSM0log=
IMU0log=tSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 191 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 171 register OK
[RegisterInterruptSource]:[39] end
[Register
IPU0log=00000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[12000
IPU1log=
HSM0log=
IMU0log=InterruptSource]:[21] begin
Interrupt 183 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 195 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Lim
IPU1log=
HSM0log=
IMU0log=
Interrupt 207 register OK
[RegisterInterruptSource]:[39] end
Init heart-beat-task end
CS0 flash do not support sfdp!
Current flash device ID[0x61a67c8]!
System supported 1 Flash.
flash cs 0 Manufacture 0xc8, DeviceId 0x1a67, A
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IPU1log=
HSM0log=
IMU0log=ddrMode[0-3B,1-4B] 0x1:
    size 0x4000000, pagesize 0x100
    read  cmd 0x13, dummy byte 0x8
    write cmd 0x12, dummy byte 0x0
    erase4k cmd 0x21, erase64k byte 0xdc
sfc init end
firstUnMskExt0Int
ThermalDimmStart Entry ...
IPU0log=33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
To
IPU1log=
HSM0log=
IMU0log=
wait ddr init done...
HacLowPowerStart Entry ...
Hello LiteOS...
pwr cap[0]: 0, 67
Init ReportPcieMmioToBmcTaskEntry end
starting Fpc Isolation Task end
pwr cap[1]: f, 27
pwr cap[2]: 1, 3
BMC_COLLECTION: bmc req last log!

IPU0log=tem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[26
IPU1log=
HSM0log=
IMU0log=DDR initing...
BMC_COLLECTION: bmc req last log!
DDR initing...
BMC_COLLECTION: bmc req last log!
DDR initing...
[0.02.00.306]DDR init done
[LOG]head = 0x0, tail = 0x1898, logSize = 0x1898
[IMU][ERR] HsmLogInit!
[IMU][ERR] HsmLo
IPU0log=00000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
uncore max freq : 2350 MHz

IPU1log=
HSM0log=
IMU0log=gInit! TRUE
set apei done!
UbConfigData size is 64
UbConfigData 0 : 0
UbConfigData 1 : 0
UbConfigData 2 : 0
UbConfigData 3 : 1
UbConfigData 4 : 31
UbConfigData 5 : 1
UbConfigData 6 : 0
UbConfigData 7 : 32
UbConfigData 8 : 0
UbCo
IPU0log=
IPU1log=
HSM0log=
IMU0log=nfigData 9 : 1
UbConfigData 10 : 2
UbConfigData 11 : 0
UbConfigData 12 : 0
UbConfigData 13 : 1
UbConfigData 14 : 0
UbConfigData 15 : 0
UbConfigData 16 : 0
UbConfigData 17 : 0
UbConfigData 18 : 0
UbConfigData 19 : 0
UbConfigData 
IPU0log=
IPU1log=
HSM0log=
IMU0log=20 : 0
UbConfigData 21 : 0
UbConfigData 22 : 11
UbConfigData 23 : 0
UbConfigData 24 : 0
UbConfigData 25 : 0
UbConfigData 26 : 0
UbConfigData 27 : 0
UbConfigData 28 : 0
UbConfigData 29 : 0
UbConfigData 30 : 0
UbConfigData 31 : 0

IPU0log=
IPU1log=
HSM0log=
IMU0log=UbConfigData 32 : 0
UbConfigData 33 : 0
UbConfigData 34 : 2
UbConfigData 35 : 1
UbConfigData 36 : 0
UbConfigData 37 : 0
UbConfigData 38 : 0
UbConfigData 39 : 0
UbConfigData 40 : 0
UbConfigData 41 : 0
UbConfigData 42 : 0
UbConfig
IPU0log=
IPU1log=
HSM0log=
IMU0log=Data 43 : 0
UbConfigData 44 : 0
UbConfigData 45 : 0
UbConfigData 46 : 0
UbConfigData 47 : 0
UbConfigData 48 : 0
UbConfigData 49 : 0
UbConfigData 50 : 0
UbConfigData 51 : 0
UbConfigData 52 : 0
UbConfigData 53 : 0
UbConfigData 54 
IPU0log=
IPU1log=
HSM0log=
IMU0log=: 0
UbConfigData 55 : 0
UbConfigData 56 : 0
UbConfigData 57 : 0
UbConfigData 58 : 0
UbConfigData 59 : 0
UbConfigData 60 : 0
UbConfigData 61 : 0
UbConfigData 62 : 0
UbConfigData 63 : 0
UbConfigData 64 : 0
ClusterSwitch: 0, 0
Clus
IPU0log=
IPU1log=
HSM0log=
IMU0log=terMode: 0, 0
ControlMode: 0, 0
EnumMode: 1, 1
BodyMask: 31, 31
CcCtxCount: 256, 256
RcCtxCount: 32, 32
UbMemEntrySize: 128, 0
MctpSupport: 1, 1
SecureMode: 0, 0
PrimaryCna: 0, 0
Upi: 0, 0
EntityId: 0, 0
SlotId: 1, 1
SocketId: 2
IPU0log=
IPU1log=
HSM0log=
IMU0log=, 2
PortIndex: 0, 0
PortCna: 0, 0
CtrlCna: 11, 11
ImpBootFlag: 2, 2
ImuBootFlag: 1, 1
SktId: 0 DieId:2, HCCS_LINK:2 PaId:2
SktId: 1 DieId:2, HCCS_LINK:0 PaId:0
CIS register: ID[0xc00007ff], owner[0x1000003], function[0x1045dc5c]
IPU0log=
IPU1log=
HSM0log=
IMU0log=.
CIS register: ID[0xc0000002], owner[0x1000003], function[0x1045dcfc].
odf: can not find od file[config]
Do not get NII route table, disable NII Send function.
UbiosTaskStart Entry ...
UbiosTaskStart create task success
IMU I
IPU0log=
IPU1log=
HSM0log=
IMU0log=mpBootFlag: 0x2
skip IMP start config...
UbiosCisTask Entry ...
ddr init done, start thermal dimm task
======dimm status======
  chl[0] dimm0 1, dimm1 0
  chl[1] dimm0 0, dimm1 0
  chl[2] dimm0 0, dimm1 0
  chl[3] dimm0 0, dimm
IPU0log=
IPU1log=
HSM0log=
IMU0log=1 0
  chl[4] dimm0 0, dimm1 0
  chl[5] dimm0 0, dimm1 0
  chl[6] dimm0 0, dimm1 0
  chl[7] dimm0 0, dimm1 0
  chl[8] dimm0 0, dimm1 0
  chl[9] dimm0 0, dimm1 0
  chl[10] dimm0 0, dimm1 0
  chl[11] dimm0 0, dimm1 0
==========end=
IPU0log=
IPU1log=
HSM0log=
IMU0log==========
sktId[0] chl[0] registered, dimm mask = 0x1
======dimm status======
  chl[0] dimm0 1, dimm1 0
  chl[1] dimm0 0, dimm1 0
  chl[2] dimm0 0, dimm1 0
  chl[3] dimm0 0, dimm1 0
  chl[4] dimm0 0, dimm1 0
  chl[5] dimm0 0, di
IPU0log=
IPU1log=
HSM0log=
IMU0log=mm1 0
  chl[6] dimm0 0, dimm1 0
  chl[7] dimm0 0, dimm1 0
  chl[8] dimm0 0, dimm1 0
  chl[9] dimm0 0, dimm1 0
  chl[10] dimm0 0, dimm1 0
  chl[11] dimm0 0, dimm1 0
==========end==========
sktId[1] chl[0] registered, dimm mask = 
IPU0log=
IPU1log=
HSM0log=
IMU0log=0x1
=====dimm temp params=====
  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
  is_thermal_thro_en  : 1
  is_aref_rate_auto   : 0
===========end============
[0.02.07.329]TF Heartbeat Start
[0.02.08.549]RECEIV
IPU0log=
IPU1log=
HSM0log=
IMU0log=E MEM SILK.
0: skt = 0 logic = 9 phy = 11 
1: skt = 1 logic = 1 phy = 0 
2: skt = 0 logic = 7 phy = 1 
3: skt = 1 logic = 4 phy = 2 
4: skt = 1 logic = 7 phy = 1 
5: skt = 0 logic = 3 phy = 10 
6: skt = 0 logic = 10 phy = 3 
7: 
IPU0log=
IPU1log=
HSM0log=
IMU0log=skt = 0 logic = 8 phy = 5 
8: skt = 0 logic = 2 phy = 4 
9: skt = 1 logic = 10 phy = 3 
10: skt = 1 logic = 2 phy = 4 
11: skt = 1 logic = 8 phy = 5 
12: skt = 1 logic = 5 phy = 6 
13: skt = 1 logic = 11 phy = 7 
14: skt = 1 log
IPU0log=
IPU1log=
HSM0log=
IMU0log=ic = 0 phy = 8 
15: skt = 1 logic = 6 phy = 9 
16: skt = 0 logic = 11 phy = 7 
17: skt = 0 logic = 4 phy = 2 
18: skt = 0 logic = 5 phy = 6 
19: skt = 1 logic = 3 phy = 10 
20: skt = 1 logic = 9 phy = 11 
21: skt = 0 logic = 1 p
IPU0log=
IPU1log=
HSM0log=
IMU0log=hy = 0 
22: skt = 0 logic = 0 phy = 8 
23: skt = 0 logic = 6 phy = 9 
get mem silk data length: 72
[0.02.11.515]PCIE INIT DONE.
[IMU][ERR] LOS_SemPend(g_pcieSemaphore, LOS_WAIT_FOREVER)
[RegisterInterruptSource]:[21] begin
Inte
IPU0log=
IPU1log=
HSM0log=
IMU0log=rrupt 258 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 262 register OK
BMC_COLLECTION: bmc req last log!
[IMU][ERR] [
HSM0log= no log data error!]
[RegisterInterruptSource]:[39]
IPU0log=
IPU1log=
HSM0log=
IMU0log= end
[RegisterInterruptSource]:[21] begin
Interrupt 266 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 270 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSour
IPU0log=
IPU1log=
HSM0log=
IMU0log=ce]:[21] begin
Interrupt 277 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 288 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 29
IPU0log=
IPU1log=
HSM0log=
IMU0log=2 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 296 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 300 register OK
[RegisterInter
IPU0log=
IPU1log=
HSM0log=
IMU0log=ruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 307 register OK
[RegisterInterruptSource]:[39] end
pmt Init done

-----------------ROUTE TABLE------------------
entryCount = 1
----------------------------
IPU0log=
IPU1log=
HSM0log=
IMU0log=------------------
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2100
----------------------------------------------
-------------
IPU0log=
IPU1log=
HSM0log=
IMU0log=----ROUTE TABLE------------------
entryCount = 2
----------------------------------------------
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 
IPU0log=
IPU1log=
HSM0log=
IMU0log=2, bdf = 0x2100
[No.1]:
eidRange = 1, startEid = 10, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2500
----------------------------------------------
---------------
IPU0log=
IPU1log=
HSM0log=
IMU0log=--ROUTE TABLE------------------
entryCount = 2
----------------------------------------------
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2,
IPU0log=
IPU1log=
HSM0log=
IMU0log= bdf = 0x2100
[No.1]:
eidRange = 1, startEid = 10, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2500
----------------------------------------------

IPU0log=
IPU1log=
HSM0log=
IMU0log=1T1N1U skt:0 CfgBusDfxPreConfig finish

********Hello Huawei LiteOS********

IMU Firmware Version : B173V01
LiteOS Kernel Version : 5.10.0
Run on Socket[0] Die[3]
Chip Version: 1
Max socket num: 2
*******************************
IPU0log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 0
cls: 6, core: 7
cpu 933 sram 1010 ddr 983
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  750|  802|  885|  933|
max  v
IPU1log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 1
cls: 6, core: 7
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  759|  821|  909|  961|
max  v: |  750|  750|  753|  781
HSM0log=[1970-01-01 00:01:12.187][HSM][INFO][30] init start
[1970-01-01 00:01:12.187][HSM][INFO][38] init over
[00:01:12.197][info] succeed to do thirdparty dfx_pabuk init
[00:01:12.203][info] os_mem_system_init default pool done
[0
IMU0log=***
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | rail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_vo
IPU0log=: |  750|  750|  754|  775|  836|  922|  980|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:7
IPU1log=|  846|  938|  994|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:750 F:1950
avs-uncore V:750
HSM0log=0:01:12.209][info] addr is already in region
[00:01:12.212][info] succeed to do thirdparty otpc_pabuk init
[1970-01-01 00:01:12.217][HSM][INFO][31] select_region: 0xc11cb55b
[1970-01-01 00:01:12.223][HSM][INFO][67] spi_nor de
IMU0log=lt:1122 mV | pmu:MP2882
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_v
IPU0log=50 F:1950
avs-uncore V:750 F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
av
IPU1log= F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
avs-uncore V:840 F:2450
avs-
HSM0log=vice_id 0xff1a67c8
[1970-01-01 00:01:12.229][HSM][INFO][50] std_cmd readback 0x30220d8
[1970-01-01 00:01:12.235][HSM][INFO][72] saf_cmd 0x0 readback 0x9f5a0604
[1970-01-01 00:01:12.242][HSM][INFO][72] saf_cmd 0x1 readback 0x5
IMU0log=olt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_
IPU0log=s-uncore V:840 F:2450
avs-uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain
IPU1log=uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | r
HSM0log=b7e938
[1970-01-01 00:01:12.248][HSM][INFO][72] saf_cmd 0x2 readback 0x1
[1970-01-01 00:01:12.254][HSM][INFO][72] saf_cmd 0x3 readback 0x0
[1970-01-01 00:01:12.260][HSM][INFO][72] saf_cmd 0x4 readback 0x0
[00:01:12.266][info
IMU0log=volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus r
IPU0log=[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | p
IPU1log=ail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_volt:1122 mV | pmu:MP2882
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[0] volt =  906 mV
pwr domain
HSM0log=] succeed to do thirdparty boot_profile_driver init
[00:01:12.272][info] succeed to do thirdparty crypto_driver init
[00:01:12.277][info] succeed to do thirdparty period_driver init
[00:01:12.283][info]  start loading interna
IMU0log=eady.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait th
IPU0log=mu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pmbus:0x480c0000 ver:0x110
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
IPU1log=[9] volt = 1103 mV
=end=
w&h rd rail:0, 904
w&h rd rail:1, 1101
pwr domain[0] set volt  904 mV succ
pwr domain[9] set volt 1103 mV succ
volt post
pwr domain[0] volt =  904 mV
pwr domain[9] volt = 1101 mV
==end==
Totem[0] Core Bo
HSM0log=l task ...
[00:01:12.288][info]  task name is ccm_task
[00:01:12.292][info]  hm_dynamic_loadelf successfully!
[00:01:12.297][info] internal task[1] task_name=ccm_task load successfully
[00:01:12.303][info]  task name is upgr
IMU0log=e cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master I
IPU0log=
avsbus resync succ
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[2] volt =  904 mV
pwr domain[7] volt =  802 mV
pwr domain[4] volt =  804 mV
pwr domain[1] volt =  804 mV
=end=
w&h rd rail:
IPU1log=ot Vol [1029]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2,
HSM0log=ade_task
[00:01:12.308][info]  hm_dynamic_loadelf successfully!
[00:01:12.312][info] internal task[2] task_name=upgrade_task load successfully
[00:01:12.319][info] created task ccm_task success!
[00:01:12.324][info] created 
IMU0log=mu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
cpu 0 entering scheduler
|--------------------------------------------------|
AtsPrint
|idx|lockCount| srcAddr| destAddr| addrLen|
|--
IPU0log=0, 904
w&h rd rail:1, 802
pwr domain[2] set volt  902 mV succ
pwr domain[7] set volt  802 mV succ
w&h rd rail:0, 806
w&h rd rail:1, 804
pwr domain[4] set volt  802 mV succ
pwr domain[1] set volt  804 mV succ
volt post
pwr domain
IPU1log= ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd8
HSM0log=task upgrade_task success!
[1970-01-01 00:01:12.329][HSM][INFO][54] Platform init 0x20250523 0x4e.
[1970-01-01 00:01:12.335][HSM][INFO][197] ccm start.
[1970-01-01 00:01:12.340][HSM][INFO][86] upgrade task init success.
[197
IMU0log=------------------------------------------------|
|  0|00000000|0x010500000|0x000110800000|0x00100000|
|  1|00000000|0x020000000|0x00001d000000|0x00800000|
|  2|00000000|0x020800000|0x000490000000|0x00100000|
|  3|00000000|0x020
IPU0log=[2] volt =  902 mV
pwr domain[7] volt =  800 mV
pwr domain[4] volt =  804 mV
pwr domain[1] volt =  802 mV
==end==
Totem[0] Core Boot Vol [1015]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0,
IPU1log=00, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
opposite dieId: 0, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 
HSM0log=0-01-01 00:01:12.346][HSM][INFO][95] upgrade recv cmd, 0x181.
[1970-01-01 00:01:12.352][HSM][INFO][103] upgrade res, 0x3a5aa5a3.
.
IMU0log=900000|0x000004000000|0x08000000|
|  4|00000000|0x028900000|0x000440580000|0x01000000|
|  5|00000000|0x029900000|0x000590000000|0x00100000|
|  6|00000000|0x029a00000|0x002000150000|0x00100000|
|  7|00000000|0x000000000|0x0000000
IPU0log= MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 
IPU1log=enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
hiboost task entry
boost wait SEF.
[INFO] mem used of task 'app_Task' is:0x2028, not zero when task being deleted
boost param OK.
Totem[0] Core[ 0] Freq Limit Low
HSM0log=
IMU0log=00000|0x00000000|
|  8|00000000|0x040000000|0x000000000000|0x08000000|
|  9|00000000|0x048000000|0x000000000000|0x08000000|
| 10|00000000|0x050000000|0x000000000000|0x08000000|
| 11|00000000|0x058000000|0x000000000000|0x08000000
IPU0log=0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
tsensor type
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Fr
HSM0log=
IMU0log=|
| 12|00000000|0x060000000|0x000000000000|0x08000000|
| 13|00000000|0x068000000|0x000000000000|0x08000000|
| 14|00000000|0x070000000|0x000000000000|0x08000000|
| 15|00000000|0x078000000|0x000490000000|0x08000000|
|-------------
IPU0log=: 3, ppuFormatK: 0x4da6, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b4,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 3, mask: fffffff8
tsensor type: 4, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=-------------------------------------|
=~=~=~=~=~=~=~=~=~=~= IMU Log @ 2026.4.18 2:53:43 =~=~=~=~=~=~=~=~=~=~=
[IMU] Watchdog Initialization done!
[RegisterInterruptSource]:[21] begin
Interrupt 32 register OK
Interrupt 34 regi
IPU0log=0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 4, mask: ffffffee
tsensor type: 5, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1

IPU1log= Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=ster OK
Interrupt 40 register OK
Interrupt 44 register OK
sram cnt 0x0, id = 43
Interrupt 43 register OK
Interrupt 36 register OK
Interrupt 57 register OK
sram cnt 0x0, id = 42
Interrupt 42 register OK
Interrupt 37 register OK
[
IPU0log=tsensor: 5, mask: ffffffda
tsensor type: 6, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 6, mask: ffffff80
tsensor type: 7, ppuFormatK: 0x437a,
IPU1log=KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=RegisterInterruptSource]:[39] end
IPMB initialization Start...
IPMB clock set done, prer = 0x18.
IPMB Rx FIFO clear empty.
IPMB initialization Done.
starting DFX Collect Task end
PowerTask Entry ...
Wait all vrd init done 
IPU0log= ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 7, mask: fffffffe
opposite dieId: 1, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
CPM max V[900]-
IPU1log= Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low
HSM0log=
IMU0log=...
All vrd init done, power task start
refresh domainId 0 Lsb 0x0
refresh domainId 9 Lsb 0x1
refresh domainId 2 Lsb 0x0
refresh domainId 7 Lsb 0x1
refresh domainId 4 Lsb 0x0
refresh domainId 1 Lsb 0x1
power sensor[0] | calib:51
IPU0log=F:2800
CPM min V[750]-F:1600
freq:2350, idx:9
cpm trim freq: 2600, idx: 4
cpm trim finish
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
recount hours 
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Fr
HSM0log=
IMU0log=20 | rshunt:1 | rshuntDiv:1000 | currLsb:1 | currLsbDiv:1000 | enableFlag:1
                | pwrLsb:25 | defPwr:25000 | minPwr:10000 | maxPwr:65000 | pwrFix:3400
                | manufacturerId: 0x5549 | dieId: 0x2260
power se
IPU0log=0x750 
hiboost task entry
boost wait SEF.
boost param OK.
Totem[0] Core[ 0] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[26
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=nsor[0] init success
ScmiTaskEntry start.
[RegisterInterruptSource]:[21] begin
Interrupt 51 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 52 register OK
[RegisterInterruptSource
IPU0log=00000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[12000
IPU1log= Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 53 register OK
[RegisterInterruptSource]:[39] end
[0.01.28.919]starting ras Init
RAS Setup Value get done!
INT_NUM_PER_SKT * HiGetSktNum() = 0x8
index = 0x0
RasIntRegi
IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Lim
IPU1log=KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=ster init 160 
index = 0x1
RasIntRegister init 172 
index = 0x2
RasIntRegister init 162 
index = 0x3
RasIntRegister init 174 
index = 0x4
RasIntRegister init 184 
index = 0x5
RasIntRegister init 196 
index = 0x6
RasIntRegister i
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IPU1log= Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low
HSM0log=
IMU0log=nit 186 
index = 0x7
RasIntRegister init 198 
RasIntRegister init 161 
RasIntRegister init 173 
RasIntRegister init 185 
RasIntRegister init 197 
RasIntRegister init 284 
RasIntRegister init 314 
MceTableHeadInit start
starting 
IPU0log=14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
To
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
uncore max freq : 23
HSM0log=
IMU0log=Ce_Storm Contrl and Ras_Data_Update Task end
[0.01.29.000]starting ras end
[IMU][ERR] skt id 0
Ub init task start Entry ...
UbInitTask Entry ...
[RegisterInterruptSource]:[21] begin
Interrupt 167 register OK
[RegisterInterrup
IPU0log=tem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[26
IPU1log=50 MHz

HSM0log=
IMU0log=tSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 191 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 171 register OK
[RegisterInterruptSource]:[39] end
[Register
IPU0log=00000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[12000
IPU1log=
HSM0log=
IMU0log=InterruptSource]:[21] begin
Interrupt 183 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 195 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Lim
IPU1log=
HSM0log=
IMU0log=
Interrupt 207 register OK
[RegisterInterruptSource]:[39] end
Init heart-beat-task end
CS0 flash do not support sfdp!
Current flash device ID[0x61a67c8]!
System supported 1 Flash.
flash cs 0 Manufacture 0xc8, DeviceId 0x1a67, A
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IPU1log=
HSM0log=
IMU0log=ddrMode[0-3B,1-4B] 0x1:
    size 0x4000000, pagesize 0x100
    read  cmd 0x13, dummy byte 0x8
    write cmd 0x12, dummy byte 0x0
    erase4k cmd 0x21, erase64k byte 0xdc
sfc init end
firstUnMskExt0Int
ThermalDimmStart Entry ...
IPU0log=33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
To
IPU1log=
HSM0log=
IMU0log=
wait ddr init done...
HacLowPowerStart Entry ...
Hello LiteOS...
pwr cap[0]: 0, 67
Init ReportPcieMmioToBmcTaskEntry end
starting Fpc Isolation Task end
pwr cap[1]: f, 27
BMC_COLLECTION: bmc req last log!
[IMU][ERR] [
IPU3l
IPU0log=tem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[26
IPU1log=
HSM0log=
IMU0log=og= no log data error!]
pwr cap[2]: 1, 3
[IMU][ERR] IMP log not ready, DDR initing...
[IMU][ERR] IMP log not ready, DDR initing...
[0.03.53.079]DDR init done
[LOG]head = 0x0, tail = 0x18ab, logSize = 0x18ab
[IMU][ERR] HsmLogIni
IPU0log=00000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
uncore max freq : 2350 MHz

IPU1log=
HSM0log=
IMU0log=t!
[IMU][ERR] HsmLogInit! TRUE
ddr init done, start thermal dimm task
======dimm status======
  chl[0] dimm0 1, dimm1 0
  chl[1] dimm0 0, dimm1 0
  chl[2] dimm0 0, dimm1 0
  chl[3] dimm0 0, dimm1 0
  chl[4] dimm0 0, dimm1 0
  ch
IPU0log=
IPU1log=
HSM0log=
IMU0log=l[5] dimm0 0, dimm1 0
  chl[6] dimm0 0, dimm1 0
  chl[7] dimm0 0, dimm1 0
  chl[8] dimm0 0, dimm1 0
  chl[9] dimm0 0, dimm1 0
  chl[10] dimm0 0, dimm1 0
  chl[11] dimm0 0, dimm1 0
==========end==========
sktId[0] chl[0] register
IPU0log=
IPU1log=
HSM0log=
IMU0log=ed, dimm mask = 0x1
======dimm status======
  chl[0] dimm0 1, dimm1 0
  chl[1] dimm0 0, dimm1 0
  chl[2] dimm0 0, dimm1 0
  chl[3] dimm0 0, dimm1 0
  chl[4] dimm0 0, dimm1 0
  chl[5] dimm0 0, dimm1 0
  chl[6] dimm0 0, dimm1 0
  
IPU0log=
IPU1log=
HSM0log=
IMU0log=chl[7] dimm0 0, dimm1 0
  chl[8] dimm0 0, dimm1 0
  chl[9] dimm0 0, dimm1 0
  chl[10] dimm0 0, dimm1 0
  chl[11] dimm0 0, dimm1 0
==========end==========
sktId[1] chl[0] registered, dimm mask = 0x1
=====dimm temp params=====
  t
IPU0log=
IPU1log=
HSM0log=
IMU0log=emp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
  is_thermal_thro_en  : 1
  is_aref_rate_auto   : 0
===========end============
set apei done!
UbConfigData size is 64
UbConfigData 0 : 0
UbConfigData 1 : 0
UbConfig
IPU0log=
IPU1log=
HSM0log=
IMU0log=Data 2 : 0
UbConfigData 3 : 1
UbConfigData 4 : 31
UbConfigData 5 : 1
UbConfigData 6 : 0
UbConfigData 7 : 32
UbConfigData 8 : 0
UbConfigData 9 : 1
UbConfigData 10 : 2
UbConfigData 11 : 0
UbConfigData 12 : 0
UbConfigData 13 : 1
Ub
IPU0log=
IPU1log=
HSM0log=
IMU0log=ConfigData 14 : 0
UbConfigData 15 : 0
UbConfigData 16 : 0
UbConfigData 17 : 0
UbConfigData 18 : 0
UbConfigData 19 : 0
UbConfigData 20 : 0
UbConfigData 21 : 0
UbConfigData 22 : 11
UbConfigData 23 : 0
UbConfigData 24 : 0
UbConfigD
IPU0log=
IPU1log=
HSM0log=
IMU0log=ata 25 : 0
UbConfigData 26 : 0
UbConfigData 27 : 0
UbConfigData 28 : 0
UbConfigData 29 : 0
UbConfigData 30 : 0
UbConfigData 31 : 0
UbConfigData 32 : 0
UbConfigData 33 : 0
UbConfigData 34 : 2
UbConfigData 35 : 1
UbConfigData 36 :
IPU0log=
IPU1log=
HSM0log=
IMU0log= 0
UbConfigData 37 : 0
UbConfigData 38 : 0
UbConfigData 39 : 0
UbConfigData 40 : 0
UbConfigData 41 : 0
UbConfigData 42 : 0
UbConfigData 43 : 0
UbConfigData 44 : 0
UbConfigData 45 : 0
UbConfigData 46 : 0
UbConfigData 47 : 0
UbCon
IPU0log=
IPU1log=
HSM0log=
IMU0log=figData 48 : 0
UbConfigData 49 : 0
UbConfigData 50 : 0
UbConfigData 51 : 0
UbConfigData 52 : 0
UbConfigData 53 : 0
UbConfigData 54 : 0
UbConfigData 55 : 0
UbConfigData 56 : 0
UbConfigData 57 : 0
UbConfigData 58 : 0
UbConfigData 
IPU0log=
IPU1log=
HSM0log=
IMU0log=59 : 0
UbConfigData 60 : 0
UbConfigData 61 : 0
UbConfigData 62 : 0
UbConfigData 63 : 0
UbConfigData 64 : 0
ClusterSwitch: 0, 0
ClusterMode: 0, 0
ControlMode: 0, 0
EnumMode: 1, 1
BodyMask: 31, 31
CcCtxCount: 256, 256
RcCtxCount: 
IPU0log=
IPU1log=
HSM0log=
IMU0log=32, 32
UbMemEntrySize: 128, 0
MctpSupport: 1, 1
SecureMode: 0, 0
PrimaryCna: 0, 0
Upi: 0, 0
EntityId: 0, 0
SlotId: 1, 1
SocketId: 2, 2
PortIndex: 0, 0
PortCna: 0, 0
CtrlCna: 11, 11
ImpBootFlag: 2, 2
ImuBootFlag: 1, 1
SktId: 0 Di
IPU0log=
IPU1log=
HSM0log=
IMU0log=eId:2, HCCS_LINK:2 PaId:2
SktId: 1 DieId:2, HCCS_LINK:0 PaId:0
CIS register: ID[0xc00007ff], owner[0x1000003], function[0x1045dc5c].
CIS register: ID[0xc0000002], owner[0x1000003], function[0x1045dcfc].
odf: can not find od file
IPU0log=
IPU1log=
HSM0log=
IMU0log=[config]
Do not get NII route table, disable NII Send function.
UbiosTaskStart Entry ...
UbiosTaskStart create task success
UbiosCisTask Entry ...
IMU ImpBootFlag: 0x2
skip IMP start config...
[IMU][ERR] [
IMP0log= no log dat
IPU0log=
IPU1log=
HSM0log=
IMU0log=a error!]
[0.04.00.189]TF Heartbeat Start
[0.04.01.433]RECEIVE MEM SILK.
0: skt = 1 logic = 9 phy = 11 
1: skt = 1 logic = 3 phy = 10 
2: skt = 1 logic = 6 phy = 9 
3: skt = 0 logic = 8 phy = 5 
4: skt = 0 logic = 1 phy = 0 
5: 
IPU0log=
IPU1log=
HSM0log=
IMU0log=skt = 1 logic = 4 phy = 2 
6: skt = 1 logic = 10 phy = 3 
7: skt = 1 logic = 2 phy = 4 
8: skt = 1 logic = 8 phy = 5 
9: skt = 1 logic = 5 phy = 6 
10: skt = 1 logic = 11 phy = 7 
11: skt = 0 logic = 7 phy = 1 
12: skt = 1 logic
IPU0log=
IPU1log=
HSM0log=
IMU0log= = 0 phy = 8 
13: skt = 0 logic = 4 phy = 2 
14: skt = 0 logic = 10 phy = 3 
15: skt = 0 logic = 2 phy = 4 
16: skt = 0 logic = 5 phy = 6 
17: skt = 0 logic = 11 phy = 7 
18: skt = 0 logic = 0 phy = 8 
19: skt = 0 logic = 6 phy 
IPU0log=
IPU1log=
HSM0log=
IMU0log== 9 
20: skt = 0 logic = 3 phy = 10 
21: skt = 0 logic = 9 phy = 11 
22: skt = 1 logic = 1 phy = 0 
23: skt = 1 logic = 7 phy = 1 
get mem silk data length: 72
[0.04.04.399]PCIE INIT DONE.
[IMU][ERR] LOS_SemPend(g_pcieSemaphore,
IPU0log=
IPU1log=
HSM0log=
IMU0log= LOS_WAIT_FOREVER)
[RegisterInterruptSource]:[21] begin
Interrupt 258 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 262 register OK
[RegisterInterruptSource]:[39] end
[Register
IPU0log=
IPU1log=
HSM0log=
IMU0log=InterruptSource]:[21] begin
Interrupt 266 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 270 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
IPU0log=
IPU1log=
HSM0log=
IMU0log=
Interrupt 277 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 288 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 292 register OK
[
IPU0log=
IPU1log=
HSM0log=
IMU0log=RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 296 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 300 register OK
[RegisterInterruptSource]:[39
IPU0log=
IPU1log=
HSM0log=
IMU0log=] end
[RegisterInterruptSource]:[21] begin
Interrupt 307 register OK
[RegisterInterruptSource]:[39] end
pmt Init done

-----------------ROUTE TABLE------------------
entryCount = 1
-------------------------------------------
IPU0log=
IPU1log=
HSM0log=
IMU0log=---
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2100
----------------------------------------------
-----------------ROUTE TABLE
IPU0log=
IPU1log=
HSM0log=
IMU0log=------------------
entryCount = 2
----------------------------------------------
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2100
IPU0log=
IPU1log=
HSM0log=
IMU0log=
[No.1]:
eidRange = 1, startEid = 10, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2500
----------------------------------------------
-----------------ROUTE TABLE--
IPU0log=
IPU1log=
HSM0log=
IMU0log=----------------
entryCount = 2
----------------------------------------------
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2100

IPU0log=
IPU1log=
HSM0log=
IMU0log=[No.1]:
eidRange = 1, startEid = 10, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2500
----------------------------------------------

IPU0log=
IPU1log=
HSM0log=
IMU0log=1T1N1U skt:0 CfgBusDfxPreConfig finish

********Hello Huawei LiteOS********

IMU Firmware Version : B173V01
LiteOS Kernel Version : 5.10.0
Run on Socket[0] Die[3]
Chip Version: 1
Max socket num: 2
*******************************
IPU0log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 0
cls: 6, core: 7
cpu 933 sram 1010 ddr 983
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  750|  802|  885|  933|
max  v
IPU1log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 1
cls: 6, core: 7
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  759|  821|  909|  961|
max  v: |  750|  750|  753|  781
HSM0log=[1970-01-01 00:01:13.287][HSM][INFO][30] init start
[1970-01-01 00:01:13.287][HSM][INFO][38] init over
[00:01:13.297][info] succeed to do thirdparty dfx_pabuk init
[00:01:13.303][info] os_mem_system_init default pool done
[0
IMU0log=***
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | rail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_vo
IPU0log=: |  750|  750|  754|  775|  836|  922|  980|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:7
IPU1log=|  846|  938|  994|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:750 F:1950
avs-uncore V:750
HSM0log=0:01:13.309][info] addr is already in region
[00:01:13.312][info] succeed to do thirdparty otpc_pabuk init
[1970-01-01 00:01:13.317][HSM][INFO][31] select_region: 0xc11cb55b
[1970-01-01 00:01:13.323][HSM][INFO][67] spi_nor de
IMU0log=lt:1122 mV | pmu:MP2882
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_v
IPU0log=50 F:1950
avs-uncore V:750 F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
av
IPU1log= F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
avs-uncore V:840 F:2450
avs-
HSM0log=vice_id 0xff1a67c8
[1970-01-01 00:01:13.329][HSM][INFO][50] std_cmd readback 0x30220d8
[1970-01-01 00:01:13.335][HSM][INFO][72] saf_cmd 0x0 readback 0x9f5a0604
[1970-01-01 00:01:13.342][HSM][INFO][72] saf_cmd 0x1 readback 0x5
IMU0log=olt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_
IPU0log=s-uncore V:840 F:2450
avs-uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain
IPU1log=uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | r
HSM0log=b7e938
[1970-01-01 00:01:13.348][HSM][INFO][72] saf_cmd 0x2 readback 0x1
[1970-01-01 00:01:13.354][HSM][INFO][72] saf_cmd 0x3 readback 0x0
[1970-01-01 00:01:13.360][HSM][INFO][72] saf_cmd 0x4 readback 0x0
[00:01:13.366][info
IMU0log=volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus r
IPU0log=[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | p
IPU1log=ail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_volt:1122 mV | pmu:MP2882
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[0] volt =  906 mV
pwr domain
HSM0log=] succeed to do thirdparty boot_profile_driver init
[00:01:13.372][info] succeed to do thirdparty crypto_driver init
[00:01:13.378][info] succeed to do thirdparty period_driver init
[00:01:13.383][info]  start loading interna
IMU0log=eady.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait th
IPU0log=mu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pmbus:0x480c0000 ver:0x110
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
IPU1log=[9] volt = 1103 mV
=end=
w&h rd rail:0, 906
w&h rd rail:1, 1103
pwr domain[0] set volt  904 mV succ
pwr domain[9] set volt 1103 mV succ
volt post
pwr domain[0] volt =  904 mV
pwr domain[9] volt = 1103 mV
==end==
Totem[0] Core Bo
HSM0log=l task ...
[00:01:13.388][info]  task name is ccm_task
[00:01:13.392][info]  hm_dynamic_loadelf successfully!
[00:01:13.397][info] internal task[1] task_name=ccm_task load successfully
[00:01:13.403][info]  task name is upgr
IMU0log=e cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master I
IPU0log=
avsbus resync succ
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[2] volt =  906 mV
pwr domain[7] volt =  804 mV
pwr domain[4] volt =  804 mV
pwr domain[1] volt =  804 mV
=end=
w&h rd rail:
IPU1log=ot Vol [1029]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2,
HSM0log=ade_task
[00:01:13.408][info]  hm_dynamic_loadelf successfully!
[00:01:13.413][info] internal task[2] task_name=upgrade_task load successfully
[00:01:13.420][info] created task ccm_task success!
[00:01:13.424][info] created 
IMU0log=mu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
cpu 0 entering scheduler
|--------------------------------------------------|
AtsPrint
|idx|lockCount| srcAddr| destAddr| addrLen|
|--
IPU0log=0, 904
w&h rd rail:1, 802
pwr domain[2] set volt  902 mV succ
pwr domain[7] set volt  802 mV succ
w&h rd rail:0, 804
w&h rd rail:1, 804
pwr domain[4] set volt  802 mV succ
pwr domain[1] set volt  802 mV succ
volt post
pwr domain
IPU1log= ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd8
HSM0log=task upgrade_task success!
[1970-01-01 00:01:13.429][HSM][INFO][54] Platform init 0x20250523 0x4e.
[1970-01-01 00:01:13.435][HSM][INFO][197] ccm start.
[1970-01-01 00:01:13.440][HSM][INFO][86] upgrade task init success.
[197
IMU0log=------------------------------------------------|
|  0|00000000|0x010500000|0x000110800000|0x00100000|
|  1|00000000|0x020000000|0x00001d000000|0x00800000|
|  2|00000000|0x020800000|0x000490000000|0x00100000|
|  3|00000000|0x020
IPU0log=[2] volt =  902 mV
pwr domain[7] volt =  802 mV
pwr domain[4] volt =  804 mV
pwr domain[1] volt =  802 mV
==end==
Totem[0] Core Boot Vol [1015]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0,
IPU1log=00, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
opposite dieId: 0, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 
HSM0log=0-01-01 00:01:13.446][HSM][INFO][95] upgrade recv cmd, 0x181.
[1970-01-01 00:01:13.452][HSM][INFO][103] upgrade res, 0x3a5aa5a3.
.
IMU0log=900000|0x000004000000|0x08000000|
|  4|00000000|0x028900000|0x000440580000|0x01000000|
|  5|00000000|0x029900000|0x000590000000|0x00100000|
|  6|00000000|0x029a00000|0x002000150000|0x00100000|
|  7|00000000|0x000000000|0x0000000
IPU0log= MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 
IPU1log=enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
hiboost task entry
boost wait SEF.
[INFO] mem used of task 'app_Task' is:0x2028, not zero when task being deleted
boost param OK.
Totem[0] Core[ 0] Freq Limit Low
HSM0log=
IMU0log=00000|0x00000000|
|  8|00000000|0x040000000|0x000000000000|0x08000000|
|  9|00000000|0x048000000|0x000000000000|0x08000000|
| 10|00000000|0x050000000|0x000000000000|0x08000000|
| 11|00000000|0x058000000|0x000000000000|0x08000000
IPU0log=0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
tsensor type
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Fr
HSM0log=
IMU0log=|
| 12|00000000|0x060000000|0x000000000000|0x08000000|
| 13|00000000|0x068000000|0x000000000000|0x08000000|
| 14|00000000|0x070000000|0x000000000000|0x08000000|
| 15|00000000|0x078000000|0x000490000000|0x08000000|
|-------------
IPU0log=: 3, ppuFormatK: 0x4da6, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b4,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 3, mask: fffffff8
tsensor type: 4, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=-------------------------------------|
=~=~=~=~=~=~=~=~=~=~= IMU Log @ 2026.4.20 21:24:28 =~=~=~=~=~=~=~=~=~=~=
[IMU] Watchdog Initialization done!
[RegisterInterruptSource]:[21] begin
Interrupt 32 register OK
Interrupt 34 reg
IPU0log=0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 4, mask: ffffffee
tsensor type: 5, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1

IPU1log= Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=ister OK
Interrupt 40 register OK
Interrupt 44 register OK
sram cnt 0x0, id = 43
Interrupt 43 register OK
Interrupt 36 register OK
Interrupt 57 register OK
sram cnt 0x0, id = 42
Interrupt 42 register OK
Interrupt 37 register OK

IPU0log=tsensor: 5, mask: ffffffda
tsensor type: 6, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 6, mask: ffffff80
tsensor type: 7, ppuFormatK: 0x437a,
IPU1log=KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=[RegisterInterruptSource]:[39] end
IPMB initialization Start...
IPMB clock set done, prer = 0x18.
IPMB Rx FIFO clear empty.
IPMB initialization Done.
starting DFX Collect Task end
PowerTask Entry ...
Wait all vrd init done
IPU0log= ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 7, mask: fffffffe
opposite dieId: 1, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
CPM max V[900]-
IPU1log= Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low
HSM0log=
IMU0log= ...
All vrd init done, power task start
refresh domainId 0 Lsb 0x0
refresh domainId 9 Lsb 0x1
refresh domainId 2 Lsb 0x0
refresh domainId 7 Lsb 0x1
refresh domainId 4 Lsb 0x0
refresh domainId 1 Lsb 0x1
power sensor[0] | calib:5
IPU0log=F:2800
CPM min V[750]-F:1600
freq:2350, idx:9
cpm trim freq: 2600, idx: 4
cpm trim finish
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
recount hours 
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Fr
HSM0log=
IMU0log=120 | rshunt:1 | rshuntDiv:1000 | currLsb:1 | currLsbDiv:1000 | enableFlag:1
                | pwrLsb:25 | defPwr:25000 | minPwr:10000 | maxPwr:65000 | pwrFix:3400
                | manufacturerId: 0x5549 | dieId: 0x2260
power s
IPU0log=0x78c 
hiboost task entry
boost wait SEF.
boost param OK.
Totem[0] Core[ 0] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[26
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=ensor[0] init success
ScmiTaskEntry start.
[RegisterInterruptSource]:[21] begin
Interrupt 51 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 52 register OK
[RegisterInterruptSourc
IPU0log=00000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[12000
IPU1log= Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=e]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 53 register OK
[RegisterInterruptSource]:[39] end
[0.01.29.987]starting ras Init
RAS Setup Value get done!
INT_NUM_PER_SKT * HiGetSktNum() = 0x8
index = 0x0
RasIntReg
IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Lim
IPU1log=KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=ister init 160 
index = 0x1
RasIntRegister init 172 
index = 0x2
RasIntRegister init 162 
index = 0x3
RasIntRegister init 174 
index = 0x4
RasIntRegister init 184 
index = 0x5
RasIntRegister init 196 
index = 0x6
RasIntRegister 
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IPU1log= Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low
HSM0log=
IMU0log=init 186 
index = 0x7
RasIntRegister init 198 
RasIntRegister init 161 
RasIntRegister init 173 
RasIntRegister init 185 
RasIntRegister init 197 
RasIntRegister init 284 
RasIntRegister init 314 
MceTableHeadInit start
starting
IPU0log=14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
To
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
uncore max freq : 23
HSM0log=
IMU0log= Ce_Storm Contrl and Ras_Data_Update Task end
[0.01.30.069]starting ras end
[IMU][ERR] skt id 0
Ub init task start Entry ...
UbInitTask Entry ...
[RegisterInterruptSource]:[21] begin
Interrupt 167 register OK
[RegisterInterru
IPU0log=tem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[26
IPU1log=50 MHz

HSM0log=
IMU0log=ptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 191 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 171 register OK
[RegisterInterruptSource]:[39] end
[Registe
IPU0log=00000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[12000
IPU1log=
HSM0log=
IMU0log=rInterruptSource]:[21] begin
Interrupt 183 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 195 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Lim
IPU1log=
HSM0log=
IMU0log=
Interrupt 207 register OK
[RegisterInterruptSource]:[39] end
Init heart-beat-task end
CS0 flash do not support sfdp!
Current flash device ID[0x61a67c8]!
System supported 1 Flash.
flash cs 0 Manufacture 0xc8, DeviceId 0x1a67, 
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IPU1log=
HSM0log=
IMU0log=AddrMode[0-3B,1-4B] 0x1:
    size 0x4000000, pagesize 0x100
    read  cmd 0x13, dummy byte 0x8
    write cmd 0x12, dummy byte 0x0
    erase4k cmd 0x21, erase64k byte 0xdc
sfc init end
firstUnMskExt0Int
ThermalDimmStart Entry ...
IPU0log=33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
To
IPU1log=
HSM0log=
IMU0log=
wait ddr init done...
HacLowPowerStart Entry ...
Hello LiteOS...
pwr cap[0]: 0, 67
Init ReportPcieMmioToBmcTaskEntry end
starting Fpc Isolation Task end
pwr cap[1]: f, 27
pwr cap[2]: 1, 3
BMC_COLLECTION: bmc req last log!
IPU0log=tem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[26
IPU1log=
HSM0log=
IMU0log=
DDR initing...
BMC_COLLECTION: bmc req last log!
DDR initing...
BMC_COLLECTION: bmc req last log!
DDR initing...
[0.02.01.273]DDR init done
[LOG]head = 0x0, tail = 0x1899, logSize = 0x1899
[IMU][ERR] HsmLogInit!
[IMU][ERR] HsmL
IPU0log=00000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
uncore max freq : 2350 MHz

IPU1log=
HSM0log=
IMU0log=ogInit! TRUE
set apei done!
UbConfigData size is 64
UbConfigData 0 : 0
UbConfigData 1 : 0
UbConfigData 2 : 0
UbConfigData 3 : 1
UbConfigData 4 : 31
UbConfigData 5 : 1
UbConfigData 6 : 0
UbConfigData 7 : 32
UbConfigData 8 : 0
UbC
IPU0log=
IPU1log=
HSM0log=
IMU0log=onfigData 9 : 1
UbConfigData 10 : 2
UbConfigData 11 : 0
UbConfigData 12 : 0
UbConfigData 13 : 1
UbConfigData 14 : 0
UbConfigData 15 : 0
UbConfigData 16 : 0
UbConfigData 17 : 0
UbConfigData 18 : 0
UbConfigData 19 : 0
UbConfigData
IPU0log=
IPU1log=
HSM0log=
IMU0log= 20 : 0
UbConfigData 21 : 0
UbConfigData 22 : 11
UbConfigData 23 : 0
UbConfigData 24 : 0
UbConfigData 25 : 0
UbConfigData 26 : 0
UbConfigData 27 : 0
UbConfigData 28 : 0
UbConfigData 29 : 0
UbConfigData 30 : 0
UbConfigData 31 : 0
IPU0log=
IPU1log=
HSM0log=
IMU0log=
UbConfigData 32 : 0
UbConfigData 33 : 0
UbConfigData 34 : 2
UbConfigData 35 : 1
UbConfigData 36 : 0
UbConfigData 37 : 0
UbConfigData 38 : 0
UbConfigData 39 : 0
UbConfigData 40 : 0
UbConfigData 41 : 0
UbConfigData 42 : 0
UbConfi
IPU0log=
IPU1log=
HSM0log=
IMU0log=gData 43 : 0
UbConfigData 44 : 0
UbConfigData 45 : 0
UbConfigData 46 : 0
UbConfigData 47 : 0
UbConfigData 48 : 0
UbConfigData 49 : 0
UbConfigData 50 : 0
UbConfigData 51 : 0
UbConfigData 52 : 0
UbConfigData 53 : 0
UbConfigData 54
IPU0log=
IPU1log=
HSM0log=
IMU0log= : 0
UbConfigData 55 : 0
UbConfigData 56 : 0
UbConfigData 57 : 0
UbConfigData 58 : 0
UbConfigData 59 : 0
UbConfigData 60 : 0
UbConfigData 61 : 0
UbConfigData 62 : 0
UbConfigData 63 : 0
UbConfigData 64 : 0
ClusterSwitch: 0, 0
Clu
IPU0log=
IPU1log=
HSM0log=
IMU0log=sterMode: 0, 0
ControlMode: 0, 0
EnumMode: 1, 1
BodyMask: 31, 31
CcCtxCount: 256, 256
RcCtxCount: 32, 32
UbMemEntrySize: 128, 0
MctpSupport: 1, 1
SecureMode: 0, 0
PrimaryCna: 0, 0
Upi: 0, 0
EntityId: 0, 0
SlotId: 1, 1
SocketId: 
IPU0log=
IPU1log=
HSM0log=
IMU0log=2, 2
PortIndex: 0, 0
PortCna: 0, 0
CtrlCna: 11, 11
ImpBootFlag: 2, 2
ImuBootFlag: 1, 1
SktId: 0 DieId:2, HCCS_LINK:2 PaId:2
SktId: 1 DieId:2, HCCS_LINK:0 PaId:0
CIS register: ID[0xc00007ff], owner[0x1000003], function[0x1045dc5c
IPU0log=
IPU1log=
HSM0log=
IMU0log=].
CIS register: ID[0xc0000002], owner[0x1000003], function[0x1045dcfc].
odf: can not find od file[config]
Do not get NII route table, disable NII Send function.
UbiosTaskStart Entry ...
UbiosTaskStart create task success
IMU 
IPU0log=
IPU1log=
HSM0log=
IMU0log=ImpBootFlag: 0x2
skip IMP start config...
UbiosCisTask Entry ...
ddr init done, start thermal dimm task
======dimm status======
  chl[0] dimm0 1, dimm1 0
  chl[1] dimm0 0, dimm1 0
  chl[2] dimm0 0, dimm1 0
  chl[3] dimm0 0, dim
IPU0log=
IPU1log=
HSM0log=
IMU0log=m1 0
  chl[4] dimm0 0, dimm1 0
  chl[5] dimm0 0, dimm1 0
  chl[6] dimm0 0, dimm1 0
  chl[7] dimm0 0, dimm1 0
  chl[8] dimm0 0, dimm1 0
  chl[9] dimm0 0, dimm1 0
  chl[10] dimm0 0, dimm1 0
  chl[11] dimm0 0, dimm1 0
==========end
IPU0log=
IPU1log=
HSM0log=
IMU0log===========
sktId[0] chl[0] registered, dimm mask = 0x1
======dimm status======
  chl[0] dimm0 1, dimm1 0
  chl[1] dimm0 0, dimm1 0
  chl[2] dimm0 0, dimm1 0
  chl[3] dimm0 0, dimm1 0
  chl[4] dimm0 0, dimm1 0
  chl[5] dimm0 0, d
IPU0log=
IPU1log=
HSM0log=
IMU0log=imm1 0
  chl[6] dimm0 0, dimm1 0
  chl[7] dimm0 0, dimm1 0
  chl[8] dimm0 0, dimm1 0
  chl[9] dimm0 0, dimm1 0
  chl[10] dimm0 0, dimm1 0
  chl[11] dimm0 0, dimm1 0
==========end==========
sktId[1] chl[0] registered, dimm mask =
IPU0log=
IPU1log=
HSM0log=
IMU0log= 0x1
=====dimm temp params=====
  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
  is_thermal_thro_en  : 1
  is_aref_rate_auto   : 0
===========end============
[0.02.08.213]TF Heartbeat Start
[0.02.09.516]RECEI
IPU0log=
IPU1log=
HSM0log=
IMU0log=VE MEM SILK.
0: skt = 0 logic = 5 phy = 6 
1: skt = 0 logic = 0 phy = 8 
2: skt = 1 logic = 8 phy = 5 
3: skt = 1 logic = 11 phy = 7 
4: skt = 1 logic = 10 phy = 3 
5: skt = 1 logic = 0 phy = 8 
6: skt = 0 logic = 3 phy = 10 
7:
IPU0log=
IPU1log=
HSM0log=
IMU0log= skt = 0 logic = 9 phy = 11 
8: skt = 1 logic = 1 phy = 0 
9: skt = 1 logic = 5 phy = 6 
10: skt = 0 logic = 7 phy = 1 
11: skt = 1 logic = 6 phy = 9 
12: skt = 1 logic = 3 phy = 10 
13: skt = 1 logic = 7 phy = 1 
14: skt = 1 lo
IPU0log=
IPU1log=
HSM0log=
IMU0log=gic = 9 phy = 11 
15: skt = 0 logic = 4 phy = 2 
16: skt = 0 logic = 10 phy = 3 
17: skt = 0 logic = 8 phy = 5 
18: skt = 0 logic = 6 phy = 9 
19: skt = 0 logic = 11 phy = 7 
20: skt = 1 logic = 2 phy = 4 
21: skt = 1 logic = 4 
IPU0log=
IPU1log=
HSM0log=
IMU0log=phy = 2 
22: skt = 0 logic = 2 phy = 4 
23: skt = 0 logic = 1 phy = 0 
get mem silk data length: 72
[0.02.12.483]PCIE INIT DONE.
[IMU][ERR] LOS_SemPend(g_pcieSemaphore, LOS_WAIT_FOREVER)
[RegisterInterruptSource]:[21] begin
Int
IPU0log=
IPU1log=
HSM0log=
IMU0log=errupt 258 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 262 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 266 register OK
[Regi
IPU0log=
IPU1log=
HSM0log=
IMU0log=sterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 270 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 277 register OK
[RegisterInterruptSource]:[39] en
IPU0log=
IPU1log=
HSM0log=
IMU0log=d
[RegisterInterruptSource]:[21] begin
Interrupt 288 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 292 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]
IPU0log=
IPU1log=
HSM0log=
IMU0log=:[21] begin
Interrupt 296 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 300 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 307 r
IPU0log=
IPU1log=
HSM0log=
IMU0log=egister OK
[RegisterInterruptSource]:[39] end
pmt Init done

-----------------ROUTE TABLE------------------
entryCount = 1
----------------------------------------------
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic
IPU0log=
IPU1log=
HSM0log=
IMU0log= = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2100
----------------------------------------------
BMC_COLLECTION: bmc req last log!
[IMU][ERR] [
HSM0log= no log data error!]
------------
IPU0log=
IPU1log=
HSM0log=
IMU0log=-----ROUTE TABLE------------------
entryCount = 2
----------------------------------------------
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize =
IPU0log=
IPU1log=
HSM0log=
IMU0log= 2, bdf = 0x2100
[No.1]:
eidRange = 1, startEid = 10, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2500
----------------------------------------------
--------------
IPU0log=
IPU1log=
HSM0log=
IMU0log=---ROUTE TABLE------------------
entryCount = 2
----------------------------------------------
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2
IPU0log=
IPU1log=
HSM0log=
IMU0log=, bdf = 0x2100
[No.1]:
eidRange = 1, startEid = 10, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2500
----------------------------------------------

IPU0log=
IPU1log=
HSM0log=
IMU0log=1T1N1U skt:0 CfgBusDfxPreConfig finish

********Hello Huawei LiteOS********

IMU Firmware Version : B173V01
LiteOS Kernel Version : 5.10.0
Run on Socket[0] Die[3]
Chip Version: 1
Max socket num: 2
*******************************
IPU0log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 0
cls: 6, core: 7
cpu 933 sram 1010 ddr 983
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  750|  802|  885|  933|
max  v
IPU1log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 1
cls: 6, core: 7
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  759|  821|  909|  961|
max  v: |  750|  750|  753|  781
HSM0log=[1970-01-01 00:01:12.296][HSM][INFO][30] init start
[1970-01-01 00:01:12.297][HSM][INFO][38] init over
[00:01:12.306][info] succeed to do thirdparty dfx_pabuk init
[00:01:12.312][info] os_mem_system_init default pool done
[0
IMU0log=***
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | rail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_vo
IPU0log=: |  750|  750|  754|  775|  836|  922|  980|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:7
IPU1log=|  846|  938|  994|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:750 F:1950
avs-uncore V:750
HSM0log=0:01:12.318][info] addr is already in region
[00:01:12.321][info] succeed to do thirdparty otpc_pabuk init
[1970-01-01 00:01:12.326][HSM][INFO][31] select_region: 0xc11cb55b
[1970-01-01 00:01:12.332][HSM][INFO][67] spi_nor de
IMU0log=lt:1122 mV | pmu:MP2882
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_v
IPU0log=50 F:1950
avs-uncore V:750 F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
av
IPU1log= F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
avs-uncore V:840 F:2450
avs-
HSM0log=vice_id 0xff1a67c8
[1970-01-01 00:01:12.339][HSM][INFO][50] std_cmd readback 0x30220d8
[1970-01-01 00:01:12.344][HSM][INFO][72] saf_cmd 0x0 readback 0x9f5a0604
[1970-01-01 00:01:12.351][HSM][INFO][72] saf_cmd 0x1 readback 0x5
IMU0log=olt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_
IPU0log=s-uncore V:840 F:2450
avs-uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain
IPU1log=uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | r
HSM0log=b7e938
[1970-01-01 00:01:12.357][HSM][INFO][72] saf_cmd 0x2 readback 0x1
[1970-01-01 00:01:12.363][HSM][INFO][72] saf_cmd 0x3 readback 0x0
[1970-01-01 00:01:12.369][HSM][INFO][72] saf_cmd 0x4 readback 0x0
[00:01:12.375][info
IMU0log=volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus r
IPU0log=[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | p
IPU1log=ail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_volt:1122 mV | pmu:MP2882
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[0] volt =  906 mV
pwr domain
HSM0log=] succeed to do thirdparty boot_profile_driver init
[00:01:12.381][info] succeed to do thirdparty crypto_driver init
[00:01:12.387][info] succeed to do thirdparty period_driver init
[00:01:12.392][info]  start loading interna
IMU0log=eady.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait th
IPU0log=mu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pmbus:0x480c0000 ver:0x110
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
IPU1log=[9] volt = 1103 mV
=end=
w&h rd rail:0, 906
w&h rd rail:1, 1103
pwr domain[0] set volt  904 mV succ
pwr domain[9] set volt 1103 mV succ
volt post
pwr domain[0] volt =  904 mV
pwr domain[9] volt = 1103 mV
==end==
Totem[0] Core Bo
HSM0log=l task ...
[00:01:12.397][info]  task name is ccm_task
[00:01:12.401][info]  hm_dynamic_loadelf successfully!
[00:01:12.406][info] internal task[1] task_name=ccm_task load successfully
[00:01:12.413][info]  task name is upgr
IMU0log=e cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master I
IPU0log=
avsbus resync succ
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[2] volt =  904 mV
pwr domain[7] volt =  802 mV
pwr domain[4] volt =  804 mV
pwr domain[1] volt =  806 mV
=end=
w&h rd rail:
IPU1log=ot Vol [1029]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2,
HSM0log=ade_task
[00:01:12.417][info]  hm_dynamic_loadelf successfully!
[00:01:12.422][info] internal task[2] task_name=upgrade_task load successfully
[00:01:12.429][info] created task ccm_task success!
[00:01:12.433][info] created 
IMU0log=mu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
cpu 0 entering scheduler
|--------------------------------------------------|
AtsPrint
|idx|lockCount| srcAddr| destAddr| addrLen|
|--
IPU0log=0, 904
w&h rd rail:1, 802
pwr domain[2] set volt  902 mV succ
pwr domain[7] set volt  802 mV succ
w&h rd rail:0, 806
w&h rd rail:1, 804
pwr domain[4] set volt  804 mV succ
pwr domain[1] set volt  802 mV succ
volt post
pwr domain
IPU1log= ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd8
HSM0log=task upgrade_task success!
[1970-01-01 00:01:12.438][HSM][INFO][54] Platform init 0x20250523 0x4e.
[1970-01-01 00:01:12.445][HSM][INFO][197] ccm start.
[1970-01-01 00:01:12.449][HSM][INFO][86] upgrade task init success.
[197
IMU0log=------------------------------------------------|
|  0|00000000|0x010500000|0x000110800000|0x00100000|
|  1|00000000|0x020000000|0x00001d000000|0x00800000|
|  2|00000000|0x020800000|0x000490000000|0x00100000|
|  3|00000000|0x020
IPU0log=[2] volt =  902 mV
pwr domain[7] volt =  802 mV
pwr domain[4] volt =  802 mV
pwr domain[1] volt =  802 mV
==end==
Totem[0] Core Boot Vol [1015]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0,
IPU1log=00, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
opposite dieId: 0, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 
HSM0log=0-01-01 00:01:12.455][HSM][INFO][95] upgrade recv cmd, 0x181.
[1970-01-01 00:01:12.461][HSM][INFO][103] upgrade res, 0x3a5aa5a3.
.
IMU0log=900000|0x000004000000|0x08000000|
|  4|00000000|0x028900000|0x000440580000|0x01000000|
|  5|00000000|0x029900000|0x000590000000|0x00100000|
|  6|00000000|0x029a00000|0x002000150000|0x00100000|
|  7|00000000|0x000000000|0x0000000
IPU0log= MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 
IPU1log=enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
hiboost task entry
boost wait SEF.
[INFO] mem used of task 'app_Task' is:0x2028, not zero when task being deleted
boost param OK.
Totem[0] Core[ 0] Freq Limit Low
HSM0log=
IMU0log=00000|0x00000000|
|  8|00000000|0x040000000|0x000000000000|0x08000000|
|  9|00000000|0x048000000|0x000000000000|0x08000000|
| 10|00000000|0x050000000|0x000000000000|0x08000000|
| 11|00000000|0x058000000|0x000000000000|0x08000000
IPU0log=0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
tsensor type
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Fr
HSM0log=
IMU0log=|
| 12|00000000|0x060000000|0x000000000000|0x08000000|
| 13|00000000|0x068000000|0x000000000000|0x08000000|
| 14|00000000|0x070000000|0x000000000000|0x08000000|
| 15|00000000|0x078000000|0x000490000000|0x08000000|
|-------------
IPU0log=: 3, ppuFormatK: 0x4da6, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b4,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 3, mask: fffffff8
tsensor type: 4, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=-------------------------------------|
=~=~=~=~=~=~=~=~=~=~= IMU Log @ 2026.4.21 5:8:32 =~=~=~=~=~=~=~=~=~=~=
[IMU] Watchdog Initialization done!
[RegisterInterruptSource]:[21] begin
Interrupt 32 register OK
Interrupt 34 regis
IPU0log=0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 4, mask: ffffffee
tsensor type: 5, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1

IPU1log= Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=ter OK
Interrupt 40 register OK
Interrupt 44 register OK
sram cnt 0x0, id = 43
Interrupt 43 register OK
Interrupt 36 register OK
Interrupt 57 register OK
sram cnt 0x0, id = 42
Interrupt 42 register OK
Interrupt 37 register OK
[R
IPU0log=tsensor: 5, mask: ffffffda
tsensor type: 6, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 6, mask: ffffff80
tsensor type: 7, ppuFormatK: 0x437a,
IPU1log=KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=egisterInterruptSource]:[39] end
IPMB initialization Start...
IPMB clock set done, prer = 0x18.
IPMB Rx FIFO clear empty.
IPMB initialization Done.
starting DFX Collect Task end
PowerTask Entry ...
Wait all vrd init done .
IPU0log= ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 7, mask: fffffffe
opposite dieId: 1, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
CPM max V[900]-
IPU1log= Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low
HSM0log=
IMU0log=..
All vrd init done, power task start
refresh domainId 0 Lsb 0x0
refresh domainId 9 Lsb 0x1
refresh domainId 2 Lsb 0x0
refresh domainId 7 Lsb 0x1
refresh domainId 4 Lsb 0x0
refresh domainId 1 Lsb 0x1
power sensor[0] | calib:512
IPU0log=F:2800
CPM min V[750]-F:1600
freq:2350, idx:9
cpm trim freq: 2600, idx: 4
cpm trim finish
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
recount hours 
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Fr
HSM0log=
IMU0log=0 | rshunt:1 | rshuntDiv:1000 | currLsb:1 | currLsbDiv:1000 | enableFlag:1
                | pwrLsb:25 | defPwr:25000 | minPwr:10000 | maxPwr:65000 | pwrFix:3400
                | manufacturerId: 0x5549 | dieId: 0x2260
power sen
IPU0log=0x78c 
hiboost task entry
boost wait SEF.
boost param OK.
Totem[0] Core[ 0] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[26
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=sor[0] init success
ScmiTaskEntry start.
[RegisterInterruptSource]:[21] begin
Interrupt 51 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 52 register OK
[RegisterInterruptSource]
IPU0log=00000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[12000
IPU1log= Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 53 register OK
[RegisterInterruptSource]:[39] end
[0.01.28.992]starting ras Init
RAS Setup Value get done!
INT_NUM_PER_SKT * HiGetSktNum() = 0x8
index = 0x0
RasIntRegis
IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Lim
IPU1log=KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=ter init 160 
index = 0x1
RasIntRegister init 172 
index = 0x2
RasIntRegister init 162 
index = 0x3
RasIntRegister init 174 
index = 0x4
RasIntRegister init 184 
index = 0x5
RasIntRegister init 196 
index = 0x6
RasIntRegister in
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IPU1log= Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low
HSM0log=
IMU0log=it 186 
index = 0x7
RasIntRegister init 198 
RasIntRegister init 161 
RasIntRegister init 173 
RasIntRegister init 185 
RasIntRegister init 197 
RasIntRegister init 284 
RasIntRegister init 314 
MceTableHeadInit start
starting C
IPU0log=14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
To
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
uncore max freq : 23
HSM0log=
IMU0log=e_Storm Contrl and Ras_Data_Update Task end
[0.01.29.074]starting ras end
[IMU][ERR] skt id 0
Ub init task start Entry ...
[RegisterInterruptSource]:[21] begin
UbInitTask Entry ...
Interrupt 167 register OK
[RegisterInterrupt
IPU0log=tem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[26
IPU1log=50 MHz

HSM0log=
IMU0log=Source]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 191 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 171 register OK
[RegisterInterruptSource]:[39] end
[RegisterI
IPU0log=00000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[12000
IPU1log=
HSM0log=
IMU0log=nterruptSource]:[21] begin
Interrupt 183 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 195 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin

IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Lim
IPU1log=
HSM0log=
IMU0log=Interrupt 207 register OK
[RegisterInterruptSource]:[39] end
Init heart-beat-task end
CS0 flash do not support sfdp!
Current flash device ID[0x61a67c8]!
System supported 1 Flash.
flash cs 0 Manufacture 0xc8, DeviceId 0x1a67, Ad
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IPU1log=
HSM0log=
IMU0log=drMode[0-3B,1-4B] 0x1:
    size 0x4000000, pagesize 0x100
    read  cmd 0x13, dummy byte 0x8
    write cmd 0x12, dummy byte 0x0
    erase4k cmd 0x21, erase64k byte 0xdc
sfc init end
firstUnMskExt0Int
ThermalDimmStart Entry ...

IPU0log=33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
To
IPU1log=
HSM0log=
IMU0log=wait ddr init done...
HacLowPowerStart Entry ...
Hello LiteOS...
Init ReportPcieMmioToBmcTaskEntry end
starting Fpc Isolation Task end
pwr cap[0]: 0, 67
pwr cap[1]: f, 27
pwr cap[2]: 1, 3
[IMU][ERR] IMP log not ready, DDR i
IPU0log=tem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[26
IPU1log=
HSM0log=
IMU0log=niting...
[IMU][ERR] IMP log not ready, DDR initing...
[0.02.00.044]Get PCIE Info CMD INVALID, PCIE No Init!
[IMU][ERR] IMP log not ready, DDR initing...
[0.02.00.219]DDR init done
[LOG]head = 0x0, tail = 0x18c1, logSize = 0x18c
IPU0log=00000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
uncore max freq : 2350 MHz

IPU1log=
HSM0log=
IMU0log=1
[IMU][ERR] HsmLogInit!
[IMU][ERR] HsmLogInit! TRUE
set apei done!
UbConfigData size is 64
UbConfigData 0 : 0
UbConfigData 1 : 0
UbConfigData 2 : 0
UbConfigData 3 : 1
UbConfigData 4 : 31
UbConfigData 5 : 1
UbConfigData 6 : 0
Ub
IPU0log=
IPU1log=
HSM0log=
IMU0log=ConfigData 7 : 32
UbConfigData 8 : 0
UbConfigData 9 : 1
UbConfigData 10 : 2
UbConfigData 11 : 0
UbConfigData 12 : 0
UbConfigData 13 : 1
UbConfigData 14 : 0
UbConfigData 15 : 0
UbConfigData 16 : 0
UbConfigData 17 : 0
UbConfigData
IPU0log=
IPU1log=
HSM0log=
IMU0log= 18 : 0
UbConfigData 19 : 0
UbConfigData 20 : 0
UbConfigData 21 : 0
UbConfigData 22 : 11
UbConfigData 23 : 0
UbConfigData 24 : 0
UbConfigData 25 : 0
UbConfigData 26 : 0
UbConfigData 27 : 0
UbConfigData 28 : 0
UbConfigData 29 : 0
IPU0log=
IPU1log=
HSM0log=
IMU0log=
UbConfigData 30 : 0
UbConfigData 31 : 0
UbConfigData 32 : 0
UbConfigData 33 : 0
UbConfigData 34 : 2
UbConfigData 35 : 1
UbConfigData 36 : 0
UbConfigData 37 : 0
UbConfigData 38 : 0
UbConfigData 39 : 0
UbConfigData 40 : 0
UbConfi
IPU0log=
IPU1log=
HSM0log=
IMU0log=gData 41 : 0
UbConfigData 42 : 0
UbConfigData 43 : 0
UbConfigData 44 : 0
UbConfigData 45 : 0
UbConfigData 46 : 0
UbConfigData 47 : 0
UbConfigData 48 : 0
UbConfigData 49 : 0
UbConfigData 50 : 0
UbConfigData 51 : 0
UbConfigData 52
IPU0log=
IPU1log=
HSM0log=
IMU0log= : 0
UbConfigData 53 : 0
UbConfigData 54 : 0
UbConfigData 55 : 0
UbConfigData 56 : 0
UbConfigData 57 : 0
UbConfigData 58 : 0
UbConfigData 59 : 0
UbConfigData 60 : 0
UbConfigData 61 : 0
UbConfigData 62 : 0
UbConfigData 63 : 0
UbC
IPU0log=
IPU1log=
HSM0log=
IMU0log=onfigData 64 : 0
ClusterSwitch: 0, 0
ClusterMode: 0, 0
ControlMode: 0, 0
EnumMode: 1, 1
BodyMask: 31, 31
CcCtxCount: 256, 256
RcCtxCount: 32, 32
UbMemEntrySize: 128, 0
MctpSupport: 1, 1
SecureMode: 0, 0
PrimaryCna: 0, 0
Upi: 0, 
IPU0log=
IPU1log=
HSM0log=
IMU0log=0
EntityId: 0, 0
SlotId: 1, 1
SocketId: 2, 2
PortIndex: 0, 0
PortCna: 0, 0
CtrlCna: 11, 11
ImpBootFlag: 2, 2
ImuBootFlag: 1, 1
SktId: 0 DieId:2, HCCS_LINK:2 PaId:2
SktId: 1 DieId:2, HCCS_LINK:0 PaId:0
CIS register: ID[0xc00007ff
IPU0log=
IPU1log=
HSM0log=
IMU0log=], owner[0x1000003], function[0x1045dc5c].
CIS register: ID[0xc0000002], owner[0x1000003], function[0x1045dcfc].
odf: can not find od file[config]
Do not get NII route table, disable NII Send function.
UbiosTaskStart Entry ...

IPU0log=
IPU1log=
HSM0log=
IMU0log=UbiosTaskStart create task success
IMU ImpBootFlag: 0x2
skip IMP start config...
UbiosCisTask Entry ...
ddr init done, start thermal dimm task
======dimm status======
  chl[0] dimm0 1, dimm1 0
  chl[1] dimm0 0, dimm1 0
  chl[2
IPU0log=
IPU1log=
HSM0log=
IMU0log=] dimm0 0, dimm1 0
  chl[3] dimm0 0, dimm1 0
  chl[4] dimm0 0, dimm1 0
  chl[5] dimm0 0, dimm1 0
  chl[6] dimm0 0, dimm1 0
  chl[7] dimm0 0, dimm1 0
  chl[8] dimm0 0, dimm1 0
  chl[9] dimm0 0, dimm1 0
  chl[10] dimm0 0, dimm1 0

IPU0log=
IPU1log=
HSM0log=
IMU0log=  chl[11] dimm0 0, dimm1 0
==========end==========
sktId[0] chl[0] registered, dimm mask = 0x1
======dimm status======
  chl[0] dimm0 1, dimm1 0
  chl[1] dimm0 0, dimm1 0
  chl[2] dimm0 0, dimm1 0
  chl[3] dimm0 0, dimm1 0
  chl
IPU0log=
IPU1log=
HSM0log=
IMU0log=[4] dimm0 0, dimm1 0
  chl[5] dimm0 0, dimm1 0
  chl[6] dimm0 0, dimm1 0
  chl[7] dimm0 0, dimm1 0
  chl[8] dimm0 0, dimm1 0
  chl[9] dimm0 0, dimm1 0
  chl[10] dimm0 0, dimm1 0
  chl[11] dimm0 0, dimm1 0
==========end==========
IPU0log=
IPU1log=
HSM0log=
IMU0log=
sktId[1] chl[0] registered, dimm mask = 0x1
=====dimm temp params=====
  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
  is_thermal_thro_en  : 1
  is_aref_rate_auto   : 0
===========end============
[0.02.07.0
IPU0log=
IPU1log=
HSM0log=
IMU0log=33]TF Heartbeat Start
[0.02.08.247]RECEIVE MEM SILK.
0: skt = 0 logic = 5 phy = 6 
1: skt = 0 logic = 0 phy = 8 
2: skt = 1 logic = 8 phy = 5 
3: skt = 1 logic = 11 phy = 7 
4: skt = 1 logic = 10 phy = 3 
5: skt = 1 logic = 0 ph
IPU0log=
IPU1log=
HSM0log=
IMU0log=y = 8 
6: skt = 0 logic = 3 phy = 10 
7: skt = 0 logic = 9 phy = 11 
8: skt = 1 logic = 1 phy = 0 
9: skt = 1 logic = 5 phy = 6 
10: skt = 0 logic = 7 phy = 1 
11: skt = 1 logic = 6 phy = 9 
12: skt = 1 logic = 3 phy = 10 
13: s
IPU0log=
IPU1log=
HSM0log=
IMU0log=kt = 1 logic = 7 phy = 1 
14: skt = 1 logic = 9 phy = 11 
15: skt = 0 logic = 4 phy = 2 
16: skt = 0 logic = 10 phy = 3 
17: skt = 0 logic = 8 phy = 5 
18: skt = 0 logic = 6 phy = 9 
19: skt = 0 logic = 11 phy = 7 
20: skt = 1 l
IPU0log=
IPU1log=
HSM0log=
IMU0log=ogic = 2 phy = 4 
21: skt = 1 logic = 4 phy = 2 
22: skt = 0 logic = 2 phy = 4 
23: skt = 0 logic = 1 phy = 0 
get mem silk data length: 72
[0.02.11.214]PCIE INIT DONE.
[IMU][ERR] LOS_SemPend(g_pcieSemaphore, LOS_WAIT_FOREVER)
[
IPU0log=
IPU1log=
HSM0log=
IMU0log=RegisterInterruptSource]:[21] begin
Interrupt 258 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 262 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21
IPU0log=
IPU1log=
HSM0log=
IMU0log=] begin
Interrupt 266 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 270 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 277 regis
IPU0log=
IPU1log=
HSM0log=
IMU0log=ter OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 288 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 292 register OK
[RegisterInterruptSou
IPU0log=
IPU1log=
HSM0log=
IMU0log=rce]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 296 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 300 register OK
[RegisterInterruptSource]:[39] end
[RegisterInte
IPU0log=
IPU1log=
HSM0log=
IMU0log=rruptSource]:[21] begin
Interrupt 307 register OK
[RegisterInterruptSource]:[39] end
pmt Init done

-----------------ROUTE TABLE------------------
entryCount = 1
----------------------------------------------
[No.0]:
eidRan
IPU0log=
IPU1log=
HSM0log=
IMU0log=ge = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2100
----------------------------------------------
[IMU][ERR] [
IMP0log= no log data error!]
------
IPU0log=
IPU1log=
HSM0log=
IMU0log=-----------ROUTE TABLE------------------
entryCount = 2
----------------------------------------------
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, address
IPU0log=
IPU1log=
HSM0log=
IMU0log=Size = 2, bdf = 0x2100
[No.1]:
eidRange = 1, startEid = 10, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2500
----------------------------------------------
--------
IPU0log=
IPU1log=
HSM0log=
IMU0log=---------ROUTE TABLE------------------
entryCount = 2
----------------------------------------------
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSi
IPU0log=
IPU1log=
HSM0log=
IMU0log=ze = 2, bdf = 0x2100
[No.1]:
eidRange = 1, startEid = 10, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2500
----------------------------------------------

IPU0log=
IPU1log=
HSM0log=
IMU0log=1T1N1U skt:0 CfgBusDfxPreConfig finish

********Hello Huawei LiteOS********

IMU Firmware Version : B173V01
LiteOS Kernel Version : 5.10.0
Run on Socket[0] Die[3]
Chip Version: 1
Max socket num: 2
*******************************
IPU0log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 0
cls: 6, core: 7
cpu 933 sram 1010 ddr 983
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  750|  802|  885|  933|
max  v
IPU1log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 1
cls: 6, core: 7
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  759|  821|  909|  961|
max  v: |  750|  750|  753|  781
HSM0log=[1970-01-01 00:01:12.776][HSM][INFO][30] init start
[1970-01-01 00:01:12.776][HSM][INFO][38] init over
[00:01:12.786][info] succeed to do thirdparty dfx_pabuk init
[00:01:12.792][info] os_mem_system_init default pool done
[0
IMU0log=***
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | rail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_vo
IPU0log=: |  750|  750|  754|  775|  836|  922|  980|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:7
IPU1log=|  846|  938|  994|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:750 F:1950
avs-uncore V:750
HSM0log=0:01:12.798][info] addr is already in region
[00:01:12.801][info] succeed to do thirdparty otpc_pabuk init
[1970-01-01 00:01:12.806][HSM][INFO][31] select_region: 0xc11cb55b
[1970-01-01 00:01:12.812][HSM][INFO][67] spi_nor de
IMU0log=lt:1122 mV | pmu:MP2882
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_v
IPU0log=50 F:1950
avs-uncore V:750 F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
av
IPU1log= F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
avs-uncore V:840 F:2450
avs-
HSM0log=vice_id 0xff1a67c8
[1970-01-01 00:01:12.818][HSM][INFO][50] std_cmd readback 0x30220d8
[1970-01-01 00:01:12.824][HSM][INFO][72] saf_cmd 0x0 readback 0x9f5a0604
[1970-01-01 00:01:12.831][HSM][INFO][72] saf_cmd 0x1 readback 0x5
IMU0log=olt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_
IPU0log=s-uncore V:840 F:2450
avs-uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain
IPU1log=uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | r
HSM0log=b7e938
[1970-01-01 00:01:12.837][HSM][INFO][72] saf_cmd 0x2 readback 0x1
[1970-01-01 00:01:12.843][HSM][INFO][72] saf_cmd 0x3 readback 0x0
[1970-01-01 00:01:12.849][HSM][INFO][72] saf_cmd 0x4 readback 0x0
[00:01:12.855][info
IMU0log=volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus r
IPU0log=[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | p
IPU1log=ail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_volt:1122 mV | pmu:MP2882
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[0] volt =  906 mV
pwr domain
HSM0log=] succeed to do thirdparty boot_profile_driver init
[00:01:12.861][info] succeed to do thirdparty crypto_driver init
[00:01:12.866][info] succeed to do thirdparty period_driver init
[00:01:12.872][info]  start loading interna
IMU0log=eady.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait th
IPU0log=mu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pmbus:0x480c0000 ver:0x110
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
IPU1log=[9] volt = 1105 mV
=end=
w&h rd rail:0, 906
w&h rd rail:1, 1103
pwr domain[0] set volt  904 mV succ
pwr domain[9] set volt 1103 mV succ
volt post
pwr domain[0] volt =  904 mV
pwr domain[9] volt = 1103 mV
==end==
Totem[0] Core Bo
HSM0log=l task ...
[00:01:12.877][info]  task name is ccm_task
[00:01:12.881][info]  hm_dynamic_loadelf successfully!
[00:01:12.886][info] internal task[1] task_name=ccm_task load successfully
[00:01:12.892][info]  task name is upgr
IMU0log=e cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master I
IPU0log=
avsbus resync succ
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[2] volt =  904 mV
pwr domain[7] volt =  804 mV
pwr domain[4] volt =  806 mV
pwr domain[1] volt =  806 mV
=end=
w&h rd rail:
IPU1log=ot Vol [1029]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2,
HSM0log=ade_task
[00:01:12.896][info]  hm_dynamic_loadelf successfully!
[00:01:12.901][info] internal task[2] task_name=upgrade_task load successfully
[00:01:12.908][info] created task ccm_task success!
[00:01:12.913][info] created 
IMU0log=mu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
cpu 0 entering scheduler
|--------------------------------------------------|
AtsPrint
|idx|lockCount| srcAddr| destAddr| addrLen|
|--
IPU0log=0, 904
w&h rd rail:1, 802
pwr domain[2] set volt  904 mV succ
pwr domain[7] set volt  802 mV succ
w&h rd rail:0, 804
w&h rd rail:1, 804
pwr domain[4] set volt  802 mV succ
pwr domain[1] set volt  802 mV succ
volt post
pwr domain
IPU1log= ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd8
HSM0log=task upgrade_task success!
[1970-01-01 00:01:12.918][HSM][INFO][54] Platform init 0x20250523 0x4e.
[1970-01-01 00:01:12.924][HSM][INFO][197] ccm start.
[1970-01-01 00:01:12.929][HSM][INFO][86] upgrade task init success.
[197
IMU0log=------------------------------------------------|
|  0|00000000|0x010500000|0x000110800000|0x00100000|
|  1|00000000|0x020000000|0x00001d000000|0x00800000|
|  2|00000000|0x020800000|0x000490000000|0x00100000|
|  3|00000000|0x020
IPU0log=[2] volt =  902 mV
pwr domain[7] volt =  802 mV
pwr domain[4] volt =  804 mV
pwr domain[1] volt =  804 mV
==end==
Totem[0] Core Boot Vol [1015]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0,
IPU1log=00, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
opposite dieId: 0, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 
HSM0log=0-01-01 00:01:12.935][HSM][INFO][95] upgrade recv cmd, 0x181.
[1970-01-01 00:01:12.941][HSM][INFO][103] upgrade res, 0x3a5aa5a3.
.
IMU0log=900000|0x000004000000|0x08000000|
|  4|00000000|0x028900000|0x000440580000|0x01000000|
|  5|00000000|0x029900000|0x000590000000|0x00100000|
|  6|00000000|0x029a00000|0x002000150000|0x00100000|
|  7|00000000|0x000000000|0x0000000
IPU0log= MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 
IPU1log=enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
hiboost task entry
boost wait SEF.
[INFO] mem used of task 'app_Task' is:0x2028, not zero when task being deleted
boost param OK.
Totem[0] Core[ 0] Freq Limit Low
HSM0log=
IMU0log=00000|0x00000000|
|  8|00000000|0x040000000|0x000000000000|0x08000000|
|  9|00000000|0x048000000|0x000000000000|0x08000000|
| 10|00000000|0x050000000|0x000000000000|0x08000000|
| 11|00000000|0x058000000|0x000000000000|0x08000000
IPU0log=0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
tsensor type
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Fr
HSM0log=
IMU0log=|
| 12|00000000|0x060000000|0x000000000000|0x08000000|
| 13|00000000|0x068000000|0x000000000000|0x08000000|
| 14|00000000|0x070000000|0x000000000000|0x08000000|
| 15|00000000|0x078000000|0x000490000000|0x08000000|
|-------------
IPU0log=: 3, ppuFormatK: 0x4da6, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b4,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 3, mask: fffffff8
tsensor type: 4, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=-------------------------------------|
=~=~=~=~=~=~=~=~=~=~= IMU Log @ 2026.4.21 5:31:4 =~=~=~=~=~=~=~=~=~=~=
[IMU] Watchdog Initialization done!
[RegisterInterruptSource]:[21] begin
Interrupt 32 register OK
Interrupt 34 regis
IPU0log=0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 4, mask: ffffffee
tsensor type: 5, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1

IPU1log= Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=ter OK
Interrupt 40 register OK
Interrupt 44 register OK
sram cnt 0x0, id = 43
Interrupt 43 register OK
Interrupt 36 register OK
Interrupt 57 register OK
sram cnt 0x0, id = 42
Interrupt 42 register OK
Interrupt 37 register OK
[R
IPU0log=tsensor: 5, mask: ffffffda
tsensor type: 6, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 6, mask: ffffff80
tsensor type: 7, ppuFormatK: 0x437a,
IPU1log=KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=egisterInterruptSource]:[39] end
IPMB initialization Start...
IPMB clock set done, prer = 0x18.
IPMB Rx FIFO clear empty.
IPMB initialization Done.
starting DFX Collect Task end
PowerTask Entry ...
Wait all vrd init done .
IPU0log= ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 7, mask: fffffffe
opposite dieId: 1, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
CPM max V[900]-
IPU1log= Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low
HSM0log=
IMU0log=..
All vrd init done, power task start
refresh domainId 0 Lsb 0x0
refresh domainId 9 Lsb 0x1
refresh domainId 2 Lsb 0x0
refresh domainId 7 Lsb 0x1
refresh domainId 4 Lsb 0x0
refresh domainId 1 Lsb 0x1
power sensor[0] | calib:512
IPU0log=F:2800
CPM min V[750]-F:1600
freq:2350, idx:9
cpm trim freq: 2600, idx: 4
cpm trim finish
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
recount hours 
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Fr
HSM0log=
IMU0log=0 | rshunt:1 | rshuntDiv:1000 | currLsb:1 | currLsbDiv:1000 | enableFlag:1
                | pwrLsb:25 | defPwr:25000 | minPwr:10000 | maxPwr:65000 | pwrFix:3400
                | manufacturerId: 0x5549 | dieId: 0x2260
power sen
IPU0log=0x78c 
hiboost task entry
boost wait SEF.
boost param OK.
Totem[0] Core[ 0] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[26
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=sor[0] init success
ScmiTaskEntry start.
[RegisterInterruptSource]:[21] begin
Interrupt 51 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 52 register OK
[RegisterInterruptSource]
IPU0log=00000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[12000
IPU1log= Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 53 register OK
[RegisterInterruptSource]:[39] end
[0.01.29.473]starting ras Init
RAS Setup Value get done!
INT_NUM_PER_SKT * HiGetSktNum() = 0x8
index = 0x0
RasIntRegis
IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Lim
IPU1log=KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=ter init 160 
index = 0x1
RasIntRegister init 172 
index = 0x2
RasIntRegister init 162 
index = 0x3
RasIntRegister init 174 
index = 0x4
RasIntRegister init 184 
index = 0x5
RasIntRegister init 196 
index = 0x6
RasIntRegister in
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IPU1log= Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low
HSM0log=
IMU0log=it 186 
index = 0x7
RasIntRegister init 198 
RasIntRegister init 161 
RasIntRegister init 173 
RasIntRegister init 185 
RasIntRegister init 197 
RasIntRegister init 284 
RasIntRegister init 314 
MceTableHeadInit start
starting C
IPU0log=14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
To
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
uncore max freq : 23
HSM0log=
IMU0log=e_Storm Contrl and Ras_Data_Update Task end
[0.01.29.555]starting ras end
[IMU][ERR] skt id 0
Ub init task start Entry ...
UbInitTask Entry ...
[RegisterInterruptSource]:[21] begin
Interrupt 167 register OK
[RegisterInterrupt
IPU0log=tem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[26
IPU1log=50 MHz

HSM0log=
IMU0log=Source]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 191 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 171 register OK
[RegisterInterruptSource]:[39] end
[RegisterI
IPU0log=00000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[12000
IPU1log=
HSM0log=
IMU0log=nterruptSource]:[21] begin
Interrupt 183 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 195 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin

IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Lim
IPU1log=
HSM0log=
IMU0log=Interrupt 207 register OK
[RegisterInterruptSource]:[39] end
Init heart-beat-task end
CS0 flash do not support sfdp!
Current flash device ID[0x61a67c8]!
System supported 1 Flash.
flash cs 0 Manufacture 0xc8, DeviceId 0x1a67, Ad
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IPU1log=
HSM0log=
IMU0log=drMode[0-3B,1-4B] 0x1:
    size 0x4000000, pagesize 0x100
    read  cmd 0x13, dummy byte 0x8
    write cmd 0x12, dummy byte 0x0
    erase4k cmd 0x21, erase64k byte 0xdc
sfc init end
firstUnMskExt0Int
ThermalDimmStart Entry ...

IPU0log=33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
To
IPU1log=
HSM0log=
IMU0log=wait ddr init done...
HacLowPowerStart Entry ...
Hello LiteOS...
Init ReportPcieMmioToBmcTaskEntry end
starting Fpc Isolation Task end
pwr cap[0]: 0, 67
BMC_COLLECTION: bmc req last log!
DDR initing...
pwr cap[1]: f, 27
pwr 
IPU0log=tem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[26
IPU1log=
HSM0log=
IMU0log=cap[2]: 1, 3
BMC_COLLECTION: bmc req last log!
DDR initing...
BMC_COLLECTION: bmc req last log!
DDR initing...
[0.02.00.770]DDR init done
[LOG]head = 0x0, tail = 0x1897, logSize = 0x1897
[IMU][ERR] HsmLogInit!
[IMU][ERR] HsmLog
IPU0log=00000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
uncore max freq : 2350 MHz

IPU1log=
HSM0log=
IMU0log=Init! TRUE
set apei done!
UbConfigData size is 64
UbConfigData 0 : 0
UbConfigData 1 : 0
UbConfigData 2 : 0
UbConfigData 3 : 1
UbConfigData 4 : 31
UbConfigData 5 : 1
UbConfigData 6 : 0
UbConfigData 7 : 32
UbConfigData 8 : 0
UbCon
IPU0log=
IPU1log=
HSM0log=
IMU0log=figData 9 : 1
UbConfigData 10 : 2
UbConfigData 11 : 0
UbConfigData 12 : 0
UbConfigData 13 : 1
UbConfigData 14 : 0
UbConfigData 15 : 0
UbConfigData 16 : 0
UbConfigData 17 : 0
UbConfigData 18 : 0
UbConfigData 19 : 0
UbConfigData 2
IPU0log=
IPU1log=
HSM0log=
IMU0log=0 : 0
UbConfigData 21 : 0
UbConfigData 22 : 11
UbConfigData 23 : 0
UbConfigData 24 : 0
UbConfigData 25 : 0
UbConfigData 26 : 0
UbConfigData 27 : 0
UbConfigData 28 : 0
UbConfigData 29 : 0
UbConfigData 30 : 0
UbConfigData 31 : 0
U
IPU0log=
IPU1log=
HSM0log=
IMU0log=bConfigData 32 : 0
UbConfigData 33 : 0
UbConfigData 34 : 2
UbConfigData 35 : 1
UbConfigData 36 : 0
UbConfigData 37 : 0
UbConfigData 38 : 0
UbConfigData 39 : 0
UbConfigData 40 : 0
UbConfigData 41 : 0
UbConfigData 42 : 0
UbConfigD
IPU0log=
IPU1log=
HSM0log=
IMU0log=ata 43 : 0
UbConfigData 44 : 0
UbConfigData 45 : 0
UbConfigData 46 : 0
UbConfigData 47 : 0
UbConfigData 48 : 0
UbConfigData 49 : 0
UbConfigData 50 : 0
UbConfigData 51 : 0
UbConfigData 52 : 0
UbConfigData 53 : 0
UbConfigData 54 :
IPU0log=
IPU1log=
HSM0log=
IMU0log= 0
UbConfigData 55 : 0
UbConfigData 56 : 0
UbConfigData 57 : 0
UbConfigData 58 : 0
UbConfigData 59 : 0
UbConfigData 60 : 0
UbConfigData 61 : 0
UbConfigData 62 : 0
UbConfigData 63 : 0
UbConfigData 64 : 0
ClusterSwitch: 0, 0
Clust
IPU0log=
IPU1log=
HSM0log=
IMU0log=erMode: 0, 0
ControlMode: 0, 0
EnumMode: 1, 1
BodyMask: 31, 31
CcCtxCount: 256, 256
RcCtxCount: 32, 32
UbMemEntrySize: 128, 0
MctpSupport: 1, 1
SecureMode: 0, 0
PrimaryCna: 0, 0
Upi: 0, 0
EntityId: 0, 0
SlotId: 1, 1
SocketId: 2,
IPU0log=
IPU1log=
HSM0log=
IMU0log= 2
PortIndex: 0, 0
PortCna: 0, 0
CtrlCna: 11, 11
ImpBootFlag: 2, 2
ImuBootFlag: 1, 1
SktId: 0 DieId:2, HCCS_LINK:2 PaId:2
SktId: 1 DieId:2, HCCS_LINK:0 PaId:0
CIS register: ID[0xc00007ff], owner[0x1000003], function[0x1045dc5c].
IPU0log=
IPU1log=
HSM0log=
IMU0log=
CIS register: ID[0xc0000002], owner[0x1000003], function[0x1045dcfc].
odf: can not find od file[config]
Do not get NII route table, disable NII Send function.
UbiosTaskStart Entry ...
UbiosTaskStart create task success
IMU Im
IPU0log=
IPU1log=
HSM0log=
IMU0log=pBootFlag: 0x2
skip IMP start config...
UbiosCisTask Entry ...
ddr init done, start thermal dimm task
======dimm status======
  chl[0] dimm0 1, dimm1 0
  chl[1] dimm0 0, dimm1 0
  chl[2] dimm0 0, dimm1 0
  chl[3] dimm0 0, dimm1
IPU0log=
IPU1log=
HSM0log=
IMU0log= 0
  chl[4] dimm0 0, dimm1 0
  chl[5] dimm0 0, dimm1 0
  chl[6] dimm0 0, dimm1 0
  chl[7] dimm0 0, dimm1 0
  chl[8] dimm0 0, dimm1 0
  chl[9] dimm0 0, dimm1 0
  chl[10] dimm0 0, dimm1 0
  chl[11] dimm0 0, dimm1 0
==========end==
IPU0log=
IPU1log=
HSM0log=
IMU0log=========
sktId[0] chl[0] registered, dimm mask = 0x1
======dimm status======
  chl[0] dimm0 1, dimm1 0
  chl[1] dimm0 0, dimm1 0
  chl[2] dimm0 0, dimm1 0
  chl[3] dimm0 0, dimm1 0
  chl[4] dimm0 0, dimm1 0
  chl[5] dimm0 0, dim
IPU0log=
IPU1log=
HSM0log=
IMU0log=m1 0
  chl[6] dimm0 0, dimm1 0
  chl[7] dimm0 0, dimm1 0
  chl[8] dimm0 0, dimm1 0
  chl[9] dimm0 0, dimm1 0
  chl[10] dimm0 0, dimm1 0
  chl[11] dimm0 0, dimm1 0
==========end==========
sktId[1] chl[0] registered, dimm mask = 0
IPU0log=
IPU1log=
HSM0log=
IMU0log=x1
=====dimm temp params=====
  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
  is_thermal_thro_en  : 1
  is_aref_rate_auto   : 0
===========end============
BMC_COLLECTION: bmc req last log!
[IMU][ERR] [
HSM0l
IPU0log=
IPU1log=
HSM0log=
IMU0log=og= no log data error!]
[0.02.07.732]TF Heartbeat Start
[0.02.08.962]RECEIVE MEM SILK.
0: skt = 0 logic = 5 phy = 6 
1: skt = 0 logic = 0 phy = 8 
2: skt = 1 logic = 8 phy = 5 
3: skt = 1 logic = 11 phy = 7 
4: skt = 1 logic = 1
IPU0log=
IPU1log=
HSM0log=
IMU0log=0 phy = 3 
5: skt = 1 logic = 0 phy = 8 
6: skt = 0 logic = 3 phy = 10 
7: skt = 0 logic = 9 phy = 11 
8: skt = 1 logic = 1 phy = 0 
9: skt = 1 logic = 5 phy = 6 
10: skt = 0 logic = 7 phy = 1 
11: skt = 1 logic = 6 phy = 9 
12:
IPU0log=
IPU1log=
HSM0log=
IMU0log= skt = 1 logic = 3 phy = 10 
13: skt = 1 logic = 7 phy = 1 
14: skt = 1 logic = 9 phy = 11 
15: skt = 0 logic = 4 phy = 2 
16: skt = 0 logic = 10 phy = 3 
17: skt = 0 logic = 8 phy = 5 
18: skt = 0 logic = 6 phy = 9 
19: skt = 0
IPU0log=
IPU1log=
HSM0log=
IMU0log= logic = 11 phy = 7 
20: skt = 1 logic = 2 phy = 4 
21: skt = 1 logic = 4 phy = 2 
22: skt = 0 logic = 2 phy = 4 
23: skt = 0 logic = 1 phy = 0 
get mem silk data length: 72
[0.02.11.928]PCIE INIT DONE.
[IMU][ERR] LOS_SemPend(g_
IPU0log=
IPU1log=
HSM0log=
IMU0log=pcieSemaphore, LOS_WAIT_FOREVER)
[RegisterInterruptSource]:[21] begin
Interrupt 258 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 262 register OK
[RegisterInterruptSource]:[39] 
IPU0log=
IPU1log=
HSM0log=
IMU0log=end
[RegisterInterruptSource]:[21] begin
Interrupt 266 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 270 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSourc
IPU0log=
IPU1log=
HSM0log=
IMU0log=e]:[21] begin
Interrupt 277 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 288 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 292
IPU0log=
IPU1log=
HSM0log=
IMU0log= register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 296 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 300 register OK
[RegisterInterr
IPU0log=
IPU1log=
HSM0log=
IMU0log=uptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 307 register OK
[RegisterInterruptSource]:[39] end
pmt Init done

-----------------ROUTE TABLE------------------
entryCount = 2
-----------------------------
IPU0log=
IPU1log=
HSM0log=
IMU0log=-----------------
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2500
[No.1]:
eidRange = 1, startEid = 10, port = 0, isStatic = 1, 
IPU0log=
IPU1log=
HSM0log=
IMU0log=entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2100
----------------------------------------------
-----------------ROUTE TABLE------------------
entryCount = 2
-------------------------------
IPU0log=
IPU1log=
HSM0log=
IMU0log=---------------
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2500
[No.1]:
eidRange = 1, startEid = 10, port = 0, isStatic = 1, en
IPU0log=
IPU1log=
HSM0log=
IMU0log=tryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2100
----------------------------------------------
-----------------ROUTE TABLE------------------
entryCount = 2
---------------------------------
IPU0log=
IPU1log=
HSM0log=
IMU0log=-------------
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2500
[No.1]:
eidRange = 1, startEid = 10, port = 0, isStatic = 1, entr
IPU0log=
IPU1log=
HSM0log=
IMU0log=yType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2100
----------------------------------------------

IPU0log=
IPU1log=
HSM0log=
IMU0log=1T1N1U skt:0 CfgBusDfxPreConfig finish

********Hello Huawei LiteOS********

IMU Firmware Version : B173V01
LiteOS Kernel Version : 5.10.0
Run on Socket[0] Die[3]
Chip Version: 1
Max socket num: 2
*******************************
IPU0log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 0
cls: 6, core: 7
cpu 933 sram 1010 ddr 983
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  750|  802|  885|  933|
max  v
IPU1log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 1
cls: 6, core: 7
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  759|  821|  909|  961|
max  v: |  750|  750|  753|  781
HSM0log=[1970-01-01 00:01:13.315][HSM][INFO][30] init start
[1970-01-01 00:01:13.315][HSM][INFO][38] init over
[00:01:13.325][info] succeed to do thirdparty dfx_pabuk init
[00:01:13.331][info] os_mem_system_init default pool done
[0
IMU0log=***
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | rail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_vo
IPU0log=: |  750|  750|  754|  775|  836|  922|  980|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:7
IPU1log=|  846|  938|  994|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:750 F:1950
avs-uncore V:750
HSM0log=0:01:13.337][info] addr is already in region
[00:01:13.340][info] succeed to do thirdparty otpc_pabuk init
[1970-01-01 00:01:13.345][HSM][INFO][31] select_region: 0xc11cb55b
[1970-01-01 00:01:13.351][HSM][INFO][67] spi_nor de
IMU0log=lt:1122 mV | pmu:MP2882
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_v
IPU0log=50 F:1950
avs-uncore V:750 F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
av
IPU1log= F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
avs-uncore V:840 F:2450
avs-
HSM0log=vice_id 0xff1a67c8
[1970-01-01 00:01:13.357][HSM][INFO][50] std_cmd readback 0x30220d8
[1970-01-01 00:01:13.363][HSM][INFO][72] saf_cmd 0x0 readback 0x9f5a0604
[1970-01-01 00:01:13.370][HSM][INFO][72] saf_cmd 0x1 readback 0x5
IMU0log=olt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_
IPU0log=s-uncore V:840 F:2450
avs-uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain
IPU1log=uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | r
HSM0log=b7e938
[1970-01-01 00:01:13.376][HSM][INFO][72] saf_cmd 0x2 readback 0x1
[1970-01-01 00:01:13.382][HSM][INFO][72] saf_cmd 0x3 readback 0x0
[1970-01-01 00:01:13.388][HSM][INFO][72] saf_cmd 0x4 readback 0x0
[00:01:13.394][info
IMU0log=volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus r
IPU0log=[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | p
IPU1log=ail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_volt:1122 mV | pmu:MP2882
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[0] volt =  908 mV
pwr domain
HSM0log=] succeed to do thirdparty boot_profile_driver init
[00:01:13.400][info] succeed to do thirdparty crypto_driver init
[00:01:13.405][info] succeed to do thirdparty period_driver init
[00:01:13.411][info]  start loading interna
IMU0log=eady.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait th
IPU0log=mu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pmbus:0x480c0000 ver:0x110
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
IPU1log=[9] volt = 1103 mV
=end=
w&h rd rail:0, 906
w&h rd rail:1, 1103
pwr domain[0] set volt  904 mV succ
pwr domain[9] set volt 1103 mV succ
volt post
pwr domain[0] volt =  904 mV
pwr domain[9] volt = 1103 mV
==end==
Totem[0] Core Bo
HSM0log=l task ...
[00:01:13.416][info]  task name is ccm_task
[00:01:13.420][info]  hm_dynamic_loadelf successfully!
[00:01:13.425][info] internal task[1] task_name=ccm_task load successfully
[00:01:13.431][info]  task name is upgr
IMU0log=e cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master I
IPU0log=
avsbus resync succ
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[2] volt =  904 mV
pwr domain[7] volt =  804 mV
pwr domain[4] volt =  806 mV
pwr domain[1] volt =  804 mV
=end=
w&h rd rail:
IPU1log=ot Vol [1029]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2,
HSM0log=ade_task
[00:01:13.436][info]  hm_dynamic_loadelf successfully!
[00:01:13.440][info] internal task[2] task_name=upgrade_task load successfully
[00:01:13.447][info] created task ccm_task success!
[00:01:13.452][info] created 
IMU0log=mu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
cpu 0 entering scheduler
|--------------------------------------------------|
AtsPrint
|idx|lockCount| srcAddr| destAddr| addrLen|
|--
IPU0log=0, 906
w&h rd rail:1, 804
pwr domain[2] set volt  902 mV succ
pwr domain[7] set volt  802 mV succ
w&h rd rail:0, 804
w&h rd rail:1, 804
pwr domain[4] set volt  802 mV succ
pwr domain[1] set volt  804 mV succ
volt post
pwr domain
IPU1log= ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd8
HSM0log=task upgrade_task success!
[1970-01-01 00:01:13.457][HSM][INFO][54] Platform init 0x20250523 0x4e.
[1970-01-01 00:01:13.463][HSM][INFO][197] ccm start.
[1970-01-01 00:01:13.468][HSM][INFO][86] upgrade task init success.
[197
IMU0log=------------------------------------------------|
|  0|00000000|0x010500000|0x000110800000|0x00100000|
|  1|00000000|0x020000000|0x00001d000000|0x00800000|
|  2|00000000|0x020800000|0x000490000000|0x00100000|
|  3|00000000|0x020
IPU0log=[2] volt =  904 mV
pwr domain[7] volt =  802 mV
pwr domain[4] volt =  802 mV
pwr domain[1] volt =  802 mV
==end==
Totem[0] Core Boot Vol [1015]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0,
IPU1log=00, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
opposite dieId: 0, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 
HSM0log=0-01-01 00:01:13.474][HSM][INFO][95] upgrade recv cmd, 0x181.
[1970-01-01 00:01:13.480][HSM][INFO][103] upgrade res, 0x3a5aa5a3.
.
IMU0log=900000|0x000004000000|0x08000000|
|  4|00000000|0x028900000|0x000440580000|0x01000000|
|  5|00000000|0x029900000|0x000590000000|0x00100000|
|  6|00000000|0x029a00000|0x002000150000|0x00100000|
|  7|00000000|0x000000000|0x0000000
IPU0log= MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 
IPU1log=enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
hiboost task entry
boost wait SEF.
[INFO] mem used of task 'app_Task' is:0x2028, not zero when task being deleted
boost param OK.
Totem[0] Core[ 0] Freq Limit Low
HSM0log=
IMU0log=00000|0x00000000|
|  8|00000000|0x040000000|0x000000000000|0x08000000|
|  9|00000000|0x048000000|0x000000000000|0x08000000|
| 10|00000000|0x050000000|0x000000000000|0x08000000|
| 11|00000000|0x058000000|0x000000000000|0x08000000
IPU0log=0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
tsensor type
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Fr
HSM0log=
IMU0log=|
| 12|00000000|0x060000000|0x000000000000|0x08000000|
| 13|00000000|0x068000000|0x000000000000|0x08000000|
| 14|00000000|0x070000000|0x000000000000|0x08000000|
| 15|00000000|0x078000000|0x000490000000|0x08000000|
|-------------
IPU0log=: 3, ppuFormatK: 0x4da6, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b4,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 3, mask: fffffff8
tsensor type: 4, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=-------------------------------------|
=~=~=~=~=~=~=~=~=~=~= IMU Log @ 2026.4.22 3:16:15 =~=~=~=~=~=~=~=~=~=~=
[IMU] Watchdog Initialization done!
[RegisterInterruptSource]:[21] begin
Interrupt 32 register OK
Interrupt 34 regi
IPU0log=0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 4, mask: ffffffee
tsensor type: 5, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1

IPU1log= Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=ster OK
Interrupt 40 register OK
Interrupt 44 register OK
sram cnt 0x0, id = 43
Interrupt 43 register OK
Interrupt 36 register OK
Interrupt 57 register OK
sram cnt 0x0, id = 42
Interrupt 42 register OK
Interrupt 37 register OK
[
IPU0log=tsensor: 5, mask: ffffffda
tsensor type: 6, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 6, mask: ffffff80
tsensor type: 7, ppuFormatK: 0x437a,
IPU1log=KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=RegisterInterruptSource]:[39] end
IPMB initialization Start...
IPMB clock set done, prer = 0x18.
IPMB Rx FIFO clear empty.
IPMB initialization Done.
starting DFX Collect Task end
PowerTask Entry ...
Wait all vrd init done 
IPU0log= ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 7, mask: fffffffe
opposite dieId: 1, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
CPM max V[900]-
IPU1log= Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low
HSM0log=
IMU0log=...
All vrd init done, power task start
refresh domainId 0 Lsb 0x0
refresh domainId 9 Lsb 0x1
refresh domainId 2 Lsb 0x0
refresh domainId 7 Lsb 0x1
refresh domainId 4 Lsb 0x0
refresh domainId 1 Lsb 0x1
power sensor[0] | calib:51
IPU0log=F:2800
CPM min V[750]-F:1600
freq:2350, idx:9
cpm trim freq: 2600, idx: 4
cpm trim finish
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
recount hours 
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Fr
HSM0log=
IMU0log=20 | rshunt:1 | rshuntDiv:1000 | currLsb:1 | currLsbDiv:1000 | enableFlag:1
                | pwrLsb:25 | defPwr:25000 | minPwr:10000 | maxPwr:65000 | pwrFix:3400
                | manufacturerId: 0x5549 | dieId: 0x2260
power se
IPU0log=0x798 
hiboost task entry
boost wait SEF.
boost param OK.
Totem[0] Core[ 0] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[26
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=nsor[0] init success
ScmiTaskEntry start.
[RegisterInterruptSource]:[21] begin
Interrupt 51 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 52 register OK
[RegisterInterruptSource
IPU0log=00000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[12000
IPU1log= Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 53 register OK
[RegisterInterruptSource]:[39] end
[0.01.30.016]starting ras Init
RAS Setup Value get done!
INT_NUM_PER_SKT * HiGetSktNum() = 0x8
index = 0x0
RasIntRegi
IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Lim
IPU1log=KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=ster init 160 
index = 0x1
RasIntRegister init 172 
index = 0x2
RasIntRegister init 162 
index = 0x3
RasIntRegister init 174 
index = 0x4
RasIntRegister init 184 
index = 0x5
RasIntRegister init 196 
index = 0x6
RasIntRegister i
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IPU1log= Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low
HSM0log=
IMU0log=nit 186 
index = 0x7
RasIntRegister init 198 
RasIntRegister init 161 
RasIntRegister init 173 
RasIntRegister init 185 
RasIntRegister init 197 
RasIntRegister init 284 
RasIntRegister init 314 
MceTableHeadInit start
starting 
IPU0log=14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
To
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
uncore max freq : 23
HSM0log=
IMU0log=Ce_Storm Contrl and Ras_Data_Update Task end
[0.01.30.098]starting ras end
[IMU][ERR] skt id 0
Ub init task start Entry ...
UbInitTask Entry ...
[RegisterInterruptSource]:[21] begin
Interrupt 167 register OK
[RegisterInterrup
IPU0log=tem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[26
IPU1log=50 MHz

HSM0log=
IMU0log=tSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 191 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 171 register OK
[RegisterInterruptSource]:[39] end
[Register
IPU0log=00000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[12000
IPU1log=
HSM0log=
IMU0log=InterruptSource]:[21] begin
Interrupt 183 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 195 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Lim
IPU1log=
HSM0log=
IMU0log=
Interrupt 207 register OK
[RegisterInterruptSource]:[39] end
Init heart-beat-task end
CS0 flash do not support sfdp!
Current flash device ID[0x61a67c8]!
System supported 1 Flash.
flash cs 0 Manufacture 0xc8, DeviceId 0x1a67, A
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IPU1log=
HSM0log=
IMU0log=ddrMode[0-3B,1-4B] 0x1:
    size 0x4000000, pagesize 0x100
    read  cmd 0x13, dummy byte 0x8
    write cmd 0x12, dummy byte 0x0
    erase4k cmd 0x21, erase64k byte 0xdc
sfc init end
BMC_COLLECTION: bmc req last log!
firstUnMskE
IPU0log=33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
To
IPU1log=
HSM0log=
IMU0log=xt0Int
DDR initing...
ThermalDimmStart Entry ...
wait ddr init done...
HacLowPowerStart Entry ...
Hello LiteOS...
Init ReportPcieMmioToBmcTaskEntry end
starting Fpc Isolation Task end
pwr cap[0]: 0, 67
pwr cap[1]: f, 27
pwr
IPU0log=tem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[26
IPU1log=
HSM0log=
IMU0log= cap[2]: 1, 3
BMC_COLLECTION: bmc req last log!
DDR initing...
BMC_COLLECTION: bmc req last log!
DDR initing...
[0.02.01.312]DDR init done
[LOG]head = 0x0, tail = 0x1898, logSize = 0x1898
[IMU][ERR] HsmLogInit!
[IMU][ERR] HsmLo
IPU0log=00000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
uncore max freq : 2350 MHz

IPU1log=
HSM0log=
IMU0log=gInit! TRUE
set apei done!
UbConfigData size is 64
UbConfigData 0 : 0
UbConfigData 1 : 0
UbConfigData 2 : 0
UbConfigData 3 : 1
UbConfigData 4 : 31
UbConfigData 5 : 1
UbConfigData 6 : 0
UbConfigData 7 : 32
UbConfigData 8 : 0
UbCo
IPU0log=
IPU1log=
HSM0log=
IMU0log=nfigData 9 : 1
UbConfigData 10 : 2
UbConfigData 11 : 0
UbConfigData 12 : 0
UbConfigData 13 : 1
UbConfigData 14 : 0
UbConfigData 15 : 0
UbConfigData 16 : 0
UbConfigData 17 : 0
UbConfigData 18 : 0
UbConfigData 19 : 0
UbConfigData 
IPU0log=
IPU1log=
HSM0log=
IMU0log=20 : 0
UbConfigData 21 : 0
UbConfigData 22 : 11
UbConfigData 23 : 0
UbConfigData 24 : 0
UbConfigData 25 : 0
UbConfigData 26 : 0
UbConfigData 27 : 0
UbConfigData 28 : 0
UbConfigData 29 : 0
UbConfigData 30 : 0
UbConfigData 31 : 0

IPU0log=
IPU1log=
HSM0log=
IMU0log=UbConfigData 32 : 0
UbConfigData 33 : 0
UbConfigData 34 : 2
UbConfigData 35 : 1
UbConfigData 36 : 0
UbConfigData 37 : 0
UbConfigData 38 : 0
UbConfigData 39 : 0
UbConfigData 40 : 0
UbConfigData 41 : 0
UbConfigData 42 : 0
UbConfig
IPU0log=
IPU1log=
HSM0log=
IMU0log=Data 43 : 0
UbConfigData 44 : 0
UbConfigData 45 : 0
UbConfigData 46 : 0
UbConfigData 47 : 0
UbConfigData 48 : 0
UbConfigData 49 : 0
UbConfigData 50 : 0
UbConfigData 51 : 0
UbConfigData 52 : 0
UbConfigData 53 : 0
UbConfigData 54 
IPU0log=
IPU1log=
HSM0log=
IMU0log=: 0
UbConfigData 55 : 0
UbConfigData 56 : 0
UbConfigData 57 : 0
UbConfigData 58 : 0
UbConfigData 59 : 0
UbConfigData 60 : 0
UbConfigData 61 : 0
UbConfigData 62 : 0
UbConfigData 63 : 0
UbConfigData 64 : 0
ClusterSwitch: 0, 0
Clus
IPU0log=
IPU1log=
HSM0log=
IMU0log=terMode: 0, 0
ControlMode: 0, 0
EnumMode: 1, 1
BodyMask: 31, 31
CcCtxCount: 256, 256
RcCtxCount: 32, 32
UbMemEntrySize: 128, 0
MctpSupport: 1, 1
SecureMode: 0, 0
PrimaryCna: 0, 0
Upi: 0, 0
EntityId: 0, 0
SlotId: 1, 1
SocketId: 2
IPU0log=
IPU1log=
HSM0log=
IMU0log=, 2
PortIndex: 0, 0
PortCna: 0, 0
CtrlCna: 11, 11
ImpBootFlag: 2, 2
ImuBootFlag: 1, 1
SktId: 0 DieId:2, HCCS_LINK:2 PaId:2
SktId: 1 DieId:2, HCCS_LINK:0 PaId:0
CIS register: ID[0xc00007ff], owner[0x1000003], function[0x1045dc5c]
IPU0log=
IPU1log=
HSM0log=
IMU0log=.
CIS register: ID[0xc0000002], owner[0x1000003], function[0x1045dcfc].
odf: can not find od file[config]
Do not get NII route table, disable NII Send function.
UbiosTaskStart Entry ...
UbiosTaskStart create task success
IMU I
IPU0log=
IPU1log=
HSM0log=
IMU0log=mpBootFlag: 0x2
skip IMP start config...
UbiosCisTask Entry ...
ddr init done, start thermal dimm task
======dimm status======
  chl[0] dimm0 1, dimm1 0
  chl[1] dimm0 0, dimm1 0
  chl[2] dimm0 0, dimm1 0
  chl[3] dimm0 0, dimm
IPU0log=
IPU1log=
HSM0log=
IMU0log=1 0
  chl[4] dimm0 0, dimm1 0
  chl[5] dimm0 0, dimm1 0
  chl[6] dimm0 0, dimm1 0
  chl[7] dimm0 0, dimm1 0
  chl[8] dimm0 0, dimm1 0
  chl[9] dimm0 0, dimm1 0
  chl[10] dimm0 0, dimm1 0
  chl[11] dimm0 0, dimm1 0
==========end=
IPU0log=
IPU1log=
HSM0log=
IMU0log==========
sktId[0] chl[0] registered, dimm mask = 0x1
======dimm status======
  chl[0] dimm0 1, dimm1 0
  chl[1] dimm0 0, dimm1 0
  chl[2] dimm0 0, dimm1 0
  chl[3] dimm0 0, dimm1 0
  chl[4] dimm0 0, dimm1 0
  chl[5] dimm0 0, di
IPU0log=
IPU1log=
HSM0log=
IMU0log=mm1 0
  chl[6] dimm0 0, dimm1 0
  chl[7] dimm0 0, dimm1 0
  chl[8] dimm0 0, dimm1 0
  chl[9] dimm0 0, dimm1 0
  chl[10] dimm0 0, dimm1 0
  chl[11] dimm0 0, dimm1 0
==========end==========
sktId[1] chl[0] registered, dimm mask = 
IPU0log=
IPU1log=
HSM0log=
IMU0log=0x1
=====dimm temp params=====
  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
  is_thermal_thro_en  : 1
  is_aref_rate_auto   : 0
===========end============
BMC_COLLECTION: bmc req last log!
[IMU][ERR] [
HSM0
IPU0log=
IPU1log=
HSM0log=
IMU0log=log= no log data error!]
[0.02.08.246]TF Heartbeat Start
[0.02.09.506]RECEIVE MEM SILK.
0: skt = 1 logic = 9 phy = 11 
1: skt = 0 logic = 3 phy = 10 
2: skt = 0 logic = 9 phy = 11 
3: skt = 1 logic = 1 phy = 0 
4: skt = 0 logic 
IPU0log=
IPU1log=
HSM0log=
IMU0log== 7 phy = 1 
5: skt = 1 logic = 7 phy = 1 
6: skt = 1 logic = 4 phy = 2 
7: skt = 1 logic = 10 phy = 3 
8: skt = 1 logic = 2 phy = 4 
9: skt = 0 logic = 4 phy = 2 
10: skt = 0 logic = 10 phy = 3 
11: skt = 0 logic = 8 phy = 5 
1
IPU0log=
IPU1log=
HSM0log=
IMU0log=2: skt = 1 logic = 5 phy = 6 
13: skt = 1 logic = 3 phy = 10 
14: skt = 1 logic = 0 phy = 8 
15: skt = 1 logic = 11 phy = 7 
16: skt = 0 logic = 1 phy = 0 
17: skt = 0 logic = 5 phy = 6 
18: skt = 1 logic = 8 phy = 5 
19: skt = 
IPU0log=
IPU1log=
HSM0log=
IMU0log=0 logic = 11 phy = 7 
20: skt = 0 logic = 0 phy = 8 
21: skt = 0 logic = 6 phy = 9 
22: skt = 0 logic = 2 phy = 4 
23: skt = 1 logic = 6 phy = 9 
get mem silk data length: 72
[0.02.12.472]PCIE INIT DONE.
[IMU][ERR] LOS_SemPend(g
IPU0log=
IPU1log=
HSM0log=
IMU0log=_pcieSemaphore, LOS_WAIT_FOREVER)
[RegisterInterruptSource]:[21] begin
Interrupt 258 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 262 register OK
[RegisterInterruptSource]:[39]
IPU0log=
IPU1log=
HSM0log=
IMU0log= end
[RegisterInterruptSource]:[21] begin
Interrupt 266 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 270 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSour
IPU0log=
IPU1log=
HSM0log=
IMU0log=ce]:[21] begin
Interrupt 277 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 288 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 29
IPU0log=
IPU1log=
HSM0log=
IMU0log=2 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 296 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 300 register OK
[RegisterInter
IPU0log=
IPU1log=
HSM0log=
IMU0log=ruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 307 register OK
[RegisterInterruptSource]:[39] end
pmt Init done

-----------------ROUTE TABLE------------------
entryCount = 1
----------------------------
IPU0log=
IPU1log=
HSM0log=
IMU0log=------------------
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2100
----------------------------------------------
-------------
IPU0log=
IPU1log=
HSM0log=
IMU0log=----ROUTE TABLE------------------
entryCount = 2
----------------------------------------------
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 
IPU0log=
IPU1log=
HSM0log=
IMU0log=2, bdf = 0x2100
[No.1]:
eidRange = 1, startEid = 10, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2500
----------------------------------------------
---------------
IPU0log=
IPU1log=
HSM0log=
IMU0log=--ROUTE TABLE------------------
entryCount = 2
----------------------------------------------
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2,
IPU0log=
IPU1log=
HSM0log=
IMU0log= bdf = 0x2100
[No.1]:
eidRange = 1, startEid = 10, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2500
----------------------------------------------

IPU0log=
IPU1log=
HSM0log=
IMU0log=1T1N1U skt:0 CfgBusDfxPreConfig finish

********Hello Huawei LiteOS********

IMU Firmware Version : B173V01
LiteOS Kernel Version : 5.10.0
Run on Socket[0] Die[3]
Chip Version: 1
Max socket num: 2
*******************************
IPU0log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 0
cls: 6, core: 7
cpu 933 sram 1010 ddr 983
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  750|  802|  885|  933|
max  v
IPU1log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 1
cls: 6, core: 7
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  759|  821|  909|  961|
max  v: |  750|  750|  753|  781
IMU0log=***
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | rail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_vo
IPU0log=: |  750|  750|  754|  775|  836|  922|  980|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:7
IPU1log=|  846|  938|  994|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:750 F:1950
avs-uncore V:750
HSM0log=[1970-01-01 00:01:12.121][HSM][INFO][30] init start
[1970-01-01 00:01:12.122][HSM][INFO][38] init over
[00:01:12.131][info] succeed to do thirdparty dfx_pabuk init
[00:01:12.137][info] os_mem_system_init default pool done
[0
IMU0log=lt:1122 mV | pmu:MP2882
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_v
IPU0log=50 F:1950
avs-uncore V:750 F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
av
IPU1log= F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
avs-uncore V:840 F:2450
avs-
HSM0log=0:01:12.143][info] addr is already in region
[00:01:12.146][info] succeed to do thirdparty otpc_pabuk init
[1970-01-01 00:01:12.151][HSM][INFO][31] select_region: 0xc11cb55b
[1970-01-01 00:01:12.157][HSM][INFO][67] spi_nor de
IMU0log=olt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_
IPU0log=s-uncore V:840 F:2450
avs-uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain
IPU1log=uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | r
HSM0log=vice_id 0xff1a67c8
[1970-01-01 00:01:12.164][HSM][INFO][50] std_cmd readback 0x30220d8
[1970-01-01 00:01:12.169][HSM][INFO][72] saf_cmd 0x0 readback 0x9f5a0604
[1970-01-01 00:01:12.176][HSM][INFO][72] saf_cmd 0x1 readback 0x5
IMU0log=volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus r
IPU0log=[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | p
IPU1log=ail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_volt:1122 mV | pmu:MP2882
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[0] volt =  906 mV
pwr domain
HSM0log=b7e938
[1970-01-01 00:01:12.182][HSM][INFO][72] saf_cmd 0x2 readback 0x1
[1970-01-01 00:01:12.188][HSM][INFO][72] saf_cmd 0x3 readback 0x0
[1970-01-01 00:01:12.194][HSM][INFO][72] saf_cmd 0x4 readback 0x0
[00:01:12.200][info
IMU0log=eady.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait th
IPU0log=mu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pmbus:0x480c0000 ver:0x110
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
IPU1log=[9] volt = 1103 mV
=end=
w&h rd rail:0, 906
w&h rd rail:1, 1103
pwr domain[0] set volt  904 mV succ
pwr domain[9] set volt 1103 mV succ
volt post
pwr domain[0] volt =  904 mV
pwr domain[9] volt = 1101 mV
==end==
Totem[0] Core Bo
HSM0log=] succeed to do thirdparty boot_profile_driver init
[00:01:12.206][info] succeed to do thirdparty crypto_driver init
[00:01:12.212][info] succeed to do thirdparty period_driver init
[00:01:12.217][info]  start loading interna
IMU0log=e cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master I
IPU0log=
avsbus resync succ
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[2] volt =  904 mV
pwr domain[7] volt =  804 mV
pwr domain[4] volt =  806 mV
pwr domain[1] volt =  804 mV
=end=
w&h rd rail:
IPU1log=ot Vol [1029]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2,
HSM0log=l task ...
[00:01:12.222][info]  task name is ccm_task
[00:01:12.226][info]  hm_dynamic_loadelf successfully!
[00:01:12.231][info] internal task[1] task_name=ccm_task load successfully
[00:01:12.238][info]  task name is upgr
IMU0log=mu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
cpu 0 entering scheduler
|--------------------------------------------------|
AtsPrint
|idx|lockCount| srcAddr| destAddr| addrLen|
|--
IPU0log=0, 904
w&h rd rail:1, 802
pwr domain[2] set volt  902 mV succ
pwr domain[7] set volt  802 mV succ
w&h rd rail:0, 806
w&h rd rail:1, 804
pwr domain[4] set volt  804 mV succ
pwr domain[1] set volt  802 mV succ
volt post
pwr domain
IPU1log= ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd8
HSM0log=ade_task
[00:01:12.242][info]  hm_dynamic_loadelf successfully!
[00:01:12.247][info] internal task[2] task_name=upgrade_task load successfully
[00:01:12.254][info] created task ccm_task success!
[00:01:12.258][info] created 
IMU0log=------------------------------------------------|
|  0|00000000|0x010500000|0x000110800000|0x00100000|
|  1|00000000|0x020000000|0x00001d000000|0x00800000|
|  2|00000000|0x020800000|0x000490000000|0x00100000|
|  3|00000000|0x020
IPU0log=[2] volt =  902 mV
pwr domain[7] volt =  800 mV
pwr domain[4] volt =  804 mV
pwr domain[1] volt =  802 mV
==end==
Totem[0] Core Boot Vol [1015]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0,
IPU1log=00, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
opposite dieId: 0, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 
HSM0log=task upgrade_task success!
[1970-01-01 00:01:12.263][HSM][INFO][54] Platform init 0x20250523 0x4e.
[1970-01-01 00:01:12.270][HSM][INFO][197] ccm start.
[1970-01-01 00:01:12.274][HSM][INFO][86] upgrade task init success.
[197
IMU0log=900000|0x000004000000|0x08000000|
|  4|00000000|0x028900000|0x000440580000|0x01000000|
|  5|00000000|0x029900000|0x000590000000|0x00100000|
|  6|00000000|0x029a00000|0x002000150000|0x00100000|
|  7|00000000|0x000000000|0x0000000
IPU0log= MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 
IPU1log=enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
hiboost task entry
boost wait SEF.
[INFO] mem used of task 'app_Task' is:0x2028, not zero when task being deleted
boost param OK.
Totem[0] Core[ 0] Freq Limit Low
HSM0log=0-01-01 00:01:12.280][HSM][INFO][95] upgrade recv cmd, 0x181.
[1970-01-01 00:01:12.286][HSM][INFO][103] upgrade res, 0x3a5aa5a3.
.
IMU0log=00000|0x00000000|
|  8|00000000|0x040000000|0x000000000000|0x08000000|
|  9|00000000|0x048000000|0x000000000000|0x08000000|
| 10|00000000|0x050000000|0x000000000000|0x08000000|
| 11|00000000|0x058000000|0x000000000000|0x08000000
IPU0log=0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
tsensor type
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Fr
HSM0log=
IMU0log=|
| 12|00000000|0x060000000|0x000000000000|0x08000000|
| 13|00000000|0x068000000|0x000000000000|0x08000000|
| 14|00000000|0x070000000|0x000000000000|0x08000000|
| 15|00000000|0x078000000|0x000490000000|0x08000000|
|-------------
IPU0log=: 3, ppuFormatK: 0x4da6, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b4,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 3, mask: fffffff8
tsensor type: 4, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=-------------------------------------|
=~=~=~=~=~=~=~=~=~=~= IMU Log @ 2026.5.8 22:2:57 =~=~=~=~=~=~=~=~=~=~=
[IMU] Watchdog Initialization done!
[RegisterInterruptSource]:[21] begin
Interrupt 32 register OK
Interrupt 34 regis
IPU0log=0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 4, mask: ffffffee
tsensor type: 5, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1

IPU1log= Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=ter OK
Interrupt 40 register OK
Interrupt 44 register OK
sram cnt 0x0, id = 43
Interrupt 43 register OK
Interrupt 36 register OK
Interrupt 57 register OK
sram cnt 0x0, id = 42
Interrupt 42 register OK
Interrupt 37 register OK
[R
IPU0log=tsensor: 5, mask: ffffffda
tsensor type: 6, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 6, mask: ffffff80
tsensor type: 7, ppuFormatK: 0x437a,
IPU1log=KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=egisterInterruptSource]:[39] end
IPMB initialization Start...
IPMB clock set done, prer = 0x18.
IPMB Rx FIFO clear empty.
IPMB initialization Done.
starting DFX Collect Task end
PowerTask Entry ...
Wait all vrd init done .
IPU0log= ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 7, mask: fffffffe
opposite dieId: 1, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
CPM max V[900]-
IPU1log= Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low
HSM0log=
IMU0log=..
All vrd init done, power task start
refresh domainId 0 Lsb 0x0
refresh domainId 9 Lsb 0x1
refresh domainId 2 Lsb 0x0
refresh domainId 7 Lsb 0x1
refresh domainId 4 Lsb 0x0
refresh domainId 1 Lsb 0x1
power sensor[0] | calib:512
IPU0log=F:2800
CPM min V[750]-F:1600
freq:2350, idx:9
cpm trim freq: 2600, idx: 4
cpm trim finish
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
recount hours 
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Fr
HSM0log=
IMU0log=0 | rshunt:1 | rshuntDiv:1000 | currLsb:1 | currLsbDiv:1000 | enableFlag:1
                | pwrLsb:25 | defPwr:25000 | minPwr:10000 | maxPwr:65000 | pwrFix:3400
                | manufacturerId: 0x5549 | dieId: 0x2260
power sen
IPU0log=0x924 
hiboost task entry
boost wait SEF.
boost param OK.
Totem[0] Core[ 0] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[26
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=sor[0] init success
ScmiTaskEntry start.
[RegisterInterruptSource]:[21] begin
Interrupt 51 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 52 register OK
[RegisterInterruptSource]
IPU0log=00000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[12000
IPU1log= Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 53 register OK
[RegisterInterruptSource]:[39] end
[0.01.28.840]starting ras Init
RAS Setup Value get done!
INT_NUM_PER_SKT * HiGetSktNum() = 0x8
index = 0x0
RasIntRegis
IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Lim
IPU1log=KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=ter init 160 
index = 0x1
RasIntRegister init 172 
index = 0x2
RasIntRegister init 162 
index = 0x3
RasIntRegister init 174 
index = 0x4
RasIntRegister init 184 
index = 0x5
RasIntRegister init 196 
index = 0x6
RasIntRegister in
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IPU1log= Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low
HSM0log=
IMU0log=it 186 
index = 0x7
RasIntRegister init 198 
RasIntRegister init 161 
RasIntRegister init 173 
RasIntRegister init 185 
RasIntRegister init 197 
RasIntRegister init 284 
RasIntRegister init 314 
MceTableHeadInit start
starting C
IPU0log=14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
To
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
uncore max freq : 23
HSM0log=
IMU0log=e_Storm Contrl and Ras_Data_Update Task end
[0.01.28.922]starting ras end
[IMU][ERR] skt id 0
Ub init task start Entry ...
UbInitTask Entry ...
[RegisterInterruptSource]:[21] begin
Interrupt 167 register OK
[RegisterInterrupt
IPU0log=tem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[26
IPU1log=50 MHz

HSM0log=
IMU0log=Source]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 191 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 171 register OK
[RegisterInterruptSource]:[39] end
[RegisterI
IPU0log=00000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[12000
IPU1log=
HSM0log=
IMU0log=nterruptSource]:[21] begin
Interrupt 183 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 195 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin

IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Lim
IPU1log=
HSM0log=
IMU0log=Interrupt 207 register OK
[RegisterInterruptSource]:[39] end
Init heart-beat-task end
CS0 flash do not support sfdp!
Current flash device ID[0x61a67c8]!
System supported 1 Flash.
flash cs 0 Manufacture 0xc8, DeviceId 0x1a67, Ad
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IPU1log=
HSM0log=
IMU0log=drMode[0-3B,1-4B] 0x1:
    size 0x4000000, pagesize 0x100
    read  cmd 0x13, dummy byte 0x8
    write cmd 0x12, dummy byte 0x0
    erase4k cmd 0x21, erase64k byte 0xdc
sfc init end
firstUnMskExt0Int
ThermalDimmStart Entry ...

IPU0log=33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
To
IPU1log=
HSM0log=
IMU0log=wait ddr init done...
HacLowPowerStart Entry ...
Hello LiteOS...
Init ReportPcieMmioToBmcTaskEntry end
starting Fpc Isolation Task end
pwr cap[0]: 0, 67
pwr cap[1]: f, 27
pwr cap[2]: 1, 3
DDR initing...
BMC_COLLECTION: bmc 
IPU0log=tem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[26
IPU1log=
HSM0log=
IMU0log=req last log!
DDR initing...
[0.02.00.088]DDR init done
[LOG]head = 0x0, tail = 0x1760, logSize = 0x1760
[IMU][ERR] HsmLogInit!
[IMU][ERR] HsmLogInit! TRUE
set apei done!
UbConfigData size is 64
UbConfigData 0 : 0
UbConfigData 1
IPU0log=00000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
uncore max freq : 2350 MHz

IPU1log=
HSM0log=
IMU0log= : 0
UbConfigData 2 : 0
UbConfigData 3 : 1
UbConfigData 4 : 31
UbConfigData 5 : 1
UbConfigData 6 : 0
UbConfigData 7 : 32
UbConfigData 8 : 0
UbConfigData 9 : 1
UbConfigData 10 : 2
UbConfigData 11 : 0
UbConfigData 12 : 0
UbConfigD
IPU0log=
IPU1log=
HSM0log=
IMU0log=ata 13 : 1
UbConfigData 14 : 0
UbConfigData 15 : 0
UbConfigData 16 : 0
UbConfigData 17 : 0
UbConfigData 18 : 0
UbConfigData 19 : 0
UbConfigData 20 : 0
UbConfigData 21 : 0
UbConfigData 22 : 11
UbConfigData 23 : 0
UbConfigData 24 
IPU0log=
IPU1log=
HSM0log=
IMU0log=: 0
UbConfigData 25 : 0
UbConfigData 26 : 0
UbConfigData 27 : 0
UbConfigData 28 : 0
UbConfigData 29 : 0
UbConfigData 30 : 0
UbConfigData 31 : 0
UbConfigData 32 : 0
UbConfigData 33 : 0
UbConfigData 34 : 2
UbConfigData 35 : 1
UbCo
IPU0log=
IPU1log=
HSM0log=
IMU0log=nfigData 36 : 0
UbConfigData 37 : 0
UbConfigData 38 : 0
UbConfigData 39 : 0
UbConfigData 40 : 0
UbConfigData 41 : 0
UbConfigData 42 : 0
UbConfigData 43 : 0
UbConfigData 44 : 0
UbConfigData 45 : 0
UbConfigData 46 : 0
UbConfigData
IPU0log=
IPU1log=
HSM0log=
IMU0log= 47 : 0
UbConfigData 48 : 0
UbConfigData 49 : 0
UbConfigData 50 : 0
UbConfigData 51 : 0
UbConfigData 52 : 0
UbConfigData 53 : 0
UbConfigData 54 : 0
UbConfigData 55 : 0
UbConfigData 56 : 0
UbConfigData 57 : 0
UbConfigData 58 : 0

IPU0log=
IPU1log=
HSM0log=
IMU0log=UbConfigData 59 : 0
UbConfigData 60 : 0
UbConfigData 61 : 0
UbConfigData 62 : 0
UbConfigData 63 : 0
UbConfigData 64 : 0
ClusterSwitch: 0, 0
ClusterMode: 0, 0
ControlMode: 0, 0
EnumMode: 1, 1
BodyMask: 31, 31
CcCtxCount: 256, 256
IPU0log=
IPU1log=
HSM0log=
IMU0log=
RcCtxCount: 32, 32
UbMemEntrySize: 128, 0
MctpSupport: 1, 1
SecureMode: 0, 0
PrimaryCna: 0, 0
Upi: 0, 0
EntityId: 0, 0
SlotId: 1, 1
SocketId: 2, 2
PortIndex: 0, 0
PortCna: 0, 0
CtrlCna: 11, 11
ImpBootFlag: 2, 2
ImuBootFlag: 1, 
IPU0log=
IPU1log=
HSM0log=
IMU0log=1
SktId: 0 DieId:2, HCCS_LINK:2 PaId:2
SktId: 1 DieId:2, HCCS_LINK:0 PaId:0
CIS register: ID[0xc00007ff], owner[0x1000003], function[0x1045dc5c].
CIS register: ID[0xc0000002], owner[0x1000003], function[0x1045dcfc].
odf: can not
IPU0log=
IPU1log=
HSM0log=
IMU0log= find od file[config]
Do not get NII route table, disable NII Send function.
UbiosTaskStart Entry ...
UbiosTaskStart create task success
IMU ImpBootFlag: 0x2
skip IMP start config...
UbiosCisTask Entry ...
ddr init done, star
IPU0log=
IPU1log=
HSM0log=
IMU0log=t thermal dimm task
======dimm status======
  chl[0] dimm0 1, dimm1 0
  chl[1] dimm0 0, dimm1 0
  chl[2] dimm0 0, dimm1 0
  chl[3] dimm0 0, dimm1 0
  chl[4] dimm0 0, dimm1 0
  chl[5] dimm0 0, dimm1 0
  chl[6] dimm0 0, dimm1 0
  
IPU0log=
IPU1log=
HSM0log=
IMU0log=chl[7] dimm0 0, dimm1 0
  chl[8] dimm0 0, dimm1 0
  chl[9] dimm0 0, dimm1 0
  chl[10] dimm0 0, dimm1 0
  chl[11] dimm0 0, dimm1 0
==========end==========
sktId[0] chl[0] registered, dimm mask = 0x1
======dimm status======
  chl[
IPU0log=
IPU1log=
HSM0log=
IMU0log=0] dimm0 1, dimm1 0
  chl[1] dimm0 0, dimm1 0
  chl[2] dimm0 0, dimm1 0
  chl[3] dimm0 0, dimm1 0
  chl[4] dimm0 0, dimm1 0
  chl[5] dimm0 0, dimm1 0
  chl[6] dimm0 0, dimm1 0
  chl[7] dimm0 0, dimm1 0
  chl[8] dimm0 0, dimm1 0

IPU0log=
IPU1log=
HSM0log=
IMU0log=  chl[9] dimm0 0, dimm1 0
  chl[10] dimm0 0, dimm1 0
  chl[11] dimm0 0, dimm1 0
==========end==========
sktId[1] chl[0] registered, dimm mask = 0x1
=====dimm temp params=====
  temp_threshold      : temp_mid:85,85 | temp_hi:95 |
IPU0log=
IPU1log=
HSM0log=
IMU0log= temp_cri:100
  is_thermal_thro_en  : 1
  is_aref_rate_auto   : 0
===========end============
BMC_COLLECTION: bmc req last log!
[IMU][ERR] [
HSM0log= no log data error!]
[0.02.07.312]TF Heartbeat Start
[0.02.08.537]RECEIVE MEM SI
IPU0log=
IPU1log=
HSM0log=
IMU0log=LK.
0: skt = 0 logic = 2 phy = 4 
1: skt = 1 logic = 7 phy = 1 
2: skt = 0 logic = 9 phy = 11 
3: skt = 1 logic = 5 phy = 6 
4: skt = 1 logic = 8 phy = 5 
5: skt = 1 logic = 9 phy = 11 
6: skt = 1 logic = 11 phy = 7 
7: skt = 0 
IPU0log=
IPU1log=
HSM0log=
IMU0log=logic = 4 phy = 2 
8: skt = 1 logic = 4 phy = 2 
9: skt = 1 logic = 1 phy = 0 
10: skt = 0 logic = 7 phy = 1 
11: skt = 0 logic = 10 phy = 3 
12: skt = 1 logic = 0 phy = 8 
13: skt = 0 logic = 8 phy = 5 
14: skt = 0 logic = 1 ph
IPU0log=
IPU1log=
HSM0log=
IMU0log=y = 0 
15: skt = 1 logic = 10 phy = 3 
16: skt = 1 logic = 2 phy = 4 
17: skt = 0 logic = 11 phy = 7 
18: skt = 0 logic = 3 phy = 10 
19: skt = 0 logic = 6 phy = 9 
20: skt = 0 logic = 0 phy = 8 
21: skt = 0 logic = 5 phy = 6 
2
IPU0log=
IPU1log=
HSM0log=
IMU0log=2: skt = 1 logic = 3 phy = 10 
23: skt = 1 logic = 6 phy = 9 
get mem silk data length: 72
[0.02.11.531]PCIE INIT DONE.
[IMU][ERR] LOS_SemPend(g_pcieSemaphore, LOS_WAIT_FOREVER)
[RegisterInterruptSource]:[21] begin
Interrupt 25
IPU0log=
IPU1log=
HSM0log=
IMU0log=8 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 262 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 266 register OK
[RegisterInter
IPU0log=
IPU1log=
HSM0log=
IMU0log=ruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 270 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 277 register OK
[RegisterInterruptSource]:[39] end
[Regis
IPU0log=
IPU1log=
HSM0log=
IMU0log=terInterruptSource]:[21] begin
Interrupt 288 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 292 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] beg
IPU0log=
IPU1log=
HSM0log=
IMU0log=in
Interrupt 296 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 300 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 307 register O
IPU0log=
IPU1log=
HSM0log=
IMU0log=K
[RegisterInterruptSource]:[39] end
pmt Init done

-----------------ROUTE TABLE------------------
entryCount = 1
----------------------------------------------
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, ent
IPU0log=
IPU1log=
HSM0log=
IMU0log=ryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2100
----------------------------------------------
-----------------ROUTE TABLE------------------
entryCount = 2
----------------------------------
IPU0log=
IPU1log=
HSM0log=
IMU0log=------------
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2100
[No.1]:
eidRange = 1, startEid = 10, port = 0, isStatic = 1, entry
IPU0log=
IPU1log=
HSM0log=
IMU0log=Type = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2500
----------------------------------------------
-----------------ROUTE TABLE------------------
entryCount = 2
------------------------------------
IPU0log=
IPU1log=
HSM0log=
IMU0log=----------
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2100
[No.1]:
eidRange = 1, startEid = 10, port = 0, isStatic = 1, entryTy
IPU0log=
IPU1log=
HSM0log=
IMU0log=pe = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2500
----------------------------------------------

IPU0log=
IPU1log=
HSM0log=
IMU0log=1T1N1U skt:0 CfgBusDfxPreConfig finish

********Hello Huawei LiteOS********

IMU Firmware Version : B173V01
LiteOS Kernel Version : 5.10.0
Run on Socket[0] Die[3]
Chip Version: 1
Max socket num: 2
*******************************
IPU0log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 0
cls: 6, core: 7
cpu 933 sram 1010 ddr 983
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  750|  802|  885|  933|
max  v
IPU1log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 1
cls: 6, core: 7
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  759|  821|  909|  961|
max  v: |  750|  750|  753|  781
HSM0log=[1970-01-01 00:01:11.893][HSM][INFO][30] init start
[1970-01-01 00:01:11.893][HSM][INFO][38] init over
[00:01:11.903][info] succeed to do thirdparty dfx_pabuk init
[00:01:11.909][info] os_mem_system_init default pool done
[0
IMU0log=***
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | rail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_vo
IPU0log=: |  750|  750|  754|  775|  836|  922|  980|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:7
IPU1log=|  846|  938|  994|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:750 F:1950
avs-uncore V:750
HSM0log=0:01:11.915][info] addr is already in region
[00:01:11.918][info] succeed to do thirdparty otpc_pabuk init
[1970-01-01 00:01:11.923][HSM][INFO][31] select_region: 0xc11cb55b
[1970-01-01 00:01:11.929][HSM][INFO][67] spi_nor de
IMU0log=lt:1122 mV | pmu:MP2882
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_v
IPU0log=50 F:1950
avs-uncore V:750 F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
av
IPU1log= F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
avs-uncore V:840 F:2450
avs-
HSM0log=vice_id 0xff1a67c8
[1970-01-01 00:01:11.935][HSM][INFO][50] std_cmd readback 0x30220d8
[1970-01-01 00:01:11.941][HSM][INFO][72] saf_cmd 0x0 readback 0x9f5a0604
[1970-01-01 00:01:11.948][HSM][INFO][72] saf_cmd 0x1 readback 0x5
IMU0log=olt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_
IPU0log=s-uncore V:840 F:2450
avs-uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain
IPU1log=uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | r
HSM0log=b7e938
[1970-01-01 00:01:11.954][HSM][INFO][72] saf_cmd 0x2 readback 0x1
[1970-01-01 00:01:11.960][HSM][INFO][72] saf_cmd 0x3 readback 0x0
[1970-01-01 00:01:11.966][HSM][INFO][72] saf_cmd 0x4 readback 0x0
[00:01:11.972][info
IMU0log=volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus r
IPU0log=[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | p
IPU1log=ail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_volt:1122 mV | pmu:MP2882
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[0] volt =  908 mV
pwr domain
HSM0log=] succeed to do thirdparty boot_profile_driver init
[00:01:11.978][info] succeed to do thirdparty crypto_driver init
[00:01:11.983][info] succeed to do thirdparty period_driver init
[00:01:11.989][info]  start loading interna
IMU0log=eady.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait th
IPU0log=mu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pmbus:0x480c0000 ver:0x110
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
IPU1log=[9] volt = 1103 mV
=end=
w&h rd rail:0, 906
w&h rd rail:1, 1105
pwr domain[0] set volt  906 mV succ
pwr domain[9] set volt 1103 mV succ
volt post
pwr domain[0] volt =  904 mV
pwr domain[9] volt = 1103 mV
==end==
Totem[0] Core Bo
HSM0log=l task ...
[00:01:11.994][info]  task name is ccm_task
[00:01:11.998][info]  hm_dynamic_loadelf successfully!
[00:01:12.003][info] internal task[1] task_name=ccm_task load successfully
[00:01:12.009][info]  task name is upgr
IMU0log=e cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master I
IPU0log=
avsbus resync succ
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[2] volt =  904 mV
pwr domain[7] volt =  804 mV
pwr domain[4] volt =  804 mV
pwr domain[1] volt =  804 mV
=end=
w&h rd rail:
IPU1log=ot Vol [1029]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2,
HSM0log=ade_task
[00:01:12.014][info]  hm_dynamic_loadelf successfully!
[00:01:12.018][info] internal task[2] task_name=upgrade_task load successfully
[00:01:12.025][info] created task ccm_task success!
[00:01:12.030][info] created 
IMU0log=mu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
cpu 0 entering scheduler
|--------------------------------------------------|
AtsPrint
|idx|lockCount| srcAddr| destAddr| addrLen|
|--
IPU0log=0, 906
w&h rd rail:1, 804
pwr domain[2] set volt  902 mV succ
pwr domain[7] set volt  802 mV succ
w&h rd rail:0, 804
w&h rd rail:1, 804
pwr domain[4] set volt  804 mV succ
pwr domain[1] set volt  802 mV succ
volt post
pwr domain
IPU1log= ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd8
HSM0log=task upgrade_task success!
[1970-01-01 00:01:12.035][HSM][INFO][54] Platform init 0x20250523 0x4e.
[1970-01-01 00:01:12.041][HSM][INFO][197] ccm start.
[1970-01-01 00:01:12.046][HSM][INFO][86] upgrade task init success.
[197
IMU0log=------------------------------------------------|
|  0|00000000|0x010500000|0x000110800000|0x00100000|
|  1|00000000|0x020000000|0x00001d000000|0x00800000|
|  2|00000000|0x020800000|0x000490000000|0x00100000|
|  3|00000000|0x020
IPU0log=[2] volt =  902 mV
pwr domain[7] volt =  800 mV
pwr domain[4] volt =  804 mV
pwr domain[1] volt =  802 mV
==end==
Totem[0] Core Boot Vol [1015]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0,
IPU1log=00, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
opposite dieId: 0, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 
HSM0log=0-01-01 00:01:12.052][HSM][INFO][95] upgrade recv cmd, 0x181.
[1970-01-01 00:01:12.058][HSM][INFO][103] upgrade res, 0x3a5aa5a3.
.
IMU0log=900000|0x000004000000|0x08000000|
|  4|00000000|0x028900000|0x000440580000|0x01000000|
|  5|00000000|0x029900000|0x000590000000|0x00100000|
|  6|00000000|0x029a00000|0x002000150000|0x00100000|
|  7|00000000|0x000000000|0x0000000
IPU0log= MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 
IPU1log=enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
hiboost task entry
boost wait SEF.
[INFO] mem used of task 'app_Task' is:0x2028, not zero when task being deleted
boost param OK.
Totem[0] Core[ 0] Freq Limit Low
HSM0log=
IMU0log=00000|0x00000000|
|  8|00000000|0x040000000|0x000000000000|0x08000000|
|  9|00000000|0x048000000|0x000000000000|0x08000000|
| 10|00000000|0x050000000|0x000000000000|0x08000000|
| 11|00000000|0x058000000|0x000000000000|0x08000000
IPU0log=0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
tsensor type
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Fr
HSM0log=
IMU0log=|
| 12|00000000|0x060000000|0x000000000000|0x08000000|
| 13|00000000|0x068000000|0x000000000000|0x08000000|
| 14|00000000|0x070000000|0x000000000000|0x08000000|
| 15|00000000|0x078000000|0x000490000000|0x08000000|
|-------------
IPU0log=: 3, ppuFormatK: 0x4da6, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b4,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 3, mask: fffffff8
tsensor type: 4, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=-------------------------------------|
=~=~=~=~=~=~=~=~=~=~= IMU Log @ 2026.5.12 22:51:16 =~=~=~=~=~=~=~=~=~=~=
[IMU] Watchdog Initialization done!
[RegisterInterruptSource]:[21] begin
Interrupt 32 register OK
Interrupt 34 reg
IPU0log=0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 4, mask: ffffffee
tsensor type: 5, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1

IPU1log= Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=ister OK
Interrupt 40 register OK
Interrupt 44 register OK
sram cnt 0x0, id = 43
Interrupt 43 register OK
Interrupt 36 register OK
Interrupt 57 register OK
sram cnt 0x0, id = 42
Interrupt 42 register OK
Interrupt 37 register OK

IPU0log=tsensor: 5, mask: ffffffda
tsensor type: 6, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 6, mask: ffffff80
tsensor type: 7, ppuFormatK: 0x437a,
IPU1log=KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=[RegisterInterruptSource]:[39] end
IPMB initialization Start...
IPMB clock set done, prer = 0x18.
IPMB Rx FIFO clear empty.
IPMB initialization Done.
starting DFX Collect Task end
PowerTask Entry ...
Wait all vrd init done
IPU0log= ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 7, mask: fffffffe
opposite dieId: 1, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
CPM max V[900]-
IPU1log= Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low
HSM0log=
IMU0log= ...
All vrd init done, power task start
refresh domainId 0 Lsb 0x0
refresh domainId 9 Lsb 0x1
refresh domainId 2 Lsb 0x0
refresh domainId 7 Lsb 0x1
refresh domainId 4 Lsb 0x0
refresh domainId 1 Lsb 0x1
power sensor[0] | calib:5
IPU0log=F:2800
CPM min V[750]-F:1600
freq:2350, idx:9
cpm trim freq: 2600, idx: 4
cpm trim finish
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
recount hours 
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Fr
HSM0log=
IMU0log=120 | rshunt:1 | rshuntDiv:1000 | currLsb:1 | currLsbDiv:1000 | enableFlag:1
                | pwrLsb:25 | defPwr:25000 | minPwr:10000 | maxPwr:65000 | pwrFix:3400
                | manufacturerId: 0x5549 | dieId: 0x2260
power s
IPU0log=0x984 
hiboost task entry
boost wait SEF.
boost param OK.
Totem[0] Core[ 0] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[26
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=ensor[0] init success
ScmiTaskEntry start.
[RegisterInterruptSource]:[21] begin
Interrupt 51 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 52 register OK
[RegisterInterruptSourc
IPU0log=00000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[12000
IPU1log= Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=e]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 53 register OK
[RegisterInterruptSource]:[39] end
[0.01.28.588]starting ras Init
RAS Setup Value get done!
INT_NUM_PER_SKT * HiGetSktNum() = 0x8
index = 0x0
RasIntReg
IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Lim
IPU1log=KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=ister init 160 
index = 0x1
RasIntRegister init 172 
index = 0x2
RasIntRegister init 162 
index = 0x3
RasIntRegister init 174 
index = 0x4
RasIntRegister init 184 
index = 0x5
RasIntRegister init 196 
index = 0x6
RasIntRegister 
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IPU1log= Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low
HSM0log=
IMU0log=init 186 
index = 0x7
RasIntRegister init 198 
RasIntRegister init 161 
RasIntRegister init 173 
RasIntRegister init 185 
RasIntRegister init 197 
RasIntRegister init 284 
RasIntRegister init 314 
MceTableHeadInit start
starting
IPU0log=14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
To
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
uncore max freq : 23
HSM0log=
IMU0log= Ce_Storm Contrl and Ras_Data_Update Task end
[0.01.28.670]starting ras end
[IMU][ERR] skt id 0
Ub init task start Entry ...
UbInitTask Entry ...
[RegisterInterruptSource]:[21] begin
Interrupt 167 register OK
[RegisterInterru
IPU0log=tem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[26
IPU1log=50 MHz

HSM0log=
IMU0log=ptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 191 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 171 register OK
[RegisterInterruptSource]:[39] end
[Registe
IPU0log=00000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[12000
IPU1log=
HSM0log=
IMU0log=rInterruptSource]:[21] begin
Interrupt 183 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 195 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Lim
IPU1log=
HSM0log=
IMU0log=
Interrupt 207 register OK
[RegisterInterruptSource]:[39] end
Init heart-beat-task end
CS0 flash do not support sfdp!
Current flash device ID[0x61a67c8]!
System supported 1 Flash.
flash cs 0 Manufacture 0xc8, DeviceId 0x1a67, 
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IPU1log=
HSM0log=
IMU0log=AddrMode[0-3B,1-4B] 0x1:
    size 0x4000000, pagesize 0x100
    read  cmd 0x13, dummy byte 0x8
    write cmd 0x12, dummy byte 0x0
    erase4k cmd 0x21, erase64k byte 0xdc
sfc init end
firstUnMskExt0Int
ThermalDimmStart Entry ...
IPU0log=33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
To
IPU1log=
HSM0log=
IMU0log=
wait ddr init done...
HacLowPowerStart Entry ...
Hello LiteOS...
pwr cap[0]: 0, 67
Init ReportPcieMmioToBmcTaskEntry end
starting Fpc Isolation Task end
pwr cap[1]: f, 27
pwr cap[2]: 1, 3
[IMU][ERR] IMP log not ready, DDR
IPU0log=tem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[26
IPU1log=
HSM0log=
IMU0log= initing...
[IMU][ERR] IMP log not ready, DDR initing...
[0.01.59.887]DDR init done
[LOG]head = 0x0, tail = 0x1860, logSize = 0x1860
[IMU][ERR] HsmLogInit!
[IMU][ERR] HsmLogInit! TRUE
set apei done!
UbConfigData size is 64
UbCon
IPU0log=00000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
uncore max freq : 2350 MHz

IPU1log=
HSM0log=
IMU0log=figData 0 : 0
UbConfigData 1 : 0
UbConfigData 2 : 0
UbConfigData 3 : 1
UbConfigData 4 : 31
UbConfigData 5 : 1
UbConfigData 6 : 0
UbConfigData 7 : 32
UbConfigData 8 : 0
UbConfigData 9 : 1
UbConfigData 10 : 2
UbConfigData 11 : 0
U
IPU0log=
IPU1log=
HSM0log=
IMU0log=bConfigData 12 : 0
UbConfigData 13 : 1
UbConfigData 14 : 0
UbConfigData 15 : 0
UbConfigData 16 : 0
UbConfigData 17 : 0
UbConfigData 18 : 0
UbConfigData 19 : 0
UbConfigData 20 : 0
UbConfigData 21 : 0
UbConfigData 22 : 11
UbConfig
IPU0log=
IPU1log=
HSM0log=
IMU0log=Data 23 : 0
UbConfigData 24 : 0
UbConfigData 25 : 0
UbConfigData 26 : 0
UbConfigData 27 : 0
UbConfigData 28 : 0
UbConfigData 29 : 0
UbConfigData 30 : 0
UbConfigData 31 : 0
UbConfigData 32 : 0
UbConfigData 33 : 0
UbConfigData 34 
IPU0log=
IPU1log=
HSM0log=
IMU0log=: 2
UbConfigData 35 : 1
UbConfigData 36 : 0
UbConfigData 37 : 0
UbConfigData 38 : 0
UbConfigData 39 : 0
UbConfigData 40 : 0
UbConfigData 41 : 0
UbConfigData 42 : 0
UbConfigData 43 : 0
UbConfigData 44 : 0
UbConfigData 45 : 0
UbCo
IPU0log=
IPU1log=
HSM0log=
IMU0log=nfigData 46 : 0
UbConfigData 47 : 0
UbConfigData 48 : 0
UbConfigData 49 : 0
UbConfigData 50 : 0
UbConfigData 51 : 0
UbConfigData 52 : 0
UbConfigData 53 : 0
UbConfigData 54 : 0
UbConfigData 55 : 0
UbConfigData 56 : 0
UbConfigData
IPU0log=
IPU1log=
HSM0log=
IMU0log= 57 : 0
UbConfigData 58 : 0
UbConfigData 59 : 0
UbConfigData 60 : 0
UbConfigData 61 : 0
UbConfigData 62 : 0
UbConfigData 63 : 0
UbConfigData 64 : 0
ClusterSwitch: 0, 0
ClusterMode: 0, 0
ControlMode: 0, 0
EnumMode: 1, 1
BodyMask:
IPU0log=
IPU1log=
HSM0log=
IMU0log= 31, 31
CcCtxCount: 256, 256
RcCtxCount: 32, 32
UbMemEntrySize: 128, 0
MctpSupport: 1, 1
SecureMode: 0, 0
PrimaryCna: 0, 0
Upi: 0, 0
EntityId: 0, 0
SlotId: 1, 1
SocketId: 2, 2
PortIndex: 0, 0
PortCna: 0, 0
CtrlCna: 11, 11
ImpBoo
IPU0log=
IPU1log=
HSM0log=
IMU0log=tFlag: 2, 2
ImuBootFlag: 1, 1
SktId: 0 DieId:2, HCCS_LINK:2 PaId:2
SktId: 1 DieId:2, HCCS_LINK:0 PaId:0
CIS register: ID[0xc00007ff], owner[0x1000003], function[0x1045dc5c].
CIS register: ID[0xc0000002], owner[0x1000003], functi
IPU0log=
IPU1log=
HSM0log=
IMU0log=on[0x1045dcfc].
odf: can not find od file[config]
Do not get NII route table, disable NII Send function.
UbiosTaskStart Entry ...
UbiosTaskStart create task success
IMU ImpBootFlag: 0x2
skip IMP start config...
UbiosCisTask En
IPU0log=
IPU1log=
HSM0log=
IMU0log=try ...
ddr init done, start thermal dimm task
======dimm status======
  chl[0] dimm0 1, dimm1 0
  chl[1] dimm0 0, dimm1 0
  chl[2] dimm0 0, dimm1 0
  chl[3] dimm0 0, dimm1 0
  chl[4] dimm0 0, dimm1 0
  chl[5] dimm0 0, dimm1 0

IPU0log=
IPU1log=
HSM0log=
IMU0log=  chl[6] dimm0 0, dimm1 0
  chl[7] dimm0 0, dimm1 0
  chl[8] dimm0 0, dimm1 0
  chl[9] dimm0 0, dimm1 0
  chl[10] dimm0 0, dimm1 0
  chl[11] dimm0 0, dimm1 0
==========end==========
sktId[0] chl[0] registered, dimm mask = 0x1
==
IPU0log=
IPU1log=
HSM0log=
IMU0log=====dimm status======
  chl[0] dimm0 1, dimm1 0
  chl[1] dimm0 0, dimm1 0
  chl[2] dimm0 0, dimm1 0
  chl[3] dimm0 0, dimm1 0
  chl[4] dimm0 0, dimm1 0
  chl[5] dimm0 0, dimm1 0
  chl[6] dimm0 0, dimm1 0
  chl[7] dimm0 0, dimm1 
IPU0log=
IPU1log=
HSM0log=
IMU0log=0
  chl[8] dimm0 0, dimm1 0
  chl[9] dimm0 0, dimm1 0
  chl[10] dimm0 0, dimm1 0
  chl[11] dimm0 0, dimm1 0
==========end==========
sktId[1] chl[0] registered, dimm mask = 0x1
=====dimm temp params=====
  temp_threshold      : t
IPU0log=
IPU1log=
HSM0log=
IMU0log=emp_mid:85,85 | temp_hi:95 | temp_cri:100
  is_thermal_thro_en  : 1
  is_aref_rate_auto   : 0
===========end============
[IMU][ERR] [
IMP0log= no log data error!]
[0.02.06.908]TF Heartbeat Start
[0.02.08.600]RECEIVE MEM SILK.
0:
IPU0log=
IPU1log=
HSM0log=
IMU0log= skt = 1 logic = 9 phy = 11 
1: skt = 0 logic = 2 phy = 4 
2: skt = 0 logic = 7 phy = 1 
3: skt = 0 logic = 4 phy = 2 
4: skt = 0 logic = 10 phy = 3 
5: skt = 1 logic = 7 phy = 1 
6: skt = 1 logic = 1 phy = 0 
7: skt = 0 logic =
IPU0log=
IPU1log=
HSM0log=
IMU0log= 3 phy = 10 
8: skt = 0 logic = 6 phy = 9 
9: skt = 0 logic = 11 phy = 7 
10: skt = 0 logic = 0 phy = 8 
11: skt = 0 logic = 5 phy = 6 
12: skt = 0 logic = 9 phy = 11 
13: skt = 1 logic = 2 phy = 4 
14: skt = 1 logic = 8 phy = 5
IPU0log=
IPU1log=
HSM0log=
IMU0log= 
15: skt = 1 logic = 5 phy = 6 
16: skt = 1 logic = 3 phy = 10 
17: skt = 1 logic = 0 phy = 8 
18: skt = 1 logic = 10 phy = 3 
19: skt = 1 logic = 6 phy = 9 
20: skt = 1 logic = 11 phy = 7 
21: skt = 1 logic = 4 phy = 2 
22: sk
IPU0log=
IPU1log=
HSM0log=
IMU0log=t = 0 logic = 8 phy = 5 
23: skt = 0 logic = 1 phy = 0 
get mem silk data length: 72
[0.02.11.561]PCIE INIT DONE.
[IMU][ERR] LOS_SemPend(g_pcieSemaphore, LOS_WAIT_FOREVER)
[RegisterInterruptSource]:[21] begin
Interrupt 258 regi
IPU0log=
IPU1log=
HSM0log=
IMU0log=ster OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 262 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 266 register OK
[RegisterInterruptSo
IPU0log=
IPU1log=
HSM0log=
IMU0log=urce]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 270 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 277 register OK
[RegisterInterruptSource]:[39] end
[RegisterInt
IPU0log=
IPU1log=
HSM0log=
IMU0log=erruptSource]:[21] begin
Interrupt 288 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 292 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
In
IPU0log=
IPU1log=
HSM0log=
IMU0log=terrupt 296 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 300 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 307 register OK
[Reg
IPU0log=
IPU1log=
HSM0log=
IMU0log=isterInterruptSource]:[39] end
pmt Init done

-----------------ROUTE TABLE------------------
entryCount = 1
----------------------------------------------
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType
IPU0log=
IPU1log=
HSM0log=
IMU0log= = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2100
----------------------------------------------
-----------------ROUTE TABLE------------------
entryCount = 2
----------------------------------------
IPU0log=
IPU1log=
HSM0log=
IMU0log=------
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2100
[No.1]:
eidRange = 1, startEid = 10, port = 0, isStatic = 1, entryType =
IPU0log=
IPU1log=
HSM0log=
IMU0log= 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2500
----------------------------------------------
-----------------ROUTE TABLE------------------
entryCount = 2
------------------------------------------
IPU0log=
IPU1log=
HSM0log=
IMU0log=----
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2100
[No.1]:
eidRange = 1, startEid = 10, port = 0, isStatic = 1, entryType = 0
IPU0log=
IPU1log=
HSM0log=
IMU0log=, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2500
----------------------------------------------

IPU0log=
IPU1log=
HSM0log=
IMU0log=1T1N1U skt:0 CfgBusDfxPreConfig finish

********Hello Huawei LiteOS********

IMU Firmware Version : B173V01
LiteOS Kernel Version : 5.10.0
Run on Socket[0] Die[3]
Chip Version: 1
Max socket num: 2
*******************************
IPU0log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 0
cls: 6, core: 7
cpu 933 sram 1010 ddr 983
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  750|  802|  885|  933|
max  v
IPU1log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 1
cls: 6, core: 7
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  759|  821|  909|  961|
max  v: |  750|  750|  753|  781
HSM0log=[1970-01-01 00:01:12.061][HSM][INFO][30] init start
[1970-01-01 00:01:12.061][HSM][INFO][38] init over
[00:01:12.070][info] succeed to do thirdparty dfx_pabuk init
[00:01:12.076][info] os_mem_system_init default pool done
[0
IMU0log=***
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | rail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_vo
IPU0log=: |  750|  750|  754|  775|  836|  922|  980|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:7
IPU1log=|  846|  938|  994|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:750 F:1950
avs-uncore V:750
HSM0log=0:01:12.082][info] addr is already in region
[00:01:12.085][info] succeed to do thirdparty otpc_pabuk init
[1970-01-01 00:01:12.091][HSM][INFO][31] select_region: 0xc11cb55b
[1970-01-01 00:01:12.097][HSM][INFO][67] spi_nor de
IMU0log=lt:1122 mV | pmu:MP2882
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_v
IPU0log=50 F:1950
avs-uncore V:750 F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
av
IPU1log= F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
avs-uncore V:840 F:2450
avs-
HSM0log=vice_id 0xff1a67c8
[1970-01-01 00:01:12.103][HSM][INFO][50] std_cmd readback 0x30220d8
[1970-01-01 00:01:12.109][HSM][INFO][72] saf_cmd 0x0 readback 0x9f5a0604
[1970-01-01 00:01:12.115][HSM][INFO][72] saf_cmd 0x1 readback 0x5
IMU0log=olt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_
IPU0log=s-uncore V:840 F:2450
avs-uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain
IPU1log=uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | r
HSM0log=b7e938
[1970-01-01 00:01:12.121][HSM][INFO][72] saf_cmd 0x2 readback 0x1
[1970-01-01 00:01:12.127][HSM][INFO][72] saf_cmd 0x3 readback 0x0
[1970-01-01 00:01:12.133][HSM][INFO][72] saf_cmd 0x4 readback 0x0
[00:01:12.139][info
IMU0log=volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus r
IPU0log=[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | p
IPU1log=ail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_volt:1122 mV | pmu:MP2882
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[0] volt =  906 mV
pwr domain
HSM0log=] succeed to do thirdparty boot_profile_driver init
[00:01:12.145][info] succeed to do thirdparty crypto_driver init
[00:01:12.151][info] succeed to do thirdparty period_driver init
[00:01:12.157][info]  start loading interna
IMU0log=eady.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait th
IPU0log=mu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pmbus:0x480c0000 ver:0x110
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
IPU1log=[9] volt = 1103 mV
=end=
w&h rd rail:0, 906
w&h rd rail:1, 1103
pwr domain[0] set volt  904 mV succ
pwr domain[9] set volt 1103 mV succ
volt post
pwr domain[0] volt =  904 mV
pwr domain[9] volt = 1105 mV
==end==
Totem[0] Core Bo
HSM0log=l task ...
[00:01:12.161][info]  task name is ccm_task
[00:01:12.165][info]  hm_dynamic_loadelf successfully!
[00:01:12.170][info] internal task[1] task_name=ccm_task load successfully
[00:01:12.177][info]  task name is upgr
IMU0log=e cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master I
IPU0log=
avsbus resync succ
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[2] volt =  904 mV
pwr domain[7] volt =  804 mV
pwr domain[4] volt =  806 mV
pwr domain[1] volt =  804 mV
=end=
w&h rd rail:
IPU1log=ot Vol [1029]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2,
HSM0log=ade_task
[00:01:12.181][info]  hm_dynamic_loadelf successfully!
[00:01:12.186][info] internal task[2] task_name=upgrade_task load successfully
[00:01:12.193][info] created task ccm_task success!
[00:01:12.197][info] created 
IMU0log=mu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
cpu 0 entering scheduler
|--------------------------------------------------|
AtsPrint
|idx|lockCount| srcAddr| destAddr| addrLen|
|--
IPU0log=0, 904
w&h rd rail:1, 804
pwr domain[2] set volt  904 mV succ
pwr domain[7] set volt  802 mV succ
w&h rd rail:0, 804
w&h rd rail:1, 806
pwr domain[4] set volt  804 mV succ
pwr domain[1] set volt  802 mV succ
volt post
pwr domain
IPU1log= ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd8
HSM0log=task upgrade_task success!
[1970-01-01 00:01:12.202][HSM][INFO][54] Platform init 0x20250523 0x4e.
[1970-01-01 00:01:12.209][HSM][INFO][197] ccm start.
[1970-01-01 00:01:12.213][HSM][INFO][86] upgrade task init success.
[197
IMU0log=------------------------------------------------|
|  0|00000000|0x010500000|0x000110800000|0x00100000|
|  1|00000000|0x020000000|0x00001d000000|0x00800000|
|  2|00000000|0x020800000|0x000490000000|0x00100000|
|  3|00000000|0x020
IPU0log=[2] volt =  902 mV
pwr domain[7] volt =  802 mV
pwr domain[4] volt =  804 mV
pwr domain[1] volt =  802 mV
==end==
Totem[0] Core Boot Vol [1015]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0,
IPU1log=00, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
opposite dieId: 0, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 
HSM0log=0-01-01 00:01:12.219][HSM][INFO][95] upgrade recv cmd, 0x181.
[1970-01-01 00:01:12.225][HSM][INFO][103] upgrade res, 0x3a5aa5a3.
.
IMU0log=900000|0x000004000000|0x08000000|
|  4|00000000|0x028900000|0x000440580000|0x01000000|
|  5|00000000|0x029900000|0x000590000000|0x00100000|
|  6|00000000|0x029a00000|0x002000150000|0x00100000|
|  7|00000000|0x000000000|0x0000000
IPU0log= MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 
IPU1log=enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
hiboost task entry
boost wait SEF.
[INFO] mem used of task 'app_Task' is:0x2028, not zero when task being deleted
boost param OK.
Totem[0] Core[ 0] Freq Limit Low
HSM0log=
IMU0log=00000|0x00000000|
|  8|00000000|0x040000000|0x000000000000|0x08000000|
|  9|00000000|0x048000000|0x000000000000|0x08000000|
| 10|00000000|0x050000000|0x000000000000|0x08000000|
| 11|00000000|0x058000000|0x000000000000|0x08000000
IPU0log=0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
tsensor type
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Fr
HSM0log=
IMU0log=|
| 12|00000000|0x060000000|0x000000000000|0x08000000|
| 13|00000000|0x068000000|0x000000000000|0x08000000|
| 14|00000000|0x070000000|0x000000000000|0x08000000|
| 15|00000000|0x078000000|0x000490000000|0x08000000|
|-------------
IPU0log=: 3, ppuFormatK: 0x4da6, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b4,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 3, mask: fffffff8
tsensor type: 4, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=-------------------------------------|
=~=~=~=~=~=~=~=~=~=~= IMU Log @ 2026.5.13 1:19:6 =~=~=~=~=~=~=~=~=~=~=
[IMU] Watchdog Initialization done!
[RegisterInterruptSource]:[21] begin
Interrupt 32 register OK
Interrupt 34 regis
IPU0log=0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 4, mask: ffffffee
tsensor type: 5, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1

IPU1log= Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=ter OK
Interrupt 40 register OK
Interrupt 44 register OK
sram cnt 0x0, id = 43
Interrupt 43 register OK
Interrupt 36 register OK
Interrupt 57 register OK
sram cnt 0x0, id = 42
Interrupt 42 register OK
Interrupt 37 register OK
[R
IPU0log=tsensor: 5, mask: ffffffda
tsensor type: 6, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 6, mask: ffffff80
tsensor type: 7, ppuFormatK: 0x437a,
IPU1log=KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=egisterInterruptSource]:[39] end
IPMB initialization Start...
IPMB clock set done, prer = 0x18.
IPMB Rx FIFO clear empty.
IPMB initialization Done.
starting DFX Collect Task end
PowerTask Entry ...
Wait all vrd init done .
IPU0log= ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 7, mask: fffffffe
opposite dieId: 1, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
CPM max V[900]-
IPU1log= Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low
HSM0log=
IMU0log=..
All vrd init done, power task start
refresh domainId 0 Lsb 0x0
refresh domainId 9 Lsb 0x1
refresh domainId 2 Lsb 0x0
refresh domainId 7 Lsb 0x1
refresh domainId 4 Lsb 0x0
refresh domainId 1 Lsb 0x1
power sensor[0] | calib:512
IPU0log=F:2800
CPM min V[750]-F:1600
freq:2350, idx:9
cpm trim freq: 2600, idx: 4
cpm trim finish
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
recount hours 
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Fr
HSM0log=
IMU0log=0 | rshunt:1 | rshuntDiv:1000 | currLsb:1 | currLsbDiv:1000 | enableFlag:1
                | pwrLsb:25 | defPwr:25000 | minPwr:10000 | maxPwr:65000 | pwrFix:3400
                | manufacturerId: 0x5549 | dieId: 0x2260
power sen
IPU0log=0x984 
hiboost task entry
boost wait SEF.
boost param OK.
Totem[0] Core[ 0] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[26
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=sor[0] init success
ScmiTaskEntry start.
[RegisterInterruptSource]:[21] begin
Interrupt 51 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 52 register OK
[RegisterInterruptSource]
IPU0log=00000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[12000
IPU1log= Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 53 register OK
[RegisterInterruptSource]:[39] end
[0.01.28.756]starting ras Init
RAS Setup Value get done!
INT_NUM_PER_SKT * HiGetSktNum() = 0x8
index = 0x0
RasIntRegis
IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Lim
IPU1log=KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=ter init 160 
index = 0x1
RasIntRegister init 172 
index = 0x2
RasIntRegister init 162 
index = 0x3
RasIntRegister init 174 
index = 0x4
RasIntRegister init 184 
index = 0x5
RasIntRegister init 196 
index = 0x6
RasIntRegister in
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IPU1log= Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low
HSM0log=
IMU0log=it 186 
index = 0x7
RasIntRegister init 198 
RasIntRegister init 161 
RasIntRegister init 173 
RasIntRegister init 185 
RasIntRegister init 197 
RasIntRegister init 284 
RasIntRegister init 314 
MceTableHeadInit start
starting C
IPU0log=14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
To
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
uncore max freq : 23
IMU0log=1T1N1U skt:0 CfgBusDfxPreConfig finish

********Hello Huawei LiteOS********

IMU Firmware Version : B173V01
LiteOS Kernel Version : 5.10.0
Run on Socket[0] Die[3]
Chip Version: 1
Max socket num: 2
*******************************
IPU0log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 0
cls: 6, core: 7
cpu 933 sram 1010 ddr 983
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  750|  802|  885|  933|
max  v
IPU1log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 1
cls: 6, core: 7
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  759|  821|  909|  961|
max  v: |  750|  750|  753|  781
IMU0log=***
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | rail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_vo
IPU0log=: |  750|  750|  754|  775|  836|  922|  980|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:7
IPU1log=|  846|  938|  994|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:750 F:1950
avs-uncore V:750
HSM0log=[1970-01-01 00:01:12.570][HSM][INFO][30] init start
[1970-01-01 00:01:12.570][HSM][INFO][38] init over
[00:01:12.580][info] succeed to do thirdparty dfx_pabuk init
[00:01:12.585][info] os_mem_system_init default pool done
[0
IMU0log=lt:1122 mV | pmu:MP2882
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_v
IPU0log=50 F:1950
avs-uncore V:750 F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
av
IPU1log= F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
avs-uncore V:840 F:2450
avs-
HSM0log=0:01:12.592][info] addr is already in region
[00:01:12.594][info] succeed to do thirdparty otpc_pabuk init
[1970-01-01 00:01:12.600][HSM][INFO][31] select_region: 0xc11cb55b
[1970-01-01 00:01:12.606][HSM][INFO][67] spi_nor de
IMU0log=olt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_
IPU0log=s-uncore V:840 F:2450
avs-uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain
IPU1log=uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | r
HSM0log=vice_id 0xff1a67c8
[1970-01-01 00:01:12.612][HSM][INFO][50] std_cmd readback 0x30220d8
[1970-01-01 00:01:12.618][HSM][INFO][72] saf_cmd 0x0 readback 0x9f5a0604
[1970-01-01 00:01:12.624][HSM][INFO][72] saf_cmd 0x1 readback 0x5
IMU0log=volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus r
IPU0log=[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | p
IPU1log=ail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_volt:1122 mV | pmu:MP2882
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[0] volt =  906 mV
pwr domain
HSM0log=b7e938
[1970-01-01 00:01:12.631][HSM][INFO][72] saf_cmd 0x2 readback 0x1
[1970-01-01 00:01:12.636][HSM][INFO][72] saf_cmd 0x3 readback 0x0
[1970-01-01 00:01:12.642][HSM][INFO][72] saf_cmd 0x4 readback 0x0
[00:01:12.649][info
IMU0log=eady.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait th
IMU0log=1T1N1U skt:0 CfgBusDfxPreConfig finish

********Hello Huawei LiteOS********

IMU Firmware Version : B173V01
LiteOS Kernel Version : 5.10.0
Run on Socket[0] Die[3]
Chip Version: 1
Max socket num: 2
*******************************
IPU0log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 0
cls: 6, core: 7
cpu 933 sram 1010 ddr 983
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  750|  802|  885|  933|
max  v
IPU1log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 1
cls: 6, core: 7
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  759|  821|  909|  961|
max  v: |  750|  750|  753|  781
HSM0log=[1970-01-01 00:01:12.535][HSM][INFO][30] init start
[1970-01-01 00:01:12.535][HSM][INFO][38] init over
[00:01:12.545][info] succeed to do thirdparty dfx_pabuk init
[00:01:12.550][info] os_mem_system_init default pool done
[0
IMU0log=***
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | rail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_vo
IPU0log=: |  750|  750|  754|  775|  836|  922|  980|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:7
IPU1log=|  846|  938|  994|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:750 F:1950
avs-uncore V:750
HSM0log=0:01:12.556][info] addr is already in region
[00:01:12.559][info] succeed to do thirdparty otpc_pabuk init
[1970-01-01 00:01:12.565][HSM][INFO][31] select_region: 0xc11cb55b
[1970-01-01 00:01:12.571][HSM][INFO][67] spi_nor de
IMU0log=lt:1122 mV | pmu:MP2882
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_v
IPU0log=50 F:1950
avs-uncore V:750 F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
av
IPU1log= F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
avs-uncore V:840 F:2450
avs-
HSM0log=vice_id 0xff1a67c8
[1970-01-01 00:01:12.577][HSM][INFO][50] std_cmd readback 0x30220d8
[1970-01-01 00:01:12.583][HSM][INFO][72] saf_cmd 0x0 readback 0x9f5a0604
[1970-01-01 00:01:12.589][HSM][INFO][72] saf_cmd 0x1 readback 0x5
IMU0log=olt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_
IPU0log=s-uncore V:840 F:2450
avs-uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain
IPU1log=uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | r
HSM0log=b7e938
[1970-01-01 00:01:12.595][HSM][INFO][72] saf_cmd 0x2 readback 0x1
[1970-01-01 00:01:12.601][HSM][INFO][72] saf_cmd 0x3 readback 0x0
[1970-01-01 00:01:12.607][HSM][INFO][72] saf_cmd 0x4 readback 0x0
[00:01:12.614][info
IMU0log=volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus r
IPU0log=[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | p
IPU1log=ail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_volt:1122 mV | pmu:MP2882
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[0] volt =  906 mV
pwr domain
HSM0log=] succeed to do thirdparty boot_profile_driver init
[00:01:12.619][info] succeed to do thirdparty crypto_driver init
[00:01:12.625][info] succeed to do thirdparty period_driver init
[00:01:12.631][info]  start loading interna
IMU0log=eady.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait th
IPU0log=mu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pmbus:0x480c0000 ver:0x110
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
IPU1log=[9] volt = 1103 mV
=end=
w&h rd rail:0, 906
w&h rd rail:1, 1103
pwr domain[0] set volt  904 mV succ
pwr domain[9] set volt 1103 mV succ
volt post
pwr domain[0] volt =  904 mV
pwr domain[9] volt = 1103 mV
==end==
Totem[0] Core Bo
HSM0log=l task ...
[00:01:12.635][info]  task name is ccm_task
[00:01:12.639][info]  hm_dynamic_loadelf successfully!
[00:01:12.644][info] internal task[1] task_name=ccm_task load successfully
[00:01:12.651][info]  task name is upgr
IMU0log=e cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master I
IPU0log=
avsbus resync succ
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[2] volt =  904 mV
pwr domain[7] volt =  804 mV
pwr domain[4] volt =  806 mV
pwr domain[1] volt =  806 mV
=end=
w&h rd rail:
IPU1log=ot Vol [1029]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2,
HSM0log=ade_task
[00:01:12.655][info]  hm_dynamic_loadelf successfully!
[00:01:12.660][info] internal task[2] task_name=upgrade_task load successfully
[00:01:12.667][info] created task ccm_task success!
[00:01:12.671][info] created 
IMU0log=mu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
cpu 0 entering scheduler
|--------------------------------------------------|
AtsPrint
|idx|lockCount| srcAddr| destAddr| addrLen|
|--
IPU0log=0, 904
w&h rd rail:1, 804
pwr domain[2] set volt  904 mV succ
pwr domain[7] set volt  802 mV succ
w&h rd rail:0, 804
w&h rd rail:1, 804
pwr domain[4] set volt  804 mV succ
pwr domain[1] set volt  804 mV succ
volt post
pwr domain
IPU1log= ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd8
HSM0log=task upgrade_task success!
[1970-01-01 00:01:12.676][HSM][INFO][54] Platform init 0x20250523 0x4e.
[1970-01-01 00:01:12.683][HSM][INFO][197] ccm start.
[1970-01-01 00:01:12.687][HSM][INFO][86] upgrade task init success.
[197
IMU0log=------------------------------------------------|
|  0|00000000|0x010500000|0x000110800000|0x00100000|
|  1|00000000|0x020000000|0x00001d000000|0x00800000|
|  2|00000000|0x020800000|0x000490000000|0x00100000|
|  3|00000000|0x020
IPU0log=[2] volt =  902 mV
pwr domain[7] volt =  800 mV
pwr domain[4] volt =  804 mV
pwr domain[1] volt =  802 mV
==end==
Totem[0] Core Boot Vol [1015]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0,
IPU1log=00, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
opposite dieId: 0, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 
HSM0log=0-01-01 00:01:12.693][HSM][INFO][95] upgrade recv cmd, 0x181.
[1970-01-01 00:01:12.699][HSM][INFO][103] upgrade res, 0x3a5aa5a3.
.
IMU0log=900000|0x000004000000|0x08000000|
|  4|00000000|0x028900000|0x000440580000|0x01000000|
|  5|00000000|0x029900000|0x000590000000|0x00100000|
|  6|00000000|0x029a00000|0x002000150000|0x00100000|
|  7|00000000|0x000000000|0x0000000
IPU0log= MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 
IPU1log=enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
hiboost task entry
boost wait SEF.
[INFO] mem used of task 'app_Task' is:0x2028, not zero when task being deleted
boost param OK.
Totem[0] Core[ 0] Freq Limit Low
HSM0log=
IMU0log=00000|0x00000000|
|  8|00000000|0x040000000|0x000000000000|0x08000000|
|  9|00000000|0x048000000|0x000000000000|0x08000000|
| 10|00000000|0x050000000|0x000000000000|0x08000000|
| 11|00000000|0x058000000|0x000000000000|0x08000000
IPU0log=0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
tsensor type
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Fr
HSM0log=
IMU0log=|
| 12|00000000|0x060000000|0x000000000000|0x08000000|
| 13|00000000|0x068000000|0x000000000000|0x08000000|
| 14|00000000|0x070000000|0x000000000000|0x08000000|
| 15|00000000|0x078000000|0x000490000000|0x08000000|
|-------------
IPU0log=: 3, ppuFormatK: 0x4da6, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b4,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 3, mask: fffffff8
tsensor type: 4, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=-------------------------------------|
=~=~=~=~=~=~=~=~=~=~= IMU Log @ 2026.5.13 1:32:7 =~=~=~=~=~=~=~=~=~=~=
[IMU] Watchdog Initialization done!
[RegisterInterruptSource]:[21] begin
Interrupt 32 register OK
Interrupt 34 regis
IPU0log=0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 4, mask: ffffffee
tsensor type: 5, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1

IPU1log= Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=ter OK
Interrupt 40 register OK
Interrupt 44 register OK
sram cnt 0x0, id = 43
Interrupt 43 register OK
Interrupt 36 register OK
Interrupt 57 register OK
sram cnt 0x0, id = 42
Interrupt 42 register OK
Interrupt 37 register OK
[R
IPU0log=tsensor: 5, mask: ffffffda
tsensor type: 6, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 6, mask: ffffff80
tsensor type: 7, ppuFormatK: 0x437a,
IPU1log=KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=egisterInterruptSource]:[39] end
IPMB initialization Start...
IPMB clock set done, prer = 0x18.
IPMB Rx FIFO clear empty.
IPMB initialization Done.
starting DFX Collect Task end
PowerTask Entry ...
Wait all vrd init done .
IPU0log= ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 7, mask: fffffffe
opposite dieId: 1, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
CPM max V[900]-
IPU1log= Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low
HSM0log=
IMU0log=..
All vrd init done, power task start
refresh domainId 0 Lsb 0x0
refresh domainId 9 Lsb 0x1
refresh domainId 2 Lsb 0x0
refresh domainId 7 Lsb 0x1
refresh domainId 4 Lsb 0x0
refresh domainId 1 Lsb 0x1
power sensor[0] | calib:512
IPU0log=F:2800
CPM min V[750]-F:1600
freq:2350, idx:9
cpm trim freq: 2600, idx: 4
cpm trim finish
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
recount hours 
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Fr
HSM0log=
IMU0log=0 | rshunt:1 | rshuntDiv:1000 | currLsb:1 | currLsbDiv:1000 | enableFlag:1
                | pwrLsb:25 | defPwr:25000 | minPwr:10000 | maxPwr:65000 | pwrFix:3400
                | manufacturerId: 0x5549 | dieId: 0x2260
power sen
IPU0log=0x984 
hiboost task entry
boost wait SEF.
boost param OK.
Totem[0] Core[ 0] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[26
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=sor[0] init success
ScmiTaskEntry start.
[RegisterInterruptSource]:[21] begin
Interrupt 51 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 52 register OK
[RegisterInterruptSource]
IPU0log=00000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[12000
IPU1log= Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 53 register OK
[RegisterInterruptSource]:[39] end
[0.01.29.230]starting ras Init
RAS Setup Value get done!
INT_NUM_PER_SKT * HiGetSktNum() = 0x8
index = 0x0
RasIntRegis
IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Lim
IPU1log=KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=ter init 160 
index = 0x1
RasIntRegister init 172 
index = 0x2
RasIntRegister init 162 
index = 0x3
RasIntRegister init 174 
index = 0x4
RasIntRegister init 184 
index = 0x5
RasIntRegister init 196 
index = 0x6
RasIntRegister in
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IPU1log= Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low
HSM0log=
IMU0log=it 186 
index = 0x7
RasIntRegister init 198 
RasIntRegister init 161 
RasIntRegister init 173 
RasIntRegister init 185 
RasIntRegister init 197 
RasIntRegister init 284 
RasIntRegister init 314 
MceTableHeadInit start
starting C
IPU0log=14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
To
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
uncore max freq : 23
HSM0log=
IMU0log=e_Storm Contrl and Ras_Data_Update Task end
[0.01.29.311]starting ras end
[IMU][ERR] skt id 0
Ub init task start Entry ...
UbInitTask Entry ...
[RegisterInterruptSource]:[21] begin
Interrupt 167 register OK
[RegisterInterrupt
IPU0log=tem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[26
IPU1log=50 MHz

HSM0log=
IMU0log=Source]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 191 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 171 register OK
[RegisterInterruptSource]:[39] end
[RegisterI
IPU0log=00000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[12000
IPU1log=
HSM0log=
IMU0log=nterruptSource]:[21] begin
Interrupt 183 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 195 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin

IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Lim
IPU1log=
HSM0log=
IMU0log=Interrupt 207 register OK
[RegisterInterruptSource]:[39] end
Init heart-beat-task end
CS0 flash do not support sfdp!
Current flash device ID[0x61a67c8]!
System supported 1 Flash.
flash cs 0 Manufacture 0xc8, DeviceId 0x1a67, Ad
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IPU1log=
HSM0log=
IMU0log=drMode[0-3B,1-4B] 0x1:
    size 0x4000000, pagesize 0x100
    read  cmd 0x13, dummy byte 0x8
    write cmd 0x12, dummy byte 0x0
    erase4k cmd 0x21, erase64k byte 0xdc
sfc init end
firstUnMskExt0Int
ThermalDimmStart Entry ...

IPU0log=33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
To
IPU1log=
HSM0log=
IMU0log=wait ddr init done...
HacLowPowerStart Entry ...
Hello LiteOS...
Init ReportPcieMmioToBmcTaskEntry end
starting Fpc Isolation Task end
pwr cap[0]: 0, 67
pwr cap[1]: f, 27
pwr cap[2]: 1, 3
BMC_COLLECTION: bmc req last log!
D
IPU0log=tem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[26
IPU1log=
HSM0log=
IMU0log=DR initing...
BMC_COLLECTION: bmc req last log!
DDR initing...
[0.02.00.454]DDR init done
[LOG]head = 0x0, tail = 0x1866, logSize = 0x1866
[IMU][ERR] HsmLogInit!
[IMU][ERR] HsmLogInit! TRUE
set apei done!
UbConfigData size is 64
IPU0log=00000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
uncore max freq : 2350 MHz

IPU1log=
HSM0log=
IMU0log=
UbConfigData 0 : 0
UbConfigData 1 : 0
UbConfigData 2 : 0
UbConfigData 3 : 1
UbConfigData 4 : 31
UbConfigData 5 : 1
UbConfigData 6 : 0
UbConfigData 7 : 32
UbConfigData 8 : 0
UbConfigData 9 : 1
UbConfigData 10 : 2
UbConfigData 11
IPU0log=
IPU1log=
HSM0log=
IMU0log= : 0
UbConfigData 12 : 0
UbConfigData 13 : 1
UbConfigData 14 : 0
UbConfigData 15 : 0
UbConfigData 16 : 0
UbConfigData 17 : 0
UbConfigData 18 : 0
UbConfigData 19 : 0
UbConfigData 20 : 0
UbConfigData 21 : 0
UbConfigData 22 : 11
Ub
IPU0log=
IPU1log=
HSM0log=
IMU0log=ConfigData 23 : 0
UbConfigData 24 : 0
UbConfigData 25 : 0
UbConfigData 26 : 0
UbConfigData 27 : 0
UbConfigData 28 : 0
UbConfigData 29 : 0
UbConfigData 30 : 0
UbConfigData 31 : 0
UbConfigData 32 : 0
UbConfigData 33 : 0
UbConfigDa
IPU0log=
IPU1log=
HSM0log=
IMU0log=ta 34 : 2
UbConfigData 35 : 1
UbConfigData 36 : 0
UbConfigData 37 : 0
UbConfigData 38 : 0
UbConfigData 39 : 0
UbConfigData 40 : 0
UbConfigData 41 : 0
UbConfigData 42 : 0
UbConfigData 43 : 0
UbConfigData 44 : 0
UbConfigData 45 : 
IPU0log=
IPU1log=
HSM0log=
IMU0log=0
UbConfigData 46 : 0
UbConfigData 47 : 0
UbConfigData 48 : 0
UbConfigData 49 : 0
UbConfigData 50 : 0
UbConfigData 51 : 0
UbConfigData 52 : 0
UbConfigData 53 : 0
UbConfigData 54 : 0
UbConfigData 55 : 0
UbConfigData 56 : 0
UbConf
IPU0log=
IPU1log=
HSM0log=
IMU0log=igData 57 : 0
UbConfigData 58 : 0
UbConfigData 59 : 0
UbConfigData 60 : 0
UbConfigData 61 : 0
UbConfigData 62 : 0
UbConfigData 63 : 0
UbConfigData 64 : 0
ClusterSwitch: 0, 0
ClusterMode: 0, 0
ControlMode: 0, 0
EnumMode: 1, 1
Bod
IPU0log=
IPU1log=
HSM0log=
IMU0log=yMask: 31, 31
CcCtxCount: 256, 256
RcCtxCount: 32, 32
UbMemEntrySize: 128, 0
MctpSupport: 1, 1
SecureMode: 0, 0
PrimaryCna: 0, 0
Upi: 0, 0
EntityId: 0, 0
SlotId: 1, 1
SocketId: 2, 2
PortIndex: 0, 0
PortCna: 0, 0
CtrlCna: 11, 11

IPU0log=
IPU1log=
HSM0log=
IMU0log=ImpBootFlag: 2, 2
ImuBootFlag: 1, 1
SktId: 0 DieId:2, HCCS_LINK:2 PaId:2
SktId: 1 DieId:2, HCCS_LINK:0 PaId:0
CIS register: ID[0xc00007ff], owner[0x1000003], function[0x1045dc5c].
CIS register: ID[0xc0000002], owner[0x1000003], 
IPU0log=
IPU1log=
HSM0log=
IMU0log=function[0x1045dcfc].
odf: can not find od file[config]
Do not get NII route table, disable NII Send function.
UbiosTaskStart Entry ...
UbiosTaskStart create task success
IMU ImpBootFlag: 0x2
skip IMP start config...
UbiosCisT
IPU0log=
IPU1log=
HSM0log=
IMU0log=ask Entry ...
BMC_COLLECTION: bmc req last log!
[IMU][ERR] [
HSM0log= no log data error!]
ddr init done, start thermal dimm task
======dimm status======
  chl[0] dimm0 1, dimm1 0
  chl[1] dimm0 0, dimm1 0
  chl[2] dimm0 0, dimm
IPU0log=
IPU1log=
HSM0log=
IMU0log=1 0
  chl[3] dimm0 0, dimm1 0
  chl[4] dimm0 0, dimm1 0
  chl[5] dimm0 0, dimm1 0
  chl[6] dimm0 0, dimm1 0
  chl[7] dimm0 0, dimm1 0
  chl[8] dimm0 0, dimm1 0
  chl[9] dimm0 0, dimm1 0
  chl[10] dimm0 0, dimm1 0
  chl[11] dimm0
IPU0log=
IPU1log=
HSM0log=
IMU0log= 0, dimm1 0
==========end==========
sktId[0] chl[0] registered, dimm mask = 0x1
======dimm status======
  chl[0] dimm0 1, dimm1 0
  chl[1] dimm0 0, dimm1 0
  chl[2] dimm0 0, dimm1 0
  chl[3] dimm0 0, dimm1 0
  chl[4] dimm0 0, di
IPU0log=
IPU1log=
HSM0log=
IMU0log=mm1 0
  chl[5] dimm0 0, dimm1 0
  chl[6] dimm0 0, dimm1 0
  chl[7] dimm0 0, dimm1 0
  chl[8] dimm0 0, dimm1 0
  chl[9] dimm0 0, dimm1 0
  chl[10] dimm0 0, dimm1 0
  chl[11] dimm0 0, dimm1 0
==========end==========
sktId[1] chl[0
IPU0log=
IPU1log=
HSM0log=
IMU0log=] registered, dimm mask = 0x1
=====dimm temp params=====
  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
  is_thermal_thro_en  : 1
  is_aref_rate_auto   : 0
===========end============
[0.02.07.470]TF Heartbeat
IPU0log=
IPU1log=
HSM0log=
IMU0log= Start
[0.02.08.797]RECEIVE MEM SILK.
0: skt = 0 logic = 1 phy = 0 
1: skt = 1 logic = 11 phy = 7 
2: skt = 0 logic = 4 phy = 2 
3: skt = 0 logic = 2 phy = 4 
4: skt = 1 logic = 0 phy = 8 
5: skt = 1 logic = 5 phy = 6 
6: skt = 
IPU0log=
IPU1log=
HSM0log=
IMU0log=1 logic = 9 phy = 11 
7: skt = 1 logic = 1 phy = 0 
8: skt = 1 logic = 8 phy = 5 
9: skt = 0 logic = 9 phy = 11 
10: skt = 1 logic = 7 phy = 1 
11: skt = 0 logic = 0 phy = 8 
12: skt = 0 logic = 6 phy = 9 
13: skt = 1 logic = 4 
IPU0log=
IPU1log=
HSM0log=
IMU0log=phy = 2 
14: skt = 1 logic = 2 phy = 4 
15: skt = 1 logic = 10 phy = 3 
16: skt = 0 logic = 3 phy = 10 
17: skt = 1 logic = 6 phy = 9 
18: skt = 0 logic = 10 phy = 3 
19: skt = 0 logic = 7 phy = 1 
20: skt = 1 logic = 3 phy = 10
IPU0log=
IPU1log=
HSM0log=
IMU0log= 
21: skt = 0 logic = 8 phy = 5 
22: skt = 0 logic = 5 phy = 6 
23: skt = 0 logic = 11 phy = 7 
get mem silk data length: 72
[0.02.11.763]PCIE INIT DONE.
[IMU][ERR] LOS_SemPend(g_pcieSemaphore, LOS_WAIT_FOREVER)
[RegisterInterru
IPU0log=
IPU1log=
HSM0log=
IMU0log=ptSource]:[21] begin
Interrupt 258 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 262 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interr
IPU0log=
IPU1log=
HSM0log=
IMU0log=upt 266 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 270 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 277 register OK
[Registe
IPU0log=
IPU1log=
HSM0log=
IMU0log=rInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 288 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 292 register OK
[RegisterInterruptSource]:[39] end

IPU0log=
IPU1log=
HSM0log=
IMU0log=[RegisterInterruptSource]:[21] begin
Interrupt 296 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 300 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[2
IPU0log=
IPU1log=
HSM0log=
IMU0log=1] begin
Interrupt 307 register OK
[RegisterInterruptSource]:[39] end
pmt Init done

-----------------ROUTE TABLE------------------
entryCount = 1
----------------------------------------------
[No.0]:
eidRange = 1, startEi
IPU0log=
IPU1log=
HSM0log=
IMU0log=d = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2100
----------------------------------------------
-----------------ROUTE TABLE------------------
entryCount = 2

IPU0log=
IPU1log=
HSM0log=
IMU0log=----------------------------------------------
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2100
[No.1]:
eidRange = 1, startEid =
IPU0log=
IPU1log=
HSM0log=
IMU0log= 10, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2500
----------------------------------------------
-----------------ROUTE TABLE------------------
entryCount = 2
--
IPU0log=
IPU1log=
HSM0log=
IMU0log=--------------------------------------------
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2100
[No.1]:
eidRange = 1, startEid = 1
IPU0log=
IPU1log=
HSM0log=
IMU0log=0, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2500
----------------------------------------------

IPU0log=
IPU1log=
HSM0log=
IMU0log=1T1N1U skt:0 CfgBusDfxPreConfig finish

********Hello Huawei LiteOS********

IMU Firmware Version : B173V01
LiteOS Kernel Version : 5.10.0
Run on Socket[0] Die[3]
Chip Version: 1
Max socket num: 2
*******************************
IPU0log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 0
cls: 6, core: 7
cpu 933 sram 1010 ddr 983
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  750|  802|  885|  933|
max  v
IPU1log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 1
cls: 6, core: 7
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  759|  821|  909|  961|
max  v: |  750|  750|  753|  781
HSM0log=[1970-01-01 00:01:12.430][HSM][INFO][30] init start
[1970-01-01 00:01:12.430][HSM][INFO][38] init over
[00:01:12.440][info] succeed to do thirdparty dfx_pabuk init
[00:01:12.445][info] os_mem_system_init default pool done
[0
IMU0log=***
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | rail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_vo
IPU0log=: |  750|  750|  754|  775|  836|  922|  980|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:7
IPU1log=|  846|  938|  994|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:750 F:1950
avs-uncore V:750
HSM0log=0:01:12.451][info] addr is already in region
[00:01:12.454][info] succeed to do thirdparty otpc_pabuk init
[1970-01-01 00:01:12.460][HSM][INFO][31] select_region: 0xc11cb55b
[1970-01-01 00:01:12.466][HSM][INFO][67] spi_nor de
IMU0log=lt:1122 mV | pmu:MP2882
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_v
IPU0log=50 F:1950
avs-uncore V:750 F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
av
IPU1log= F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
avs-uncore V:840 F:2450
avs-
HSM0log=vice_id 0xff1a67c8
[1970-01-01 00:01:12.472][HSM][INFO][50] std_cmd readback 0x30220d8
[1970-01-01 00:01:12.478][HSM][INFO][72] saf_cmd 0x0 readback 0x9f5a0604
[1970-01-01 00:01:12.484][HSM][INFO][72] saf_cmd 0x1 readback 0x5
IMU0log=olt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_
IPU0log=s-uncore V:840 F:2450
avs-uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain
IPU1log=uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | r
HSM0log=b7e938
[1970-01-01 00:01:12.490][HSM][INFO][72] saf_cmd 0x2 readback 0x1
[1970-01-01 00:01:12.496][HSM][INFO][72] saf_cmd 0x3 readback 0x0
[1970-01-01 00:01:12.502][HSM][INFO][72] saf_cmd 0x4 readback 0x0
[00:01:12.509][info
IMU0log=volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus r
IPU0log=[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | p
IPU1log=ail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_volt:1122 mV | pmu:MP2882
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[0] volt =  906 mV
pwr domain
HSM0log=] succeed to do thirdparty boot_profile_driver init
[00:01:12.514][info] succeed to do thirdparty crypto_driver init
[00:01:12.520][info] succeed to do thirdparty period_driver init
[00:01:12.526][info]  start loading interna
IMU0log=eady.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait th
IPU0log=mu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pmbus:0x480c0000 ver:0x110
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
IPU1log=[9] volt = 1103 mV
=end=
w&h rd rail:0, 906
w&h rd rail:1, 1103
pwr domain[0] set volt  904 mV succ
pwr domain[9] set volt 1103 mV succ
volt post
pwr domain[0] volt =  904 mV
pwr domain[9] volt = 1105 mV
==end==
Totem[0] Core Bo
HSM0log=l task ...
[00:01:12.530][info]  task name is ccm_task
[00:01:12.534][info]  hm_dynamic_loadelf successfully!
[00:01:12.539][info] internal task[1] task_name=ccm_task load successfully
[00:01:12.546][info]  task name is upgr
IMU0log=e cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master I
IPU0log=
avsbus resync succ
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[2] volt =  904 mV
pwr domain[7] volt =  802 mV
pwr domain[4] volt =  806 mV
pwr domain[1] volt =  804 mV
=end=
w&h rd rail:
IPU1log=ot Vol [1029]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2,
HSM0log=ade_task
[00:01:12.550][info]  hm_dynamic_loadelf successfully!
[00:01:12.555][info] internal task[2] task_name=upgrade_task load successfully
[00:01:12.562][info] created task ccm_task success!
[00:01:12.567][info] created 
IMU0log=mu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
cpu 0 entering scheduler
|--------------------------------------------------|
AtsPrint
|idx|lockCount| srcAddr| destAddr| addrLen|
|--
IPU0log=0, 904
w&h rd rail:1, 804
pwr domain[2] set volt  904 mV succ
pwr domain[7] set volt  802 mV succ
w&h rd rail:0, 806
w&h rd rail:1, 804
pwr domain[4] set volt  804 mV succ
pwr domain[1] set volt  802 mV succ
volt post
pwr domain
IPU1log= ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd8
HSM0log=task upgrade_task success!
[1970-01-01 00:01:12.571][HSM][INFO][54] Platform init 0x20250523 0x4e.
[1970-01-01 00:01:12.578][HSM][INFO][197] ccm start.
[1970-01-01 00:01:12.582][HSM][INFO][86] upgrade task init success.
[197
IMU0log=------------------------------------------------|
|  0|00000000|0x010500000|0x000110800000|0x00100000|
|  1|00000000|0x020000000|0x00001d000000|0x00800000|
|  2|00000000|0x020800000|0x000490000000|0x00100000|
|  3|00000000|0x020
IPU0log=[2] volt =  902 mV
pwr domain[7] volt =  802 mV
pwr domain[4] volt =  804 mV
pwr domain[1] volt =  802 mV
==end==
Totem[0] Core Boot Vol [1015]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0,
IPU1log=00, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
opposite dieId: 0, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 
HSM0log=0-01-01 00:01:12.588][HSM][INFO][95] upgrade recv cmd, 0x181.
[1970-01-01 00:01:12.594][HSM][INFO][103] upgrade res, 0x3a5aa5a3.
.
IMU0log=900000|0x000004000000|0x08000000|
|  4|00000000|0x028900000|0x000440580000|0x01000000|
|  5|00000000|0x029900000|0x000590000000|0x00100000|
|  6|00000000|0x029a00000|0x002000150000|0x00100000|
|  7|00000000|0x000000000|0x0000000
IPU0log= MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 
IPU1log=enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
hiboost task entry
boost wait SEF.
[INFO] mem used of task 'app_Task' is:0x2028, not zero when task being deleted
boost param OK.
Totem[0] Core[ 0] Freq Limit Low
HSM0log=
IMU0log=00000|0x00000000|
|  8|00000000|0x040000000|0x000000000000|0x08000000|
|  9|00000000|0x048000000|0x000000000000|0x08000000|
| 10|00000000|0x050000000|0x000000000000|0x08000000|
| 11|00000000|0x058000000|0x000000000000|0x08000000
IPU0log=0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
tsensor type
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Fr
HSM0log=
IMU0log=|
| 12|00000000|0x060000000|0x000000000000|0x08000000|
| 13|00000000|0x068000000|0x000000000000|0x08000000|
| 14|00000000|0x070000000|0x000000000000|0x08000000|
| 15|00000000|0x078000000|0x000490000000|0x08000000|
|-------------
IPU0log=: 3, ppuFormatK: 0x4da6, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b4,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 3, mask: fffffff8
tsensor type: 4, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=-------------------------------------|
=~=~=~=~=~=~=~=~=~=~= IMU Log @ 2026.5.13 1:46:49 =~=~=~=~=~=~=~=~=~=~=
[IMU] Watchdog Initialization done!
[RegisterInterruptSource]:[21] begin
Interrupt 32 register OK
Interrupt 34 regi
IPU0log=0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 4, mask: ffffffee
tsensor type: 5, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1

IPU1log= Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=ster OK
Interrupt 40 register OK
Interrupt 44 register OK
sram cnt 0x0, id = 43
Interrupt 43 register OK
Interrupt 36 register OK
Interrupt 57 register OK
sram cnt 0x0, id = 42
Interrupt 42 register OK
Interrupt 37 register OK
[
IPU0log=tsensor: 5, mask: ffffffda
tsensor type: 6, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 6, mask: ffffff80
tsensor type: 7, ppuFormatK: 0x437a,
IPU1log=KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=RegisterInterruptSource]:[39] end
IPMB initialization Start...
IPMB clock set done, prer = 0x18.
IPMB Rx FIFO clear empty.
IPMB initialization Done.
starting DFX Collect Task end
PowerTask Entry ...
Wait all vrd init done 
IPU0log= ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 7, mask: fffffffe
opposite dieId: 1, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
CPM max V[900]-
IPU1log= Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low
HSM0log=
IMU0log=...
All vrd init done, power task start
refresh domainId 0 Lsb 0x0
refresh domainId 9 Lsb 0x1
refresh domainId 2 Lsb 0x0
refresh domainId 7 Lsb 0x1
refresh domainId 4 Lsb 0x0
refresh domainId 1 Lsb 0x1
power sensor[0] | calib:51
IPU0log=F:2800
CPM min V[750]-F:1600
freq:2350, idx:9
cpm trim freq: 2600, idx: 4
cpm trim finish
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
recount hours 
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Fr
HSM0log=
IMU0log=20 | rshunt:1 | rshuntDiv:1000 | currLsb:1 | currLsbDiv:1000 | enableFlag:1
                | pwrLsb:25 | defPwr:25000 | minPwr:10000 | maxPwr:65000 | pwrFix:3400
                | manufacturerId: 0x5549 | dieId: 0x2260
power se
IPU0log=0x984 
hiboost task entry
boost wait SEF.
boost param OK.
Totem[0] Core[ 0] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[26
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=nsor[0] init success
ScmiTaskEntry start.
[RegisterInterruptSource]:[21] begin
Interrupt 51 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 52 register OK
[RegisterInterruptSource
IPU0log=00000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[12000
IPU1log= Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 53 register OK
[RegisterInterruptSource]:[39] end
[0.01.29.127]starting ras Init
RAS Setup Value get done!
INT_NUM_PER_SKT * HiGetSktNum() = 0x8
index = 0x0
RasIntRegi
IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Lim
IPU1log=KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=ster init 160 
index = 0x1
RasIntRegister init 172 
index = 0x2
RasIntRegister init 162 
index = 0x3
RasIntRegister init 174 
index = 0x4
RasIntRegister init 184 
index = 0x5
RasIntRegister init 196 
index = 0x6
RasIntRegister i
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IPU1log= Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low
HSM0log=
IMU0log=nit 186 
index = 0x7
RasIntRegister init 198 
RasIntRegister init 161 
RasIntRegister init 173 
RasIntRegister init 185 
RasIntRegister init 197 
RasIntRegister init 284 
RasIntRegister init 314 
MceTableHeadInit start
starting 
IPU0log=14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
To
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
uncore max freq : 23
HSM0log=
IMU0log=Ce_Storm Contrl and Ras_Data_Update Task end
[0.01.29.208]starting ras end
[IMU][ERR] skt id 0
Ub init task start Entry ...
UbInitTask Entry ...
[RegisterInterruptSource]:[21] begin
Interrupt 167 register OK
[RegisterInterrup
IPU0log=tem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[26
IPU1log=50 MHz

HSM0log=
IMU0log=tSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 191 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 171 register OK
[RegisterInterruptSource]:[39] end
[Register
IPU0log=00000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[12000
IPU1log=
HSM0log=
IMU0log=InterruptSource]:[21] begin
Interrupt 183 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 195 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Lim
IPU1log=
HSM0log=
IMU0log=
Interrupt 207 register OK
[RegisterInterruptSource]:[39] end
Init heart-beat-task end
CS0 flash do not support sfdp!
Current flash device ID[0x61a67c8]!
System supported 1 Flash.
flash cs 0 Manufacture 0xc8, DeviceId 0x1a67, A
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IPU1log=
HSM0log=
IMU0log=ddrMode[0-3B,1-4B] 0x1:
    size 0x4000000, pagesize 0x100
    read  cmd 0x13, dummy byte 0x8
    write cmd 0x12, dummy byte 0x0
    erase4k cmd 0x21, erase64k byte 0xdc
sfc init end
firstUnMskExt0Int
ThermalDimmStart Entry ...
IPU0log=33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
To
IPU1log=
HSM0log=
IMU0log=
wait ddr init done...
HacLowPowerStart Entry ...
Hello LiteOS...
pwr cap[0]: 0, 67
Init ReportPcieMmioToBmcTaskEntry end
starting Fpc Isolation Task end
BMC_COLLECTION: bmc req last log!
[IMU][ERR] [
IPU3log= no log data err
IPU0log=tem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[26
IPU1log=
HSM0log=
IMU0log=or!]
pwr cap[1]: f, 27
pwr cap[2]: 1, 3
[0.02.00.354]DDR init done
[LOG]head = 0x0, tail = 0x1851, logSize = 0x1851
[IMU][ERR] HsmLogInit!
[IMU][ERR] HsmLogInit! TRUE
set apei done!
UbConfigData size is 64
UbConfigData 0 : 0
U
IPU0log=00000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
uncore max freq : 2350 MHz

IPU1log=
HSM0log=
IMU0log=bConfigData 1 : 0
UbConfigData 2 : 0
UbConfigData 3 : 1
UbConfigData 4 : 31
UbConfigData 5 : 1
UbConfigData 6 : 0
UbConfigData 7 : 32
UbConfigData 8 : 0
UbConfigData 9 : 1
UbConfigData 10 : 2
UbConfigData 11 : 0
UbConfigData 12 
IPU0log=
IPU1log=
HSM0log=
IMU0log=: 0
UbConfigData 13 : 1
UbConfigData 14 : 0
UbConfigData 15 : 0
UbConfigData 16 : 0
UbConfigData 17 : 0
UbConfigData 18 : 0
UbConfigData 19 : 0
UbConfigData 20 : 0
UbConfigData 21 : 0
UbConfigData 22 : 11
UbConfigData 23 : 0
UbC
IPU0log=
IPU1log=
HSM0log=
IMU0log=onfigData 24 : 0
UbConfigData 25 : 0
UbConfigData 26 : 0
UbConfigData 27 : 0
UbConfigData 28 : 0
UbConfigData 29 : 0
UbConfigData 30 : 0
UbConfigData 31 : 0
UbConfigData 32 : 0
UbConfigData 33 : 0
UbConfigData 34 : 2
UbConfigDat
IPU0log=
IPU1log=
HSM0log=
IMU0log=a 35 : 1
UbConfigData 36 : 0
UbConfigData 37 : 0
UbConfigData 38 : 0
UbConfigData 39 : 0
UbConfigData 40 : 0
UbConfigData 41 : 0
UbConfigData 42 : 0
UbConfigData 43 : 0
UbConfigData 44 : 0
UbConfigData 45 : 0
UbConfigData 46 : 0
IPU0log=
IPU1log=
HSM0log=
IMU0log=
UbConfigData 47 : 0
UbConfigData 48 : 0
UbConfigData 49 : 0
UbConfigData 50 : 0
UbConfigData 51 : 0
UbConfigData 52 : 0
UbConfigData 53 : 0
UbConfigData 54 : 0
UbConfigData 55 : 0
UbConfigData 56 : 0
UbConfigData 57 : 0
UbConfi
IPU0log=
IPU1log=
HSM0log=
IMU0log=gData 58 : 0
UbConfigData 59 : 0
UbConfigData 60 : 0
UbConfigData 61 : 0
UbConfigData 62 : 0
UbConfigData 63 : 0
UbConfigData 64 : 0
ClusterSwitch: 0, 0
ClusterMode: 0, 0
ControlMode: 0, 0
EnumMode: 1, 1
BodyMask: 31, 31
CcCtxCo
IPU0log=
IPU1log=
HSM0log=
IMU0log=unt: 256, 256
RcCtxCount: 32, 32
UbMemEntrySize: 128, 0
MctpSupport: 1, 1
SecureMode: 0, 0
PrimaryCna: 0, 0
Upi: 0, 0
EntityId: 0, 0
SlotId: 1, 1
SocketId: 2, 2
PortIndex: 0, 0
PortCna: 0, 0
CtrlCna: 11, 11
ImpBootFlag: 2, 2
Imu
IPU0log=
IPU1log=
HSM0log=
IMU0log=BootFlag: 1, 1
SktId: 0 DieId:2, HCCS_LINK:2 PaId:2
SktId: 1 DieId:2, HCCS_LINK:0 PaId:0
CIS register: ID[0xc00007ff], owner[0x1000003], function[0x1045dc5c].
CIS register: ID[0xc0000002], owner[0x1000003], function[0x1045dcfc].
IPU0log=
IPU1log=
HSM0log=
IMU0log=
odf: can not find od file[config]
Do not get NII route table, disable NII Send function.
UbiosTaskStart Entry ...
UbiosTaskStart create task success
IMU ImpBootFlag: 0x2
skip IMP start config...
UbiosCisTask Entry ...
ddr in
IPU0log=
IPU1log=
HSM0log=
IMU0log=it done, start thermal dimm task
======dimm status======
  chl[0] dimm0 1, dimm1 0
  chl[1] dimm0 0, dimm1 0
  chl[2] dimm0 0, dimm1 0
  chl[3] dimm0 0, dimm1 0
  chl[4] dimm0 0, dimm1 0
  chl[5] dimm0 0, dimm1 0
  chl[6] dimm0 
IPU0log=
IPU1log=
HSM0log=
IMU0log=0, dimm1 0
  chl[7] dimm0 0, dimm1 0
  chl[8] dimm0 0, dimm1 0
  chl[9] dimm0 0, dimm1 0
  chl[10] dimm0 0, dimm1 0
  chl[11] dimm0 0, dimm1 0
==========end==========
sktId[0] chl[0] registered, dimm mask = 0x1
======dimm status
IPU0log=
IPU1log=
HSM0log=
IMU0log=======
  chl[0] dimm0 1, dimm1 0
  chl[1] dimm0 0, dimm1 0
  chl[2] dimm0 0, dimm1 0
  chl[3] dimm0 0, dimm1 0
  chl[4] dimm0 0, dimm1 0
  chl[5] dimm0 0, dimm1 0
  chl[6] dimm0 0, dimm1 0
  chl[7] dimm0 0, dimm1 0
  chl[8] dimm
IPU0log=
IPU1log=
HSM0log=
IMU0log=0 0, dimm1 0
  chl[9] dimm0 0, dimm1 0
  chl[10] dimm0 0, dimm1 0
  chl[11] dimm0 0, dimm1 0
==========end==========
sktId[1] chl[0] registered, dimm mask = 0x1
=====dimm temp params=====
  temp_threshold      : temp_mid:85,85 |
IPU0log=
IPU1log=
HSM0log=
IMU0log= temp_hi:95 | temp_cri:100
  is_thermal_thro_en  : 1
  is_aref_rate_auto   : 0
===========end============
[0.02.07.438]TF Heartbeat Start
[0.02.09.010]RECEIVE MEM SILK.
0: skt = 0 logic = 1 phy = 0 
1: skt = 1 logic = 11 phy = 7
IPU0log=
IPU1log=
HSM0log=
IMU0log= 
2: skt = 0 logic = 4 phy = 2 
3: skt = 0 logic = 2 phy = 4 
4: skt = 1 logic = 0 phy = 8 
5: skt = 1 logic = 5 phy = 6 
6: skt = 1 logic = 9 phy = 11 
7: skt = 1 logic = 1 phy = 0 
8: skt = 1 logic = 8 phy = 5 
9: skt = 0 logi
IPU0log=
IPU1log=
HSM0log=
IMU0log=c = 9 phy = 11 
10: skt = 1 logic = 7 phy = 1 
11: skt = 0 logic = 0 phy = 8 
12: skt = 0 logic = 6 phy = 9 
13: skt = 1 logic = 4 phy = 2 
14: skt = 1 logic = 2 phy = 4 
15: skt = 1 logic = 10 phy = 3 
16: skt = 0 logic = 3 phy
IPU0log=
IPU1log=
HSM0log=
IMU0log= = 10 
17: skt = 1 logic = 6 phy = 9 
18: skt = 0 logic = 10 phy = 3 
19: skt = 0 logic = 7 phy = 1 
20: skt = 1 logic = 3 phy = 10 
21: skt = 0 logic = 8 phy = 5 
22: skt = 0 logic = 5 phy = 6 
23: skt = 0 logic = 11 phy = 7 
g
IPU0log=
IPU1log=
HSM0log=
IMU0log=et mem silk data length: 72
[0.02.11.976]PCIE INIT DONE.
[IMU][ERR] LOS_SemPend(g_pcieSemaphore, LOS_WAIT_FOREVER)
[RegisterInterruptSource]:[21] begin
Interrupt 258 register OK
[RegisterInterruptSource]:[39] end
[RegisterInte
IPU0log=
IPU1log=
HSM0log=
IMU0log=rruptSource]:[21] begin
Interrupt 262 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 266 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Int
IPU0log=
IPU1log=
HSM0log=
IMU0log=errupt 270 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 277 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 288 register OK
[Regi
IPU0log=
IPU1log=
HSM0log=
IMU0log=sterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 292 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 296 register OK
[RegisterInterruptSource]:[39] en
IPU0log=
IPU1log=
HSM0log=
IMU0log=d
[RegisterInterruptSource]:[21] begin
Interrupt 300 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 307 register OK
[RegisterInterruptSource]:[39] end
pmt Init done

----------
IPU0log=
IPU1log=
HSM0log=
IMU0log=-------ROUTE TABLE------------------
entryCount = 2
----------------------------------------------
[No.0]:
eidRange = 1, startEid = 10, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSiz
IPU0log=
IPU1log=
HSM0log=
IMU0log=e = 2, bdf = 0x2500
[No.1]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2100
----------------------------------------------
------------
IPU0log=
IPU1log=
HSM0log=
IMU0log=-----ROUTE TABLE------------------
entryCount = 2
----------------------------------------------
[No.0]:
eidRange = 1, startEid = 10, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize 
IPU0log=
IPU1log=
HSM0log=
IMU0log== 2, bdf = 0x2500
[No.1]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2100
----------------------------------------------
--------------
IPU0log=
IPU1log=
HSM0log=
IMU0log=---ROUTE TABLE------------------
entryCount = 2
----------------------------------------------
[No.0]:
eidRange = 1, startEid = 10, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 
IPU0log=
IPU1log=
IMU0log=1T1N1U skt:0 CfgBusDfxPreConfig finish

********Hello Huawei LiteOS********

IMU Firmware Version : B173V01
LiteOS Kernel Version : 5.10.0
Run on Socket[0] Die[3]
Chip Version: 1
Max socket num: 2
*******************************
IPU0log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 0
cls: 6, core: 7
cpu 933 sram 1010 ddr 983
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  750|  802|  885|  933|
max  v
IPU1log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 1
cls: 6, core: 7
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  759|  821|  909|  961|
max  v: |  750|  750|  753|  781
HSM0log=[1970-01-01 00:01:12.120][HSM][INFO][30] init start
[1970-01-01 00:01:12.121][HSM][INFO][38] init over
[00:01:12.130][info] succeed to do thirdparty dfx_pabuk init
[00:01:12.136][info] os_mem_system_init default pool done
[0
IMU0log=***
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | rail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_vo
IPU0log=: |  750|  750|  754|  775|  836|  922|  980|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:7
IPU1log=|  846|  938|  994|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:750 F:1950
avs-uncore V:750
HSM0log=0:01:12.142][info] addr is already in region
[00:01:12.145][info] succeed to do thirdparty otpc_pabuk init
[1970-01-01 00:01:12.150][HSM][INFO][31] select_region: 0xc11cb55b
[1970-01-01 00:01:12.156][HSM][INFO][67] spi_nor de
IMU0log=lt:1122 mV | pmu:MP2882
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_v
IPU0log=50 F:1950
avs-uncore V:750 F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
av
IPU1log= F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
avs-uncore V:840 F:2450
avs-
HSM0log=vice_id 0xff1a67c8
[1970-01-01 00:01:12.162][HSM][INFO][50] std_cmd readback 0x30220d8
[1970-01-01 00:01:12.168][HSM][INFO][72] saf_cmd 0x0 readback 0x9f5a0604
[1970-01-01 00:01:12.175][HSM][INFO][72] saf_cmd 0x1 readback 0x5
IMU0log=olt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_
IPU0log=s-uncore V:840 F:2450
avs-uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain
IPU1log=uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | r
HSM0log=b7e938
[1970-01-01 00:01:12.181][HSM][INFO][72] saf_cmd 0x2 readback 0x1
[1970-01-01 00:01:12.187][HSM][INFO][72] saf_cmd 0x3 readback 0x0
[1970-01-01 00:01:12.193][HSM][INFO][72] saf_cmd 0x4 readback 0x0
[00:01:12.199][info
IMU0log=volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus r
IPU0log=[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | p
IPU1log=ail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_volt:1122 mV | pmu:MP2882
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[0] volt =  906 mV
pwr domain
HSM0log=] succeed to do thirdparty boot_profile_driver init
[00:01:12.205][info] succeed to do thirdparty crypto_driver init
[00:01:12.211][info] succeed to do thirdparty period_driver init
[00:01:12.216][info]  start loading interna
IMU0log=eady.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait th
IPU0log=mu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pmbus:0x480c0000 ver:0x110
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
IPU1log=[9] volt = 1105 mV
=end=
w&h rd rail:0, 906
w&h rd rail:1, 1103
pwr domain[0] set volt  904 mV succ
pwr domain[9] set volt 1103 mV succ
volt post
pwr domain[0] volt =  904 mV
pwr domain[9] volt = 1103 mV
==end==
Totem[0] Core Bo
HSM0log=l task ...
[00:01:12.221][info]  task name is ccm_task
[00:01:12.225][info]  hm_dynamic_loadelf successfully!
[00:01:12.230][info] internal task[1] task_name=ccm_task load successfully
[00:01:12.237][info]  task name is upgr
IMU0log=e cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master I
IPU0log=
avsbus resync succ
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[2] volt =  904 mV
pwr domain[7] volt =  804 mV
pwr domain[4] volt =  806 mV
pwr domain[1] volt =  806 mV
=end=
w&h rd rail:
IPU1log=ot Vol [1029]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2,
HSM0log=ade_task
[00:01:12.241][info]  hm_dynamic_loadelf successfully!
[00:01:12.246][info] internal task[2] task_name=upgrade_task load successfully
[00:01:12.253][info] created task ccm_task success!
[00:01:12.257][info] created 
IMU0log=mu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
cpu 0 entering scheduler
|--------------------------------------------------|
AtsPrint
|idx|lockCount| srcAddr| destAddr| addrLen|
|--
IPU0log=0, 904
w&h rd rail:1, 804
pwr domain[2] set volt  902 mV succ
pwr domain[7] set volt  802 mV succ
w&h rd rail:0, 806
w&h rd rail:1, 804
pwr domain[4] set volt  804 mV succ
pwr domain[1] set volt  804 mV succ
volt post
pwr domain
IPU1log= ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd8
HSM0log=task upgrade_task success!
[1970-01-01 00:01:12.262][HSM][INFO][54] Platform init 0x20250523 0x4e.
[1970-01-01 00:01:12.268][HSM][INFO][197] ccm start.
[1970-01-01 00:01:12.273][HSM][INFO][86] upgrade task init success.
[197
IMU0log=------------------------------------------------|
|  0|00000000|0x010500000|0x000110800000|0x00100000|
|  1|00000000|0x020000000|0x00001d000000|0x00800000|
|  2|00000000|0x020800000|0x000490000000|0x00100000|
|  3|00000000|0x020
IPU0log=[2] volt =  904 mV
pwr domain[7] volt =  800 mV
pwr domain[4] volt =  802 mV
pwr domain[1] volt =  804 mV
==end==
Totem[0] Core Boot Vol [1015]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0,
IPU1log=00, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
opposite dieId: 0, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 
HSM0log=0-01-01 00:01:12.279][HSM][INFO][95] upgrade recv cmd, 0x181.
[1970-01-01 00:01:12.285][HSM][INFO][103] upgrade res, 0x3a5aa5a3.
.
IMU0log=900000|0x000004000000|0x08000000|
|  4|00000000|0x028900000|0x000440580000|0x01000000|
|  5|00000000|0x029900000|0x000590000000|0x00100000|
|  6|00000000|0x029a00000|0x002000150000|0x00100000|
|  7|00000000|0x000000000|0x0000000
IPU0log= MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 
IPU1log=enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
hiboost task entry
boost wait SEF.
[INFO] mem used of task 'app_Task' is:0x2028, not zero when task being deleted
boost param OK.
Totem[0] Core[ 0] Freq Limit Low
HSM0log=
IMU0log=00000|0x00000000|
|  8|00000000|0x040000000|0x000000000000|0x08000000|
|  9|00000000|0x048000000|0x000000000000|0x08000000|
| 10|00000000|0x050000000|0x000000000000|0x08000000|
| 11|00000000|0x058000000|0x000000000000|0x08000000
IPU0log=0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
tsensor type
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Fr
HSM0log=
IMU0log=|
| 12|00000000|0x060000000|0x000000000000|0x08000000|
| 13|00000000|0x068000000|0x000000000000|0x08000000|
| 14|00000000|0x070000000|0x000000000000|0x08000000|
| 15|00000000|0x078000000|0x000490000000|0x08000000|
|-------------
IPU0log=: 3, ppuFormatK: 0x4da6, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b4,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 3, mask: fffffff8
tsensor type: 4, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=-------------------------------------|
=~=~=~=~=~=~=~=~=~=~= IMU Log @ 2026.5.13 1:57:59 =~=~=~=~=~=~=~=~=~=~=
[IMU] Watchdog Initialization done!
[RegisterInterruptSource]:[21] begin
Interrupt 32 register OK
Interrupt 34 regi
IPU0log=0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 4, mask: ffffffee
tsensor type: 5, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1

IPU1log= Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=ster OK
Interrupt 40 register OK
Interrupt 44 register OK
sram cnt 0x0, id = 43
Interrupt 43 register OK
Interrupt 36 register OK
Interrupt 57 register OK
sram cnt 0x0, id = 42
Interrupt 42 register OK
Interrupt 37 register OK
[
IPU0log=tsensor: 5, mask: ffffffda
tsensor type: 6, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 6, mask: ffffff80
tsensor type: 7, ppuFormatK: 0x437a,
IPU1log=KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=RegisterInterruptSource]:[39] end
IPMB initialization Start...
IPMB clock set done, prer = 0x18.
IPMB Rx FIFO clear empty.
IPMB initialization Done.
starting DFX Collect Task end
PowerTask Entry ...
Wait all vrd init done 
IPU0log= ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 7, mask: fffffffe
opposite dieId: 1, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
CPM max V[900]-
IPU1log= Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low
HSM0log=
IMU0log=...
All vrd init done, power task start
refresh domainId 0 Lsb 0x0
refresh domainId 9 Lsb 0x1
refresh domainId 2 Lsb 0x0
refresh domainId 7 Lsb 0x1
refresh domainId 4 Lsb 0x0
refresh domainId 1 Lsb 0x1
power sensor[0] | calib:51
IPU0log=F:2800
CPM min V[750]-F:1600
freq:2350, idx:9
cpm trim freq: 2600, idx: 4
cpm trim finish
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
recount hours 
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Fr
HSM0log=
IMU0log=20 | rshunt:1 | rshuntDiv:1000 | currLsb:1 | currLsbDiv:1000 | enableFlag:1
                | pwrLsb:25 | defPwr:25000 | minPwr:10000 | maxPwr:65000 | pwrFix:3400
                | manufacturerId: 0x5549 | dieId: 0x2260
power se
IPU0log=0x984 
hiboost task entry
boost wait SEF.
boost param OK.
Totem[0] Core[ 0] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[26
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=nsor[0] init success
ScmiTaskEntry start.
[RegisterInterruptSource]:[21] begin
Interrupt 51 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 52 register OK
[RegisterInterruptSource
IPU0log=00000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[12000
IPU1log= Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 53 register OK
[RegisterInterruptSource]:[39] end
[0.01.28.816]starting ras Init
RAS Setup Value get done!
INT_NUM_PER_SKT * HiGetSktNum() = 0x8
index = 0x0
RasIntRegi
IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Lim
IPU1log=KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=ster init 160 
index = 0x1
RasIntRegister init 172 
index = 0x2
RasIntRegister init 162 
index = 0x3
RasIntRegister init 174 
index = 0x4
RasIntRegister init 184 
index = 0x5
RasIntRegister init 196 
index = 0x6
RasIntRegister i
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IPU1log= Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low
HSM0log=
IMU0log=nit 186 
index = 0x7
RasIntRegister init 198 
RasIntRegister init 161 
RasIntRegister init 173 
RasIntRegister init 185 
RasIntRegister init 197 
RasIntRegister init 284 
RasIntRegister init 314 
MceTableHeadInit start
starting 
IPU0log=14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
To
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
uncore max freq : 23
HSM0log=
IMU0log=Ce_Storm Contrl and Ras_Data_Update Task end
[0.01.28.898]starting ras end
[IMU][ERR] skt id 0
Ub init task start Entry ...
UbInitTask Entry ...
[RegisterInterruptSource]:[21] begin
Interrupt 167 register OK
[RegisterInterrup
IPU0log=tem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[26
IPU1log=50 MHz

HSM0log=
IMU0log=tSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 191 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 171 register OK
[RegisterInterruptSource]:[39] end
[Register
IPU0log=00000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[12000
IPU1log=
HSM0log=
IMU0log=InterruptSource]:[21] begin
Interrupt 183 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 195 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Lim
IPU1log=
HSM0log=
IMU0log=
Interrupt 207 register OK
[RegisterInterruptSource]:[39] end
Init heart-beat-task end
CS0 flash do not support sfdp!
Current flash device ID[0x61a67c8]!
System supported 1 Flash.
flash cs 0 Manufacture 0xc8, DeviceId 0x1a67, A
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IPU1log=
HSM0log=
IMU0log=ddrMode[0-3B,1-4B] 0x1:
    size 0x4000000, pagesize 0x100
    read  cmd 0x13, dummy byte 0x8
    write cmd 0x12, dummy byte 0x0
    erase4k cmd 0x21, erase64k byte 0xdc
sfc init end
firstUnMskExt0Int
ThermalDimmStart Entry ...
IPU0log=33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
To
IPU1log=
HSM0log=
IMU0log=
wait ddr init done...
HacLowPowerStart Entry ...
Hello LiteOS...
pwr cap[0]: 0, 67
Init ReportPcieMmioToBmcTaskEntry end
starting Fpc Isolation Task end
BMC_COLLECTION: bmc req last log!
DDR initing...
pwr cap[1]: f, 27
pwr
IPU0log=tem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[26
IPU1log=
HSM0log=
IMU0log= cap[2]: 1, 3
BMC_COLLECTION: bmc req last log!
DDR initing...
BMC_COLLECTION: bmc req last log!
DDR initing...
[0.02.00.066]DDR init done
[LOG]head = 0x0, tail = 0x1898, logSize = 0x1898
[IMU][ERR] HsmLogInit!
[IMU][ERR] HsmLo
IPU0log=00000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
uncore max freq : 2350 MHz

IPU1log=
HSM0log=
IMU0log=gInit! TRUE
set apei done!
UbConfigData size is 64
UbConfigData 0 : 0
UbConfigData 1 : 0
UbConfigData 2 : 0
UbConfigData 3 : 1
UbConfigData 4 : 31
UbConfigData 5 : 1
UbConfigData 6 : 0
UbConfigData 7 : 32
UbConfigData 8 : 0
UbCo
IPU0log=
IPU1log=
HSM0log=
IMU0log=nfigData 9 : 1
UbConfigData 10 : 2
UbConfigData 11 : 0
UbConfigData 12 : 0
UbConfigData 13 : 1
UbConfigData 14 : 0
UbConfigData 15 : 0
UbConfigData 16 : 0
UbConfigData 17 : 0
UbConfigData 18 : 0
UbConfigData 19 : 0
UbConfigData 
IPU0log=
IPU1log=
HSM0log=
IMU0log=20 : 0
UbConfigData 21 : 0
UbConfigData 22 : 11
UbConfigData 23 : 0
UbConfigData 24 : 0
UbConfigData 25 : 0
UbConfigData 26 : 0
UbConfigData 27 : 0
UbConfigData 28 : 0
UbConfigData 29 : 0
UbConfigData 30 : 0
UbConfigData 31 : 0

IPU0log=
IPU1log=
HSM0log=
IMU0log=UbConfigData 32 : 0
UbConfigData 33 : 0
UbConfigData 34 : 2
UbConfigData 35 : 1
UbConfigData 36 : 0
UbConfigData 37 : 0
UbConfigData 38 : 0
UbConfigData 39 : 0
UbConfigData 40 : 0
UbConfigData 41 : 0
UbConfigData 42 : 0
UbConfig
IPU0log=
IPU1log=
HSM0log=
IMU0log=Data 43 : 0
UbConfigData 44 : 0
UbConfigData 45 : 0
UbConfigData 46 : 0
UbConfigData 47 : 0
UbConfigData 48 : 0
UbConfigData 49 : 0
UbConfigData 50 : 0
UbConfigData 51 : 0
UbConfigData 52 : 0
UbConfigData 53 : 0
UbConfigData 54 
IPU0log=
IPU1log=
HSM0log=
IMU0log=: 0
UbConfigData 55 : 0
UbConfigData 56 : 0
UbConfigData 57 : 0
UbConfigData 58 : 0
UbConfigData 59 : 0
UbConfigData 60 : 0
UbConfigData 61 : 0
UbConfigData 62 : 0
UbConfigData 63 : 0
UbConfigData 64 : 0
ClusterSwitch: 0, 0
Clus
IPU0log=
IPU1log=
HSM0log=
IMU0log=terMode: 0, 0
ControlMode: 0, 0
EnumMode: 1, 1
BodyMask: 31, 31
CcCtxCount: 256, 256
RcCtxCount: 32, 32
UbMemEntrySize: 128, 0
MctpSupport: 1, 1
SecureMode: 0, 0
PrimaryCna: 0, 0
Upi: 0, 0
EntityId: 0, 0
SlotId: 1, 1
SocketId: 2
IPU0log=
IPU1log=
HSM0log=
IMU0log=, 2
PortIndex: 0, 0
PortCna: 0, 0
CtrlCna: 11, 11
ImpBootFlag: 2, 2
ImuBootFlag: 1, 1
SktId: 0 DieId:2, HCCS_LINK:2 PaId:2
SktId: 1 DieId:2, HCCS_LINK:0 PaId:0
CIS register: ID[0xc00007ff], owner[0x1000003], function[0x1045dc5c]
IPU0log=
IPU1log=
HSM0log=
IMU0log=.
CIS register: ID[0xc0000002], owner[0x1000003], function[0x1045dcfc].
odf: can not find od file[config]
Do not get NII route table, disable NII Send function.
UbiosTaskStart Entry ...
UbiosTaskStart create task success
IMU I
IPU0log=
IPU1log=
HSM0log=
IMU0log=mpBootFlag: 0x2
skip IMP start config...
UbiosCisTask Entry ...
ddr init done, start thermal dimm task
======dimm status======
  chl[0] dimm0 1, dimm1 0
  chl[1] dimm0 0, dimm1 0
  chl[2] dimm0 0, dimm1 0
  chl[3] dimm0 0, dimm
IPU0log=
IPU1log=
HSM0log=
IMU0log=1 0
  chl[4] dimm0 0, dimm1 0
  chl[5] dimm0 0, dimm1 0
  chl[6] dimm0 0, dimm1 0
  chl[7] dimm0 0, dimm1 0
  chl[8] dimm0 0, dimm1 0
  chl[9] dimm0 0, dimm1 0
  chl[10] dimm0 0, dimm1 0
  chl[11] dimm0 0, dimm1 0
==========end=
IPU0log=
IPU1log=
HSM0log=
IMU0log==========
sktId[0] chl[0] registered, dimm mask = 0x1
======dimm status======
  chl[0] dimm0 1, dimm1 0
  chl[1] dimm0 0, dimm1 0
  chl[2] dimm0 0, dimm1 0
  chl[3] dimm0 0, dimm1 0
  chl[4] dimm0 0, dimm1 0
  chl[5] dimm0 0, di
IPU0log=
IPU1log=
HSM0log=
IMU0log=mm1 0
  chl[6] dimm0 0, dimm1 0
  chl[7] dimm0 0, dimm1 0
  chl[8] dimm0 0, dimm1 0
  chl[9] dimm0 0, dimm1 0
  chl[10] dimm0 0, dimm1 0
  chl[11] dimm0 0, dimm1 0
==========end==========
sktId[1] chl[0] registered, dimm mask = 
IPU0log=
IPU1log=
HSM0log=
IMU0log=0x1
=====dimm temp params=====
  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
  is_thermal_thro_en  : 1
  is_aref_rate_auto   : 0
===========end============
BMC_COLLECTION: bmc req last log!
[IMU][ERR] [
HSM0
IPU0log=
IPU1log=
HSM0log=
IMU0log=log= no log data error!]
[0.02.07.019]TF Heartbeat Start
[0.02.08.480]RECEIVE MEM SILK.
0: skt = 0 logic = 1 phy = 0 
1: skt = 1 logic = 11 phy = 7 
2: skt = 0 logic = 4 phy = 2 
3: skt = 0 logic = 2 phy = 4 
4: skt = 1 logic = 
IPU0log=
IPU1log=
HSM0log=
IMU0log=0 phy = 8 
5: skt = 1 logic = 5 phy = 6 
6: skt = 1 logic = 9 phy = 11 
7: skt = 1 logic = 1 phy = 0 
8: skt = 1 logic = 8 phy = 5 
9: skt = 0 logic = 9 phy = 11 
10: skt = 1 logic = 7 phy = 1 
11: skt = 0 logic = 0 phy = 8 
12:
IPU0log=
IPU1log=
HSM0log=
IMU0log= skt = 0 logic = 6 phy = 9 
13: skt = 1 logic = 4 phy = 2 
14: skt = 1 logic = 2 phy = 4 
15: skt = 1 logic = 10 phy = 3 
16: skt = 0 logic = 3 phy = 10 
17: skt = 1 logic = 6 phy = 9 
18: skt = 0 logic = 10 phy = 3 
19: skt = 0
IPU0log=
IPU1log=
HSM0log=
IMU0log= logic = 7 phy = 1 
20: skt = 1 logic = 3 phy = 10 
21: skt = 0 logic = 8 phy = 5 
22: skt = 0 logic = 5 phy = 6 
23: skt = 0 logic = 11 phy = 7 
get mem silk data length: 72
[0.02.11.446]PCIE INIT DONE.
[IMU][ERR] LOS_SemPend(g
IPU0log=
IPU1log=
HSM0log=
IMU0log=_pcieSemaphore, LOS_WAIT_FOREVER)
[RegisterInterruptSource]:[21] begin
Interrupt 258 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 262 register OK
[RegisterInterruptSource]:[39]
IPU0log=
IPU1log=
HSM0log=
IMU0log= end
[RegisterInterruptSource]:[21] begin
Interrupt 266 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 270 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSour
IPU0log=
IPU1log=
HSM0log=
IMU0log=ce]:[21] begin
Interrupt 277 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 288 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 29
IPU0log=
IPU1log=
HSM0log=
IMU0log=2 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 296 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 300 register OK
[RegisterInter
IPU0log=
IPU1log=
HSM0log=
IMU0log=ruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 307 register OK
[RegisterInterruptSource]:[39] end
pmt Init done

-----------------ROUTE TABLE------------------
entryCount = 1
----------------------------
IPU0log=
IPU1log=
HSM0log=
IMU0log=------------------
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2100
----------------------------------------------
-------------
IPU0log=
IPU1log=
HSM0log=
IMU0log=----ROUTE TABLE------------------
entryCount = 2
----------------------------------------------
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 
IPU0log=
IPU1log=
HSM0log=
IMU0log=2, bdf = 0x2100
[No.1]:
eidRange = 1, startEid = 10, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2500
----------------------------------------------
---------------
IPU0log=
IPU1log=
HSM0log=
IMU0log=--ROUTE TABLE------------------
entryCount = 2
----------------------------------------------
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2,
IPU0log=
IPU1log=
HSM0log=
IMU0log= bdf = 0x2100
[No.1]:
eidRange = 1, startEid = 10, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2500
----------------------------------------------
HotPlug Open
slo
IPU0log=
IPU1log=
HSM0log=
IMU0log=tNum = 42
portIdx = 0
portIdx = 1
portIdx = 2
portIdx = 3
portIdx = 4
portIdx = 5
portIdx = 6
portIdx = 7
portIdx = 8
portIdx = 9
portIdx = a
portIdx = b
portIdx = c
portIdx = d
portIdx = e
portIdx = f
portIdx =
IPU0log=
IPU1log=
HSM0log=
IMU0log= 10
portIdx = 11
portIdx = 12
portIdx = 13
portIdx = 14
portIdx = 15
portIdx = 16
portIdx = 17
portIdx = 18
portIdx = 19
portIdx = 1a
portIdx = 1b
portIdx = 1c
portIdx = 1d
portIdx = 1e
portIdx = 1f
portIdx = 20
IPU0log=
IPU1log=
HSM0log=
IMU0log=
portIdx = 40
portIdx = 41
portIdx = 42
portIdx = 43
portIdx = 44
portIdx = 45
portIdx = 46
portIdx = 47
portIdx = 48
portIdx = 49
portIdx = 4a
portIdx = 4b
portIdx = 4c
portIdx = 4d
portIdx = 4e
portIdx = 4f
por
IPU0log=
IPU1log=
HSM0log=
IMU0log=tIdx = 50
portIdx = 51
portIdx = 52
portIdx = 53
portIdx = 54
portIdx = 55
portIdx = 56
portIdx = 57
portIdx = 58
portIdx = 59
portIdx = 5a
portIdx = 5b
portIdx = 5c
portIdx = 5d
portIdx = 5e
portIdx = 5f
portIdx
IPU0log=
IPU1log=
HSM0log=
IMU0log= = 60
Pcie slot[0] port:0 base 0x2c01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[0] port:0 base 0x2c01000000, pcieSlotCtrl.data (after)0x0.

Pcie slot[1] port
IPU0log=
IPU1log=
HSM0log=
IMU0log=:1 base 0x2c01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[1] port:1 base 0x2c01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[2] port:2 base 0x2c0100000
IPU0log=
IPU1log=
HSM0log=
IMU0log=0, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[2] port:2 base 0x2c01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[3] port:3 base 0x2c01000000, pcieSlotCtrl.dat
IPU0log=
IPU1log=
HSM0log=
IMU0log=a (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[3] port:3 base 0x2c01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[4] port:4 base 0x2c01000000, pcieSlotCtrl.data (before)0x10003c0
IPU0log=
IPU1log=
HSM0log=
IMU0log=.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[4] port:4 base 0x2c01000000, pcieSlotCtrl.data (after)0x14801c0.

Pcie slot[5] port:5 base 0x2c01000000, pcieSlotCtrl.data (before)0x3c0.
pcieSlotCtrl.
IPU0log=
IPU1log=
HSM0log=
IMU0log=bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[5] port:5 base 0x2c01000000, pcieSlotCtrl.data (after)0x4801c0.

Pcie slot[6] port:6 base 0x2c01000000, pcieSlotCtrl.data (before)0x3c0.
pcieSlotCtrl.bits.presencd_det
IPU0log=
IPU1log=
HSM0log=
IMU0log=_st = 1
present:1, pwr_en:0.
Pcie slot[6] port:6 base 0x2c01000000, pcieSlotCtrl.data (after)0x4801c0.

Pcie slot[7] port:7 base 0x2c01000000, pcieSlotCtrl.data (before)0x3c0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:
IPU0log=
IPU1log=
HSM0log=
IMU0log=1, pwr_en:0.
Pcie slot[7] port:7 base 0x2c01000000, pcieSlotCtrl.data (after)0x4801c0.

Pcie slot[8] port:8 base 0x2c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie 
IPU0log=
IPU1log=
HSM0log=
IMU0log=slot[8] port:8 base 0x2c02000000, pcieSlotCtrl.data (after)0x0.

Pcie slot[9] port:9 base 0x2c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[9] port:9 base 0x2c
IPU0log=
IPU1log=
HSM0log=
IMU0log=02000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[10] port:10 base 0x2c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[10] port:10 base 0x2c02000000, pcieS
IPU0log=
IPU1log=
HSM0log=
IMU0log=lotCtrl.data (after)0x480100.

Pcie slot[11] port:11 base 0x2c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[11] port:11 base 0x2c02000000, pcieSlotCtrl.data (a
IPU0log=
IPU1log=
HSM0log=
IMU0log=fter)0x480100.

Pcie slot[12] port:12 base 0x2c02000000, pcieSlotCtrl.data (before)0x10003c0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[12] port:12 base 0x2c02000000, pcieSlotCtrl.data (after)0x14
IPU0log=
IPU1log=
HSM0log=
IMU0log=801c0.

Pcie slot[13] port:13 base 0x2c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[13] port:13 base 0x2c02000000, pcieSlotCtrl.data (after)0x480100.

Pcie 
IPU0log=
IPU1log=
HSM0log=
IMU0log=slot[14] port:14 base 0x2c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[14] port:14 base 0x2c02000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[15] port:1
IPU0log=
IPU1log=
HSM0log=
IMU0log=5 base 0x2c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[15] port:15 base 0x2c02000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[16] port:16 base 0x2d0100
IPU0log=
IPU1log=
HSM0log=
IMU0log=0000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[16] port:16 base 0x2d01000000, pcieSlotCtrl.data (after)0x0.

Pcie slot[17] port:17 base 0x2d01000000, pcieSlotCtrl.d
IPU0log=
IPU1log=
HSM0log=
IMU0log=ata (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[17] port:17 base 0x2d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[18] port:18 base 0x2d01000000, pcieSlotCtrl.data (before)0x0
IPU0log=
IPU1log=
HSM0log=
IMU0log=.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[18] port:18 base 0x2d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[19] port:19 base 0x2d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl
IPU0log=
IPU1log=
HSM0log=
IMU0log=.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[19] port:19 base 0x2d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[20] port:20 base 0x2d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_
IPU0log=
IPU1log=
HSM0log=
IMU0log=det_st = 1
present:1, pwr_en:0.
Pcie slot[20] port:20 base 0x2d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[21] port:21 base 0x2d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
pre
IPU0log=
IPU1log=
HSM0log=
IMU0log=sent:1, pwr_en:0.
Pcie slot[21] port:21 base 0x2d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[22] port:22 base 0x2d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:
IPU0log=
IPU1log=
HSM0log=
IMU0log=0.
Pcie slot[22] port:22 base 0x2d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[23] port:23 base 0x2d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[2
IPU0log=
IPU1log=
HSM0log=
IMU0log=3] port:23 base 0x2d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[24] port:24 base 0x2d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[24] port:24 base
IPU0log=
IPU1log=
HSM0log=
IMU0log= 0x2d02000000, pcieSlotCtrl.data (after)0x0.

Pcie slot[25] port:25 base 0x2d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[25] port:25 base 0x2d02000000, pcieS
IPU0log=
IPU1log=
HSM0log=
IMU0log=lotCtrl.data (after)0x700.

Pcie slot[26] port:26 base 0x2d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[26] port:26 base 0x2d02000000, pcieSlotCtrl.data (afte
IPU0log=
IPU1log=
HSM0log=
IMU0log=r)0x700.

Pcie slot[27] port:27 base 0x2d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[27] port:27 base 0x2d02000000, pcieSlotCtrl.data (after)0x700.

Pcie s
IPU0log=
IPU1log=
HSM0log=
IMU0log=lot[28] port:28 base 0x2d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[28] port:28 base 0x2d02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[29] port:29 ba
IPU0log=
IPU1log=
HSM0log=
IMU0log=se 0x2d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[29] port:29 base 0x2d02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[30] port:30 base 0x2d02000000, p
IPU0log=
IPU1log=
HSM0log=
IMU0log=cieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[30] port:30 base 0x2d02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[31] port:31 base 0x2d02000000, pcieSlotCtrl.data (
IPU0log=
IPU1log=
HSM0log=
IMU0log=before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[31] port:31 base 0x2d02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[32] port:32 base 0x3210000000, pcieSlotCtrl.data (before)0x0.
pcieS
IPU0log=
IPU1log=
HSM0log=
IMU0log=lotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[32] port:32 base 0x3210000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[33] port:0 base 0x6c01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presen
IPU0log=
IPU1log=
HSM0log=
IMU0log=cd_det_st = 1
present:1, pwr_en:0.
Pcie slot[33] port:0 base 0x6c01000000, pcieSlotCtrl.data (after)0x0.

Pcie slot[34] port:1 base 0x6c01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present
IPU0log=
IPU1log=
HSM0log=
IMU0log=:1, pwr_en:0.
Pcie slot[34] port:1 base 0x6c01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[35] port:2 base 0x6c01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pc
IPU0log=
IPU1log=
HSM0log=
IMU0log=ie slot[35] port:2 base 0x6c01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[36] port:3 base 0x6c01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[36] port:
IPU0log=
IPU1log=
HSM0log=
IMU0log=3 base 0x6c01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[37] port:4 base 0x6c01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[37] port:4 base 0x6c010000
IPU0log=
IPU1log=
HSM0log=
IMU0log=00, pcieSlotCtrl.data (after)0x480100.

Pcie slot[38] port:5 base 0x6c01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[38] port:5 base 0x6c01000000, pcieSlotCtrl.
IPU0log=
IPU1log=
HSM0log=
IMU0log=data (after)0x480100.

Pcie slot[39] port:6 base 0x6c01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[39] port:6 base 0x6c01000000, pcieSlotCtrl.data (after)0x480
IPU0log=
IPU1log=
HSM0log=
IMU0log=100.

Pcie slot[40] port:7 base 0x6c01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[40] port:7 base 0x6c01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot
IPU0log=
IPU1log=
HSM0log=
IMU0log=[41] port:8 base 0x6c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[41] port:8 base 0x6c02000000, pcieSlotCtrl.data (after)0x0.

Pcie slot[42] port:9 base 0x6c0
IPU0log=
IPU1log=
HSM0log=
IMU0log=2000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[42] port:9 base 0x6c02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[43] port:10 base 0x6c02000000, pcieSlotCt
IPU0log=
IPU1log=
HSM0log=
IMU0log=rl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[43] port:10 base 0x6c02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[44] port:11 base 0x6c02000000, pcieSlotCtrl.data (before)0x
IPU0log=
IPU1log=
HSM0log=
IMU0log=0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[44] port:11 base 0x6c02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[45] port:12 base 0x6c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.b
IPU0log=
IPU1log=
HSM0log=
IMU0log=its.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[45] port:12 base 0x6c02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[46] port:13 base 0x6c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_s
IPU0log=
IPU1log=
HSM0log=
IMU0log=t = 0
present:0, pwr_en:1.
Pcie slot[46] port:13 base 0x6c02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[47] port:14 base 0x6c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, 
IPU0log=
IPU1log=
HSM0log=
IMU0log=pwr_en:1.
Pcie slot[47] port:14 base 0x6c02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[48] port:15 base 0x6c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie sl
IPU0log=
IPU1log=
HSM0log=
IMU0log=ot[48] port:15 base 0x6c02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[49] port:16 base 0x6d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[49] port:16 bas
IPU0log=
IPU1log=
HSM0log=
IMU0log=e 0x6d01000000, pcieSlotCtrl.data (after)0x0.

Pcie slot[50] port:17 base 0x6d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[50] port:17 base 0x6d01000000, pcie
IPU0log=
IPU1log=
HSM0log=
IMU0log=SlotCtrl.data (after)0x480100.

Pcie slot[51] port:18 base 0x6d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[51] port:18 base 0x6d01000000, pcieSlotCtrl.data (
IPU0log=
IPU1log=
HSM0log=
IMU0log=after)0x480100.

Pcie slot[52] port:19 base 0x6d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[52] port:19 base 0x6d01000000, pcieSlotCtrl.data (after)0x480100.
IPU0log=
IPU1log=
HSM0log=
IMU0log=

Pcie slot[53] port:20 base 0x6d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[53] port:20 base 0x6d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[5
IPU0log=
IPU1log=
HSM0log=
IMU0log=4] port:21 base 0x6d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[54] port:21 base 0x6d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[55] port:22 base
IPU0log=
IPU1log=
HSM0log=
IMU0log= 0x6d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[55] port:22 base 0x6d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[56] port:23 base 0x6d01000000, 
IPU0log=
IPU1log=
HSM0log=
IMU0log=pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[56] port:23 base 0x6d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[57] port:24 base 0x6d02000000, pcieSlotCtrl.da
IPU0log=
IPU1log=
HSM0log=
IMU0log=ta (before)0x3c0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[57] port:24 base 0x6d02000000, pcieSlotCtrl.data (after)0x7c0.

Pcie slot[58] port:25 base 0x6d02000000, pcieSlotCtrl.data (before)0x0.
IPU0log=
IPU1log=
HSM0log=
IMU0log=
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[58] port:25 base 0x6d02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[59] port:26 base 0x6d02000000, pcieSlotCtrl.data (before)0x3c0.
pcieSlotCtrl.bi
IPU0log=
IPU1log=
HSM0log=
IMU0log=ts.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[59] port:26 base 0x6d02000000, pcieSlotCtrl.data (after)0x7c0.

Pcie slot[60] port:27 base 0x6d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st
IPU0log=
IPU1log=
HSM0log=
IMU0log= = 0
present:0, pwr_en:1.
Pcie slot[60] port:27 base 0x6d02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[61] port:28 base 0x6d02000000, pcieSlotCtrl.data (before)0x3c0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0,
IPU0log=
IPU1log=
HSM0log=
IMU0log= pwr_en:1.
Pcie slot[61] port:28 base 0x6d02000000, pcieSlotCtrl.data (after)0x7c0.

Pcie slot[62] port:29 base 0x6d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie s
IPU0log=
IPU1log=
HSM0log=
IMU0log=lot[62] port:29 base 0x6d02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[63] port:30 base 0x6d02000000, pcieSlotCtrl.data (before)0x3c0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[63] port:30 
IPU0log=
IPU1log=
HSM0log=
IMU0log=base 0x6d02000000, pcieSlotCtrl.data (after)0x7c0.

Pcie slot[64] port:31 base 0x6d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[64] port:31 base 0x6d02000000,
IPU0log=
IPU1log=
HSM0log=
IMU0log= pcieSlotCtrl.data (after)0x700.

Pcie slot[65] port:32 base 0x7210000000, pcieSlotCtrl.data (before)0xffffffff.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[65] port:32 base 0x7210000000, pcieSlotCt
IPU0log=
IPU1log=
HSM0log=
IMU0log=rl.data (after)0xffffffff.

[RegisterInterruptSource]:[21] begin
Interrupt 61 register OK
[RegisterInterruptSource]:[39] end
fristMskExt0Int

Pcie Hotplug init done, with 66 port(s).
[0.06.28.802]BIOS POST END.
slot[0] por
IPU0log=
IPU1log=
HSM0log=
IMU0log=t:0 begin to power ON.
slot[0] port:0 pwr_indicator = 0, att_indicator = 0
ledStatus:0 invalid!
[HotPlugMonitorTask][248L]Pcie slot[0] port:0 base 0x2c01000000, pcieSlotCtrl.data (after)0x100000.
slot[1] port:1 begin to powe
IPU0log=
IPU1log=
HSM0log=
IMU0log=r ON.
slot[2] port:2 begin to power ON.
slot[3] port:3 begin to power ON.
slot[4] port:4 begin to power ON.
slot[5] port:5 begin to power ON.
slot[6] port:6 begin to power ON.
slot[7] port:7 begin to power ON.
slot[8] por
IPU0log=
IPU1log=
HSM0log=
IMU0log=t:8 begin to power ON.
slot[8] port:8 pwr_indicator = 0, att_indicator = 0
ledStatus:0 invalid!
[HotPlugMonitorTask][248L]Pcie slot[8] port:8 base 0x2c02000000, pcieSlotCtrl.data (after)0x100000.
slot[9] port:9 begin to powe
IPU0log=
IPU1log=
HSM0log=
IMU0log=r ON.
slot[10] port:10 begin to power ON.
slot[11] port:11 begin to power ON.
slot[12] port:12 begin to power ON.
slot[13] port:13 begin to power ON.
slot[14] port:14 begin to power ON.
slot[15] port:15 begin to power ON.
IPU0log=
IPU1log=
HSM0log=
IMU0log=
slot[16] port:16 begin to power ON.
slot[16] port:16 pwr_indicator = 0, att_indicator = 0
ledStatus:0 invalid!
[HotPlugMonitorTask][248L]Pcie slot[16] port:16 base 0x2d01000000, pcieSlotCtrl.data (after)0x100000.
slot[17] p
IPU0log=
IPU1log=
HSM0log=
IMU0log=ort:17 begin to power ON.
slot[18] port:18 begin to power ON.
slot[19] port:19 begin to power ON.
slot[20] port:20 begin to power ON.
slot[21] port:21 begin to power ON.
slot[22] port:22 begin to power ON.
slot[23] port:23
IPU0log=
IPU1log=
HSM0log=
IMU0log= begin to power ON.
slot[24] port:24 pwr_indicator = 0, att_indicator = 0
ledStatus:0 invalid!
[HotPlugMonitorTask][248L]Pcie slot[24] port:24 base 0x2d02000000, pcieSlotCtrl.data (after)0x100000.
slot[25] port:25 begin to p
IPU0log=
IPU1log=
HSM0log=
IMU0log=ower OFF.
slot[26] port:26 begin to power OFF.
slot[27] port:27 begin to power OFF.
slot[28] port:28 begin to power OFF.
slot[29] port:29 begin to power OFF.
slot[30] port:30 begin to power OFF.
slot[31] port:31 begin to p
IPU0log=
IPU1log=
HSM0log=
IMU0log=ower OFF.
slot[32] port:32 begin to power OFF.
slot[33] port:0 begin to power ON.
slot[33] port:0 pwr_indicator = 0, att_indicator = 0
ledStatus:0 invalid!
[HotPlugMonitorTask][248L]Pcie slot[33] port:0 base 0x6c01000000, p
IPU0log=
IPU1log=
HSM0log=
IMU0log=cieSlotCtrl.data (after)0x100000.
slot[34] port:1 begin to power ON.
slot[35] port:2 begin to power ON.
slot[36] port:3 begin to power ON.
slot[37] port:4 begin to power ON.
slot[38] port:5 begin to power ON.
slot[39] port
IPU0log=
IPU1log=
HSM0log=
IMU0log=:6 begin to power ON.
slot[40] port:7 begin to power ON.
slot[41] port:8 pwr_indicator = 0, att_indicator = 0
ledStatus:0 invalid!
[HotPlugMonitorTask][248L]Pcie slot[41] port:8 base 0x6c02000000, pcieSlotCtrl.data (after)0x
IPU0log=
IPU1log=
HSM0log=
IMU0log=100000.
slot[42] port:9 begin to power OFF.
slot[43] port:10 begin to power OFF.
slot[44] port:11 begin to power OFF.
slot[45] port:12 begin to power OFF.
slot[46] port:13 begin to power OFF.
slot[47] port:14 begin to powe
IPU0log=
IPU1log=
HSM0log=
IMU0log=r OFF.
slot[48] port:15 begin to power OFF.
slot[49] port:16 begin to power ON.
slot[49] port:16 pwr_indicator = 0, att_indicator = 0
ledStatus:0 invalid!
[HotPlugMonitorTask][248L]Pcie slot[49] port:16 base 0x6d01000000, p
IPU0log=
IPU1log=
HSM0log=
IMU0log=cieSlotCtrl.data (after)0x100000.
slot[50] port:17 begin to power ON.
slot[51] port:18 begin to power ON.
slot[52] port:19 begin to power ON.
slot[53] port:20 begin to power ON.
slot[54] port:21 begin to power ON.
slot[55]
IPU0log=
IPU1log=
HSM0log=
IMU0log= port:22 begin to power ON.
slot[56] port:23 begin to power ON.
slot[57] port:24 begin to power OFF.
slot[58] port:25 begin to power OFF.
slot[59] port:26 begin to power OFF.
slot[60] port:27 begin to power OFF.
slot[61] p
IPU0log=
IPU1log=
HSM0log=
IMU0log=ort:28 begin to power OFF.
slot[62] port:29 begin to power OFF.
slot[63] port:30 begin to power OFF.
slot[64] port:31 begin to power OFF.
[0.06.29.361]wait 5 mins to update pciemmio..
slot[65] port:32 begin to power OFF.
[0
IPU0log=
IPU1log=
HSM0log=
IMU0log=.11.29.361]IpmiCmdReportPcieMMIO start
[0.11.33.093]IpmiCmdReportPcieMMIO end

IPU0log=
IPU1log=
HSM0log=
IMU0log=1T1N1U skt:0 CfgBusDfxPreConfig finish

********Hello Huawei LiteOS********

IMU Firmware Version : B173V01
LiteOS Kernel Version : 5.10.0
Run on Socket[0] Die[3]
Chip Version: 1
Max socket num: 2
*******************************
IPU0log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 0
cls: 6, core: 7
cpu 933 sram 1010 ddr 983
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  750|  802|  885|  933|
max  v
IPU1log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 1
cls: 6, core: 7
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  759|  821|  909|  961|
max  v: |  750|  750|  753|  781
HSM0log=[1970-01-01 00:01:12.329][HSM][INFO][30] init start
[1970-01-01 00:01:12.329][HSM][INFO][38] init over
[00:01:12.339][info] succeed to do thirdparty dfx_pabuk init
[00:01:12.344][info] os_mem_system_init default pool done
[0
IMU0log=***
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | rail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_vo
IPU0log=: |  750|  750|  754|  775|  836|  922|  980|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:7
IPU1log=|  846|  938|  994|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:750 F:1950
avs-uncore V:750
HSM0log=0:01:12.351][info] addr is already in region
[00:01:12.353][info] succeed to do thirdparty otpc_pabuk init
[1970-01-01 00:01:12.359][HSM][INFO][31] select_region: 0xc11cb55b
[1970-01-01 00:01:12.365][HSM][INFO][67] spi_nor de
IMU0log=lt:1122 mV | pmu:MP2882
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_v
IPU0log=50 F:1950
avs-uncore V:750 F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
av
IPU1log= F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
avs-uncore V:840 F:2450
avs-
HSM0log=vice_id 0xff1a67c8
[1970-01-01 00:01:12.371][HSM][INFO][50] std_cmd readback 0x30220d8
[1970-01-01 00:01:12.377][HSM][INFO][72] saf_cmd 0x0 readback 0x9f5a0604
[1970-01-01 00:01:12.383][HSM][INFO][72] saf_cmd 0x1 readback 0x5
IMU0log=olt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_
IPU0log=s-uncore V:840 F:2450
avs-uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain
IPU1log=uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | r
HSM0log=b7e938
[1970-01-01 00:01:12.390][HSM][INFO][72] saf_cmd 0x2 readback 0x1
[1970-01-01 00:01:12.396][HSM][INFO][72] saf_cmd 0x3 readback 0x0
[1970-01-01 00:01:12.401][HSM][INFO][72] saf_cmd 0x4 readback 0x0
[00:01:12.408][info
IMU0log=volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus r
IPU0log=[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | p
IPU1log=ail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_volt:1122 mV | pmu:MP2882
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[0] volt =  906 mV
pwr domain
HSM0log=] succeed to do thirdparty boot_profile_driver init
[00:01:12.413][info] succeed to do thirdparty crypto_driver init
[00:01:12.419][info] succeed to do thirdparty period_driver init
[00:01:12.425][info]  start loading interna
IMU0log=eady.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait th
IPU0log=mu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pmbus:0x480c0000 ver:0x110
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
IPU1log=[9] volt = 1103 mV
=end=
w&h rd rail:0, 906
w&h rd rail:1, 1103
pwr domain[0] set volt  906 mV succ
pwr domain[9] set volt 1105 mV succ
volt post
pwr domain[0] volt =  904 mV
pwr domain[9] volt = 1103 mV
==end==
Totem[0] Core Bo
HSM0log=l task ...
[00:01:12.430][info]  task name is ccm_task
[00:01:12.434][info]  hm_dynamic_loadelf successfully!
[00:01:12.438][info] internal task[1] task_name=ccm_task load successfully
[00:01:12.445][info]  task name is upgr
IMU0log=e cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master I
IPU0log=
avsbus resync succ
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[2] volt =  904 mV
pwr domain[7] volt =  802 mV
pwr domain[4] volt =  806 mV
pwr domain[1] volt =  804 mV
=end=
w&h rd rail:
IPU1log=ot Vol [1029]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2,
HSM0log=ade_task
[00:01:12.449][info]  hm_dynamic_loadelf successfully!
[00:01:12.454][info] internal task[2] task_name=upgrade_task load successfully
[00:01:12.461][info] created task ccm_task success!
[00:01:12.466][info] created 
IMU0log=mu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
cpu 0 entering scheduler
|--------------------------------------------------|
AtsPrint
|idx|lockCount| srcAddr| destAddr| addrLen|
|--
IPU0log=0, 904
w&h rd rail:1, 804
pwr domain[2] set volt  902 mV succ
pwr domain[7] set volt  802 mV succ
w&h rd rail:0, 806
w&h rd rail:1, 804
pwr domain[4] set volt  804 mV succ
pwr domain[1] set volt  802 mV succ
volt post
pwr domain
IPU1log= ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd8
HSM0log=task upgrade_task success!
[1970-01-01 00:01:12.471][HSM][INFO][54] Platform init 0x20250523 0x4e.
[1970-01-01 00:01:12.477][HSM][INFO][197] ccm start.
[1970-01-01 00:01:12.482][HSM][INFO][86] upgrade task init success.
[197
IMU0log=------------------------------------------------|
|  0|00000000|0x010500000|0x000110800000|0x00100000|
|  1|00000000|0x020000000|0x00001d000000|0x00800000|
|  2|00000000|0x020800000|0x000490000000|0x00100000|
|  3|00000000|0x020
IPU0log=[2] volt =  902 mV
pwr domain[7] volt =  800 mV
pwr domain[4] volt =  802 mV
pwr domain[1] volt =  804 mV
==end==
Totem[0] Core Boot Vol [1015]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0,
IPU1log=00, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
opposite dieId: 0, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 
HSM0log=0-01-01 00:01:12.488][HSM][INFO][95] upgrade recv cmd, 0x181.
[1970-01-01 00:01:12.493][HSM][INFO][103] upgrade res, 0x3a5aa5a3.
.
IMU0log=900000|0x000004000000|0x08000000|
|  4|00000000|0x028900000|0x000440580000|0x01000000|
|  5|00000000|0x029900000|0x000590000000|0x00100000|
|  6|00000000|0x029a00000|0x002000150000|0x00100000|
|  7|00000000|0x000000000|0x0000000
IPU0log= MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 
IPU1log=enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
hiboost task entry
boost wait SEF.
[INFO] mem used of task 'app_Task' is:0x2028, not zero when task being deleted
boost param OK.
Totem[0] Core[ 0] Freq Limit Low
HSM0log=
IMU0log=00000|0x00000000|
|  8|00000000|0x040000000|0x000000000000|0x08000000|
|  9|00000000|0x048000000|0x000000000000|0x08000000|
| 10|00000000|0x050000000|0x000000000000|0x08000000|
| 11|00000000|0x058000000|0x000000000000|0x08000000
IPU0log=0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
tsensor type
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Fr
HSM0log=
IMU0log=|
| 12|00000000|0x060000000|0x000000000000|0x08000000|
| 13|00000000|0x068000000|0x000000000000|0x08000000|
| 14|00000000|0x070000000|0x000000000000|0x08000000|
| 15|00000000|0x078000000|0x000490000000|0x08000000|
|-------------
IPU0log=: 3, ppuFormatK: 0x4da6, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b4,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 3, mask: fffffff8
tsensor type: 4, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=-------------------------------------|
=~=~=~=~=~=~=~=~=~=~= IMU Log @ 2026.5.13 2:36:22 =~=~=~=~=~=~=~=~=~=~=
[IMU] Watchdog Initialization done!
[RegisterInterruptSource]:[21] begin
Interrupt 32 register OK
Interrupt 34 regi
IPU0log=0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 4, mask: ffffffee
tsensor type: 5, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1

IPU1log= Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=ster OK
Interrupt 40 register OK
Interrupt 44 register OK
sram cnt 0x0, id = 43
Interrupt 43 register OK
Interrupt 36 register OK
Interrupt 57 register OK
sram cnt 0x0, id = 42
Interrupt 42 register OK
Interrupt 37 register OK
[
IPU0log=tsensor: 5, mask: ffffffda
tsensor type: 6, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 6, mask: ffffff80
tsensor type: 7, ppuFormatK: 0x437a,
IPU1log=KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=RegisterInterruptSource]:[39] end
IPMB initialization Start...
IPMB clock set done, prer = 0x18.
IPMB Rx FIFO clear empty.
IPMB initialization Done.
starting DFX Collect Task end
PowerTask Entry ...
Wait all vrd init done 
IPU0log= ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 7, mask: fffffffe
opposite dieId: 1, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
CPM max V[900]-
IPU1log= Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low
HSM0log=
IMU0log=...
All vrd init done, power task start
refresh domainId 0 Lsb 0x0
refresh domainId 9 Lsb 0x1
refresh domainId 2 Lsb 0x0
refresh domainId 7 Lsb 0x1
refresh domainId 4 Lsb 0x0
refresh domainId 1 Lsb 0x1
power sensor[0] | calib:51
IPU0log=F:2800
CPM min V[750]-F:1600
freq:2350, idx:9
cpm trim freq: 2600, idx: 4
cpm trim finish
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
recount hours 
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Fr
HSM0log=
IMU0log=20 | rshunt:1 | rshuntDiv:1000 | currLsb:1 | currLsbDiv:1000 | enableFlag:1
                | pwrLsb:25 | defPwr:25000 | minPwr:10000 | maxPwr:65000 | pwrFix:3400
                | manufacturerId: 0x5549 | dieId: 0x2260
power se
IPU0log=0x984 
hiboost task entry
boost wait SEF.
boost param OK.
Totem[0] Core[ 0] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[26
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=nsor[0] init success
ScmiTaskEntry start.
[RegisterInterruptSource]:[21] begin
Interrupt 51 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 52 register OK
[RegisterInterruptSource
IPU0log=00000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[12000
IPU1log= Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 53 register OK
[RegisterInterruptSource]:[39] end
[0.01.29.024]starting ras Init
RAS Setup Value get done!
INT_NUM_PER_SKT * HiGetSktNum() = 0x8
index = 0x0
RasIntRegi
IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Lim
IPU1log=KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=ster init 160 
index = 0x1
RasIntRegister init 172 
index = 0x2
[IMU][ERR] IMP log not ready, DDR initing...
RasIntRegister init 162 
index = 0x3
RasIntRegister init 174 
index = 0x4
RasIntRegister init 184 
index = 0x5
RasIntRe
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IPU1log= Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low
HSM0log=
IMU0log=gister init 196 
index = 0x6
RasIntRegister init 186 
index = 0x7
RasIntRegister init 198 
RasIntRegister init 161 
RasIntRegister init 173 
RasIntRegister init 185 
RasIntRegister init 197 
RasIntRegister init 284 
RasIntRegist
IPU0log=14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
To
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
uncore max freq : 23
HSM0log=
IMU0log=er init 314 
starting Ce_Storm Contrl and Ras_Data_Update Task end
[0.01.29.105]starting ras end
MceTableHeadInit start
[IMU][ERR] skt id 0
Ub init task start Entry ...
[RegisterInterruptSource]:[21] begin
UbInitTask Entry ...
IPU0log=tem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[26
IPU1log=50 MHz

HSM0log=
IMU0log=
Interrupt 167 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 191 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 171 register OK

IPU0log=00000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[12000
IPU1log=
HSM0log=
IMU0log=[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 183 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 195 register OK
[RegisterInterruptSource]:[3
IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Lim
IPU1log=
HSM0log=
IMU0log=9] end
[RegisterInterruptSource]:[21] begin
Interrupt 207 register OK
[RegisterInterruptSource]:[39] end
Init heart-beat-task end
CS0 flash do not support sfdp!
Current flash device ID[0x61a67c8]!
System supported 1 Flash.
fl
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IPU1log=
HSM0log=
IMU0log=ash cs 0 Manufacture 0xc8, DeviceId 0x1a67, AddrMode[0-3B,1-4B] 0x1:
    size 0x4000000, pagesize 0x100
    read  cmd 0x13, dummy byte 0x8
    write cmd 0x12, dummy byte 0x0
    erase4k cmd 0x21, erase64k byte 0xdc
sfc init end

IPU0log=33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
To
IPU1log=
HSM0log=
IMU0log=firstUnMskExt0Int
ThermalDimmStart Entry ...
wait ddr init done...
HacLowPowerStart Entry ...
Hello LiteOS...
Init ReportPcieMmioToBmcTaskEntry end
starting Fpc Isolation Task end
pwr cap[0]: 0, 67
pwr cap[1]: f, 27
pwr cap
IPU0log=tem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[26
IPU1log=
HSM0log=
IMU0log=[2]: 1, 3
[IMU][ERR] IMP log not ready, DDR initing...
[IMU][ERR] IMP log not ready, DDR initing...
[0.02.00.274]DDR init done
[LOG]head = 0x0, tail = 0x188c, logSize = 0x188c
[IMU][ERR] HsmLogInit!
[IMU][ERR] HsmLogInit! TRUE

IPU0log=00000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
uncore max freq : 2350 MHz

IPU1log=
HSM0log=
IMU0log=set apei done!
UbConfigData size is 64
UbConfigData 0 : 0
UbConfigData 1 : 0
UbConfigData 2 : 0
UbConfigData 3 : 1
UbConfigData 4 : 31
UbConfigData 5 : 1
UbConfigData 6 : 0
UbConfigData 7 : 32
UbConfigData 8 : 0
UbConfigData 9 :
IPU0log=
IPU1log=
HSM0log=
IMU0log= 1
UbConfigData 10 : 2
UbConfigData 11 : 0
UbConfigData 12 : 0
UbConfigData 13 : 1
UbConfigData 14 : 0
UbConfigData 15 : 0
UbConfigData 16 : 0
UbConfigData 17 : 0
UbConfigData 18 : 0
UbConfigData 19 : 0
UbConfigData 20 : 0
UbCon
IPU0log=
IPU1log=
HSM0log=
IMU0log=figData 21 : 0
UbConfigData 22 : 11
UbConfigData 23 : 0
UbConfigData 24 : 0
UbConfigData 25 : 0
UbConfigData 26 : 0
UbConfigData 27 : 0
UbConfigData 28 : 0
UbConfigData 29 : 0
UbConfigData 30 : 0
UbConfigData 31 : 0
UbConfigData
IPU0log=
IPU1log=
HSM0log=
IMU0log= 32 : 0
UbConfigData 33 : 0
UbConfigData 34 : 2
UbConfigData 35 : 1
UbConfigData 36 : 0
UbConfigData 37 : 0
UbConfigData 38 : 0
UbConfigData 39 : 0
UbConfigData 40 : 0
UbConfigData 41 : 0
UbConfigData 42 : 0
UbConfigData 43 : 0

IPU0log=
IPU1log=
HSM0log=
IMU0log=UbConfigData 44 : 0
UbConfigData 45 : 0
UbConfigData 46 : 0
UbConfigData 47 : 0
UbConfigData 48 : 0
UbConfigData 49 : 0
UbConfigData 50 : 0
UbConfigData 51 : 0
UbConfigData 52 : 0
UbConfigData 53 : 0
UbConfigData 54 : 0
UbConfig
IPU0log=
IPU1log=
HSM0log=
IMU0log=Data 55 : 0
UbConfigData 56 : 0
UbConfigData 57 : 0
UbConfigData 58 : 0
UbConfigData 59 : 0
UbConfigData 60 : 0
UbConfigData 61 : 0
UbConfigData 62 : 0
UbConfigData 63 : 0
UbConfigData 64 : 0
ClusterSwitch: 0, 0
ClusterMode: 0, 
IPU0log=
IPU1log=
HSM0log=
IMU0log=0
ControlMode: 0, 0
EnumMode: 1, 1
BodyMask: 31, 31
CcCtxCount: 256, 256
RcCtxCount: 32, 32
UbMemEntrySize: 128, 0
MctpSupport: 1, 1
SecureMode: 0, 0
PrimaryCna: 0, 0
Upi: 0, 0
EntityId: 0, 0
SlotId: 1, 1
SocketId: 2, 2
PortInde
IPU0log=
IPU1log=
HSM0log=
IMU0log=x: 0, 0
PortCna: 0, 0
CtrlCna: 11, 11
ImpBootFlag: 2, 2
ImuBootFlag: 1, 1
SktId: 0 DieId:2, HCCS_LINK:2 PaId:2
SktId: 1 DieId:2, HCCS_LINK:0 PaId:0
CIS register: ID[0xc00007ff], owner[0x1000003], function[0x1045dc5c].
CIS regist
IPU0log=
IPU1log=
HSM0log=
IMU0log=er: ID[0xc0000002], owner[0x1000003], function[0x1045dcfc].
odf: can not find od file[config]
Do not get NII route table, disable NII Send function.
UbiosTaskStart Entry ...
UbiosTaskStart create task success
IMU ImpBootFlag: 
IPU0log=
IPU1log=
HSM0log=
IMU0log=0x2
skip IMP start config...
UbiosCisTask Entry ...
ddr init done, start thermal dimm task
======dimm status======
  chl[0] dimm0 1, dimm1 0
  chl[1] dimm0 0, dimm1 0
  chl[2] dimm0 0, dimm1 0
  chl[3] dimm0 0, dimm1 0
  chl[4]
IPU0log=
IPU1log=
HSM0log=
IMU0log= dimm0 0, dimm1 0
  chl[5] dimm0 0, dimm1 0
  chl[6] dimm0 0, dimm1 0
  chl[7] dimm0 0, dimm1 0
  chl[8] dimm0 0, dimm1 0
  chl[9] dimm0 0, dimm1 0
  chl[10] dimm0 0, dimm1 0
  chl[11] dimm0 0, dimm1 0
==========end==========
sk
IPU0log=
IPU1log=
HSM0log=
IMU0log=tId[0] chl[0] registered, dimm mask = 0x1
======dimm status======
  chl[0] dimm0 1, dimm1 0
  chl[1] dimm0 0, dimm1 0
  chl[2] dimm0 0, dimm1 0
  chl[3] dimm0 0, dimm1 0
  chl[4] dimm0 0, dimm1 0
  chl[5] dimm0 0, dimm1 0
  chl[
IPU0log=
IPU1log=
HSM0log=
IMU0log=6] dimm0 0, dimm1 0
  chl[7] dimm0 0, dimm1 0
  chl[8] dimm0 0, dimm1 0
  chl[9] dimm0 0, dimm1 0
  chl[10] dimm0 0, dimm1 0
  chl[11] dimm0 0, dimm1 0
==========end==========
sktId[1] chl[0] registered, dimm mask = 0x1
=====dim
IPU0log=
IPU1log=
HSM0log=
IMU0log=m temp params=====
  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
  is_thermal_thro_en  : 1
  is_aref_rate_auto   : 0
===========end============
[IMU][ERR] [
IMP1log= no log data error!]
[0.02.07.294]TF Heart
IPU0log=
IPU1log=
HSM0log=
IMU0log=beat Start
[0.02.08.631]RECEIVE MEM SILK.
0: skt = 0 logic = 1 phy = 0 
1: skt = 1 logic = 11 phy = 7 
2: skt = 0 logic = 4 phy = 2 
3: skt = 0 logic = 2 phy = 4 
4: skt = 1 logic = 0 phy = 8 
5: skt = 1 logic = 5 phy = 6 
6: sk
IPU0log=
IPU1log=
HSM0log=
IMU0log=t = 1 logic = 9 phy = 11 
7: skt = 1 logic = 1 phy = 0 
8: skt = 1 logic = 8 phy = 5 
9: skt = 0 logic = 9 phy = 11 
10: skt = 1 logic = 7 phy = 1 
11: skt = 0 logic = 0 phy = 8 
12: skt = 0 logic = 6 phy = 9 
13: skt = 1 logic 
IPU0log=
IPU1log=
HSM0log=
IMU0log== 4 phy = 2 
14: skt = 1 logic = 2 phy = 4 
15: skt = 1 logic = 10 phy = 3 
16: skt = 0 logic = 3 phy = 10 
17: skt = 1 logic = 6 phy = 9 
18: skt = 0 logic = 10 phy = 3 
19: skt = 0 logic = 7 phy = 1 
20: skt = 1 logic = 3 phy 
IPU0log=
IPU1log=
HSM0log=
IMU0log== 10 
21: skt = 0 logic = 8 phy = 5 
22: skt = 0 logic = 5 phy = 6 
23: skt = 0 logic = 11 phy = 7 
get mem silk data length: 72
[0.02.11.604]PCIE INIT DONE.
[IMU][ERR] LOS_SemPend(g_pcieSemaphore, LOS_WAIT_FOREVER)
[RegisterInt
IPU0log=
IPU1log=
HSM0log=
IMU0log=erruptSource]:[21] begin
Interrupt 258 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 262 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
In
IPU0log=
IPU1log=
HSM0log=
IMU0log=terrupt 266 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 270 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 277 register OK
[Reg
IPU0log=
IPU1log=
HSM0log=
IMU0log=isterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 288 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 292 register OK
[RegisterInterruptSource]:[39] e
IPU0log=
IPU1log=
HSM0log=
IMU0log=nd
[RegisterInterruptSource]:[21] begin
Interrupt 296 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 300 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource
IPU0log=
IPU1log=
HSM0log=
IMU0log=]:[21] begin
Interrupt 307 register OK
[RegisterInterruptSource]:[39] end
pmt Init done

-----------------ROUTE TABLE------------------
entryCount = 1
----------------------------------------------
[No.0]:
eidRange = 1, sta
IPU0log=
IPU1log=
HSM0log=
IMU0log=rtEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2100
----------------------------------------------
-----------------ROUTE TABLE------------------
entryCount 
IPU0log=
IPU1log=
HSM0log=
IMU0log== 2
----------------------------------------------
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2100
[No.1]:
eidRange = 1, startE
IPU0log=
IPU1log=
HSM0log=
IMU0log=id = 10, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2500
----------------------------------------------
-----------------ROUTE TABLE------------------
entryCount = 
IPU0log=
IPU1log=
HSM0log=
IMU0log=2
----------------------------------------------
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2100
[No.1]:
eidRange = 1, startEid
IPU0log=
IPU1log=
HSM0log=
IMU0log= = 10, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2500
----------------------------------------------

IPU0log=
IPU1log=
HSM0log=
IMU0log=1T1N1U skt:0 CfgBusDfxPreConfig finish

********Hello Huawei LiteOS********

IMU Firmware Version : B173V01
LiteOS Kernel Version : 5.10.0
Run on Socket[0] Die[3]
Chip Version: 1
Max socket num: 2
*******************************
IPU0log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 0
cls: 6, core: 7
cpu 933 sram 1010 ddr 983
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  750|  802|  885|  933|
max  v
IPU1log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 1
cls: 6, core: 7
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  759|  821|  909|  961|
max  v: |  750|  750|  753|  781
HSM0log=[1970-01-01 00:01:12.210][HSM][INFO][30] init start
[1970-01-01 00:01:12.210][HSM][INFO][38] init over
[00:01:12.220][info] succeed to do thirdparty dfx_pabuk init
[00:01:12.226][info] os_mem_system_init default pool done
[0
IMU0log=***
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | rail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_vo
IPU0log=: |  750|  750|  754|  775|  836|  922|  980|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:7
IPU1log=|  846|  938|  994|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:750 F:1950
avs-uncore V:750
HSM0log=0:01:12.232][info] addr is already in region
[00:01:12.235][info] succeed to do thirdparty otpc_pabuk init
[1970-01-01 00:01:12.240][HSM][INFO][31] select_region: 0xc11cb55b
[1970-01-01 00:01:12.246][HSM][INFO][67] spi_nor de
IMU0log=lt:1122 mV | pmu:MP2882
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_v
IPU0log=50 F:1950
avs-uncore V:750 F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
av
IPU1log= F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
avs-uncore V:840 F:2450
avs-
HSM0log=vice_id 0xff1a67c8
[1970-01-01 00:01:12.252][HSM][INFO][50] std_cmd readback 0x30220d8
[1970-01-01 00:01:12.258][HSM][INFO][72] saf_cmd 0x0 readback 0x9f5a0604
[1970-01-01 00:01:12.265][HSM][INFO][72] saf_cmd 0x1 readback 0x5
IMU0log=olt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_
IPU0log=s-uncore V:840 F:2450
avs-uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain
IPU1log=uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | r
HSM0log=b7e938
[1970-01-01 00:01:12.271][HSM][INFO][72] saf_cmd 0x2 readback 0x1
[1970-01-01 00:01:12.277][HSM][INFO][72] saf_cmd 0x3 readback 0x0
[1970-01-01 00:01:12.283][HSM][INFO][72] saf_cmd 0x4 readback 0x0
[00:01:12.289][info
IMU0log=volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus r
IPU0log=[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | p
IPU1log=ail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_volt:1122 mV | pmu:MP2882
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[0] volt =  906 mV
pwr domain
HSM0log=] succeed to do thirdparty boot_profile_driver init
[00:01:12.295][info] succeed to do thirdparty crypto_driver init
[00:01:12.301][info] succeed to do thirdparty period_driver init
[00:01:12.306][info]  start loading interna
IMU0log=eady.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait th
IPU0log=mu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pmbus:0x480c0000 ver:0x110
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
IPU1log=[9] volt = 1103 mV
=end=
w&h rd rail:0, 906
w&h rd rail:1, 1105
pwr domain[0] set volt  904 mV succ
pwr domain[9] set volt 1103 mV succ
volt post
pwr domain[0] volt =  904 mV
pwr domain[9] volt = 1103 mV
==end==
Totem[0] Core Bo
HSM0log=l task ...
[00:01:12.311][info]  task name is ccm_task
[00:01:12.315][info]  hm_dynamic_loadelf successfully!
[00:01:12.320][info] internal task[1] task_name=ccm_task load successfully
[00:01:12.326][info]  task name is upgr
IMU0log=e cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master I
IPU0log=
avsbus resync succ
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[2] volt =  904 mV
pwr domain[7] volt =  804 mV
pwr domain[4] volt =  806 mV
pwr domain[1] volt =  804 mV
=end=
w&h rd rail:
IPU1log=ot Vol [1029]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2,
HSM0log=ade_task
[00:01:12.331][info]  hm_dynamic_loadelf successfully!
[00:01:12.336][info] internal task[2] task_name=upgrade_task load successfully
[00:01:12.343][info] created task ccm_task success!
[00:01:12.347][info] created 
IMU0log=mu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
cpu 0 entering scheduler
|--------------------------------------------------|
AtsPrint
|idx|lockCount| srcAddr| destAddr| addrLen|
|--
IPU0log=0, 904
w&h rd rail:1, 802
pwr domain[2] set volt  902 mV succ
pwr domain[7] set volt  800 mV succ
w&h rd rail:0, 806
w&h rd rail:1, 806
pwr domain[4] set volt  804 mV succ
pwr domain[1] set volt  802 mV succ
volt post
pwr domain
IPU1log= ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd8
HSM0log=task upgrade_task success!
[1970-01-01 00:01:12.352][HSM][INFO][54] Platform init 0x20250523 0x4e.
[1970-01-01 00:01:12.358][HSM][INFO][197] ccm start.
[1970-01-01 00:01:12.363][HSM][INFO][86] upgrade task init success.
[197
IMU0log=------------------------------------------------|
|  0|00000000|0x010500000|0x000110800000|0x00100000|
|  1|00000000|0x020000000|0x00001d000000|0x00800000|
|  2|00000000|0x020800000|0x000490000000|0x00100000|
|  3|00000000|0x020
IPU0log=[2] volt =  902 mV
pwr domain[7] volt =  802 mV
pwr domain[4] volt =  804 mV
pwr domain[1] volt =  802 mV
==end==
Totem[0] Core Boot Vol [1015]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0,
IPU1log=00, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
opposite dieId: 0, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 
HSM0log=0-01-01 00:01:12.369][HSM][INFO][95] upgrade recv cmd, 0x181.
[1970-01-01 00:01:12.375][HSM][INFO][103] upgrade res, 0x3a5aa5a3.
.