
IMU0log=900000|0x000004000000|0x08000000|
|  4|00000000|0x028900000|0x000440580000|0x01000000|
|  5|00000000|0x029900000|0x000590000000|0x00100000|
|  6|00000000|0x029a00000|0x002000150000|0x00100000|
|  7|00000000|0x000000000|0x0000000
IPU0log= MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 
IPU1log=enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
hiboost task entry
boost wait SEF.
[INFO] mem used of task 'app_Task' is:0x2028, not zero when task being deleted
boost param OK.
Totem[0] Core[ 0] Freq Limit Low
HSM0log=
IMU0log=00000|0x00000000|
|  8|00000000|0x040000000|0x000000000000|0x08000000|
|  9|00000000|0x048000000|0x000000000000|0x08000000|
| 10|00000000|0x050000000|0x000000000000|0x08000000|
| 11|00000000|0x058000000|0x000000000000|0x08000000
IPU0log=0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
tsensor type
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Fr
HSM0log=
IMU0log=|
| 12|00000000|0x060000000|0x000000000000|0x08000000|
| 13|00000000|0x068000000|0x000000000000|0x08000000|
| 14|00000000|0x070000000|0x000000000000|0x08000000|
| 15|00000000|0x078000000|0x000490000000|0x08000000|
|-------------
IPU0log=: 3, ppuFormatK: 0x4da6, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b4,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 3, mask: fffffff8
tsensor type: 4, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=-------------------------------------|
=~=~=~=~=~=~=~=~=~=~= IMU Log @ 2026.5.13 2:50:35 =~=~=~=~=~=~=~=~=~=~=
[IMU] Watchdog Initialization done!
[RegisterInterruptSource]:[21] begin
Interrupt 32 register OK
Interrupt 34 regi
IPU0log=0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 4, mask: ffffffee
tsensor type: 5, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1

IPU1log= Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=ster OK
Interrupt 40 register OK
Interrupt 44 register OK
sram cnt 0x0, id = 43
Interrupt 43 register OK
Interrupt 36 register OK
Interrupt 57 register OK
sram cnt 0x0, id = 42
Interrupt 42 register OK
Interrupt 37 register OK
[
IPU0log=tsensor: 5, mask: ffffffda
tsensor type: 6, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 6, mask: ffffff80
tsensor type: 7, ppuFormatK: 0x437a,
IPU1log=KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=RegisterInterruptSource]:[39] end
IPMB initialization Start...
IPMB clock set done, prer = 0x18.
IPMB Rx FIFO clear empty.
IPMB initialization Done.
starting DFX Collect Task end
PowerTask Entry ...
Wait all vrd init done 
IPU0log= ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 7, mask: fffffffe
opposite dieId: 1, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
CPM max V[900]-
IPU1log= Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low
HSM0log=
IMU0log=...
All vrd init done, power task start
refresh domainId 0 Lsb 0x0
refresh domainId 9 Lsb 0x1
refresh domainId 2 Lsb 0x0
refresh domainId 7 Lsb 0x1
refresh domainId 4 Lsb 0x0
refresh domainId 1 Lsb 0x1
power sensor[0] | calib:51
IPU0log=F:2800
CPM min V[750]-F:1600
freq:2350, idx:9
cpm trim freq: 2600, idx: 4
cpm trim finish
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
recount hours 
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Fr
HSM0log=
IMU0log=20 | rshunt:1 | rshuntDiv:1000 | currLsb:1 | currLsbDiv:1000 | enableFlag:1
                | pwrLsb:25 | defPwr:25000 | minPwr:10000 | maxPwr:65000 | pwrFix:3400
                | manufacturerId: 0x5549 | dieId: 0x2260
power se
IPU0log=0x984 
hiboost task entry
boost wait SEF.
boost param OK.
Totem[0] Core[ 0] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[26
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=nsor[0] init success
ScmiTaskEntry start.
[RegisterInterruptSource]:[21] begin
Interrupt 51 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 52 register OK
[RegisterInterruptSource
IPU0log=00000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[12000
IPU1log= Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 53 register OK
[RegisterInterruptSource]:[39] end
[0.01.28.905]starting ras Init
RAS Setup Value get done!
INT_NUM_PER_SKT * HiGetSktNum() = 0x8
index = 0x0
RasIntRegi
IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Lim
IPU1log=KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=ster init 160 
index = 0x1
RasIntRegister init 172 
index = 0x2
RasIntRegister init 162 
index = 0x3
RasIntRegister init 174 
index = 0x4
RasIntRegister init 184 
index = 0x5
RasIntRegister init 196 
index = 0x6
RasIntRegister i
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IPU1log= Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low
HSM0log=
IMU0log=nit 186 
index = 0x7
RasIntRegister init 198 
RasIntRegister init 161 
RasIntRegister init 173 
RasIntRegister init 185 
RasIntRegister init 197 
RasIntRegister init 284 
RasIntRegister init 314 
MceTableHeadInit start
starting 
IPU0log=14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
To
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
uncore max freq : 23
HSM0log=
IMU0log=Ce_Storm Contrl and Ras_Data_Update Task end
[0.01.28.987]starting ras end
[IMU][ERR] skt id 0
Ub init task start Entry ...
UbInitTask Entry ...
[RegisterInterruptSource]:[21] begin
Interrupt 167 register OK
[RegisterInterrup
IPU0log=tem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[26
IPU1log=50 MHz

HSM0log=
IMU0log=tSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 191 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 171 register OK
[RegisterInterruptSource]:[39] end
[Register
IPU0log=00000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[12000
IPU1log=
HSM0log=
IMU0log=InterruptSource]:[21] begin
Interrupt 183 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 195 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Lim
IPU1log=
HSM0log=
IMU0log=
Interrupt 207 register OK
[RegisterInterruptSource]:[39] end
Init heart-beat-task end
CS0 flash do not support sfdp!
Current flash device ID[0x61a67c8]!
System supported 1 Flash.
flash cs 0 Manufacture 0xc8, DeviceId 0x1a67, A
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IPU1log=
HSM0log=
IMU0log=ddrMode[0-3B,1-4B] 0x1:
    size 0x4000000, pagesize 0x100
    read  cmd 0x13, dummy byte 0x8
    write cmd 0x12, dummy byte 0x0
    erase4k cmd 0x21, erase64k byte 0xdc
sfc init end
firstUnMskExt0Int
ThermalDimmStart Entry ...
IPU0log=33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
To
IPU1log=
HSM0log=
IMU0log=
wait ddr init done...
HacLowPowerStart Entry ...
Hello LiteOS...
pwr cap[0]: 0, 67
Init ReportPcieMmioToBmcTaskEntry end
starting Fpc Isolation Task end
[IMU][ERR] IMP log not ready, DDR initing...
pwr cap[1]: f, 27
pwr cap
IPU0log=tem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[26
IPU1log=
HSM0log=
IMU0log=[2]: 1, 3
[IMU][ERR] IMP log not ready, DDR initing...
[IMU][ERR] IMP log not ready, DDR initing...
[0.02.00.201]DDR init done
[LOG]head = 0x0, tail = 0x188c, logSize = 0x188c
[IMU][ERR] HsmLogInit!
[IMU][ERR] HsmLogInit! TRUE

IPU0log=00000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
uncore max freq : 2350 MHz

IPU1log=
HSM0log=
IMU0log=set apei done!
UbConfigData size is 64
UbConfigData 0 : 0
UbConfigData 1 : 0
UbConfigData 2 : 0
UbConfigData 3 : 1
UbConfigData 4 : 31
UbConfigData 5 : 1
UbConfigData 6 : 0
UbConfigData 7 : 32
UbConfigData 8 : 0
UbConfigData 9 :
IPU0log=
IPU1log=
HSM0log=
IMU0log= 1
UbConfigData 10 : 2
UbConfigData 11 : 0
UbConfigData 12 : 0
UbConfigData 13 : 1
UbConfigData 14 : 0
UbConfigData 15 : 0
UbConfigData 16 : 0
UbConfigData 17 : 0
UbConfigData 18 : 0
UbConfigData 19 : 0
UbConfigData 20 : 0
UbCon
IPU0log=
IPU1log=
HSM0log=
IMU0log=figData 21 : 0
UbConfigData 22 : 11
UbConfigData 23 : 0
UbConfigData 24 : 0
UbConfigData 25 : 0
UbConfigData 26 : 0
UbConfigData 27 : 0
UbConfigData 28 : 0
UbConfigData 29 : 0
UbConfigData 30 : 0
UbConfigData 31 : 0
UbConfigData
IPU0log=
IPU1log=
HSM0log=
IMU0log= 32 : 0
UbConfigData 33 : 0
UbConfigData 34 : 2
UbConfigData 35 : 1
UbConfigData 36 : 0
UbConfigData 37 : 0
UbConfigData 38 : 0
UbConfigData 39 : 0
UbConfigData 40 : 0
UbConfigData 41 : 0
UbConfigData 42 : 0
UbConfigData 43 : 0

IPU0log=
IPU1log=
HSM0log=
IMU0log=UbConfigData 44 : 0
UbConfigData 45 : 0
UbConfigData 46 : 0
UbConfigData 47 : 0
UbConfigData 48 : 0
UbConfigData 49 : 0
UbConfigData 50 : 0
UbConfigData 51 : 0
UbConfigData 52 : 0
UbConfigData 53 : 0
UbConfigData 54 : 0
UbConfig
IPU0log=
IPU1log=
HSM0log=
IMU0log=Data 55 : 0
UbConfigData 56 : 0
UbConfigData 57 : 0
UbConfigData 58 : 0
UbConfigData 59 : 0
UbConfigData 60 : 0
UbConfigData 61 : 0
UbConfigData 62 : 0
UbConfigData 63 : 0
UbConfigData 64 : 0
ClusterSwitch: 0, 0
ClusterMode: 0, 
IPU0log=
IPU1log=
HSM0log=
IMU0log=0
ControlMode: 0, 0
EnumMode: 1, 1
BodyMask: 31, 31
CcCtxCount: 256, 256
RcCtxCount: 32, 32
UbMemEntrySize: 128, 0
MctpSupport: 1, 1
SecureMode: 0, 0
PrimaryCna: 0, 0
Upi: 0, 0
EntityId: 0, 0
SlotId: 1, 1
SocketId: 2, 2
PortInde
IPU0log=
IPU1log=
HSM0log=
IMU0log=x: 0, 0
PortCna: 0, 0
CtrlCna: 11, 11
ImpBootFlag: 2, 2
ImuBootFlag: 1, 1
SktId: 0 DieId:2, HCCS_LINK:2 PaId:2
SktId: 1 DieId:2, HCCS_LINK:0 PaId:0
CIS register: ID[0xc00007ff], owner[0x1000003], function[0x1045dc5c].
CIS regist
IPU0log=
IPU1log=
HSM0log=
IMU0log=er: ID[0xc0000002], owner[0x1000003], function[0x1045dcfc].
odf: can not find od file[config]
Do not get NII route table, disable NII Send function.
UbiosTaskStart Entry ...
UbiosTaskStart create task success
IMU ImpBootFlag: 
IPU0log=
IPU1log=
HSM0log=
IMU0log=0x2
skip IMP start config...
UbiosCisTask Entry ...
ddr init done, start thermal dimm task
======dimm status======
  chl[0] dimm0 1, dimm1 0
  chl[1] dimm0 0, dimm1 0
  chl[2] dimm0 0, dimm1 0
  chl[3] dimm0 0, dimm1 0
  chl[4]
IPU0log=
IPU1log=
HSM0log=
IMU0log= dimm0 0, dimm1 0
  chl[5] dimm0 0, dimm1 0
  chl[6] dimm0 0, dimm1 0
  chl[7] dimm0 0, dimm1 0
  chl[8] dimm0 0, dimm1 0
  chl[9] dimm0 0, dimm1 0
  chl[10] dimm0 0, dimm1 0
  chl[11] dimm0 0, dimm1 0
==========end==========
sk
IPU0log=
IPU1log=
HSM0log=
IMU0log=tId[0] chl[0] registered, dimm mask = 0x1
======dimm status======
  chl[0] dimm0 1, dimm1 0
  chl[1] dimm0 0, dimm1 0
  chl[2] dimm0 0, dimm1 0
  chl[3] dimm0 0, dimm1 0
  chl[4] dimm0 0, dimm1 0
  chl[5] dimm0 0, dimm1 0
  chl[
IPU0log=
IPU1log=
HSM0log=
IMU0log=6] dimm0 0, dimm1 0
  chl[7] dimm0 0, dimm1 0
  chl[8] dimm0 0, dimm1 0
  chl[9] dimm0 0, dimm1 0
  chl[10] dimm0 0, dimm1 0
  chl[11] dimm0 0, dimm1 0
==========end==========
sktId[1] chl[0] registered, dimm mask = 0x1
=====dim
IPU0log=
IPU1log=
HSM0log=
IMU0log=m temp params=====
  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
  is_thermal_thro_en  : 1
  is_aref_rate_auto   : 0
===========end============
[IMU][ERR] [
IMP0log= no log data error!]
[0.02.07.212]TF Heart
IPU0log=
IPU1log=
HSM0log=
IMU0log=beat Start
[0.02.08.633]RECEIVE MEM SILK.
0: skt = 0 logic = 1 phy = 0 
1: skt = 1 logic = 11 phy = 7 
2: skt = 0 logic = 4 phy = 2 
3: skt = 0 logic = 2 phy = 4 
4: skt = 1 logic = 0 phy = 8 
5: skt = 1 logic = 5 phy = 6 
6: sk
IPU0log=
IPU1log=
HSM0log=
IMU0log=t = 1 logic = 9 phy = 11 
7: skt = 1 logic = 1 phy = 0 
8: skt = 1 logic = 8 phy = 5 
9: skt = 0 logic = 9 phy = 11 
10: skt = 1 logic = 7 phy = 1 
11: skt = 0 logic = 0 phy = 8 
12: skt = 0 logic = 6 phy = 9 
13: skt = 1 logic 
IPU0log=
IPU1log=
HSM0log=
IMU0log== 4 phy = 2 
14: skt = 1 logic = 2 phy = 4 
15: skt = 1 logic = 10 phy = 3 
16: skt = 0 logic = 3 phy = 10 
17: skt = 1 logic = 6 phy = 9 
18: skt = 0 logic = 10 phy = 3 
19: skt = 0 logic = 7 phy = 1 
20: skt = 1 logic = 3 phy 
IPU0log=
IPU1log=
HSM0log=
IMU0log== 10 
21: skt = 0 logic = 8 phy = 5 
22: skt = 0 logic = 5 phy = 6 
23: skt = 0 logic = 11 phy = 7 
get mem silk data length: 72
[0.02.11.610]PCIE INIT DONE.
[IMU][ERR] LOS_SemPend(g_pcieSemaphore, LOS_WAIT_FOREVER)
[RegisterInt
IPU0log=
IPU1log=
HSM0log=
IMU0log=erruptSource]:[21] begin
Interrupt 258 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 262 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
In
IPU0log=
IPU1log=
HSM0log=
IMU0log=terrupt 266 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 270 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 277 register OK
[Reg
IPU0log=
IPU1log=
HSM0log=
IMU0log=isterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 288 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 292 register OK
[RegisterInterruptSource]:[39] e
IPU0log=
IPU1log=
HSM0log=
IMU0log=nd
[RegisterInterruptSource]:[21] begin
Interrupt 296 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 300 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource
IPU0log=
IPU1log=
HSM0log=
IMU0log=]:[21] begin
Interrupt 307 register OK
[RegisterInterruptSource]:[39] end
pmt Init done

-----------------ROUTE TABLE------------------
entryCount = 1
----------------------------------------------
[No.0]:
eidRange = 1, sta
IPU0log=
IPU1log=
HSM0log=
IMU0log=rtEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2100
----------------------------------------------
-----------------ROUTE TABLE------------------
entryCount 
IPU0log=
IPU1log=
HSM0log=
IMU0log== 2
----------------------------------------------
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2100
[No.1]:
eidRange = 1, startE
IPU0log=
IPU1log=
HSM0log=
IMU0log=id = 10, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2500
----------------------------------------------
-----------------ROUTE TABLE------------------
entryCount = 
IPU0log=
IPU1log=
HSM0log=
IMU0log=2
----------------------------------------------
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2100
[No.1]:
eidRange = 1, startEid
IPU0log=
IPU1log=
HSM0log=
IMU0log= = 10, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2500
----------------------------------------------
HotPlug Open
slotNum = 42
portIdx = 0
portIdx = 1
portIdx =
IPU0log=
IPU1log=
HSM0log=
IMU0log= 2
portIdx = 3
portIdx = 4
portIdx = 5
portIdx = 6
portIdx = 7
portIdx = 8
portIdx = 9
portIdx = a
portIdx = b
portIdx = c
portIdx = d
portIdx = e
portIdx = f
portIdx = 10
portIdx = 11
portIdx = 12
portIdx = 13
IPU0log=
IPU1log=
HSM0log=
IMU0log=
portIdx = 14
portIdx = 15
portIdx = 16
portIdx = 17
portIdx = 18
portIdx = 19
portIdx = 1a
portIdx = 1b
portIdx = 1c
portIdx = 1d
portIdx = 1e
portIdx = 1f
portIdx = 20
portIdx = 40
portIdx = 41
portIdx = 42
por
IPU0log=
IPU1log=
HSM0log=
IMU0log=tIdx = 43
portIdx = 44
portIdx = 45
portIdx = 46
portIdx = 47
portIdx = 48
portIdx = 49
portIdx = 4a
portIdx = 4b
portIdx = 4c
portIdx = 4d
portIdx = 4e
portIdx = 4f
portIdx = 50
portIdx = 51
portIdx = 52
portIdx
IPU0log=
IPU1log=
HSM0log=
IMU0log= = 53
portIdx = 54
portIdx = 55
portIdx = 56
portIdx = 57
portIdx = 58
portIdx = 59
portIdx = 5a
portIdx = 5b
portIdx = 5c
portIdx = 5d
portIdx = 5e
portIdx = 5f
portIdx = 60
Pcie slot[0] port:0 base 0x2c01000000, 
IPU0log=
IPU1log=
HSM0log=
IMU0log=pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[0] port:0 base 0x2c01000000, pcieSlotCtrl.data (after)0x0.

Pcie slot[1] port:1 base 0x2c01000000, pcieSlotCtrl.data (befor
IPU0log=
IPU1log=
HSM0log=
IMU0log=e)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[1] port:1 base 0x2c01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[2] port:2 base 0x2c01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtr
IPU0log=
IPU1log=
HSM0log=
IMU0log=l.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[2] port:2 base 0x2c01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[3] port:3 base 0x2c01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det
IPU0log=
IPU1log=
HSM0log=
IMU0log=_st = 1
present:1, pwr_en:0.
Pcie slot[3] port:3 base 0x2c01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[4] port:4 base 0x2c01000000, pcieSlotCtrl.data (before)0x10003c0.
pcieSlotCtrl.bits.presencd_det_st = 1
pres
IPU0log=
IPU1log=
HSM0log=
IMU0log=ent:1, pwr_en:0.
Pcie slot[4] port:4 base 0x2c01000000, pcieSlotCtrl.data (after)0x14801c0.

Pcie slot[5] port:5 base 0x2c01000000, pcieSlotCtrl.data (before)0x3c0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
IPU0log=
IPU1log=
HSM0log=
IMU0log=
Pcie slot[5] port:5 base 0x2c01000000, pcieSlotCtrl.data (after)0x4801c0.

Pcie slot[6] port:6 base 0x2c01000000, pcieSlotCtrl.data (before)0x3c0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[6] po
IPU0log=
IPU1log=
HSM0log=
IMU0log=rt:6 base 0x2c01000000, pcieSlotCtrl.data (after)0x4801c0.

Pcie slot[7] port:7 base 0x2c01000000, pcieSlotCtrl.data (before)0x3c0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[7] port:7 base 0x2c010
IPU0log=
IPU1log=
HSM0log=
IMU0log=00000, pcieSlotCtrl.data (after)0x4801c0.

Pcie slot[8] port:8 base 0x2c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[8] port:8 base 0x2c02000000, pcieSlotCtrl
IPU0log=
IPU1log=
HSM0log=
IMU0log=.data (after)0x0.

Pcie slot[9] port:9 base 0x2c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[9] port:9 base 0x2c02000000, pcieSlotCtrl.data (after)0x480100.

IPU0log=
IPU1log=
HSM0log=
IMU0log=
Pcie slot[10] port:10 base 0x2c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[10] port:10 base 0x2c02000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[11]
IPU0log=
IPU1log=
HSM0log=
IMU0log= port:11 base 0x2c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[11] port:11 base 0x2c02000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[12] port:12 base 0
IPU0log=
IPU1log=
HSM0log=
IMU0log=x2c02000000, pcieSlotCtrl.data (before)0x10003c0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[12] port:12 base 0x2c02000000, pcieSlotCtrl.data (after)0x14801c0.

Pcie slot[13] port:13 base 0x2c02000
IPU0log=
IPU1log=
HSM0log=
IMU0log=000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[13] port:13 base 0x2c02000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[14] port:14 base 0x2c02000000, pcieSlotCt
IPU0log=
IPU1log=
HSM0log=
IMU0log=rl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[14] port:14 base 0x2c02000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[15] port:15 base 0x2c02000000, pcieSlotCtrl.data (before
IPU0log=
IPU1log=
HSM0log=
IMU0log=)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[15] port:15 base 0x2c02000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[16] port:16 base 0x2d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlot
IPU0log=
IPU1log=
HSM0log=
IMU0log=Ctrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[16] port:16 base 0x2d01000000, pcieSlotCtrl.data (after)0x0.

Pcie slot[17] port:17 base 0x2d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_d
IPU0log=
IPU1log=
HSM0log=
IMU0log=et_st = 1
present:1, pwr_en:0.
Pcie slot[17] port:17 base 0x2d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[18] port:18 base 0x2d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
pres
IPU0log=
IPU1log=
HSM0log=
IMU0log=ent:1, pwr_en:0.
Pcie slot[18] port:18 base 0x2d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[19] port:19 base 0x2d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0
IPU0log=
IPU1log=
HSM0log=
IMU0log=.
Pcie slot[19] port:19 base 0x2d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[20] port:20 base 0x2d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[20
IPU0log=
IPU1log=
HSM0log=
IMU0log=] port:20 base 0x2d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[21] port:21 base 0x2d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[21] port:21 base 
IPU0log=
IPU1log=
HSM0log=
IMU0log=0x2d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[22] port:22 base 0x2d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[22] port:22 base 0x2d01000000, p
IPU0log=
IPU1log=
HSM0log=
IMU0log=cieSlotCtrl.data (after)0x480100.

Pcie slot[23] port:23 base 0x2d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[23] port:23 base 0x2d01000000, pcieSlotCtrl.dat
IPU0log=
IPU1log=
HSM0log=
IMU0log=a (after)0x480100.

Pcie slot[24] port:24 base 0x2d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[24] port:24 base 0x2d02000000, pcieSlotCtrl.data (after)0x0.

IPU0log=
IPU1log=
HSM0log=
IMU0log=
Pcie slot[25] port:25 base 0x2d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[25] port:25 base 0x2d02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[26] po
IPU0log=
IPU1log=
HSM0log=
IMU0log=rt:26 base 0x2d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[26] port:26 base 0x2d02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[27] port:27 base 0x2d020
IPU0log=
IPU1log=
HSM0log=
IMU0log=00000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[27] port:27 base 0x2d02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[28] port:28 base 0x2d02000000, pcieSlotCtr
IPU0log=
IPU1log=
HSM0log=
IMU0log=l.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[28] port:28 base 0x2d02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[29] port:29 base 0x2d02000000, pcieSlotCtrl.data (before)0x0
IPU0log=
IPU1log=
HSM0log=
IMU0log=.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[29] port:29 base 0x2d02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[30] port:30 base 0x2d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bi
IPU0log=
IPU1log=
HSM0log=
IMU0log=ts.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[30] port:30 base 0x2d02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[31] port:31 base 0x2d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st
IPU0log=
IPU1log=
HSM0log=
IMU0log= = 0
present:0, pwr_en:1.
Pcie slot[31] port:31 base 0x2d02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[32] port:32 base 0x3210000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, p
IPU0log=
IPU1log=
HSM0log=
IMU0log=wr_en:1.
Pcie slot[32] port:32 base 0x3210000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[33] port:0 base 0x6c01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot
IPU0log=
IPU1log=
HSM0log=
IMU0log=[33] port:0 base 0x6c01000000, pcieSlotCtrl.data (after)0x0.

Pcie slot[34] port:1 base 0x6c01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[34] port:1 base 0x6c0
IPU0log=
IPU1log=
HSM0log=
IMU0log=1000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[35] port:2 base 0x6c01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[35] port:2 base 0x6c01000000, pcieSlot
IPU0log=
IPU1log=
HSM0log=
IMU0log=Ctrl.data (after)0x480100.

Pcie slot[36] port:3 base 0x6c01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[36] port:3 base 0x6c01000000, pcieSlotCtrl.data (after)
IPU0log=
IPU1log=
HSM0log=
IMU0log=0x480100.

Pcie slot[37] port:4 base 0x6c01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[37] port:4 base 0x6c01000000, pcieSlotCtrl.data (after)0x480100.

Pcie
IPU0log=
IPU1log=
HSM0log=
IMU0log= slot[38] port:5 base 0x6c01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[38] port:5 base 0x6c01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[39] port:6 
IPU0log=
IPU1log=
HSM0log=
IMU0log=base 0x6c01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[39] port:6 base 0x6c01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[40] port:7 base 0x6c01000000
IPU0log=
IPU1log=
HSM0log=
IMU0log=, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[40] port:7 base 0x6c01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[41] port:8 base 0x6c02000000, pcieSlotCtrl.da
IPU0log=
IPU1log=
HSM0log=
IMU0log=ta (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[41] port:8 base 0x6c02000000, pcieSlotCtrl.data (after)0x0.

Pcie slot[42] port:9 base 0x6c02000000, pcieSlotCtrl.data (before)0x0.
pcieS
IPU0log=
IPU1log=
HSM0log=
IMU0log=lotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[42] port:9 base 0x6c02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[43] port:10 base 0x6c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presen
IPU0log=
IPU1log=
HSM0log=
IMU0log=cd_det_st = 0
present:0, pwr_en:1.
Pcie slot[43] port:10 base 0x6c02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[44] port:11 base 0x6c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
pre
IPU0log=
IPU1log=
HSM0log=
IMU0log=sent:0, pwr_en:1.
Pcie slot[44] port:11 base 0x6c02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[45] port:12 base 0x6c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
IPU0log=
IPU1log=
HSM0log=
IMU0log=
Pcie slot[45] port:12 base 0x6c02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[46] port:13 base 0x6c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[46] por
IPU0log=
IPU1log=
HSM0log=
IMU0log=t:13 base 0x6c02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[47] port:14 base 0x6c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[47] port:14 base 0x6c0200
IPU0log=
IPU1log=
HSM0log=
IMU0log=0000, pcieSlotCtrl.data (after)0x700.

Pcie slot[48] port:15 base 0x6c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[48] port:15 base 0x6c02000000, pcieSlotCtrl
IPU0log=
IPU1log=
HSM0log=
IMU0log=.data (after)0x700.

Pcie slot[49] port:16 base 0x6d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[49] port:16 base 0x6d01000000, pcieSlotCtrl.data (after)0x0.
IPU0log=
IPU1log=
HSM0log=
IMU0log=

Pcie slot[50] port:17 base 0x6d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[50] port:17 base 0x6d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[51
IPU0log=
IPU1log=
HSM0log=
IMU0log=] port:18 base 0x6d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[51] port:18 base 0x6d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[52] port:19 base 
IPU0log=
IPU1log=
HSM0log=
IMU0log=0x6d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[52] port:19 base 0x6d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[53] port:20 base 0x6d01000000, p
IPU0log=
IPU1log=
HSM0log=
IMU0log=cieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[53] port:20 base 0x6d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[54] port:21 base 0x6d01000000, pcieSlotCtrl.dat
IPU0log=
IPU1log=
HSM0log=
IMU0log=a (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[54] port:21 base 0x6d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[55] port:22 base 0x6d01000000, pcieSlotCtrl.data (before)0x0.
IPU0log=
IPU1log=
HSM0log=
IMU0log=
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[55] port:22 base 0x6d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[56] port:23 base 0x6d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.b
IPU0log=
IPU1log=
HSM0log=
IMU0log=its.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[56] port:23 base 0x6d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[57] port:24 base 0x6d02000000, pcieSlotCtrl.data (before)0x3c0.
pcieSlotCtrl.bits.presencd_
IPU0log=
IPU1log=
HSM0log=
IMU0log=det_st = 0
present:0, pwr_en:1.
Pcie slot[57] port:24 base 0x6d02000000, pcieSlotCtrl.data (after)0x7c0.

Pcie slot[58] port:25 base 0x6d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
presen
IPU0log=
IPU1log=
HSM0log=
IMU0log=t:0, pwr_en:1.
Pcie slot[58] port:25 base 0x6d02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[59] port:26 base 0x6d02000000, pcieSlotCtrl.data (before)0x3c0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.

IPU0log=
IPU1log=
HSM0log=
IMU0log=Pcie slot[59] port:26 base 0x6d02000000, pcieSlotCtrl.data (after)0x7c0.

Pcie slot[60] port:27 base 0x6d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[60] port
IPU0log=
IPU1log=
HSM0log=
IMU0log=:27 base 0x6d02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[61] port:28 base 0x6d02000000, pcieSlotCtrl.data (before)0x3c0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[61] port:28 base 0x6d020
IPU0log=
IPU1log=
HSM0log=
IMU0log=00000, pcieSlotCtrl.data (after)0x7c0.

Pcie slot[62] port:29 base 0x6d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[62] port:29 base 0x6d02000000, pcieSlotCtr
IPU0log=
IPU1log=
HSM0log=
IMU0log=l.data (after)0x700.

Pcie slot[63] port:30 base 0x6d02000000, pcieSlotCtrl.data (before)0x3c0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[63] port:30 base 0x6d02000000, pcieSlotCtrl.data (after)0x
IPU0log=
IPU1log=
HSM0log=
IMU0log=7c0.

Pcie slot[64] port:31 base 0x6d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[64] port:31 base 0x6d02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[
IPU0log=
IPU1log=
HSM0log=
IMU0log=65] port:32 base 0x7210000000, pcieSlotCtrl.data (before)0xffffffff.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[65] port:32 base 0x7210000000, pcieSlotCtrl.data (after)0xffffffff.

[RegisterInterru
IPU0log=
IPU1log=
HSM0log=
IMU0log=ptSource]:[21] begin
Interrupt 61 register OK
[RegisterInterruptSource]:[39] end
fristMskExt0Int

Pcie Hotplug init done, with 66 port(s).
[0.06.17.500]BIOS POST END.
slot[0] port:0 begin to power ON.
slot[0] port:0 pwr_ind
IPU0log=
IPU1log=
HSM0log=
IMU0log=icator = 0, att_indicator = 0
ledStatus:0 invalid!
[HotPlugMonitorTask][248L]Pcie slot[0] port:0 base 0x2c01000000, pcieSlotCtrl.data (after)0x100000.
slot[1] port:1 begin to power ON.
slot[2] port:2 begin to power ON.
slot
IPU0log=
IPU1log=
HSM0log=
IMU0log=[3] port:3 begin to power ON.
slot[4] port:4 begin to power ON.
slot[5] port:5 begin to power ON.
slot[6] port:6 begin to power ON.
slot[7] port:7 begin to power ON.
slot[8] port:8 begin to power ON.
slot[8] port:8 pwr_ind
IPU0log=
IPU1log=
HSM0log=
IMU0log=icator = 0, att_indicator = 0
ledStatus:0 invalid!
[HotPlugMonitorTask][248L]Pcie slot[8] port:8 base 0x2c02000000, pcieSlotCtrl.data (after)0x100000.
slot[9] port:9 begin to power ON.
slot[10] port:10 begin to power ON.
sl
IPU0log=
IPU1log=
HSM0log=
IMU0log=ot[11] port:11 begin to power ON.
slot[12] port:12 begin to power ON.
slot[13] port:13 begin to power ON.
slot[14] port:14 begin to power ON.
slot[15] port:15 begin to power ON.
slot[16] port:16 begin to power ON.
slot[16]
IPU0log=
IPU1log=
HSM0log=
IMU0log= port:16 pwr_indicator = 0, att_indicator = 0
ledStatus:0 invalid!
[HotPlugMonitorTask][248L]Pcie slot[16] port:16 base 0x2d01000000, pcieSlotCtrl.data (after)0x100000.
slot[17] port:17 begin to power ON.
slot[18] port:18 be
IPU0log=
IPU1log=
HSM0log=
IMU0log=gin to power ON.
slot[19] port:19 begin to power ON.
slot[20] port:20 begin to power ON.
slot[21] port:21 begin to power ON.
slot[22] port:22 begin to power ON.
slot[23] port:23 begin to power ON.
slot[24] port:24 pwr_indi
IPU0log=
IPU1log=
HSM0log=
IMU0log=cator = 0, att_indicator = 0
ledStatus:0 invalid!
[HotPlugMonitorTask][248L]Pcie slot[24] port:24 base 0x2d02000000, pcieSlotCtrl.data (after)0x100000.
slot[25] port:25 begin to power OFF.
slot[26] port:26 begin to power OFF
IPU0log=
IPU1log=
HSM0log=
IMU0log=.
slot[27] port:27 begin to power OFF.
slot[28] port:28 begin to power OFF.
slot[29] port:29 begin to power OFF.
slot[30] port:30 begin to power OFF.
slot[31] port:31 begin to power OFF.
slot[32] port:32 begin to power OFF
IPU0log=
IPU1log=
IMU0log=1T1N1U skt:0 CfgBusDfxPreConfig finish

********Hello Huawei LiteOS********

IMU Firmware Version : B173V01
LiteOS Kernel Version : 5.10.0
Run on Socket[0] Die[3]
Chip Version: 1
Max socket num: 2
*******************************
IPU0log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 0
cls: 6, core: 7
cpu 933 sram 1010 ddr 983
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  750|  802|  885|  933|
max  v
IPU1log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 1
cls: 6, core: 7
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  759|  821|  909|  961|
max  v: |  750|  750|  753|  781
HSM0log=[1970-01-01 00:01:11.742][HSM][INFO][30] init start
[1970-01-01 00:01:11.742][HSM][INFO][38] init over
[00:01:11.751][info] succeed to do thirdparty dfx_pabuk init
[00:01:11.757][info] os_mem_system_init default pool done
[0
IMU0log=***
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | rail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_vo
IPU0log=: |  750|  750|  754|  775|  836|  922|  980|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:7
IPU1log=|  846|  938|  994|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:750 F:1950
avs-uncore V:750
HSM0log=0:01:11.763][info] addr is already in region
[00:01:11.766][info] succeed to do thirdparty otpc_pabuk init
[1970-01-01 00:01:11.772][HSM][INFO][31] select_region: 0xc11cb55b
[1970-01-01 00:01:11.778][HSM][INFO][67] spi_nor de
IMU0log=lt:1122 mV | pmu:MP2882
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_v
IPU0log=50 F:1950
avs-uncore V:750 F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
av
IPU1log= F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
avs-uncore V:840 F:2450
avs-
HSM0log=vice_id 0xff1a67c8
[1970-01-01 00:01:11.784][HSM][INFO][50] std_cmd readback 0x30220d8
[1970-01-01 00:01:11.790][HSM][INFO][72] saf_cmd 0x0 readback 0x9f5a0604
[1970-01-01 00:01:11.796][HSM][INFO][72] saf_cmd 0x1 readback 0x5
IMU0log=olt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_
IPU0log=s-uncore V:840 F:2450
avs-uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain
IPU1log=uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | r
HSM0log=b7e938
[1970-01-01 00:01:11.802][HSM][INFO][72] saf_cmd 0x2 readback 0x1
[1970-01-01 00:01:11.808][HSM][INFO][72] saf_cmd 0x3 readback 0x0
[1970-01-01 00:01:11.814][HSM][INFO][72] saf_cmd 0x4 readback 0x0
[00:01:11.821][info
IMU0log=volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus r
IPU0log=[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | p
IPU1log=ail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_volt:1122 mV | pmu:MP2882
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[0] volt =  908 mV
pwr domain
HSM0log=] succeed to do thirdparty boot_profile_driver init
[00:01:11.826][info] succeed to do thirdparty crypto_driver init
[00:01:11.832][info] succeed to do thirdparty period_driver init
[00:01:11.838][info]  start loading interna
IMU0log=eady.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait th
IPU0log=mu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pmbus:0x480c0000 ver:0x110
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
IPU1log=[9] volt = 1103 mV
=end=
w&h rd rail:0, 906
w&h rd rail:1, 1103
pwr domain[0] set volt  906 mV succ
pwr domain[9] set volt 1103 mV succ
volt post
pwr domain[0] volt =  904 mV
pwr domain[9] volt = 1103 mV
==end==
Totem[0] Core Bo
HSM0log=l task ...
[00:01:11.842][info]  task name is ccm_task
[00:01:11.846][info]  hm_dynamic_loadelf successfully!
[00:01:11.851][info] internal task[1] task_name=ccm_task load successfully
[00:01:11.858][info]  task name is upgr
IMU0log=e cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master I
IPU0log=
avsbus resync succ
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[2] volt =  904 mV
pwr domain[7] volt =  804 mV
pwr domain[4] volt =  806 mV
pwr domain[1] volt =  804 mV
=end=
w&h rd rail:
IPU1log=ot Vol [1029]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2,
HSM0log=ade_task
[00:01:11.862][info]  hm_dynamic_loadelf successfully!
[00:01:11.867][info] internal task[2] task_name=upgrade_task load successfully
[00:01:11.874][info] created task ccm_task success!
[00:01:11.878][info] created 
IMU0log=mu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
cpu 0 entering scheduler
|--------------------------------------------------|
AtsPrint
|idx|lockCount| srcAddr| destAddr| addrLen|
|--
IPU0log=0, 904
w&h rd rail:1, 804
pwr domain[2] set volt  902 mV succ
pwr domain[7] set volt  802 mV succ
w&h rd rail:0, 804
w&h rd rail:1, 804
pwr domain[4] set volt  802 mV succ
pwr domain[1] set volt  802 mV succ
volt post
pwr domain
IPU1log= ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd8
HSM0log=task upgrade_task success!
[1970-01-01 00:01:11.883][HSM][INFO][54] Platform init 0x20250523 0x4e.
[1970-01-01 00:01:11.890][HSM][INFO][197] ccm start.
[1970-01-01 00:01:11.894][HSM][INFO][86] upgrade task init success.
[197
IMU0log=------------------------------------------------|
|  0|00000000|0x010500000|0x000110800000|0x00100000|
|  1|00000000|0x020000000|0x00001d000000|0x00800000|
|  2|00000000|0x020800000|0x000490000000|0x00100000|
|  3|00000000|0x020
IPU0log=[2] volt =  902 mV
pwr domain[7] volt =  800 mV
pwr domain[4] volt =  802 mV
pwr domain[1] volt =  802 mV
==end==
Totem[0] Core Boot Vol [1015]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0,
IPU1log=00, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
opposite dieId: 0, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 
HSM0log=0-01-01 00:01:11.900][HSM][INFO][95] upgrade recv cmd, 0x181.
[1970-01-01 00:01:11.906][HSM][INFO][103] upgrade res, 0x3a5aa5a3.
.
IMU0log=900000|0x000004000000|0x08000000|
|  4|00000000|0x028900000|0x000440580000|0x01000000|
|  5|00000000|0x029900000|0x000590000000|0x00100000|
|  6|00000000|0x029a00000|0x002000150000|0x00100000|
|  7|00000000|0x000000000|0x0000000
IPU0log= MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 
IPU1log=enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
hiboost task entry
boost wait SEF.
[INFO] mem used of task 'app_Task' is:0x2028, not zero when task being deleted
boost param OK.
Totem[0] Core[ 0] Freq Limit Low
HSM0log=
IMU0log=00000|0x00000000|
|  8|00000000|0x040000000|0x000000000000|0x08000000|
|  9|00000000|0x048000000|0x000000000000|0x08000000|
| 10|00000000|0x050000000|0x000000000000|0x08000000|
| 11|00000000|0x058000000|0x000000000000|0x08000000
IPU0log=0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
tsensor type
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Fr
HSM0log=
IMU0log=|
| 12|00000000|0x060000000|0x000000000000|0x08000000|
| 13|00000000|0x068000000|0x000000000000|0x08000000|
| 14|00000000|0x070000000|0x000000000000|0x08000000|
| 15|00000000|0x078000000|0x000490000000|0x08000000|
|-------------
IPU0log=: 3, ppuFormatK: 0x4da6, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b4,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 3, mask: fffffff8
tsensor type: 4, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=-------------------------------------|
=~=~=~=~=~=~=~=~=~=~= IMU Log @ 2026.5.13 3:13:23 =~=~=~=~=~=~=~=~=~=~=
[IMU] Watchdog Initialization done!
[RegisterInterruptSource]:[21] begin
Interrupt 32 register OK
Interrupt 34 regi
IPU0log=0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 4, mask: ffffffee
tsensor type: 5, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1

IPU1log= Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=ster OK
Interrupt 40 register OK
Interrupt 44 register OK
sram cnt 0x0, id = 43
Interrupt 43 register OK
Interrupt 36 register OK
Interrupt 57 register OK
sram cnt 0x0, id = 42
Interrupt 42 register OK
Interrupt 37 register OK
[
IPU0log=tsensor: 5, mask: ffffffda
tsensor type: 6, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 6, mask: ffffff80
tsensor type: 7, ppuFormatK: 0x437a,
IPU1log=KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=RegisterInterruptSource]:[39] end
IPMB initialization Start...
IPMB clock set done, prer = 0x18.
IPMB Rx FIFO clear empty.
IPMB initialization Done.
starting DFX Collect Task end
PowerTask Entry ...
Wait all vrd init done 
IPU0log= ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 7, mask: fffffffe
opposite dieId: 1, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
CPM max V[900]-
IPU1log= Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low
HSM0log=
IMU0log=...
All vrd init done, power task start
refresh domainId 0 Lsb 0x0
refresh domainId 9 Lsb 0x1
refresh domainId 2 Lsb 0x0
refresh domainId 7 Lsb 0x1
refresh domainId 4 Lsb 0x0
refresh domainId 1 Lsb 0x1
power sensor[0] | calib:51
IPU0log=F:2800
CPM min V[750]-F:1600
freq:2350, idx:9
cpm trim freq: 2600, idx: 4
cpm trim finish
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
recount hours 
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Fr
HSM0log=
IMU0log=20 | rshunt:1 | rshuntDiv:1000 | currLsb:1 | currLsbDiv:1000 | enableFlag:1
                | pwrLsb:25 | defPwr:25000 | minPwr:10000 | maxPwr:65000 | pwrFix:3400
                | manufacturerId: 0x5549 | dieId: 0x2260
power se
IPU0log=0x984 
hiboost task entry
boost wait SEF.
boost param OK.
Totem[0] Core[ 0] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[26
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=nsor[0] init success
ScmiTaskEntry start.
[RegisterInterruptSource]:[21] begin
Interrupt 51 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 52 register OK
[RegisterInterruptSource
IPU0log=00000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[12000
IPU1log= Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 53 register OK
[RegisterInterruptSource]:[39] end
[0.01.28.473]starting ras Init
RAS Setup Value get done!
INT_NUM_PER_SKT * HiGetSktNum() = 0x8
index = 0x0
RasIntRegi
IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Lim
IPU1log=KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=ster init 160 
index = 0x1
RasIntRegister init 172 
index = 0x2
RasIntRegister init 162 
index = 0x3
RasIntRegister init 174 
index = 0x4
RasIntRegister init 184 
index = 0x5
RasIntRegister init 196 
index = 0x6
RasIntRegister i
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IPU1log= Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low
HSM0log=
IMU0log=nit 186 
index = 0x7
RasIntRegister init 198 
RasIntRegister init 161 
RasIntRegister init 173 
RasIntRegister init 185 
RasIntRegister init 197 
RasIntRegister init 284 
RasIntRegister init 314 
MceTableHeadInit start
starting 
IPU0log=14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
To
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
uncore max freq : 23
HSM0log=
IMU0log=Ce_Storm Contrl and Ras_Data_Update Task end
[0.01.28.555]starting ras end
[IMU][ERR] skt id 0
Ub init task start Entry ...
UbInitTask Entry ...
[RegisterInterruptSource]:[21] begin
Interrupt 167 register OK
[RegisterInterrup
IPU0log=tem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[26
IPU1log=50 MHz

HSM0log=
IMU0log=tSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 191 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 171 register OK
[RegisterInterruptSource]:[39] end
[Register
IPU0log=00000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[12000
IPU1log=
HSM0log=
IMU0log=InterruptSource]:[21] begin
Interrupt 183 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 195 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Lim
IPU1log=
HSM0log=
IMU0log=
Interrupt 207 register OK
[RegisterInterruptSource]:[39] end
Init heart-beat-task end
CS0 flash do not support sfdp!
Current flash device ID[0x61a67c8]!
System supported 1 Flash.
flash cs 0 Manufacture 0xc8, DeviceId 0x1a67, A
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IPU1log=
HSM0log=
IMU0log=ddrMode[0-3B,1-4B] 0x1:
    size 0x4000000, pagesize 0x100
    read  cmd 0x13, dummy byte 0x8
    write cmd 0x12, dummy byte 0x0
    erase4k cmd 0x21, erase64k byte 0xdc
sfc init end
firstUnMskExt0Int
ThermalDimmStart Entry ...
IPU0log=33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
To
IPU1log=
HSM0log=
IMU0log=
wait ddr init done...
HacLowPowerStart Entry ...
Hello LiteOS...
pwr cap[0]: 0, 67
Init ReportPcieMmioToBmcTaskEntry end
starting Fpc Isolation Task end
pwr cap[1]: f, 27
pwr cap[2]: 1, 3
[0.01.59.765]DDR init done
[LOG]he
IPU0log=tem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[26
IPU1log=
HSM0log=
IMU0log=ad = 0x0, tail = 0x1805, logSize = 0x1805
[IMU][ERR] HsmLogInit!
[IMU][ERR] HsmLogInit! TRUE
set apei done!
UbConfigData size is 64
UbConfigData 0 : 0
UbConfigData 1 : 0
UbConfigData 2 : 0
UbConfigData 3 : 1
UbConfigData 4 : 31

IPU0log=00000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
uncore max freq : 2350 MHz

IPU1log=
HSM0log=
IMU0log=UbConfigData 5 : 1
UbConfigData 6 : 0
UbConfigData 7 : 32
UbConfigData 8 : 0
UbConfigData 9 : 1
UbConfigData 10 : 2
UbConfigData 11 : 0
UbConfigData 12 : 0
UbConfigData 13 : 1
UbConfigData 14 : 0
UbConfigData 15 : 0
UbConfigData
IPU0log=
IPU1log=
HSM0log=
IMU0log= 16 : 0
UbConfigData 17 : 0
UbConfigData 18 : 0
UbConfigData 19 : 0
UbConfigData 20 : 0
UbConfigData 21 : 0
UbConfigData 22 : 11
UbConfigData 23 : 0
UbConfigData 24 : 0
UbConfigData 25 : 0
UbConfigData 26 : 0
UbConfigData 27 : 0
IPU0log=
IPU1log=
HSM0log=
IMU0log=
UbConfigData 28 : 0
UbConfigData 29 : 0
UbConfigData 30 : 0
UbConfigData 31 : 0
UbConfigData 32 : 0
UbConfigData 33 : 0
UbConfigData 34 : 2
UbConfigData 35 : 1
UbConfigData 36 : 0
UbConfigData 37 : 0
UbConfigData 38 : 0
UbConfi
IPU0log=
IPU1log=
HSM0log=
IMU0log=gData 39 : 0
UbConfigData 40 : 0
UbConfigData 41 : 0
UbConfigData 42 : 0
UbConfigData 43 : 0
UbConfigData 44 : 0
UbConfigData 45 : 0
UbConfigData 46 : 0
UbConfigData 47 : 0
UbConfigData 48 : 0
UbConfigData 49 : 0
UbConfigData 50
IPU0log=
IPU1log=
HSM0log=
IMU0log= : 0
UbConfigData 51 : 0
UbConfigData 52 : 0
UbConfigData 53 : 0
UbConfigData 54 : 0
UbConfigData 55 : 0
UbConfigData 56 : 0
UbConfigData 57 : 0
UbConfigData 58 : 0
UbConfigData 59 : 0
UbConfigData 60 : 0
UbConfigData 61 : 0
UbC
IPU0log=
IPU1log=
HSM0log=
IMU0log=onfigData 62 : 0
UbConfigData 63 : 0
UbConfigData 64 : 0
ClusterSwitch: 0, 0
ClusterMode: 0, 0
ControlMode: 0, 0
EnumMode: 1, 1
BodyMask: 31, 31
CcCtxCount: 256, 256
RcCtxCount: 32, 32
UbMemEntrySize: 128, 0
MctpSupport: 1, 1
Se
IPU0log=
IPU1log=
HSM0log=
IMU0log=cureMode: 0, 0
PrimaryCna: 0, 0
Upi: 0, 0
EntityId: 0, 0
SlotId: 1, 1
SocketId: 2, 2
PortIndex: 0, 0
PortCna: 0, 0
CtrlCna: 11, 11
ImpBootFlag: 2, 2
ImuBootFlag: 1, 1
SktId: 0 DieId:2, HCCS_LINK:2 PaId:2
SktId: 1 DieId:2, HCCS_L
IPU0log=
IPU1log=
HSM0log=
IMU0log=INK:0 PaId:0
CIS register: ID[0xc00007ff], owner[0x1000003], function[0x1045dc5c].
CIS register: ID[0xc0000002], owner[0x1000003], function[0x1045dcfc].
odf: can not find od file[config]
Do not get NII route table, disable NII S
IPU0log=
IPU1log=
HSM0log=
IMU0log=end function.
UbiosTaskStart Entry ...
UbiosTaskStart create task success
IMU ImpBootFlag: 0x2
skip IMP start config...
UbiosCisTask Entry ...
ddr init done, start thermal dimm task
======dimm status======
  chl[0] dimm0 1, d
IPU0log=
IPU1log=
HSM0log=
IMU0log=imm1 0
  chl[1] dimm0 0, dimm1 0
  chl[2] dimm0 0, dimm1 0
  chl[3] dimm0 0, dimm1 0
  chl[4] dimm0 0, dimm1 0
  chl[5] dimm0 0, dimm1 0
  chl[6] dimm0 0, dimm1 0
  chl[7] dimm0 0, dimm1 0
  chl[8] dimm0 0, dimm1 0
  chl[9] dimm
IPU0log=
IPU1log=
HSM0log=
IMU0log=0 0, dimm1 0
  chl[10] dimm0 0, dimm1 0
  chl[11] dimm0 0, dimm1 0
==========end==========
sktId[0] chl[0] registered, dimm mask = 0x1
======dimm status======
  chl[0] dimm0 1, dimm1 0
  chl[1] dimm0 0, dimm1 0
  chl[2] dimm0 0,
IPU0log=
IPU1log=
HSM0log=
IMU0log= dimm1 0
  chl[3] dimm0 0, dimm1 0
  chl[4] dimm0 0, dimm1 0
  chl[5] dimm0 0, dimm1 0
  chl[6] dimm0 0, dimm1 0
  chl[7] dimm0 0, dimm1 0
  chl[8] dimm0 0, dimm1 0
  chl[9] dimm0 0, dimm1 0
  chl[10] dimm0 0, dimm1 0
  chl[11] 
IPU0log=
IPU1log=
HSM0log=
IMU0log=dimm0 0, dimm1 0
==========end==========
sktId[1] chl[0] registered, dimm mask = 0x1
=====dimm temp params=====
  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
  is_thermal_thro_en  : 1
  is_aref_rate_auto   :
IPU0log=
IPU1log=
HSM0log=
IMU0log= 0
===========end============
[0.02.06.717]TF Heartbeat Start
[0.02.08.122]RECEIVE MEM SILK.
0: skt = 0 logic = 1 phy = 0 
1: skt = 1 logic = 11 phy = 7 
2: skt = 0 logic = 4 phy = 2 
3: skt = 0 logic = 2 phy = 4 
4: skt = 1 log
IPU0log=
IPU1log=
HSM0log=
IMU0log=ic = 0 phy = 8 
5: skt = 1 logic = 5 phy = 6 
6: skt = 1 logic = 9 phy = 11 
7: skt = 1 logic = 1 phy = 0 
8: skt = 1 logic = 8 phy = 5 
9: skt = 0 logic = 9 phy = 11 
10: skt = 1 logic = 7 phy = 1 
11: skt = 0 logic = 0 phy = 8
IPU0log=
IPU1log=
HSM0log=
IMU0log= 
12: skt = 0 logic = 6 phy = 9 
13: skt = 1 logic = 4 phy = 2 
14: skt = 1 logic = 2 phy = 4 
15: skt = 1 logic = 10 phy = 3 
16: skt = 0 logic = 3 phy = 10 
17: skt = 1 logic = 6 phy = 9 
18: skt = 0 logic = 10 phy = 3 
19: sk
IPU0log=
IPU1log=
HSM0log=
IMU0log=t = 0 logic = 7 phy = 1 
20: skt = 1 logic = 3 phy = 10 
21: skt = 0 logic = 8 phy = 5 
22: skt = 0 logic = 5 phy = 6 
23: skt = 0 logic = 11 phy = 7 
get mem silk data length: 72
[0.02.11.101]PCIE INIT DONE.
[IMU][ERR] LOS_SemP
IPU0log=
IPU1log=
HSM0log=
IMU0log=end(g_pcieSemaphore, LOS_WAIT_FOREVER)
[RegisterInterruptSource]:[21] begin
Interrupt 258 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 262 register OK
[RegisterInterruptSource]
IPU0log=
IPU1log=
HSM0log=
IMU0log=:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 266 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 270 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterrup
IPU0log=
IPU1log=
HSM0log=
IMU0log=tSource]:[21] begin
Interrupt 277 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 288 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interru
IPU0log=
IPU1log=
HSM0log=
IMU0log=pt 292 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 296 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 300 register OK
[Register
IPU0log=
IPU1log=
HSM0log=
IMU0log=InterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 307 register OK
[RegisterInterruptSource]:[39] end
pmt Init done

-----------------ROUTE TABLE------------------
entryCount = 2
-----------------------
IPU0log=
IPU1log=
HSM0log=
IMU0log=-----------------------
[No.0]:
eidRange = 1, startEid = 10, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2500
[No.1]:
eidRange = 1, startEid = 9, port = 0, isStatic
IPU0log=
IPU1log=
HSM0log=
IMU0log= = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2100
----------------------------------------------
-----------------ROUTE TABLE------------------
entryCount = 2
-------------------------
IPU0log=
IPU1log=
HSM0log=
IMU0log=---------------------
[No.0]:
eidRange = 1, startEid = 10, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2500
[No.1]:
eidRange = 1, startEid = 9, port = 0, isStatic =
IPU0log=
IPU1log=
HSM0log=
IMU0log= 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2100
----------------------------------------------
-----------------ROUTE TABLE------------------
entryCount = 2
---------------------------
IPU0log=
IPU1log=
HSM0log=
IMU0log=-------------------
[No.0]:
eidRange = 1, startEid = 10, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2500
[No.1]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1
IPU0log=
IPU1log=
HSM0log=
IMU0log=, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2100
----------------------------------------------
HotPlug Open
slotNum = 42
portIdx = 0
portIdx = 1
portIdx = 2
portIdx = 3
portIdx = 4
IPU0log=
IPU1log=
HSM0log=
IMU0log=
portIdx = 5
portIdx = 6
portIdx = 7
portIdx = 8
portIdx = 9
portIdx = a
portIdx = b
portIdx = c
portIdx = d
portIdx = e
portIdx = f
portIdx = 10
portIdx = 11
portIdx = 12
portIdx = 13
portIdx = 14
portIdx = 15

IPU0log=
IPU1log=
HSM0log=
IMU0log=portIdx = 16
portIdx = 17
portIdx = 18
portIdx = 19
portIdx = 1a
portIdx = 1b
portIdx = 1c
portIdx = 1d
portIdx = 1e
portIdx = 1f
portIdx = 20
portIdx = 40
portIdx = 41
portIdx = 42
portIdx = 43
portIdx = 44
port
IPU0log=
IPU1log=
HSM0log=
IMU0log=Idx = 45
portIdx = 46
portIdx = 47
portIdx = 48
portIdx = 49
portIdx = 4a
portIdx = 4b
portIdx = 4c
portIdx = 4d
portIdx = 4e
portIdx = 4f
portIdx = 50
portIdx = 51
portIdx = 52
portIdx = 53
portIdx = 54
portIdx 
IPU0log=
IPU1log=
HSM0log=
IMU0log== 55
portIdx = 56
portIdx = 57
portIdx = 58
portIdx = 59
portIdx = 5a
portIdx = 5b
portIdx = 5c
portIdx = 5d
portIdx = 5e
portIdx = 5f
portIdx = 60
Pcie slot[0] port:0 base 0x2c01000000, pcieSlotCtrl.data (before)0x0
IPU0log=
IPU1log=
HSM0log=
IMU0log=.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[0] port:0 base 0x2c01000000, pcieSlotCtrl.data (after)0x0.

Pcie slot[1] port:1 base 0x2c01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.pre
IPU0log=
IPU1log=
HSM0log=
IMU0log=sencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[1] port:1 base 0x2c01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[2] port:2 base 0x2c01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
p
IPU0log=
IPU1log=
HSM0log=
IMU0log=resent:1, pwr_en:0.
Pcie slot[2] port:2 base 0x2c01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[3] port:3 base 0x2c01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
IPU0log=
IPU1log=
HSM0log=
IMU0log=
Pcie slot[3] port:3 base 0x2c01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[4] port:4 base 0x2c01000000, pcieSlotCtrl.data (before)0x10003c0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[4
IPU0log=
IPU1log=
HSM0log=
IMU0log=] port:4 base 0x2c01000000, pcieSlotCtrl.data (after)0x14801c0.

Pcie slot[5] port:5 base 0x2c01000000, pcieSlotCtrl.data (before)0x3c0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[5] port:5 base 0x
IPU0log=
IPU1log=
HSM0log=
IMU0log=2c01000000, pcieSlotCtrl.data (after)0x4801c0.

Pcie slot[6] port:6 base 0x2c01000000, pcieSlotCtrl.data (before)0x3c0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[6] port:6 base 0x2c01000000, pcieS
IPU0log=
IPU1log=
HSM0log=
IMU0log=lotCtrl.data (after)0x4801c0.

Pcie slot[7] port:7 base 0x2c01000000, pcieSlotCtrl.data (before)0x3c0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[7] port:7 base 0x2c01000000, pcieSlotCtrl.data (aft
IPU0log=
IPU1log=
HSM0log=
IMU0log=er)0x4801c0.

Pcie slot[8] port:8 base 0x2c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[8] port:8 base 0x2c02000000, pcieSlotCtrl.data (after)0x0.

Pcie slo
IPU0log=
IPU1log=
HSM0log=
IMU0log=t[9] port:9 base 0x2c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[9] port:9 base 0x2c02000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[10] port:10 base 
IPU0log=
IPU1log=
HSM0log=
IMU0log=0x2c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[10] port:10 base 0x2c02000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[11] port:11 base 0x2c02000000, p
IPU0log=
IPU1log=
HSM0log=
IMU0log=cieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[11] port:11 base 0x2c02000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[12] port:12 base 0x2c02000000, pcieSlotCtrl.dat
IPU0log=
IPU1log=
HSM0log=
IMU0log=a (before)0x10003c0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[12] port:12 base 0x2c02000000, pcieSlotCtrl.data (after)0x14801c0.

Pcie slot[13] port:13 base 0x2c02000000, pcieSlotCtrl.data (befor
IPU0log=
IPU1log=
HSM0log=
IMU0log=e)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[13] port:13 base 0x2c02000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[14] port:14 base 0x2c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlo
IPU0log=
IPU1log=
HSM0log=
IMU0log=tCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[14] port:14 base 0x2c02000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[15] port:15 base 0x2c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.pres
IPU0log=
IPU1log=
HSM0log=
IMU0log=encd_det_st = 1
present:1, pwr_en:0.
Pcie slot[15] port:15 base 0x2c02000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[16] port:16 base 0x2d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
IPU0log=
IPU1log=
HSM0log=
IMU0log=
present:1, pwr_en:0.
Pcie slot[16] port:16 base 0x2d01000000, pcieSlotCtrl.data (after)0x0.

Pcie slot[17] port:17 base 0x2d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:
IPU0log=
IPU1log=
HSM0log=
IMU0log=0.
Pcie slot[17] port:17 base 0x2d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[18] port:18 base 0x2d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[1
IPU0log=
IPU1log=
HSM0log=
IMU0log=8] port:18 base 0x2d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[19] port:19 base 0x2d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[19] port:19 base
IPU0log=
IPU1log=
HSM0log=
IMU0log= 0x2d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[20] port:20 base 0x2d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[20] port:20 base 0x2d01000000, 
IPU0log=
IPU1log=
HSM0log=
IMU0log=pcieSlotCtrl.data (after)0x480100.

Pcie slot[21] port:21 base 0x2d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[21] port:21 base 0x2d01000000, pcieSlotCtrl.da
IPU0log=
IPU1log=
HSM0log=
IMU0log=ta (after)0x480100.

Pcie slot[22] port:22 base 0x2d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[22] port:22 base 0x2d01000000, pcieSlotCtrl.data (after)0x480
IPU0log=
IPU1log=
HSM0log=
IMU0log=100.

Pcie slot[23] port:23 base 0x2d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[23] port:23 base 0x2d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie sl
IPU0log=
IPU1log=
HSM0log=
IMU0log=ot[24] port:24 base 0x2d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[24] port:24 base 0x2d02000000, pcieSlotCtrl.data (after)0x0.

Pcie slot[25] port:25 base 
IPU0log=
IPU1log=
HSM0log=
IMU0log=0x2d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[25] port:25 base 0x2d02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[26] port:26 base 0x2d02000000, pcie
IPU0log=
IPU1log=
HSM0log=
IMU0log=SlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[26] port:26 base 0x2d02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[27] port:27 base 0x2d02000000, pcieSlotCtrl.data (bef
IPU0log=
IPU1log=
HSM0log=
IMU0log=ore)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[27] port:27 base 0x2d02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[28] port:28 base 0x2d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlot
IPU0log=
IPU1log=
HSM0log=
IMU0log=Ctrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[28] port:28 base 0x2d02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[29] port:29 base 0x2d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd
IPU0log=
IPU1log=
HSM0log=
IMU0log=_det_st = 0
present:0, pwr_en:1.
Pcie slot[29] port:29 base 0x2d02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[30] port:30 base 0x2d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
prese
IPU0log=
IPU1log=
HSM0log=
IMU0log=nt:0, pwr_en:1.
Pcie slot[30] port:30 base 0x2d02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[31] port:31 base 0x2d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
P
IPU0log=
IPU1log=
HSM0log=
IMU0log=cie slot[31] port:31 base 0x2d02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[32] port:32 base 0x3210000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[32] port:
IPU0log=
IPU1log=
HSM0log=
IMU0log=32 base 0x3210000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[33] port:0 base 0x6c01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[33] port:0 base 0x6c01000000
IPU0log=
IPU1log=
HSM0log=
IMU0log=, pcieSlotCtrl.data (after)0x0.

Pcie slot[34] port:1 base 0x6c01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[34] port:1 base 0x6c01000000, pcieSlotCtrl.data (a
IPU0log=
IPU1log=
HSM0log=
IMU0log=fter)0x480100.

Pcie slot[35] port:2 base 0x6c01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[35] port:2 base 0x6c01000000, pcieSlotCtrl.data (after)0x480100.

IPU0log=
IPU1log=
HSM0log=
IMU0log=
Pcie slot[36] port:3 base 0x6c01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[36] port:3 base 0x6c01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[37] po
IPU0log=
IPU1log=
HSM0log=
IMU0log=rt:4 base 0x6c01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[37] port:4 base 0x6c01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[38] port:5 base 0x6c010
IPU0log=
IPU1log=
HSM0log=
IMU0log=00000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[38] port:5 base 0x6c01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[39] port:6 base 0x6c01000000, pcieSlotCt
IPU0log=
IPU1log=
HSM0log=
IMU0log=rl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[39] port:6 base 0x6c01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[40] port:7 base 0x6c01000000, pcieSlotCtrl.data (before)0
IPU0log=
IPU1log=
HSM0log=
IMU0log=x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[40] port:7 base 0x6c01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[41] port:8 base 0x6c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl
IPU0log=
IPU1log=
HSM0log=
IMU0log=.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[41] port:8 base 0x6c02000000, pcieSlotCtrl.data (after)0x0.

Pcie slot[42] port:9 base 0x6c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st 
IPU0log=
IPU1log=
HSM0log=
IMU0log== 0
present:0, pwr_en:1.
Pcie slot[42] port:9 base 0x6c02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[43] port:10 base 0x6c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr
IPU0log=
IPU1log=
HSM0log=
IMU0log=_en:1.
Pcie slot[43] port:10 base 0x6c02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[44] port:11 base 0x6c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[
IPU0log=
IPU1log=
HSM0log=
IMU0log=44] port:11 base 0x6c02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[45] port:12 base 0x6c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[45] port:12 base 0
IPU0log=
IPU1log=
HSM0log=
IMU0log=x6c02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[46] port:13 base 0x6c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[46] port:13 base 0x6c02000000, pcieS
IPU0log=
IPU1log=
HSM0log=
IMU0log=lotCtrl.data (after)0x700.

Pcie slot[47] port:14 base 0x6c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[47] port:14 base 0x6c02000000, pcieSlotCtrl.data (afte
IPU0log=
IPU1log=
HSM0log=
IMU0log=r)0x700.

Pcie slot[48] port:15 base 0x6c02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[48] port:15 base 0x6c02000000, pcieSlotCtrl.data (after)0x700.

Pcie s
IPU0log=
IPU1log=
HSM0log=
IMU0log=lot[49] port:16 base 0x6d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[49] port:16 base 0x6d01000000, pcieSlotCtrl.data (after)0x0.

Pcie slot[50] port:17 base
IPU0log=
IPU1log=
HSM0log=
IMU0log= 0x6d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[50] port:17 base 0x6d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[51] port:18 base 0x6d01000000, 
IPU0log=
IPU1log=
HSM0log=
IMU0log=pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[51] port:18 base 0x6d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[52] port:19 base 0x6d01000000, pcieSlotCtrl.da
IPU0log=
IPU1log=
HSM0log=
IMU0log=ta (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[52] port:19 base 0x6d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[53] port:20 base 0x6d01000000, pcieSlotCtrl.data (before)0x0.
IPU0log=
IPU1log=
HSM0log=
IMU0log=
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[53] port:20 base 0x6d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[54] port:21 base 0x6d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.
IPU0log=
IPU1log=
HSM0log=
IMU0log=bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[54] port:21 base 0x6d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[55] port:22 base 0x6d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_d
IPU0log=
IPU1log=
HSM0log=
IMU0log=et_st = 1
present:1, pwr_en:0.
Pcie slot[55] port:22 base 0x6d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[56] port:23 base 0x6d01000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 1
pres
IPU0log=
IPU1log=
HSM0log=
IMU0log=ent:1, pwr_en:0.
Pcie slot[56] port:23 base 0x6d01000000, pcieSlotCtrl.data (after)0x480100.

Pcie slot[57] port:24 base 0x6d02000000, pcieSlotCtrl.data (before)0x3c0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en
IPU0log=
IPU1log=
HSM0log=
IMU0log=:1.
Pcie slot[57] port:24 base 0x6d02000000, pcieSlotCtrl.data (after)0x7c0.

Pcie slot[58] port:25 base 0x6d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[58]
IPU0log=
IPU1log=
HSM0log=
IMU0log= port:25 base 0x6d02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[59] port:26 base 0x6d02000000, pcieSlotCtrl.data (before)0x3c0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[59] port:26 base 0x
IPU0log=
IPU1log=
HSM0log=
IMU0log=6d02000000, pcieSlotCtrl.data (after)0x7c0.

Pcie slot[60] port:27 base 0x6d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[60] port:27 base 0x6d02000000, pcieSl
IPU0log=
IPU1log=
HSM0log=
IMU0log=otCtrl.data (after)0x700.

Pcie slot[61] port:28 base 0x6d02000000, pcieSlotCtrl.data (before)0x3c0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[61] port:28 base 0x6d02000000, pcieSlotCtrl.data (aft
IPU0log=
IPU1log=
HSM0log=
IMU0log=er)0x7c0.

Pcie slot[62] port:29 base 0x6d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[62] port:29 base 0x6d02000000, pcieSlotCtrl.data (after)0x700.

Pcie 
IPU0log=
IPU1log=
HSM0log=
IMU0log=slot[63] port:30 base 0x6d02000000, pcieSlotCtrl.data (before)0x3c0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[63] port:30 base 0x6d02000000, pcieSlotCtrl.data (after)0x7c0.

Pcie slot[64] port:31
IPU0log=
IPU1log=
HSM0log=
IMU0log= base 0x6d02000000, pcieSlotCtrl.data (before)0x0.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[64] port:31 base 0x6d02000000, pcieSlotCtrl.data (after)0x700.

Pcie slot[65] port:32 base 0x7210000000
IPU0log=
IPU1log=
HSM0log=
IMU0log=, pcieSlotCtrl.data (before)0xffffffff.
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[65] port:32 base 0x7210000000, pcieSlotCtrl.data (after)0xffffffff.

[RegisterInterruptSource]:[21] begin
Interru
IPU0log=
IPU1log=
HSM0log=
IMU0log=pt 61 register OK
[RegisterInterruptSource]:[39] end
fristMskExt0Int

Pcie Hotplug init done, with 66 port(s).
[0.06.23.562]BIOS POST END.
slot[0] port:0 begin to power ON.
slot[0] port:0 pwr_indicator = 0, att_indicator = 0
IPU0log=
IPU1log=
HSM0log=
IMU0log=
ledStatus:0 invalid!
[HotPlugMonitorTask][248L]Pcie slot[0] port:0 base 0x2c01000000, pcieSlotCtrl.data (after)0x100000.
slot[1] port:1 begin to power ON.
slot[2] port:2 begin to power ON.
slot[3] port:3 begin to power ON.
IPU0log=
IPU1log=
HSM0log=
IMU0log=
slot[4] port:4 begin to power ON.
slot[5] port:5 begin to power ON.
slot[6] port:6 begin to power ON.
slot[7] port:7 begin to power ON.
slot[8] port:8 begin to power ON.
slot[8] port:8 pwr_indicator = 0, att_indicator = 0
IPU0log=
IPU1log=
HSM0log=
IMU0log=
ledStatus:0 invalid!
[HotPlugMonitorTask][248L]Pcie slot[8] port:8 base 0x2c02000000, pcieSlotCtrl.data (after)0x100000.
slot[9] port:9 begin to power ON.
slot[10] port:10 begin to power ON.
slot[11] port:11 begin to power
IPU0log=
IPU1log=
HSM0log=
IMU0log= ON.
slot[12] port:12 begin to power ON.
slot[13] port:13 begin to power ON.
slot[14] port:14 begin to power ON.
slot[15] port:15 begin to power ON.
slot[16] port:16 begin to power ON.
slot[16] port:16 pwr_indicator = 0, a
IPU0log=
IPU1log=
HSM0log=
IMU0log=tt_indicator = 0
ledStatus:0 invalid!
[HotPlugMonitorTask][248L]Pcie slot[16] port:16 base 0x2d01000000, pcieSlotCtrl.data (after)0x100000.
slot[17] port:17 begin to power ON.
slot[18] port:18 begin to power ON.
slot[19] po
IPU0log=
IPU1log=
HSM0log=
IMU0log=rt:19 begin to power ON.
slot[20] port:20 begin to power ON.
slot[21] port:21 begin to power ON.
slot[22] port:22 begin to power ON.
slot[23] port:23 begin to power ON.
slot[24] port:24 pwr_indicator = 0, att_indicator = 0
IPU0log=
IPU1log=
HSM0log=
IMU0log=
ledStatus:0 invalid!
[HotPlugMonitorTask][248L]Pcie slot[24] port:24 base 0x2d02000000, pcieSlotCtrl.data (after)0x100000.
slot[25] port:25 begin to power OFF.
slot[26] port:26 begin to power OFF.
slot[27] port:27 begin to 
IPU0log=
IPU1log=
HSM0log=
IMU0log=power OFF.
slot[28] port:28 begin to power OFF.
slot[29] port:29 begin to power OFF.
slot[30] port:30 begin to power OFF.
slot[31] port:31 begin to power OFF.
slot[32] port:32 begin to power OFF.
slot[33] port:0 begin to p
IPU0log=
IPU1log=
HSM0log=
IMU0log=ower ON.
slot[33] port:0 pwr_indicator = 0, att_indicator = 0
ledStatus:0 invalid!
[HotPlugMonitorTask][248L]Pcie slot[33] port:0 base 0x6c01000000, pcieSlotCtrl.data (after)0x100000.
slot[34] port:1 begin to power ON.
slot
IPU0log=
IPU1log=
HSM0log=
IMU0log=[35] port:2 begin to power ON.
slot[36] port:3 begin to power ON.
slot[37] port:4 begin to power ON.
slot[38] port:5 begin to power ON.
slot[39] port:6 begin to power ON.
slot[40] port:7 begin to power ON.
slot[41] port:8 
IPU0log=
IPU1log=
HSM0log=
IMU0log=pwr_indicator = 0, att_indicator = 0
ledStatus:0 invalid!
[HotPlugMonitorTask][248L]Pcie slot[41] port:8 base 0x6c02000000, pcieSlotCtrl.data (after)0x100000.
slot[42] port:9 begin to power OFF.
slot[43] port:10 begin to pow
IPU0log=
IPU1log=
HSM0log=
IMU0log=er OFF.
[0.06.24.018]slot[44] port:11 begin to power OFF.
wait 5 mins to update pciemmio..
slot[45] port:12 begin to power OFF.
slot[46] port:13 begin to power OFF.
slot[47] port:14 begin to power OFF.
slot[48] port:15 begi
IPU0log=
IPU1log=
HSM0log=
IMU0log=n to power OFF.
slot[49] port:16 begin to power ON.
slot[49] port:16 pwr_indicator = 0, att_indicator = 0
ledStatus:0 invalid!
[HotPlugMonitorTask][248L]Pcie slot[49] port:16 base 0x6d01000000, pcieSlotCtrl.data (after)0x100
IPU0log=
IPU1log=
HSM0log=
IMU0log=000.
slot[50] port:17 begin to power ON.
slot[51] port:18 begin to power ON.
slot[52] port:19 begin to power ON.
slot[53] port:20 begin to power ON.
slot[54] port:21 begin to power ON.
slot[55] port:22 begin to power ON.

IPU0log=
IPU1log=
HSM0log=
IMU0log=slot[56] port:23 begin to power ON.
slot[57] port:24 begin to power OFF.
slot[58] port:25 begin to power OFF.
slot[59] port:26 begin to power OFF.
slot[60] port:27 begin to power OFF.
slot[61] port:28 begin to power OFF.
s
IPU0log=
IPU1log=
HSM0log=
IMU0log=lot[62] port:29 begin to power OFF.
slot[63] port:30 begin to power OFF.
slot[64] port:31 begin to power OFF.
slot[65] port:32 begin to power OFF.
[0.11.24.051]IpmiCmdReportPcieMMIO start
[0.11.27.789]IpmiCmdReportPcieMMIO e
IPU0log=
IPU1log=
HSM0log=
IMU0log=nd

IPU0log=
IPU1log=
HSM0log=
IMU0log=1T1N1U skt:0 CfgBusDfxPreConfig finish

********Hello Huawei LiteOS********

IMU Firmware Version : B173V01
LiteOS Kernel Version : 5.10.0
Run on Socket[0] Die[3]
Chip Version: 1
Max socket num: 2
*******************************
IPU0log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 0
cls: 6, core: 7
cpu 933 sram 1010 ddr 983
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  750|  802|  885|  933|
max  v
IPU1log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 1
cls: 6, core: 7
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  759|  821|  909|  961|
max  v: |  750|  750|  753|  781
IMU0log=***
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | rail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_vo
IPU0log=: |  750|  750|  754|  775|  836|  922|  980|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:7
IPU1log=|  846|  938|  994|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:750 F:1950
avs-uncore V:750
HSM0log=[1970-01-01 00:01:12.571][HSM][INFO][30] init start
[1970-01-01 00:01:12.571][HSM][INFO][38] init over
[00:01:12.581][info] succeed to do thirdparty dfx_pabuk init
[00:01:12.586][info] os_mem_system_init default pool done
[0
IMU0log=lt:1122 mV | pmu:MP2882
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_v
IPU0log=50 F:1950
avs-uncore V:750 F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
av
IPU1log= F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
avs-uncore V:840 F:2450
avs-
HSM0log=0:01:12.592][info] addr is already in region
[00:01:12.595][info] succeed to do thirdparty otpc_pabuk init
[1970-01-01 00:01:12.601][HSM][INFO][31] select_region: 0xc11cb55b
[1970-01-01 00:01:12.607][HSM][INFO][67] spi_nor de
IMU0log=olt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_
IPU0log=s-uncore V:840 F:2450
avs-uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain
IPU1log=uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | r
HSM0log=vice_id 0xff1a67c8
[1970-01-01 00:01:12.613][HSM][INFO][50] std_cmd readback 0x30220d8
[1970-01-01 00:01:12.619][HSM][INFO][72] saf_cmd 0x0 readback 0x9f5a0604
[1970-01-01 00:01:12.625][HSM][INFO][72] saf_cmd 0x1 readback 0x5
IMU0log=volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus r
IPU0log=[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | p
IPU1log=ail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_volt:1122 mV | pmu:MP2882
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[0] volt =  906 mV
pwr domain
HSM0log=b7e938
[1970-01-01 00:01:12.631][HSM][INFO][72] saf_cmd 0x2 readback 0x1
[1970-01-01 00:01:12.637][HSM][INFO][72] saf_cmd 0x3 readback 0x0
[1970-01-01 00:01:12.643][HSM][INFO][72] saf_cmd 0x4 readback 0x0
[00:01:12.650][info
IMU0log=eady.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait th
IPU0log=mu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pmbus:0x480c0000 ver:0x110
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
IPU1log=[9] volt = 1103 mV
=end=
w&h rd rail:0, 906
w&h rd rail:1, 1101
pwr domain[0] set volt  904 mV succ
pwr domain[9] set volt 1103 mV succ
volt post
pwr domain[0] volt =  904 mV
pwr domain[9] volt = 1103 mV
==end==
Totem[0] Core Bo
HSM0log=] succeed to do thirdparty boot_profile_driver init
[00:01:12.655][info] succeed to do thirdparty crypto_driver init
[00:01:12.661][info] succeed to do thirdparty period_driver init
[00:01:12.667][info]  start loading interna
IMU0log=e cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master I
IPU0log=
avsbus resync succ
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[2] volt =  904 mV
pwr domain[7] volt =  802 mV
pwr domain[4] volt =  804 mV
pwr domain[1] volt =  804 mV
=end=
w&h rd rail:
IPU1log=ot Vol [1029]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2,
HSM0log=l task ...
[00:01:12.671][info]  task name is ccm_task
[00:01:12.675][info]  hm_dynamic_loadelf successfully!
[00:01:12.680][info] internal task[1] task_name=ccm_task load successfully
[00:01:12.687][info]  task name is upgr
IMU0log=mu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
cpu 0 entering scheduler
|--------------------------------------------------|
AtsPrint
|idx|lockCount| srcAddr| destAddr| addrLen|
|--
IPU0log=0, 904
w&h rd rail:1, 802
pwr domain[2] set volt  902 mV succ
pwr domain[7] set volt  802 mV succ
w&h rd rail:0, 804
w&h rd rail:1, 804
pwr domain[4] set volt  802 mV succ
pwr domain[1] set volt  802 mV succ
volt post
pwr domain
IPU1log= ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd8
HSM0log=ade_task
[00:01:12.691][info]  hm_dynamic_loadelf successfully!
[00:01:12.696][info] internal task[2] task_name=upgrade_task load successfully
[00:01:12.703][info] created task ccm_task success!
[00:01:12.707][info] created 
IMU0log=------------------------------------------------|
|  0|00000000|0x010500000|0x000110800000|0x00100000|
|  1|00000000|0x020000000|0x00001d000000|0x00800000|
|  2|00000000|0x020800000|0x000490000000|0x00100000|
|  3|00000000|0x020
IPU0log=[2] volt =  902 mV
pwr domain[7] volt =  800 mV
pwr domain[4] volt =  804 mV
pwr domain[1] volt =  802 mV
==end==
Totem[0] Core Boot Vol [1015]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0,
IPU1log=00, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
opposite dieId: 0, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 
HSM0log=task upgrade_task success!
[1970-01-01 00:01:12.712][HSM][INFO][54] Platform init 0x20250523 0x4e.
[1970-01-01 00:01:12.719][HSM][INFO][197] ccm start.
[1970-01-01 00:01:12.723][HSM][INFO][86] upgrade task init success.
[197
IMU0log=900000|0x000004000000|0x08000000|
|  4|00000000|0x028900000|0x000440580000|0x01000000|
|  5|00000000|0x029900000|0x000590000000|0x00100000|
|  6|00000000|0x029a00000|0x002000150000|0x00100000|
|  7|00000000|0x000000000|0x0000000
IPU0log= MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 
IPU1log=enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
hiboost task entry
boost wait SEF.
[INFO] mem used of task 'app_Task' is:0x2028, not zero when task being deleted
boost param OK.
Totem[0] Core[ 0] Freq Limit Low
HSM0log=0-01-01 00:01:12.729][HSM][INFO][95] upgrade recv cmd, 0x181.
[1970-01-01 00:01:12.735][HSM][INFO][103] upgrade res, 0x3a5aa5a3.
.
IMU0log=00000|0x00000000|
|  8|00000000|0x040000000|0x000000000000|0x08000000|
|  9|00000000|0x048000000|0x000000000000|0x08000000|
| 10|00000000|0x050000000|0x000000000000|0x08000000|
| 11|00000000|0x058000000|0x000000000000|0x08000000
IPU0log=0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
tsensor type
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Fr
HSM0log=
IMU0log=|
| 12|00000000|0x060000000|0x000000000000|0x08000000|
| 13|00000000|0x068000000|0x000000000000|0x08000000|
| 14|00000000|0x070000000|0x000000000000|0x08000000|
| 15|00000000|0x078000000|0x000490000000|0x08000000|
|-------------
IPU0log=: 3, ppuFormatK: 0x4da6, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b4,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 3, mask: fffffff8
tsensor type: 4, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=-------------------------------------|
=~=~=~=~=~=~=~=~=~=~= IMU Log @ 2026.5.13 3:57:30 =~=~=~=~=~=~=~=~=~=~=
[IMU] Watchdog Initialization done!
[RegisterInterruptSource]:[21] begin
Interrupt 32 register OK
Interrupt 34 regi
IPU0log=0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 4, mask: ffffffee
tsensor type: 5, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1

IPU1log= Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=ster OK
Interrupt 40 register OK
Interrupt 44 register OK
sram cnt 0x0, id = 43
Interrupt 43 register OK
Interrupt 36 register OK
Interrupt 57 register OK
sram cnt 0x0, id = 42
Interrupt 42 register OK
Interrupt 37 register OK
[
IPU0log=tsensor: 5, mask: ffffffda
tsensor type: 6, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 6, mask: ffffff80
tsensor type: 7, ppuFormatK: 0x437a,
IPU1log=KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=RegisterInterruptSource]:[39] end
IPMB initialization Start...
IPMB clock set done, prer = 0x18.
IPMB Rx FIFO clear empty.
IPMB initialization Done.
starting DFX Collect Task end
PowerTask Entry ...
Wait all vrd init done 
IPU0log= ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 7, mask: fffffffe
opposite dieId: 1, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
CPM max V[900]-
IPU1log= Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low
HSM0log=
IMU0log=...
All vrd init done, power task start
refresh domainId 0 Lsb 0x0
refresh domainId 9 Lsb 0x1
refresh domainId 2 Lsb 0x0
refresh domainId 7 Lsb 0x1
refresh domainId 4 Lsb 0x0
refresh domainId 1 Lsb 0x1
power sensor[0] | calib:51
IPU0log=F:2800
CPM min V[750]-F:1600
freq:2350, idx:9
cpm trim freq: 2600, idx: 4
cpm trim finish
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
recount hours 
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Fr
HSM0log=
IMU0log=20 | rshunt:1 | rshuntDiv:1000 | currLsb:1 | currLsbDiv:1000 | enableFlag:1
                | pwrLsb:25 | defPwr:25000 | minPwr:10000 | maxPwr:65000 | pwrFix:3400
                | manufacturerId: 0x5549 | dieId: 0x2260
power se
IPU0log=0x984 
hiboost task entry
boost wait SEF.
boost param OK.
Totem[0] Core[ 0] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[26
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=nsor[0] init success
ScmiTaskEntry start.
[RegisterInterruptSource]:[21] begin
Interrupt 51 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 52 register OK
[RegisterInterruptSource
IPU0log=00000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[12000
IPU1log= Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 53 register OK
[RegisterInterruptSource]:[39] end
[0.01.29.269]starting ras Init
RAS Setup Value get done!
INT_NUM_PER_SKT * HiGetSktNum() = 0x8
index = 0x0
RasIntRegi
IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Lim
IPU1log=KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=ster init 160 
index = 0x1
RasIntRegister init 172 
index = 0x2
RasIntRegister init 162 
index = 0x3
RasIntRegister init 174 
index = 0x4
RasIntRegister init 184 
index = 0x5
RasIntRegister init 196 
index = 0x6
RasIntRegister i
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IPU1log= Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low
HSM0log=
IMU0log=nit 186 
index = 0x7
RasIntRegister init 198 
RasIntRegister init 161 
RasIntRegister init 173 
RasIntRegister init 185 
RasIntRegister init 197 
RasIntRegister init 284 
RasIntRegister init 314 
MceTableHeadInit start
starting 
IPU0log=14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
To
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
uncore max freq : 23
HSM0log=
IMU0log=Ce_Storm Contrl and Ras_Data_Update Task end
[0.01.29.350]starting ras end
[IMU][ERR] skt id 0
Ub init task start Entry ...
UbInitTask Entry ...
[RegisterInterruptSource]:[21] begin
Interrupt 167 register OK
[RegisterInterrup
IPU0log=tem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[26
IPU1log=50 MHz

HSM0log=
IMU0log=tSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 191 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 171 register OK
[RegisterInterruptSource]:[39] end
[Register
IPU0log=00000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[12000
IPU1log=
HSM0log=
IMU0log=InterruptSource]:[21] begin
Interrupt 183 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 195 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Lim
IPU1log=
HSM0log=
IMU0log=
Interrupt 207 register OK
[RegisterInterruptSource]:[39] end
Init heart-beat-task end
CS0 flash do not support sfdp!
Current flash device ID[0x61a67c8]!
System supported 1 Flash.
flash cs 0 Manufacture 0xc8, DeviceId 0x1a67, A
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IPU1log=
HSM0log=
IMU0log=ddrMode[0-3B,1-4B] 0x1:
    size 0x4000000, pagesize 0x100
    read  cmd 0x13, dummy byte 0x8
    write cmd 0x12, dummy byte 0x0
    erase4k cmd 0x21, erase64k byte 0xdc
sfc init end
firstUnMskExt0Int
ThermalDimmStart Entry ...
IPU0log=33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
To
IPU1log=
HSM0log=
IMU0log=
wait ddr init done...
HacLowPowerStart Entry ...
Hello LiteOS...
Init ReportPcieMmioToBmcTaskEntry end
starting Fpc Isolation Task end
pwr cap[0]: 0, 67
pwr cap[1]: f, 27
pwr cap[2]: 1, 3
DDR initing...
[0.02.01.650]DDR in
IPU0log=tem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[26
IPU1log=
HSM0log=
IMU0log=it done
[LOG]head = 0x0, tail = 0x1730, logSize = 0x1730
[IMU][ERR] HsmLogInit!
[IMU][ERR] HsmLogInit! TRUE
set apei done!
UbConfigData size is 64
UbConfigData 0 : 0
UbConfigData 1 : 0
UbConfigData 2 : 0
UbConfigData 3 : 1
UbCon
IPU0log=00000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
uncore max freq : 2350 MHz

IPU1log=
HSM0log=
IMU0log=figData 4 : 31
UbConfigData 5 : 1
UbConfigData 6 : 0
UbConfigData 7 : 32
UbConfigData 8 : 0
UbConfigData 9 : 1
UbConfigData 10 : 2
UbConfigData 11 : 0
UbConfigData 12 : 0
UbConfigData 13 : 1
UbConfigData 14 : 0
UbConfigData 15 :
IPU0log=
IPU1log=
HSM0log=
IMU0log= 0
UbConfigData 16 : 0
UbConfigData 17 : 0
UbConfigData 18 : 0
UbConfigData 19 : 0
UbConfigData 20 : 0
UbConfigData 21 : 0
UbConfigData 22 : 11
UbConfigData 23 : 0
UbConfigData 24 : 0
UbConfigData 25 : 0
UbConfigData 26 : 0
UbCo
IPU0log=
IPU1log=
HSM0log=
IMU0log=nfigData 27 : 0
UbConfigData 28 : 0
UbConfigData 29 : 0
UbConfigData 30 : 0
UbConfigData 31 : 0
UbConfigData 32 : 0
UbConfigData 33 : 0
UbConfigData 34 : 2
UbConfigData 35 : 1
UbConfigData 36 : 0
UbConfigData 37 : 0
UbConfigData
IPU0log=
IPU1log=
HSM0log=
IMU0log= 38 : 0
UbConfigData 39 : 0
UbConfigData 40 : 0
UbConfigData 41 : 0
UbConfigData 42 : 0
UbConfigData 43 : 0
UbConfigData 44 : 0
UbConfigData 45 : 0
UbConfigData 46 : 0
UbConfigData 47 : 0
UbConfigData 48 : 0
UbConfigData 49 : 0

IPU0log=
IPU1log=
HSM0log=
IMU0log=UbConfigData 50 : 0
UbConfigData 51 : 0
UbConfigData 52 : 0
UbConfigData 53 : 0
UbConfigData 54 : 0
UbConfigData 55 : 0
UbConfigData 56 : 0
UbConfigData 57 : 0
UbConfigData 58 : 0
UbConfigData 59 : 0
UbConfigData 60 : 0
UbConfig
IPU0log=
IPU1log=
HSM0log=
IMU0log=Data 61 : 0
UbConfigData 62 : 0
UbConfigData 63 : 0
UbConfigData 64 : 0
ClusterSwitch: 0, 0
ClusterMode: 0, 0
ControlMode: 0, 0
EnumMode: 1, 1
BodyMask: 31, 31
CcCtxCount: 256, 256
RcCtxCount: 32, 32
UbMemEntrySize: 128, 0
MctpS
IPU0log=
IPU1log=
HSM0log=
IMU0log=upport: 1, 1
SecureMode: 0, 0
PrimaryCna: 0, 0
Upi: 0, 0
EntityId: 0, 0
SlotId: 1, 1
SocketId: 2, 2
PortIndex: 0, 0
PortCna: 0, 0
CtrlCna: 11, 11
ImpBootFlag: 2, 2
ImuBootFlag: 1, 1
SktId: 0 DieId:2, HCCS_LINK:2 PaId:2
SktId: 1 
IPU0log=
IPU1log=
HSM0log=
IMU0log=DieId:2, HCCS_LINK:0 PaId:0
CIS register: ID[0xc00007ff], owner[0x1000003], function[0x1045dc5c].
CIS register: ID[0xc0000002], owner[0x1000003], function[0x1045dcfc].
odf: can not find od file[config]
Do not get NII route table
IPU0log=
IPU1log=
HSM0log=
IMU0log=, disable NII Send function.
UbiosTaskStart Entry ...
UbiosTaskStart create task success
IMU ImpBootFlag: 0x2
skip IMP start config...
UbiosCisTask Entry ...
BMC_COLLECTION: bmc req last log!
[IMU][ERR] [
HSM0log= no log data
IPU0log=
IPU1log=
HSM0log=
IMU0log= error!]
ddr init done, start thermal dimm task
======dimm status======
  chl[0] dimm0 1, dimm1 0
  chl[1] dimm0 0, dimm1 0
  chl[2] dimm0 0, dimm1 0
  chl[3] dimm0 0, dimm1 0
  chl[4] dimm0 0, dimm1 0
  chl[5] dimm0 0, dimm1 0

IPU0log=
IPU1log=
HSM0log=
IMU0log=  chl[6] dimm0 0, dimm1 0
  chl[7] dimm0 0, dimm1 0
  chl[8] dimm0 0, dimm1 0
  chl[9] dimm0 0, dimm1 0
  chl[10] dimm0 0, dimm1 0
  chl[11] dimm0 0, dimm1 0
==========end==========
sktId[0] chl[0] registered, dimm mask = 0x1
==
IPU0log=
IPU1log=
HSM0log=
IMU0log=====dimm status======
  chl[0] dimm0 1, dimm1 0
  chl[1] dimm0 0, dimm1 0
  chl[2] dimm0 0, dimm1 0
  chl[3] dimm0 0, dimm1 0
  chl[4] dimm0 0, dimm1 0
  chl[5] dimm0 0, dimm1 0
  chl[6] dimm0 0, dimm1 0
  chl[7] dimm0 0, dimm1 
IPU0log=
IPU1log=
HSM0log=
IMU0log=0
  chl[8] dimm0 0, dimm1 0
  chl[9] dimm0 0, dimm1 0
  chl[10] dimm0 0, dimm1 0
  chl[11] dimm0 0, dimm1 0
==========end==========
sktId[1] chl[0] registered, dimm mask = 0x1
=====dimm temp params=====
  temp_threshold      : t
IPU0log=
IPU1log=
HSM0log=
IMU0log=emp_mid:85,85 | temp_hi:95 | temp_cri:100
  is_thermal_thro_en  : 1
  is_aref_rate_auto   : 0
===========end============
[0.02.09.678]TF Heartbeat Start
[0.02.11.425]RECEIVE MEM SILK.
0: skt = 0 logic = 9 phy = 11 
1: skt = 0 lo
IPU0log=
IPU1log=
HSM0log=
IMU0log=gic = 0 phy = 8 
2: skt = 0 logic = 5 phy = 6 
3: skt = 1 logic = 1 phy = 0 
4: skt = 1 logic = 7 phy = 1 
5: skt = 1 logic = 11 phy = 7 
6: skt = 1 logic = 4 phy = 2 
7: skt = 0 logic = 4 phy = 2 
8: skt = 1 logic = 10 phy = 3 
IPU0log=
IPU1log=
HSM0log=
IMU0log=
9: skt = 1 logic = 2 phy = 4 
10: skt = 0 logic = 2 phy = 4 
11: skt = 1 logic = 8 phy = 5 
12: skt = 0 logic = 7 phy = 1 
13: skt = 1 logic = 6 phy = 9 
14: skt = 0 logic = 6 phy = 9 
15: skt = 1 logic = 0 phy = 8 
16: skt = 0
IPU0log=
IPU1log=
HSM0log=
IMU0log= logic = 3 phy = 10 
17: skt = 0 logic = 8 phy = 5 
18: skt = 1 logic = 9 phy = 11 
19: skt = 1 logic = 3 phy = 10 
20: skt = 1 logic = 5 phy = 6 
21: skt = 0 logic = 10 phy = 3 
22: skt = 0 logic = 11 phy = 7 
23: skt = 0 logic
IPU0log=
IPU1log=
HSM0log=
IMU0log= = 1 phy = 0 
get mem silk data length: 72
[0.02.14.468]PCIE INIT DONE.
[IMU][ERR] LOS_SemPend(g_pcieSemaphore, LOS_WAIT_FOREVER)
[RegisterInterruptSource]:[21] begin
Interrupt 258 register OK
[RegisterInterruptSource]:[39] end
IPU0log=
IPU1log=
HSM0log=
IMU0log=
[RegisterInterruptSource]:[21] begin
Interrupt 262 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 266 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:
IPU0log=
IPU1log=
HSM0log=
IMU0log=[21] begin
Interrupt 270 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 277 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 288 re
IPU0log=
IPU1log=
HSM0log=
IMU0log=gister OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 292 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 296 register OK
[RegisterInterrupt
IPU0log=
IPU1log=
HSM0log=
IMU0log=Source]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 300 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 307 register OK
[RegisterInterruptSource]:[39] end
pmt Init d
IPU0log=
IPU1log=
HSM0log=
IMU0log=one

-----------------ROUTE TABLE------------------
entryCount = 3
----------------------------------------------
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 
IPU0log=
IPU1log=
HSM0log=
IMU0log=15, addressSize = 2, bdf = 0x9300
[No.1]:
eidRange = 1, startEid = 10, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x9100
[No.2]:
eidRange = 1, startEid = 11, port = 
IPU0log=
IPU1log=
HSM0log=
IMU0log=0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2100
----------------------------------------------
-----------------ROUTE TABLE------------------
entryCount = 4
--------------
IPU0log=
IPU1log=
HSM0log=
IMU0log=--------------------------------
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x9300
[No.1]:
eidRange = 1, startEid = 10, port = 0,
IPU0log=
IPU1log=
HSM0log=
IMU0log= isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x9100
[No.2]:
eidRange = 1, startEid = 11, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSiz
IPU0log=
IPU1log=
HSM0log=
IMU0log=e = 2, bdf = 0x2100
[No.3]:
eidRange = 1, startEid = 12, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2500
----------------------------------------------
-----------
IPU0log=
IPU1log=
HSM0log=
IMU0log=------ROUTE TABLE------------------
entryCount = 4
----------------------------------------------
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize 
IPU0log=
IPU1log=
HSM0log=
IMU0log== 2, bdf = 0x9300
[No.1]:
eidRange = 1, startEid = 10, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x9100
[No.2]:
eidRange = 1, startEid = 11, port = 0, isStatic = 1,
IPU0log=
IPU1log=
HSM0log=
IMU0log= entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2100
[No.3]:
eidRange = 1, startEid = 12, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0
IPU0log=
IPU1log=
HSM0log=
IMU0log=x2500
----------------------------------------------

IPU0log=
IPU1log=
HSM0log=
IMU0log=1T1N1U skt:0 CfgBusDfxPreConfig finish

********Hello Huawei LiteOS********

IMU Firmware Version : B173V01
LiteOS Kernel Version : 5.10.0
Run on Socket[0] Die[3]
Chip Version: 1
Max socket num: 2
*******************************
IPU0log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 0
cls: 6, core: 7
cpu 933 sram 1010 ddr 983
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  750|  802|  885|  933|
max  v
IPU1log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 1
cls: 6, core: 7
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  759|  821|  909|  961|
max  v: |  750|  750|  753|  781
HSM0log=[1970-01-01 00:01:12.413][HSM][INFO][30] init start
[1970-01-01 00:01:12.413][HSM][INFO][38] init over
[00:01:12.423][info] succeed to do thirdparty dfx_pabuk init
[00:01:12.428][info] os_mem_system_init default pool done
[0
IMU0log=***
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | rail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_vo
IPU0log=: |  750|  750|  754|  775|  836|  922|  980|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:7
IPU1log=|  846|  938|  994|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:750 F:1950
avs-uncore V:750
HSM0log=0:01:12.434][info] addr is already in region
[00:01:12.437][info] succeed to do thirdparty otpc_pabuk init
[1970-01-01 00:01:12.443][HSM][INFO][31] select_region: 0xc11cb55b
[1970-01-01 00:01:12.449][HSM][INFO][67] spi_nor de
IMU0log=lt:1122 mV | pmu:MP2882
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_v
IPU0log=50 F:1950
avs-uncore V:750 F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
av
IPU1log= F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
avs-uncore V:840 F:2450
avs-
HSM0log=vice_id 0xff1a67c8
[1970-01-01 00:01:12.455][HSM][INFO][50] std_cmd readback 0x30220d8
[1970-01-01 00:01:12.461][HSM][INFO][72] saf_cmd 0x0 readback 0x9f5a0604
[1970-01-01 00:01:12.467][HSM][INFO][72] saf_cmd 0x1 readback 0x5
IMU0log=olt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_
IPU0log=s-uncore V:840 F:2450
avs-uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain
IPU1log=uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | r
HSM0log=b7e938
[1970-01-01 00:01:12.473][HSM][INFO][72] saf_cmd 0x2 readback 0x1
[1970-01-01 00:01:12.479][HSM][INFO][72] saf_cmd 0x3 readback 0x0
[1970-01-01 00:01:12.485][HSM][INFO][72] saf_cmd 0x4 readback 0x0
[00:01:12.492][info
IMU0log=volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus r
IPU0log=[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | p
IPU1log=ail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_volt:1122 mV | pmu:MP2882
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[0] volt =  906 mV
pwr domain
HSM0log=] succeed to do thirdparty boot_profile_driver init
[00:01:12.497][info] succeed to do thirdparty crypto_driver init
[00:01:12.503][info] succeed to do thirdparty period_driver init
[00:01:12.509][info]  start loading interna
IMU0log=eady.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait th
IPU0log=mu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pmbus:0x480c0000 ver:0x110
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
IPU1log=[9] volt = 1103 mV
=end=
w&h rd rail:0, 906
w&h rd rail:1, 1103
pwr domain[0] set volt  904 mV succ
pwr domain[9] set volt 1103 mV succ
volt post
pwr domain[0] volt =  904 mV
pwr domain[9] volt = 1103 mV
==end==
Totem[0] Core Bo
HSM0log=l task ...
[00:01:12.513][info]  task name is ccm_task
[00:01:12.517][info]  hm_dynamic_loadelf successfully!
[00:01:12.522][info] internal task[1] task_name=ccm_task load successfully
[00:01:12.529][info]  task name is upgr
IMU0log=e cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master I
IPU0log=
avsbus resync succ
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[2] volt =  904 mV
pwr domain[7] volt =  802 mV
pwr domain[4] volt =  806 mV
pwr domain[1] volt =  806 mV
=end=
w&h rd rail:
IPU1log=ot Vol [1029]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2,
HSM0log=ade_task
[00:01:12.533][info]  hm_dynamic_loadelf successfully!
[00:01:12.538][info] internal task[2] task_name=upgrade_task load successfully
[00:01:12.545][info] created task ccm_task success!
[00:01:12.549][info] created 
IMU0log=mu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
cpu 0 entering scheduler
|--------------------------------------------------|
AtsPrint
|idx|lockCount| srcAddr| destAddr| addrLen|
|--
IPU0log=0, 904
w&h rd rail:1, 802
pwr domain[2] set volt  902 mV succ
pwr domain[7] set volt  802 mV succ
w&h rd rail:0, 806
w&h rd rail:1, 804
pwr domain[4] set volt  802 mV succ
pwr domain[1] set volt  802 mV succ
volt post
pwr domain
IPU1log= ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd8
HSM0log=task upgrade_task success!
[1970-01-01 00:01:12.554][HSM][INFO][54] Platform init 0x20250523 0x4e.
[1970-01-01 00:01:12.561][HSM][INFO][197] ccm start.
[1970-01-01 00:01:12.565][HSM][INFO][86] upgrade task init success.
[197
IMU0log=------------------------------------------------|
|  0|00000000|0x010500000|0x000110800000|0x00100000|
|  1|00000000|0x020000000|0x00001d000000|0x00800000|
|  2|00000000|0x020800000|0x000490000000|0x00100000|
|  3|00000000|0x020
IPU0log=[2] volt =  902 mV
pwr domain[7] volt =  800 mV
pwr domain[4] volt =  804 mV
pwr domain[1] volt =  802 mV
==end==
Totem[0] Core Boot Vol [1015]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0,
IPU1log=00, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
opposite dieId: 0, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 
HSM0log=0-01-01 00:01:12.571][HSM][INFO][95] upgrade recv cmd, 0x181.
[1970-01-01 00:01:12.577][HSM][INFO][103] upgrade res, 0x3a5aa5a3.
.
IMU0log=900000|0x000004000000|0x08000000|
|  4|00000000|0x028900000|0x000440580000|0x01000000|
|  5|00000000|0x029900000|0x000590000000|0x00100000|
|  6|00000000|0x029a00000|0x002000150000|0x00100000|
|  7|00000000|0x000000000|0x0000000
IPU0log= MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 
IPU1log=enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
hiboost task entry
boost wait SEF.
[INFO] mem used of task 'app_Task' is:0x2028, not zero when task being deleted
boost param OK.
Totem[0] Core[ 0] Freq Limit Low
HSM0log=
IMU0log=00000|0x00000000|
|  8|00000000|0x040000000|0x000000000000|0x08000000|
|  9|00000000|0x048000000|0x000000000000|0x08000000|
| 10|00000000|0x050000000|0x000000000000|0x08000000|
| 11|00000000|0x058000000|0x000000000000|0x08000000
IPU0log=0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
tsensor type
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Fr
HSM0log=
IMU0log=|
| 12|00000000|0x060000000|0x000000000000|0x08000000|
| 13|00000000|0x068000000|0x000000000000|0x08000000|
| 14|00000000|0x070000000|0x000000000000|0x08000000|
| 15|00000000|0x078000000|0x000490000000|0x08000000|
|-------------
IPU0log=: 3, ppuFormatK: 0x4da6, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b4,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 3, mask: fffffff8
tsensor type: 4, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=-------------------------------------|
=~=~=~=~=~=~=~=~=~=~= IMU Log @ 2026.5.26 21:9:8 =~=~=~=~=~=~=~=~=~=~=
[IMU] Watchdog Initialization done!
[RegisterInterruptSource]:[21] begin
Interrupt 32 register OK
Interrupt 34 regis
IPU0log=0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 4, mask: ffffffee
tsensor type: 5, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1

IPU1log= Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=ter OK
Interrupt 40 register OK
Interrupt 44 register OK
sram cnt 0x0, id = 43
Interrupt 43 register OK
Interrupt 36 register OK
Interrupt 57 register OK
sram cnt 0x0, id = 42
Interrupt 42 register OK
Interrupt 37 register OK
[R
IPU0log=tsensor: 5, mask: ffffffda
tsensor type: 6, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 6, mask: ffffff80
tsensor type: 7, ppuFormatK: 0x437a,
IPU1log=KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=egisterInterruptSource]:[39] end
IPMB initialization Start...
IPMB clock set done, prer = 0x18.
IPMB Rx FIFO clear empty.
IPMB initialization Done.
starting DFX Collect Task end
PowerTask Entry ...
Wait all vrd init done .
IPU0log= ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 7, mask: fffffffe
opposite dieId: 1, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
CPM max V[900]-
IPU1log= Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low
HSM0log=
IMU0log=..
All vrd init done, power task start
refresh domainId 0 Lsb 0x0
refresh domainId 9 Lsb 0x1
refresh domainId 2 Lsb 0x0
refresh domainId 7 Lsb 0x1
refresh domainId 4 Lsb 0x0
refresh domainId 1 Lsb 0x1
power sensor[0] | calib:512
IPU0log=F:2800
CPM min V[750]-F:1600
freq:2350, idx:9
cpm trim freq: 2600, idx: 4
cpm trim finish
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
recount hours 
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Fr
HSM0log=
IMU0log=0 | rshunt:1 | rshuntDiv:1000 | currLsb:1 | currLsbDiv:1000 | enableFlag:1
                | pwrLsb:25 | defPwr:25000 | minPwr:10000 | maxPwr:65000 | pwrFix:3400
                | manufacturerId: 0x5549 | dieId: 0x2260
power sen
IPU0log=0xac8 
hiboost task entry
boost wait SEF.
boost param OK.
Totem[0] Core[ 0] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[26
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=sor[0] init success
ScmiTaskEntry start.
[RegisterInterruptSource]:[21] begin
Interrupt 51 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 52 register OK
[RegisterInterruptSource]
IPU0log=00000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[12000
IPU1log= Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 53 register OK
[RegisterInterruptSource]:[39] end
[0.01.29.111]starting ras Init
RAS Setup Value get done!
INT_NUM_PER_SKT * HiGetSktNum() = 0x8
index = 0x0
RasIntRegis
IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Lim
IPU1log=KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=ter init 160 
index = 0x1
RasIntRegister init 172 
index = 0x2
RasIntRegister init 162 
index = 0x3
RasIntRegister init 174 
index = 0x4
RasIntRegister init 184 
index = 0x5
RasIntRegister init 196 
index = 0x6
RasIntRegister in
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IPU1log= Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low
HSM0log=
IMU0log=it 186 
index = 0x7
RasIntRegister init 198 
RasIntRegister init 161 
RasIntRegister init 173 
RasIntRegister init 185 
RasIntRegister init 197 
RasIntRegister init 284 
RasIntRegister init 314 
MceTableHeadInit start
starting C
IPU0log=14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
To
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
uncore max freq : 23
HSM0log=
IMU0log=e_Storm Contrl and Ras_Data_Update Task end
[0.01.29.192]starting ras end
[IMU][ERR] skt id 0
Ub init task start Entry ...
UbInitTask Entry ...
[RegisterInterruptSource]:[21] begin
Interrupt 167 register OK
[RegisterInterrupt
IPU0log=tem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[26
IPU1log=50 MHz

HSM0log=
IMU0log=Source]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 191 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 171 register OK
[RegisterInterruptSource]:[39] end
[RegisterI
IPU0log=00000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[12000
IPU1log=
HSM0log=
IMU0log=nterruptSource]:[21] begin
Interrupt 183 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 195 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin

IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Lim
IPU1log=
HSM0log=
IMU0log=Interrupt 207 register OK
[RegisterInterruptSource]:[39] end
Init heart-beat-task end
CS0 flash do not support sfdp!
Current flash device ID[0x61a67c8]!
System supported 1 Flash.
flash cs 0 Manufacture 0xc8, DeviceId 0x1a67, Ad
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IPU1log=
HSM0log=
IMU0log=drMode[0-3B,1-4B] 0x1:
    size 0x4000000, pagesize 0x100
    read  cmd 0x13, dummy byte 0x8
    write cmd 0x12, dummy byte 0x0
    erase4k cmd 0x21, erase64k byte 0xdc
sfc init end
firstUnMskExt0Int
ThermalDimmStart Entry ...

IPU0log=33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
To
IPU1log=
HSM0log=
IMU0log=wait ddr init done...
HacLowPowerStart Entry ...
Hello LiteOS...
Init ReportPcieMmioToBmcTaskEntry end
starting Fpc Isolation Task end
pwr cap[0]: 0, 67
pwr cap[1]: f, 27
pwr cap[2]: 1, 3
BMC_COLLECTION: bmc req last log!
D
IPU0log=tem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[26
IPU1log=
HSM0log=
IMU0log=DR initing...
BMC_COLLECTION: bmc req last log!
DDR initing...
BMC_COLLECTION: bmc req last log!
DDR initing...
BMC_COLLECTION: bmc req last log!
DDR initing...
BMC_COLLECTION: bmc req last log!
DDR initing...
BMC_COLLECTION: bm
IPU0log=00000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
uncore max freq : 2350 MHz

IPU1log=
HSM0log=
IMU0log=c req last log!
DDR initing...
BMC_COLLECTION: bmc req last log!
DDR initing...
BMC_COLLECTION: bmc req last log!
DDR initing...
BMC_COLLECTION: bmc req last log!
DDR initing...
BMC_COLLECTION: bmc req last log!
DDR initing...
B
IPU0log=
IPU1log=
HSM0log=
IMU0log=MC_COLLECTION: bmc req last log!
DDR initing...
BMC_COLLECTION: bmc req last log!
DDR initing...
[0.03.53.592]DDR init done
[LOG]head = 0x0, tail = 0x1a50, logSize = 0x1a50
[IMU][ERR] HsmLogInit!
[IMU][ERR] HsmLogInit! TRUE
set 
IPU0log=
IPU1log=
HSM0log=
IMU0log=apei done!
UbConfigData size is 64
UbConfigData 0 : 0
UbConfigData 1 : 0
UbConfigData 2 : 0
UbConfigData 3 : 1
UbConfigData 4 : 31
UbConfigData 5 : 1
UbConfigData 6 : 0
UbConfigData 7 : 32
UbConfigData 8 : 0
UbConfigData 9 : 1
U
IPU0log=
IPU1log=
HSM0log=
IMU0log=bConfigData 10 : 2
UbConfigData 11 : 0
UbConfigData 12 : 0
UbConfigData 13 : 1
UbConfigData 14 : 0
UbConfigData 15 : 0
UbConfigData 16 : 0
UbConfigData 17 : 0
UbConfigData 18 : 0
UbConfigData 19 : 0
UbConfigData 20 : 0
UbConfigD
IPU0log=
IPU1log=
HSM0log=
IMU0log=ata 21 : 0
UbConfigData 22 : 11
UbConfigData 23 : 0
UbConfigData 24 : 0
UbConfigData 25 : 0
UbConfigData 26 : 0
UbConfigData 27 : 0
UbConfigData 28 : 0
UbConfigData 29 : 0
UbConfigData 30 : 0
UbConfigData 31 : 0
UbConfigData 32 
IPU0log=
IPU1log=
HSM0log=
IMU0log=: 0
UbConfigData 33 : 0
UbConfigData 34 : 2
UbConfigData 35 : 1
UbConfigData 36 : 0
UbConfigData 37 : 0
UbConfigData 38 : 0
UbConfigData 39 : 0
UbConfigData 40 : 0
UbConfigData 41 : 0
UbConfigData 42 : 0
UbConfigData 43 : 0
UbCo
IPU0log=
IPU1log=
HSM0log=
IMU0log=nfigData 44 : 0
UbConfigData 45 : 0
UbConfigData 46 : 0
UbConfigData 47 : 0
UbConfigData 48 : 0
UbConfigData 49 : 0
UbConfigData 50 : 0
UbConfigData 51 : 0
UbConfigData 52 : 0
UbConfigData 53 : 0
ddr init done, start thermal dim
IPU0log=
IPU1log=
HSM0log=
IMU0log=m task
======dimm status======
  chl[0] dimm0 1, dimm1 0
  chl[1] dimm0 0, dimm1 0
  chl[2] dimm0 0, dimm1 0
  chl[3] dimm0 0, dimm1 0
  chl[4] dimm0 0, dimm1 0
  chl[5] dimm0 0, dimm1 0
  chl[6] dimm0 0, dimm1 0
  chl[7] dimm0 
IPU0log=
IPU1log=
HSM0log=
IMU0log=0, dimm1 0
  chl[8] dimm0 0, dimm1 0
  chl[9] dimm0 0, dimm1 0
  chl[10] dimm0 0, dimm1 0
  chl[11] dimm0 0, dimm1 0
==========end==========
sktId[0] chl[0] registered, dimm mask = 0x1
======dimm status======
  chl[0] dimm0 1, d
IPU0log=
IPU1log=
HSM0log=
IMU0log=imm1 0
  chl[1] dimm0 0, dimm1 0
  chl[2] dimm0 0, dimm1 0
  chl[3] dimm0 0, dimm1 0
  chl[4] dimm0 0, dimm1 0
  chl[5] dimm0 0, dimm1 0
  chl[6] dimm0 0, dimm1 0
  chl[7] dimm0 0, dimm1 0
  chl[8] dimm0 0, dimm1 0
  chl[9] dimm
IPU0log=
IPU1log=
HSM0log=
IMU0log=0 0, dimm1 0
  chl[10] dimm0 0, dimm1 0
  chl[11] dimm0 0, dimm1 0
==========end==========
sktId[1] chl[0] registered, dimm mask = 0x1
=====dimm temp params=====
  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
IPU0log=
IPU1log=
HSM0log=
IMU0log=
  is_thermal_thro_en  : 1
  is_aref_rate_auto   : 0
===========end============
UbConfigData 54 : 0
UbConfigData 55 : 0
UbConfigData 56 : 0
UbConfigData 57 : 0
UbConfigData 58 : 0
UbConfigData 59 : 0
UbConfigData 60 : 0
UbConfig
IPU0log=
IPU1log=
HSM0log=
IMU0log=Data 61 : 0
UbConfigData 62 : 0
UbConfigData 63 : 0
UbConfigData 64 : 0
ClusterSwitch: 0, 0
ClusterMode: 0, 0
ControlMode: 0, 0
EnumMode: 1, 1
BodyMask: 31, 31
CcCtxCount: 256, 256
RcCtxCount: 32, 32
UbMemEntrySize: 128, 0
MctpS
IPU0log=
IPU1log=
HSM0log=
IMU0log=upport: 1, 1
SecureMode: 0, 0
PrimaryCna: 0, 0
Upi: 0, 0
EntityId: 0, 0
SlotId: 1, 1
SocketId: 2, 2
PortIndex: 0, 0
PortCna: 0, 0
CtrlCna: 11, 11
ImpBootFlag: 2, 2
ImuBootFlag: 1, 1
SktId: 0 DieId:2, HCCS_LINK:2 PaId:2
SktId: 1 
IPU0log=
IPU1log=
HSM0log=
IMU0log=DieId:2, HCCS_LINK:0 PaId:0
CIS register: ID[0xc00007ff], owner[0x1000003], function[0x1045dd8c].
CIS register: ID[0xc0000002], owner[0x1000003], function[0x1045de2c].
odf: can not find od file[config]
Do not get NII route table
IPU0log=
IPU1log=
HSM0log=
IMU0log=, disable NII Send function.
UbiosTaskStart Entry ...
UbiosTaskStart create task success
UbiosCisTask Entry ...
IMU ImpBootFlag: 0x2
skip IMP start config...
BMC_COLLECTION: bmc req last log!
[IMU][ERR] [
HSM0log= no log data
IPU0log=
IPU1log=
HSM0log=
IMU0log= error!]
[0.04.00.518]TF Heartbeat Start
[0.04.01.957]RECEIVE MEM SILK.
0: skt = 0 logic = 9 phy = 11 
1: skt = 0 logic = 0 phy = 8 
2: skt = 0 logic = 5 phy = 6 
3: skt = 1 logic = 1 phy = 0 
4: skt = 1 logic = 7 phy = 1 
5: sk
IPU0log=
IPU1log=
HSM0log=
IMU0log=t = 1 logic = 11 phy = 7 
6: skt = 1 logic = 4 phy = 2 
7: skt = 0 logic = 4 phy = 2 
8: skt = 1 logic = 10 phy = 3 
9: skt = 1 logic = 2 phy = 4 
10: skt = 0 logic = 2 phy = 4 
11: skt = 1 logic = 8 phy = 5 
12: skt = 0 logic =
IPU0log=
IPU1log=
HSM0log=
IMU0log= 7 phy = 1 
13: skt = 1 logic = 6 phy = 9 
14: skt = 0 logic = 6 phy = 9 
15: skt = 1 logic = 0 phy = 8 
16: skt = 0 logic = 3 phy = 10 
17: skt = 0 logic = 8 phy = 5 
18: skt = 1 logic = 9 phy = 11 
19: skt = 1 logic = 3 phy = 
IPU0log=
IPU1log=
HSM0log=
IMU0log=10 
20: skt = 1 logic = 5 phy = 6 
21: skt = 0 logic = 10 phy = 3 
22: skt = 0 logic = 11 phy = 7 
23: skt = 0 logic = 1 phy = 0 
get mem silk data length: 72
[0.04.04.998]PCIE INIT DONE.
[IMU][ERR] LOS_SemPend(g_pcieSemaphore, 
IPU0log=
IPU1log=
HSM0log=
IMU0log=LOS_WAIT_FOREVER)
[RegisterInterruptSource]:[21] begin
Interrupt 258 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 262 register OK
[RegisterInterruptSource]:[39] end
[RegisterI
IPU0log=
IPU1log=
HSM0log=
IMU0log=nterruptSource]:[21] begin
Interrupt 266 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 270 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin

IPU0log=
IPU1log=
HSM0log=
IMU0log=Interrupt 277 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 288 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 292 register OK
[R
IPU0log=
IPU1log=
HSM0log=
IMU0log=egisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 296 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 300 register OK
[RegisterInterruptSource]:[39]
IPU0log=
IPU1log=
HSM0log=
IMU0log= end
[RegisterInterruptSource]:[21] begin
Interrupt 307 register OK
[RegisterInterruptSource]:[39] end
pmt Init done

-----------------ROUTE TABLE------------------
entryCount = 3
--------------------------------------------
IPU0log=
IPU1log=
HSM0log=
IMU0log=--
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x9300
[No.1]:
eidRange = 1, startEid = 10, port = 0, isStatic = 1, entryType = 0, 
IPU0log=
IPU1log=
HSM0log=
IMU0log=
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x9100
[No.2]:
eidRange = 1, startEid = 11, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2100
---------
IPU0log=
IPU1log=
HSM0log=
IMU0log=-------------------------------------
-----------------ROUTE TABLE------------------
entryCount = 4
----------------------------------------------
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 

IPU0log=
IPU1log=
HSM0log=
IMU0log=transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x9300
[No.1]:
eidRange = 1, startEid = 10, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x9100
[No.2]:
ei
IPU0log=
IPU1log=
HSM0log=
IMU0log=dRange = 1, startEid = 11, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2100
[No.3]:
eidRange = 1, startEid = 12, port = 0, isStatic = 1, entryType = 0, 
transportBin
IPU0log=
IPU1log=
HSM0log=
IMU0log=ding = 2, mediaType = 15, addressSize = 2, bdf = 0x2500
----------------------------------------------
-----------------ROUTE TABLE------------------
entryCount = 4
----------------------------------------------
[No.0]:
eid
IPU0log=
IPU1log=
HSM0log=
IMU0log=Range = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x9300
[No.1]:
eidRange = 1, startEid = 10, port = 0, isStatic = 1, entryType = 0, 
transportBindi
IPU0log=
IPU1log=
HSM0log=
IMU0log=ng = 2, mediaType = 15, addressSize = 2, bdf = 0x9100
[No.2]:
eidRange = 1, startEid = 11, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2100
[No.3]:
eidRange = 1, st
IPU0log=
IPU1log=
HSM0log=
IMU0log=artEid = 12, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2500
----------------------------------------------

IPU0log=
IPU1log=
HSM0log=
IPU0log=tempInt: 61, 120 degrees celsius will power down

IPU1log=
HSM0log=
IMU0log=
IPU0log=tempInt: 64, 120 degrees celsius will power down

IPU1log=
HSM0log=
IMU0log=
IPU0log=tempInt: 66, 120 degrees celsius will power down
tempInt: 68, 120 degrees celsius will power down
tempInt: 70, 120 degrees celsius will power down

IPU1log=
HSM0log=
IMU0log=
IPU0log=tempInt: 72, 120 degrees celsius will power down

IPU1log=
HSM0log=
IMU0log=
IPU0log=tempInt: 74, 120 degrees celsius will power down
tempInt: 77, 120 degrees celsius will power down
tempInt: 75, 120 degrees celsius will power down

IPU1log=
HSM0log=
IMU0log=
IPU0log=tempInt: 72, 120 degrees celsius will power down

IPU1log=
HSM0log=
IMU0log=
IPU0log=tempInt: 69, 120 degrees celsius will power down
tempInt: 67, 120 degrees celsius will power down
tempInt: 64, 120 degrees celsius will power down

IPU1log=
HSM0log=
IMU0log=
IPU0log=tempInt: 63, 120 degrees celsius will power down

IPU1log=
HSM0log=
IMU0log=
IPU0log=tempInt: 61, 120 degrees celsius will power down

IPU1log=
HSM0log=
IMU0log=
IMU0log=1T1N1U skt:0 CfgBusDfxPreConfig finish

********Hello Huawei LiteOS********

IMU Firmware Version : B173V01
LiteOS Kernel Version : 5.10.0
Run on Socket[0] Die[3]
Chip Version: 1
Max socket num: 2
*******************************
IPU0log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 0
cls: 6, core: 7
cpu 933 sram 1010 ddr 983
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  750|  802|  885|  933|
max  v
IPU1log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 1
cls: 6, core: 7
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  759|  821|  909|  961|
max  v: |  750|  750|  753|  781
IMU0log=***
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | rail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_vo
IPU0log=: |  750|  750|  754|  775|  836|  922|  980|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:7
IPU1log=|  846|  938|  994|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:750 F:1950
avs-uncore V:750
HSM0log=[1970-01-01 00:01:13.088][HSM][INFO][30] init start
[1970-01-01 00:01:13.088][HSM][INFO][38] init over
[00:01:13.098][info] succeed to do thirdparty dfx_pabuk init
[00:01:13.104][info] os_mem_system_init default pool done
[0
IMU0log=lt:1122 mV | pmu:MP2882
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_v
IPU0log=50 F:1950
avs-uncore V:750 F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
av
IPU1log= F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
avs-uncore V:840 F:2450
avs-
HSM0log=0:01:13.110][info] addr is already in region
[00:01:13.113][info] succeed to do thirdparty otpc_pabuk init
[1970-01-01 00:01:13.118][HSM][INFO][31] select_region: 0xc11cb55b
[1970-01-01 00:01:13.124][HSM][INFO][67] spi_nor de
IMU0log=olt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_
IPU0log=s-uncore V:840 F:2450
avs-uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain
IPU1log=uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | r
HSM0log=vice_id 0xff1a67c8
[1970-01-01 00:01:13.130][HSM][INFO][50] std_cmd readback 0x30220d8
[1970-01-01 00:01:13.136][HSM][INFO][72] saf_cmd 0x0 readback 0x9f5a0604
[1970-01-01 00:01:13.143][HSM][INFO][72] saf_cmd 0x1 readback 0x5
IMU0log=volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus r
IPU0log=[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | p
IPU1log=ail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_volt:1122 mV | pmu:MP2882
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[0] volt =  906 mV
pwr domain
HSM0log=b7e938
[1970-01-01 00:01:13.149][HSM][INFO][72] saf_cmd 0x2 readback 0x1
[1970-01-01 00:01:13.155][HSM][INFO][72] saf_cmd 0x3 readback 0x0
[1970-01-01 00:01:13.160][HSM][INFO][72] saf_cmd 0x4 readback 0x0
[00:01:13.167][info
IMU0log=eady.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait th
IPU0log=mu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pmbus:0x480c0000 ver:0x110
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
IPU1log=[9] volt = 1103 mV
=end=
w&h rd rail:0, 906
w&h rd rail:1, 1103
pwr domain[0] set volt  904 mV succ
pwr domain[9] set volt 1101 mV succ
volt post
pwr domain[0] volt =  904 mV
pwr domain[9] volt = 1103 mV
==end==
Totem[0] Core Bo
HSM0log=] succeed to do thirdparty boot_profile_driver init
[00:01:13.173][info] succeed to do thirdparty crypto_driver init
[00:01:13.178][info] succeed to do thirdparty period_driver init
[00:01:13.184][info]  start loading interna
IMU0log=e cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master I
IPU0log=
avsbus resync succ
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[2] volt =  904 mV
pwr domain[7] volt =  802 mV
pwr domain[4] volt =  806 mV
pwr domain[1] volt =  804 mV
=end=
w&h rd rail:
IPU1log=ot Vol [1029]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2,
HSM0log=l task ...
[00:01:13.189][info]  task name is ccm_task
[00:01:13.193][info]  hm_dynamic_loadelf successfully!
[00:01:13.198][info] internal task[1] task_name=ccm_task load successfully
[00:01:13.204][info]  task name is upgr
IMU0log=mu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
cpu 0 entering scheduler
|--------------------------------------------------|
AtsPrint
|idx|lockCount| srcAddr| destAddr| addrLen|
|--
IPU0log=0, 904
w&h rd rail:1, 802
pwr domain[2] set volt  902 mV succ
pwr domain[7] set volt  800 mV succ
w&h rd rail:0, 806
w&h rd rail:1, 806
pwr domain[4] set volt  804 mV succ
pwr domain[1] set volt  802 mV succ
volt post
pwr domain
IPU1log= ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd8
HSM0log=ade_task
[00:01:13.208][info]  hm_dynamic_loadelf successfully!
[00:01:13.213][info] internal task[2] task_name=upgrade_task load successfully
[00:01:13.220][info] created task ccm_task success!
[00:01:13.225][info] created 
IMU0log=------------------------------------------------|
|  0|00000000|0x010500000|0x000110800000|0x00100000|
|  1|00000000|0x020000000|0x00001d000000|0x00800000|
|  2|00000000|0x020800000|0x000490000000|0x00100000|
|  3|00000000|0x020
IPU0log=[2] volt =  902 mV
pwr domain[7] volt =  802 mV
pwr domain[4] volt =  804 mV
pwr domain[1] volt =  802 mV
==end==
Totem[0] Core Boot Vol [1015]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0,
IPU1log=00, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
opposite dieId: 0, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 
HSM0log=task upgrade_task success!
[1970-01-01 00:01:13.230][HSM][INFO][54] Platform init 0x20250523 0x4e.
[1970-01-01 00:01:13.236][HSM][INFO][197] ccm start.
[1970-01-01 00:01:13.241][HSM][INFO][86] upgrade task init success.
[197
IMU0log=900000|0x000004000000|0x08000000|
|  4|00000000|0x028900000|0x000440580000|0x01000000|
|  5|00000000|0x029900000|0x000590000000|0x00100000|
|  6|00000000|0x029a00000|0x002000150000|0x00100000|
|  7|00000000|0x000000000|0x0000000
IPU0log= MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 
IPU1log=enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
hiboost task entry
boost wait SEF.
[INFO] mem used of task 'app_Task' is:0x2028, not zero when task being deleted
boost param OK.
Totem[0] Core[ 0] Freq Limit Low
HSM0log=0-01-01 00:01:13.247][HSM][INFO][95] upgrade recv cmd, 0x181.
[1970-01-01 00:01:13.253][HSM][INFO][103] upgrade res, 0x3a5aa5a3.
.
IMU0log=00000|0x00000000|
|  8|00000000|0x040000000|0x000000000000|0x08000000|
|  9|00000000|0x048000000|0x000000000000|0x08000000|
| 10|00000000|0x050000000|0x000000000000|0x08000000|
| 11|00000000|0x058000000|0x000000000000|0x08000000
IPU0log=0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
tsensor type
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Fr
HSM0log=
IMU0log=|
| 12|00000000|0x060000000|0x000000000000|0x08000000|
| 13|00000000|0x068000000|0x000000000000|0x08000000|
| 14|00000000|0x070000000|0x000000000000|0x08000000|
| 15|00000000|0x078000000|0x000490000000|0x08000000|
|-------------
IPU0log=: 3, ppuFormatK: 0x4da6, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b4,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 3, mask: fffffff8
tsensor type: 4, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=-------------------------------------|
=~=~=~=~=~=~=~=~=~=~= IMU Log @ 2026.6.1 4:14:54 =~=~=~=~=~=~=~=~=~=~=
[IMU] Watchdog Initialization done!
[RegisterInterruptSource]:[21] begin
Interrupt 32 register OK
Interrupt 34 regis
IPU0log=0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 4, mask: ffffffee
tsensor type: 5, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1

IPU1log= Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=ter OK
Interrupt 40 register OK
Interrupt 44 register OK
sram cnt 0x0, id = 43
Interrupt 43 register OK
Interrupt 36 register OK
Interrupt 57 register OK
sram cnt 0x0, id = 42
Interrupt 42 register OK
Interrupt 37 register OK
[R
IPU0log=tsensor: 5, mask: ffffffda
tsensor type: 6, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 6, mask: ffffff80
tsensor type: 7, ppuFormatK: 0x437a,
IPU1log=KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=egisterInterruptSource]:[39] end
IPMB initialization Start...
IPMB clock set done, prer = 0x18.
IPMB Rx FIFO clear empty.
IPMB initialization Done.
starting DFX Collect Task end
PowerTask Entry ...
Wait all vrd init done .
IPU0log= ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 7, mask: fffffffe
opposite dieId: 1, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
CPM max V[900]-
IPU1log= Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low
HSM0log=
IMU0log=..
All vrd init done, power task start
refresh domainId 0 Lsb 0x0
refresh domainId 9 Lsb 0x1
refresh domainId 2 Lsb 0x0
refresh domainId 7 Lsb 0x1
refresh domainId 4 Lsb 0x0
refresh domainId 1 Lsb 0x1
power sensor[0] | calib:512
IPU0log=F:2800
CPM min V[750]-F:1600
freq:2350, idx:9
cpm trim freq: 2600, idx: 4
cpm trim finish
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
recount hours 
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Fr
HSM0log=
IMU0log=0 | rshunt:1 | rshuntDiv:1000 | currLsb:1 | currLsbDiv:1000 | enableFlag:1
                | pwrLsb:25 | defPwr:25000 | minPwr:10000 | maxPwr:65000 | pwrFix:3400
                | manufacturerId: 0x5549 | dieId: 0x2260
power sen
IPU0log=0xb40 
hiboost task entry
boost wait SEF.
boost param OK.
Totem[0] Core[ 0] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[26
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=sor[0] init success
ScmiTaskEntry start.
[RegisterInterruptSource]:[21] begin
Interrupt 51 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 52 register OK
[RegisterInterruptSource]
IPU0log=00000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[12000
IPU1log= Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 53 register OK
[RegisterInterruptSource]:[39] end
[0.01.29.780]starting ras Init
RAS Setup Value get done!
INT_NUM_PER_SKT * HiGetSktNum() = 0x8
index = 0x0
RasIntRegis
IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Lim
IPU1log=KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=ter init 160 
index = 0x1
RasIntRegister init 172 
index = 0x2
RasIntRegister init 162 
index = 0x3
RasIntRegister init 174 
index = 0x4
RasIntRegister init 184 
index = 0x5
RasIntRegister init 196 
index = 0x6
RasIntRegister in
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IPU1log= Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low
HSM0log=
IMU0log=it 186 
index = 0x7
RasIntRegister init 198 
RasIntRegister init 161 
RasIntRegister init 173 
RasIntRegister init 185 
RasIntRegister init 197 
RasIntRegister init 284 
RasIntRegister init 314 
MceTableHeadInit start
starting C
IPU0log=14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
To
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
uncore max freq : 23
HSM0log=
IMU0log=e_Storm Contrl and Ras_Data_Update Task end
[0.01.29.862]starting ras end
[IMU][ERR] skt id 0
Ub init task start Entry ...
UbInitTask Entry ...
[RegisterInterruptSource]:[21] begin
Interrupt 167 register OK
[RegisterInterrupt
IPU0log=tem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[26
IPU1log=50 MHz

HSM0log=
IMU0log=Source]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 191 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 171 register OK
[RegisterInterruptSource]:[39] end
[RegisterI
IPU0log=00000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[12000
IPU1log=
HSM0log=
IMU0log=nterruptSource]:[21] begin
Interrupt 183 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 195 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin

IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Lim
IPU1log=
HSM0log=
IMU0log=Interrupt 207 register OK
[RegisterInterruptSource]:[39] end
Init heart-beat-task end
CS0 flash do not support sfdp!
Current flash device ID[0x61a67c8]!
System supported 1 Flash.
flash cs 0 Manufacture 0xc8, DeviceId 0x1a67, Ad
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IPU1log=
HSM0log=
IMU0log=drMode[0-3B,1-4B] 0x1:
    size 0x4000000, pagesize 0x100
    read  cmd 0x13, dummy byte 0x8
    write cmd 0x12, dummy byte 0x0
    erase4k cmd 0x21, erase64k byte 0xdc
sfc init end
firstUnMskExt0Int
ThermalDimmStart Entry ...

IPU0log=33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
To
IPU1log=
HSM0log=
IMU0log=wait ddr init done...
HacLowPowerStart Entry ...
Hello LiteOS...
Init ReportPcieMmioToBmcTaskEntry end
starting Fpc Isolation Task end
pwr cap[0]: 0, 67
pwr cap[1]: f, 27
pwr cap[2]: 1, 3
DDR initing...
BMC_COLLECTION: bmc 
IPU0log=tem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[26
IPU1log=
HSM0log=
IMU0log=req last log!
DDR initing...
[0.02.01.262]DDR init done
[LOG]head = 0x0, tail = 0x1760, logSize = 0x1760
[IMU][ERR] HsmLogInit!
[IMU][ERR] HsmLogInit! TRUE
UbConfigData size is 64
UbConfigData 0 : 0
UbConfigData 1 : 0
UbConfigDa
IPU0log=00000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
uncore max freq : 2350 MHz

IPU1log=
HSM0log=
IMU0log=ta 2 : 0
UbConfigData 3 : 1
UbConfigData 4 : 31
UbConfigData 5 : 1
UbConfigData 6 : 0
UbConfigData 7 : 32
UbConfigData 8 : 0
UbConfigData 9 : 1
UbConfigData 10 : 2
UbConfigData 11 : 0
UbConfigData 12 : 0
UbConfigData 13 : 1
UbCo
IPU0log=
IPU1log=
HSM0log=
IMU0log=nfigData 14 : 0
UbConfigData 15 : 0
UbConfigData 16 : 0
UbConfigData 17 : 0
UbConfigData 18 : 0
UbConfigData 19 : 0
UbConfigData 20 : 0
UbConfigData 21 : 0
UbConfigData 22 : 11
UbConfigData 23 : 0
UbConfigData 24 : 0
UbConfigDat
IPU0log=
IPU1log=
HSM0log=
IMU0log=a 25 : 0
UbConfigData 26 : 0
UbConfigData 27 : 0
UbConfigData 28 : 0
UbConfigData 29 : 0
UbConfigData 30 : 0
UbConfigData 31 : 0
UbConfigData 32 : 0
UbConfigData 33 : 0
UbConfigData 34 : 2
UbConfigData 35 : 1
UbConfigData 36 : 0
IPU0log=
IPU1log=
HSM0log=
IMU0log=
UbConfigData 37 : 0
UbConfigData 38 : 0
UbConfigData 39 : 0
UbConfigData 40 : 0
UbConfigData 41 : 0
UbConfigData 42 : 0
UbConfigData 43 : 0
UbConfigData 44 : 0
UbConfigData 45 : 0
UbConfigData 46 : 0
UbConfigData 47 : 0
UbConfi
IPU0log=
IPU1log=
HSM0log=
IMU0log=gData 48 : 0
UbConfigData 49 : 0
UbConfigData 50 : 0
UbConfigData 51 : 0
UbConfigData 52 : 0
UbConfigData 53 : 0
UbConfigData 54 : 0
UbConfigData 55 : 0
UbConfigData 56 : 0
UbConfigData 57 : 0
UbConfigData 58 : 0
UbConfigData 59
IPU0log=
IPU1log=
HSM0log=
IMU0log= : 0
UbConfigData 60 : 0
UbConfigData 61 : 0
UbConfigData 62 : 0
UbConfigData 63 : 0
UbConfigData 64 : 0
ClusterSwitch: 0, 0
ClusterMode: 0, 0
ControlMode: 0, 0
EnumMode: 1, 1
BodyMask: 31, 31
CcCtxCount: 256, 256
RcCtxCount: 32
IPU0log=
IPU1log=
HSM0log=
IMU0log=, 32
UbMemEntrySize: 128, 0
MctpSupport: 1, 1
SecureMode: 0, 0
PrimaryCna: 0, 0
Upi: 0, 0
EntityId: 0, 0
SlotId: 1, 1
SocketId: 2, 2
PortIndex: 0, 0
PortCna: 0, 0
CtrlCna: 11, 11
ImpBootFlag: 2, 2
ImuBootFlag: 1, 1
SktId: 0 DieI
IPU0log=
IPU1log=
HSM0log=
IMU0log=d:2, HCCS_LINK:2 PaId:2
SktId: 1 DieId:2, HCCS_LINK:0 PaId:0
CIS register: ID[0xc00007ff], owner[0x1000003], function[0x1045dd8c].
CIS register: ID[0xc0000002], owner[0x1000003], function[0x1045de2c].
odf: can not find od file[c
IPU0log=
IPU1log=
HSM0log=
IMU0log=onfig]
Do not get NII route table, disable NII Send function.
UbiosTaskStart Entry ...
UbiosTaskStart create task success
IMU ImpBootFlag: 0x2
skip IMP start config...
UbiosCisTask Entry ...
ddr init done, start thermal dimm 
IPU0log=
IPU1log=
HSM0log=
IMU0log=task
======dimm status======
  chl[0] dimm0 1, dimm1 0
  chl[1] dimm0 0, dimm1 0
  chl[2] dimm0 0, dimm1 0
  chl[3] dimm0 0, dimm1 0
  chl[4] dimm0 0, dimm1 0
  chl[5] dimm0 0, dimm1 0
  chl[6] dimm0 0, dimm1 0
  chl[7] dimm0 0,
IPU0log=
IPU1log=
HSM0log=
IMU0log= dimm1 0
  chl[8] dimm0 0, dimm1 0
  chl[9] dimm0 0, dimm1 0
  chl[10] dimm0 0, dimm1 0
  chl[11] dimm0 0, dimm1 0
==========end==========
sktId[0] chl[0] registered, dimm mask = 0x1
======dimm status======
  chl[0] dimm0 1, dim
IPU0log=
IPU1log=
HSM0log=
IMU0log=m1 0
  chl[1] dimm0 0, dimm1 0
  chl[2] dimm0 0, dimm1 0
  chl[3] dimm0 0, dimm1 0
  chl[4] dimm0 0, dimm1 0
  chl[5] dimm0 0, dimm1 0
  chl[6] dimm0 0, dimm1 0
  chl[7] dimm0 0, dimm1 0
  chl[8] dimm0 0, dimm1 0
  chl[9] dimm0 
IPU0log=
IPU1log=
HSM0log=
IMU0log=0, dimm1 0
  chl[10] dimm0 0, dimm1 0
  chl[11] dimm0 0, dimm1 0
==========end==========
sktId[1] chl[0] registered, dimm mask = 0x1
=====dimm temp params=====
  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
 
IPU0log=
IPU1log=
HSM0log=
IMU0log= is_thermal_thro_en  : 1
  is_aref_rate_auto   : 0
===========end============
set apei done!
[0.02.08.646]TF Heartbeat Start
BMC_COLLECTION: bmc req last log!
[IMU][ERR] [
HSM0log= no log data error!]
[0.02.10.323]RECEIVE MEM SI
IPU0log=
IPU1log=
HSM0log=
IMU0log=LK.
0: skt = 0 logic = 4 phy = 2 
1: skt = 0 logic = 10 phy = 3 
2: skt = 0 logic = 2 phy = 4 
3: skt = 1 logic = 6 phy = 9 
4: skt = 0 logic = 8 phy = 5 
5: skt = 0 logic = 11 phy = 7 
6: skt = 1 logic = 7 phy = 1 
7: skt = 1 l
IPU0log=
IPU1log=
HSM0log=
IMU0log=ogic = 4 phy = 2 
8: skt = 1 logic = 10 phy = 3 
9: skt = 0 logic = 9 phy = 11 
10: skt = 1 logic = 3 phy = 10 
11: skt = 1 logic = 2 phy = 4 
12: skt = 0 logic = 5 phy = 6 
13: skt = 1 logic = 8 phy = 5 
14: skt = 1 logic = 5 p
IPU0log=
IPU1log=
HSM0log=
IMU0log=hy = 6 
15: skt = 1 logic = 11 phy = 7 
16: skt = 1 logic = 0 phy = 8 
17: skt = 1 logic = 1 phy = 0 
18: skt = 1 logic = 9 phy = 11 
19: skt = 0 logic = 3 phy = 10 
20: skt = 0 logic = 6 phy = 9 
21: skt = 0 logic = 0 phy = 8 

IPU0log=
IPU1log=
HSM0log=
IMU0log=22: skt = 0 logic = 7 phy = 1 
23: skt = 0 logic = 1 phy = 0 
get mem silk data length: 72
[0.02.13.329]PCIE INIT DONE.
[IMU][ERR] LOS_SemPend(g_pcieSemaphore, LOS_WAIT_FOREVER)
[RegisterInterruptSource]:[21] begin
Interrupt 25
IPU0log=
IPU1log=
HSM0log=
IMU0log=8 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 262 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 266 register OK
[RegisterInter
IPU0log=
IPU1log=
HSM0log=
IMU0log=ruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 270 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 277 register OK
[RegisterInterruptSource]:[39] end
[Regis
IPU0log=
IPU1log=
HSM0log=
IMU0log=terInterruptSource]:[21] begin
Interrupt 288 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 292 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] beg
IPU0log=
IPU1log=
HSM0log=
IMU0log=in
Interrupt 296 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 300 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 307 register O
IPU0log=
IPU1log=
HSM0log=
IMU0log=K
[RegisterInterruptSource]:[39] end
pmt Init done

-----------------ROUTE TABLE------------------
entryCount = 4
----------------------------------------------
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, ent
IPU0log=
IPU1log=
HSM0log=
IMU0log=ryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x9100
[No.1]:
eidRange = 1, startEid = 10, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x930
IPU0log=
IPU1log=
HSM0log=
IMU0log=0
[No.2]:
eidRange = 1, startEid = 12, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2500
[No.3]:
eidRange = 1, startEid = 11, port = 0, isStatic = 1, entryType = 0, 
IPU0log=
IPU1log=
HSM0log=
IMU0log=
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2100
----------------------------------------------
-----------------ROUTE TABLE------------------
entryCount = 4
----------------------------------------------
IPU0log=
IPU1log=
HSM0log=
IMU0log=
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x9100
[No.1]:
eidRange = 1, startEid = 10, port = 0, isStatic = 1, entryType = 0, 

IPU0log=
IPU1log=
HSM0log=
IMU0log=transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x9300
[No.2]:
eidRange = 1, startEid = 12, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2500
[No.3]:
ei
IPU0log=
IPU1log=
HSM0log=
IMU0log=dRange = 1, startEid = 11, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2100
----------------------------------------------
-----------------ROUTE TABLE---------------
IPU0log=
IPU1log=
HSM0log=
IMU0log=---
entryCount = 4
----------------------------------------------
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x9100
[No.1]:
eidR
IPU0log=
IPU1log=
HSM0log=
IMU0log=ange = 1, startEid = 10, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x9300
[No.2]:
eidRange = 1, startEid = 12, port = 0, isStatic = 1, entryType = 0, 
transportBindi
IPU0log=
IPU1log=
HSM0log=
IMU0log=ng = 2, mediaType = 15, addressSize = 2, bdf = 0x2500
[No.3]:
eidRange = 1, startEid = 11, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2100
-------------------------
IPU0log=
IPU1log=
HSM0log=
IMU0log=---------------------

IPU0log=
IPU1log=
HSM0log=
IMU0log=1T1N1U skt:0 CfgBusDfxPreConfig finish

********Hello Huawei LiteOS********

IMU Firmware Version : B173V01
LiteOS Kernel Version : 5.10.0
Run on Socket[0] Die[3]
Chip Version: 1
Max socket num: 2
*******************************
IPU0log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 0
cls: 6, core: 7
cpu 933 sram 1010 ddr 983
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  750|  802|  885|  933|
max  v
IPU1log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 1
cls: 6, core: 7
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  759|  821|  909|  961|
max  v: |  750|  750|  753|  781
HSM0log=[1970-01-01 00:01:12.371][HSM][INFO][30] init start
[1970-01-01 00:01:12.371][HSM][INFO][38] init over
[00:01:12.381][info] succeed to do thirdparty dfx_pabuk init
[00:01:12.387][info] os_mem_system_init default pool done
[0
IMU0log=***
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | rail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_vo
IPU0log=: |  750|  750|  754|  775|  836|  922|  980|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:7
IPU1log=|  846|  938|  994|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:750 F:1950
avs-uncore V:750
HSM0log=0:01:12.393][info] addr is already in region
[00:01:12.396][info] succeed to do thirdparty otpc_pabuk init
[1970-01-01 00:01:12.401][HSM][INFO][31] select_region: 0xc11cb55b
[1970-01-01 00:01:12.407][HSM][INFO][67] spi_nor de
IMU0log=lt:1122 mV | pmu:MP2882
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_v
IPU0log=50 F:1950
avs-uncore V:750 F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
av
IPU1log= F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
avs-uncore V:840 F:2450
avs-
HSM0log=vice_id 0xff1a67c8
[1970-01-01 00:01:12.413][HSM][INFO][50] std_cmd readback 0x30220d8
[1970-01-01 00:01:12.419][HSM][INFO][72] saf_cmd 0x0 readback 0x9f5a0604
[1970-01-01 00:01:12.426][HSM][INFO][72] saf_cmd 0x1 readback 0x5
IMU0log=olt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_
IPU0log=s-uncore V:840 F:2450
avs-uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain
IPU1log=uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | r
HSM0log=b7e938
[1970-01-01 00:01:12.432][HSM][INFO][72] saf_cmd 0x2 readback 0x1
[1970-01-01 00:01:12.438][HSM][INFO][72] saf_cmd 0x3 readback 0x0
[1970-01-01 00:01:12.444][HSM][INFO][72] saf_cmd 0x4 readback 0x0
[00:01:12.450][info
IMU0log=volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus r
IPU0log=[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | p
IPU1log=ail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_volt:1122 mV | pmu:MP2882
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[0] volt =  908 mV
pwr domain
HSM0log=] succeed to do thirdparty boot_profile_driver init
[00:01:12.456][info] succeed to do thirdparty crypto_driver init
[00:01:12.461][info] succeed to do thirdparty period_driver init
[00:01:12.467][info]  start loading interna
IMU0log=eady.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait th
IPU0log=mu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pmbus:0x480c0000 ver:0x110
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
IPU1log=[9] volt = 1103 mV
=end=
w&h rd rail:0, 908
w&h rd rail:1, 1103
pwr domain[0] set volt  904 mV succ
pwr domain[9] set volt 1103 mV succ
volt post
pwr domain[0] volt =  904 mV
pwr domain[9] volt = 1103 mV
==end==
Totem[0] Core Bo
HSM0log=l task ...
[00:01:12.472][info]  task name is ccm_task
[00:01:12.476][info]  hm_dynamic_loadelf successfully!
[00:01:12.481][info] internal task[1] task_name=ccm_task load successfully
[00:01:12.487][info]  task name is upgr
IMU0log=e cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master I
IPU0log=
avsbus resync succ
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[2] volt =  904 mV
pwr domain[7] volt =  804 mV
pwr domain[4] volt =  806 mV
pwr domain[1] volt =  804 mV
=end=
w&h rd rail:
IPU1log=ot Vol [1029]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2,
HSM0log=ade_task
[00:01:12.492][info]  hm_dynamic_loadelf successfully!
[00:01:12.496][info] internal task[2] task_name=upgrade_task load successfully
[00:01:12.503][info] created task ccm_task success!
[00:01:12.508][info] created 
IMU0log=mu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
cpu 0 entering scheduler
|--------------------------------------------------|
AtsPrint
|idx|lockCount| srcAddr| destAddr| addrLen|
|--
IPU0log=0, 906
w&h rd rail:1, 802
pwr domain[2] set volt  902 mV succ
pwr domain[7] set volt  800 mV succ
w&h rd rail:0, 806
w&h rd rail:1, 806
pwr domain[4] set volt  804 mV succ
pwr domain[1] set volt  802 mV succ
volt post
pwr domain
IPU1log= ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd8
HSM0log=task upgrade_task success!
[1970-01-01 00:01:12.513][HSM][INFO][54] Platform init 0x20250523 0x4e.
[1970-01-01 00:01:12.519][HSM][INFO][197] ccm start.
[1970-01-01 00:01:12.524][HSM][INFO][86] upgrade task init success.
[197
IMU0log=------------------------------------------------|
|  0|00000000|0x010500000|0x000110800000|0x00100000|
|  1|00000000|0x020000000|0x00001d000000|0x00800000|
|  2|00000000|0x020800000|0x000490000000|0x00100000|
|  3|00000000|0x020
IPU0log=[2] volt =  902 mV
pwr domain[7] volt =  802 mV
pwr domain[4] volt =  802 mV
pwr domain[1] volt =  802 mV
==end==
Totem[0] Core Boot Vol [1015]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0,
IPU1log=00, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
opposite dieId: 0, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 
HSM0log=0-01-01 00:01:12.530][HSM][INFO][95] upgrade recv cmd, 0x181.
[1970-01-01 00:01:12.536][HSM][INFO][103] upgrade res, 0x3a5aa5a3.
.
IMU0log=900000|0x000004000000|0x08000000|
|  4|00000000|0x028900000|0x000440580000|0x01000000|
|  5|00000000|0x029900000|0x000590000000|0x00100000|
|  6|00000000|0x029a00000|0x002000150000|0x00100000|
|  7|00000000|0x000000000|0x0000000
IPU0log= MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 
IPU1log=enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
hiboost task entry
boost wait SEF.
[INFO] mem used of task 'app_Task' is:0x2028, not zero when task being deleted
boost param OK.
Totem[0] Core[ 0] Freq Limit Low
HSM0log=
IMU0log=00000|0x00000000|
|  8|00000000|0x040000000|0x000000000000|0x08000000|
|  9|00000000|0x048000000|0x000000000000|0x08000000|
| 10|00000000|0x050000000|0x000000000000|0x08000000|
| 11|00000000|0x058000000|0x000000000000|0x08000000
IPU0log=0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
tsensor type
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Fr
HSM0log=
IMU0log=|
| 12|00000000|0x060000000|0x000000000000|0x08000000|
| 13|00000000|0x068000000|0x000000000000|0x08000000|
| 14|00000000|0x070000000|0x000000000000|0x08000000|
| 15|00000000|0x078000000|0x000490000000|0x08000000|
|-------------
IPU0log=: 3, ppuFormatK: 0x4da6, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b4,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 3, mask: fffffff8
tsensor type: 4, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=-------------------------------------|
=~=~=~=~=~=~=~=~=~=~= IMU Log @ 2026.6.1 7:29:54 =~=~=~=~=~=~=~=~=~=~=
[IMU] Watchdog Initialization done!
[RegisterInterruptSource]:[21] begin
Interrupt 32 register OK
Interrupt 34 regis
IPU0log=0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 4, mask: ffffffee
tsensor type: 5, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1

IPU1log= Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=ter OK
Interrupt 40 register OK
Interrupt 44 register OK
sram cnt 0x0, id = 43
Interrupt 43 register OK
Interrupt 36 register OK
Interrupt 57 register OK
sram cnt 0x0, id = 42
Interrupt 42 register OK
Interrupt 37 register OK
[R
IPU0log=tsensor: 5, mask: ffffffda
tsensor type: 6, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 6, mask: ffffff80
tsensor type: 7, ppuFormatK: 0x437a,
IPU1log=KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=egisterInterruptSource]:[39] end
IPMB initialization Start...
IPMB clock set done, prer = 0x18.
IPMB Rx FIFO clear empty.
IPMB initialization Done.
starting DFX Collect Task end
PowerTask Entry ...
Wait all vrd init done .
IPU0log= ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 7, mask: fffffffe
opposite dieId: 1, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
CPM max V[900]-
IPU1log= Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low
HSM0log=
IMU0log=..
All vrd init done, power task start
refresh domainId 0 Lsb 0x0
refresh domainId 9 Lsb 0x1
refresh domainId 2 Lsb 0x0
refresh domainId 7 Lsb 0x1
refresh domainId 4 Lsb 0x0
refresh domainId 1 Lsb 0x1
power sensor[0] | calib:512
IPU0log=F:2800
CPM min V[750]-F:1600
freq:2350, idx:9
cpm trim freq: 2600, idx: 4
cpm trim finish
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
recount hours 
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Fr
HSM0log=
IMU0log=0 | rshunt:1 | rshuntDiv:1000 | currLsb:1 | currLsbDiv:1000 | enableFlag:1
                | pwrLsb:25 | defPwr:25000 | minPwr:10000 | maxPwr:65000 | pwrFix:3400
                | manufacturerId: 0x5549 | dieId: 0x2260
power sen
IPU0log=0xb40 
hiboost task entry
boost wait SEF.
boost param OK.
Totem[0] Core[ 0] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[26
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=sor[0] init success
ScmiTaskEntry start.
[RegisterInterruptSource]:[21] begin
Interrupt 51 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 52 register OK
[RegisterInterruptSource]
IPU0log=00000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[12000
IPU1log= Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 53 register OK
[RegisterInterruptSource]:[39] end
[0.01.29.095]starting ras Init
RAS Setup Value get done!
INT_NUM_PER_SKT * HiGetSktNum() = 0x8
index = 0x0
RasIntRegis
IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Lim
IPU1log=KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=ter init 160 
index = 0x1
RasIntRegister init 172 
index = 0x2
RasIntRegister init 162 
index = 0x3
RasIntRegister init 174 
index = 0x4
RasIntRegister init 184 
index = 0x5
RasIntRegister init 196 
index = 0x6
RasIntRegister in
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IPU1log= Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low
HSM0log=
IMU0log=it 186 
index = 0x7
RasIntRegister init 198 
RasIntRegister init 161 
RasIntRegister init 173 
RasIntRegister init 185 
RasIntRegister init 197 
RasIntRegister init 284 
RasIntRegister init 314 
MceTableHeadInit start
starting C
IPU0log=14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
To
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
uncore max freq : 23
HSM0log=
IMU0log=e_Storm Contrl and Ras_Data_Update Task end
[0.01.29.177]starting ras end
[IMU][ERR] skt id 0
Ub init task start Entry ...
UbInitTask Entry ...
[RegisterInterruptSource]:[21] begin
Interrupt 167 register OK
[RegisterInterrupt
IPU0log=tem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[26
IPU1log=50 MHz

HSM0log=
IMU0log=Source]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 191 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 171 register OK
[RegisterInterruptSource]:[39] end
[RegisterI
IPU0log=00000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[12000
IPU1log=
HSM0log=
IMU0log=nterruptSource]:[21] begin
Interrupt 183 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 195 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin

IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Lim
IPU1log=
HSM0log=
IMU0log=Interrupt 207 register OK
[RegisterInterruptSource]:[39] end
Init heart-beat-task end
CS0 flash do not support sfdp!
Current flash device ID[0x61a67c8]!
System supported 1 Flash.
flash cs 0 Manufacture 0xc8, DeviceId 0x1a67, Ad
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IPU1log=
HSM0log=
IMU0log=drMode[0-3B,1-4B] 0x1:
    size 0x4000000, pagesize 0x100
    read  cmd 0x13, dummy byte 0x8
    write cmd 0x12, dummy byte 0x0
    erase4k cmd 0x21, erase64k byte 0xdc
sfc init end
firstUnMskExt0Int
ThermalDimmStart Entry ...

IPU0log=33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
To
IPU1log=
HSM0log=
IMU0log=wait ddr init done...
HacLowPowerStart Entry ...
Hello LiteOS...
Init ReportPcieMmioToBmcTaskEntry end
starting Fpc Isolation Task end
pwr cap[0]: 0, 67
[IMU][ERR] IMP log not ready, DDR initing...
pwr cap[1]: f, 27
pwr cap[
IPU0log=tem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[26
IPU1log=
HSM0log=
IMU0log=2]: 1, 3
[IMU][ERR] IMP log not ready, DDR initing...
[IMU][ERR] IMP log not ready, DDR initing...
[0.02.00.459]DDR init done
[LOG]head = 0x0, tail = 0x188b, logSize = 0x188b
[IMU][ERR] HsmLogInit!
[IMU][ERR] HsmLogInit! TRUE
s
IPU0log=00000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
uncore max freq : 2350 MHz

IPU1log=
HSM0log=
IMU0log=et apei done!
UbConfigData size is 64
UbConfigData 0 : 0
UbConfigData 1 : 0
UbConfigData 2 : 0
UbConfigData 3 : 1
UbConfigData 4 : 31
UbConfigData 5 : 1
UbConfigData 6 : 0
UbConfigData 7 : 32
UbConfigData 8 : 0
UbConfigData 9 : 
IPU0log=
IPU1log=
HSM0log=
IMU0log=1
UbConfigData 10 : 2
UbConfigData 11 : 0
UbConfigData 12 : 0
UbConfigData 13 : 1
UbConfigData 14 : 0
UbConfigData 15 : 0
UbConfigData 16 : 0
UbConfigData 17 : 0
UbConfigData 18 : 0
UbConfigData 19 : 0
UbConfigData 20 : 0
UbConf
IPU0log=
IPU1log=
HSM0log=
IMU0log=igData 21 : 0
UbConfigData 22 : 11
UbConfigData 23 : 0
UbConfigData 24 : 0
UbConfigData 25 : 0
UbConfigData 26 : 0
UbConfigData 27 : 0
UbConfigData 28 : 0
UbConfigData 29 : 0
UbConfigData 30 : 0
UbConfigData 31 : 0
UbConfigData 
IPU0log=
IMU0log=1T1N1U skt:0 CfgBusDfxPreConfig finish

********Hello Huawei LiteOS********

IMU Firmware Version : B173V01
LiteOS Kernel Version : 5.10.0
Run on Socket[0] Die[3]
Chip Version: 1
Max socket num: 2
*******************************
IPU0log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 0
cls: 6, core: 7
cpu 933 sram 1010 ddr 983
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  750|  802|  885|  933|
max  v
IPU1log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 1
cls: 6, core: 7
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  759|  821|  909|  961|
max  v: |  750|  750|  753|  781
HSM0log=[1970-01-01 00:01:13.380][HSM][INFO][30] init start
[1970-01-01 00:01:13.380][HSM][INFO][38] init over
[00:01:13.390][info] succeed to do thirdparty dfx_pabuk init
[00:01:13.395][info] os_mem_system_init default pool done
[0
IMU0log=***
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | rail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_vo
IPU0log=: |  750|  750|  754|  775|  836|  922|  980|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:7
IPU1log=|  846|  938|  994|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:750 F:1950
avs-uncore V:750
HSM0log=0:01:13.401][info] addr is already in region
[00:01:13.404][info] succeed to do thirdparty otpc_pabuk init
[1970-01-01 00:01:13.410][HSM][INFO][31] select_region: 0xc11cb55b
[1970-01-01 00:01:13.416][HSM][INFO][67] spi_nor de
IMU0log=lt:1122 mV | pmu:MP2882
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_v
IPU0log=50 F:1950
avs-uncore V:750 F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
av
IPU1log= F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
avs-uncore V:840 F:2450
avs-
HSM0log=vice_id 0xff1a67c8
[1970-01-01 00:01:13.422][HSM][INFO][50] std_cmd readback 0x30220d8
[1970-01-01 00:01:13.428][HSM][INFO][72] saf_cmd 0x0 readback 0x9f5a0604
[1970-01-01 00:01:13.434][HSM][INFO][72] saf_cmd 0x1 readback 0x5
IMU0log=olt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_
IPU0log=s-uncore V:840 F:2450
avs-uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain
IPU1log=uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | r
HSM0log=b7e938
[1970-01-01 00:01:13.440][HSM][INFO][72] saf_cmd 0x2 readback 0x1
[1970-01-01 00:01:13.446][HSM][INFO][72] saf_cmd 0x3 readback 0x0
[1970-01-01 00:01:13.452][HSM][INFO][72] saf_cmd 0x4 readback 0x0
[00:01:13.459][info
IMU0log=volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus r
IPU0log=[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | p
IPU1log=ail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_volt:1122 mV | pmu:MP2882
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[0] volt =  906 mV
pwr domain
HSM0log=] succeed to do thirdparty boot_profile_driver init
[00:01:13.464][info] succeed to do thirdparty crypto_driver init
[00:01:13.470][info] succeed to do thirdparty period_driver init
[00:01:13.476][info]  start loading interna
IMU0log=eady.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait th
IPU0log=mu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pmbus:0x480c0000 ver:0x110
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
IPU1log=[9] volt = 1103 mV
=end=
w&h rd rail:0, 906
w&h rd rail:1, 1105
pwr domain[0] set volt  904 mV succ
pwr domain[9] set volt 1103 mV succ
volt post
pwr domain[0] volt =  906 mV
pwr domain[9] volt = 1105 mV
==end==
Totem[0] Core Bo
HSM0log=l task ...
[00:01:13.480][info]  task name is ccm_task
[00:01:13.484][info]  hm_dynamic_loadelf successfully!
[00:01:13.489][info] internal task[1] task_name=ccm_task load successfully
[00:01:13.496][info]  task name is upgr
IMU0log=e cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master I
IPU0log=
avsbus resync succ
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[2] volt =  904 mV
pwr domain[7] volt =  802 mV
pwr domain[4] volt =  804 mV
pwr domain[1] volt =  804 mV
=end=
w&h rd rail:
IPU1log=ot Vol [1029]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2,
HSM0log=ade_task
[00:01:13.500][info]  hm_dynamic_loadelf successfully!
[00:01:13.505][info] internal task[2] task_name=upgrade_task load successfully
[00:01:13.512][info] created task ccm_task success!
[00:01:13.516][info] created 
IMU0log=mu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
cpu 0 entering scheduler
|--------------------------------------------------|
AtsPrint
|idx|lockCount| srcAddr| destAddr| addrLen|
|--
IPU0log=0, 904
w&h rd rail:1, 804
pwr domain[2] set volt  902 mV succ
pwr domain[7] set volt  802 mV succ
w&h rd rail:0, 804
w&h rd rail:1, 804
pwr domain[4] set volt  804 mV succ
pwr domain[1] set volt  802 mV succ
volt post
pwr domain
IPU1log= ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd8
HSM0log=task upgrade_task success!
[1970-01-01 00:01:13.521][HSM][INFO][54] Platform init 0x20250523 0x4e.
[1970-01-01 00:01:13.528][HSM][INFO][197] ccm start.
[1970-01-01 00:01:13.532][HSM][INFO][86] upgrade task init success.
[197
IMU0log=------------------------------------------------|
|  0|00000000|0x010500000|0x000110800000|0x00100000|
|  1|00000000|0x020000000|0x00001d000000|0x00800000|
|  2|00000000|0x020800000|0x000490000000|0x00100000|
|  3|00000000|0x020
IPU0log=[2] volt =  902 mV
pwr domain[7] volt =  802 mV
pwr domain[4] volt =  804 mV
pwr domain[1] volt =  802 mV
==end==
Totem[0] Core Boot Vol [1015]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0,
IPU1log=00, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
opposite dieId: 0, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 
HSM0log=0-01-01 00:01:13.538][HSM][INFO][95] upgrade recv cmd, 0x181.
[1970-01-01 00:01:13.544][HSM][INFO][103] upgrade res, 0x3a5aa5a3.
.
IMU0log=900000|0x000004000000|0x08000000|
|  4|00000000|0x028900000|0x000440580000|0x01000000|
|  5|00000000|0x029900000|0x000590000000|0x00100000|
|  6|00000000|0x029a00000|0x002000150000|0x00100000|
|  7|00000000|0x000000000|0x0000000
IPU0log= MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 
IPU1log=enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
hiboost task entry
boost wait SEF.
[INFO] mem used of task 'app_Task' is:0x2028, not zero when task being deleted
boost param OK.
Totem[0] Core[ 0] Freq Limit Low
HSM0log=
IMU0log=00000|0x00000000|
|  8|00000000|0x040000000|0x000000000000|0x08000000|
|  9|00000000|0x048000000|0x000000000000|0x08000000|
| 10|00000000|0x050000000|0x000000000000|0x08000000|
| 11|00000000|0x058000000|0x000000000000|0x08000000
IPU0log=0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
tsensor type
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Fr
HSM0log=
IMU0log=|
| 12|00000000|0x060000000|0x000000000000|0x08000000|
| 13|00000000|0x068000000|0x000000000000|0x08000000|
| 14|00000000|0x070000000|0x000000000000|0x08000000|
| 15|00000000|0x078000000|0x000490000000|0x08000000|
|-------------
IPU0log=: 3, ppuFormatK: 0x4da6, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b4,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 3, mask: fffffff8
tsensor type: 4, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=-------------------------------------|
=~=~=~=~=~=~=~=~=~=~= IMU Log @ 2026.6.1 7:36:21 =~=~=~=~=~=~=~=~=~=~=
[IMU] Watchdog Initialization done!
[RegisterInterruptSource]:[21] begin
Interrupt 32 register OK
Interrupt 34 regis
IPU0log=0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 4, mask: ffffffee
tsensor type: 5, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1

IPU1log= Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=ter OK
Interrupt 40 register OK
Interrupt 44 register OK
sram cnt 0x0, id = 43
Interrupt 43 register OK
Interrupt 36 register OK
Interrupt 57 register OK
sram cnt 0x0, id = 42
Interrupt 42 register OK
Interrupt 37 register OK
[R
IMU0log=1T1N1U skt:0 CfgBusDfxPreConfig finish

********Hello Huawei LiteOS********

IMU Firmware Version : B173V01
LiteOS Kernel Version : 5.10.0
Run on Socket[0] Die[3]
Chip Version: 1
Max socket num: 2
*******************************
IPU0log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 0
cls: 6, core: 7
cpu 933 sram 1010 ddr 983
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  750|  802|  885|  933|
max  v
IPU1log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 1
cls: 6, core: 7
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  759|  821|  909|  961|
max  v: |  750|  750|  753|  781
HSM0log=[1970-01-01 00:01:11.459][HSM][INFO][30] init start
[1970-01-01 00:01:11.459][HSM][INFO][38] init over
[00:01:11.469][info] succeed to do thirdparty dfx_pabuk init
[00:01:11.474][info] os_mem_system_init default pool done
[0
IMU0log=***
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | rail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_vo
IPU0log=: |  750|  750|  754|  775|  836|  922|  980|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:7
IPU1log=|  846|  938|  994|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:750 F:1950
avs-uncore V:750
HSM0log=0:01:11.480][info] addr is already in region
[00:01:11.483][info] succeed to do thirdparty otpc_pabuk init
[1970-01-01 00:01:11.489][HSM][INFO][31] select_region: 0xc11cb55b
[1970-01-01 00:01:11.495][HSM][INFO][67] spi_nor de
IMU0log=lt:1122 mV | pmu:MP2882
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_v
IPU0log=50 F:1950
avs-uncore V:750 F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
av
IPU1log= F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
avs-uncore V:840 F:2450
avs-
HSM0log=vice_id 0xff1a67c8
[1970-01-01 00:01:11.501][HSM][INFO][50] std_cmd readback 0x30220d8
[1970-01-01 00:01:11.507][HSM][INFO][72] saf_cmd 0x0 readback 0x9f5a0604
[1970-01-01 00:01:11.513][HSM][INFO][72] saf_cmd 0x1 readback 0x5
IMU0log=olt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_
IPU0log=s-uncore V:840 F:2450
avs-uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain
IPU1log=uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | r
HSM0log=b7e938
[1970-01-01 00:01:11.520][HSM][INFO][72] saf_cmd 0x2 readback 0x1
[1970-01-01 00:01:11.525][HSM][INFO][72] saf_cmd 0x3 readback 0x0
[1970-01-01 00:01:11.531][HSM][INFO][72] saf_cmd 0x4 readback 0x0
[00:01:11.538][info
IMU0log=volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus r
IPU0log=[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | p
IPU1log=ail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_volt:1122 mV | pmu:MP2882
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[0] volt =  906 mV
pwr domain
HSM0log=] succeed to do thirdparty boot_profile_driver init
[00:01:11.543][info] succeed to do thirdparty crypto_driver init
[00:01:11.549][info] succeed to do thirdparty period_driver init
[00:01:11.555][info]  start loading interna
IMU0log=eady.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait th
IPU0log=mu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pmbus:0x480c0000 ver:0x110
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
IPU1log=[9] volt = 1105 mV
=end=
w&h rd rail:0, 908
w&h rd rail:1, 1103
pwr domain[0] set volt  906 mV succ
pwr domain[9] set volt 1103 mV succ
volt post
pwr domain[0] volt =  904 mV
pwr domain[9] volt = 1103 mV
==end==
Totem[0] Core Bo
HSM0log=l task ...
[00:01:11.559][info]  task name is ccm_task
[00:01:11.563][info]  hm_dynamic_loadelf successfully!
[00:01:11.568][info] internal task[1] task_name=ccm_task load successfully
[00:01:11.575][info]  task name is upgr
IMU0log=e cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master I
IPU0log=
avsbus resync succ
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[2] volt =  904 mV
pwr domain[7] volt =  804 mV
pwr domain[4] volt =  806 mV
pwr domain[1] volt =  804 mV
=end=
w&h rd rail:
IPU1log=ot Vol [1029]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2,
HSM0log=ade_task
[00:01:11.579][info]  hm_dynamic_loadelf successfully!
[00:01:11.584][info] internal task[2] task_name=upgrade_task load successfully
[00:01:11.591][info] created task ccm_task success!
[00:01:11.596][info] created 
IMU0log=mu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
cpu 0 entering scheduler
|--------------------------------------------------|
AtsPrint
|idx|lockCount| srcAddr| destAddr| addrLen|
|--
IPU0log=0, 904
w&h rd rail:1, 802
pwr domain[2] set volt  904 mV succ
pwr domain[7] set volt  800 mV succ
w&h rd rail:0, 804
w&h rd rail:1, 804
pwr domain[4] set volt  804 mV succ
pwr domain[1] set volt  802 mV succ
volt post
pwr domain
IPU1log= ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd8
HSM0log=task upgrade_task success!
[1970-01-01 00:01:11.600][HSM][INFO][54] Platform init 0x20250523 0x4e.
[1970-01-01 00:01:11.607][HSM][INFO][197] ccm start.
[1970-01-01 00:01:11.611][HSM][INFO][86] upgrade task init success.
[197
IMU0log=------------------------------------------------|
|  0|00000000|0x010500000|0x000110800000|0x00100000|
|  1|00000000|0x020000000|0x00001d000000|0x00800000|
|  2|00000000|0x020800000|0x000490000000|0x00100000|
|  3|00000000|0x020
IPU0log=[2] volt =  902 mV
pwr domain[7] volt =  802 mV
pwr domain[4] volt =  804 mV
pwr domain[1] volt =  802 mV
==end==
Totem[0] Core Boot Vol [1015]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0,
IPU1log=00, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
opposite dieId: 0, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 
HSM0log=0-01-01 00:01:11.617][HSM][INFO][95] upgrade recv cmd, 0x181.
[1970-01-01 00:01:11.623][HSM][INFO][103] upgrade res, 0x3a5aa5a3.
.
IMU0log=900000|0x000004000000|0x08000000|
|  4|00000000|0x028900000|0x000440580000|0x01000000|
|  5|00000000|0x029900000|0x000590000000|0x00100000|
|  6|00000000|0x029a00000|0x002000150000|0x00100000|
|  7|00000000|0x000000000|0x0000000
IPU0log= MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 
IPU1log=enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
hiboost task entry
boost wait SEF.
[INFO] mem used of task 'app_Task' is:0x2028, not zero when task being deleted
boost param OK.
Totem[0] Core[ 0] Freq Limit Low
HSM0log=
IMU0log=00000|0x00000000|
|  8|00000000|0x040000000|0x000000000000|0x08000000|
|  9|00000000|0x048000000|0x000000000000|0x08000000|
| 10|00000000|0x050000000|0x000000000000|0x08000000|
| 11|00000000|0x058000000|0x000000000000|0x08000000
IPU0log=0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
tsensor type
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Fr
IMU0log=1T1N1U skt:0 CfgBusDfxPreConfig finish

********Hello Huawei LiteOS********

IMU Firmware Version : B173V01
LiteOS Kernel Version : 5.10.0
Run on Socket[0] Die[3]
Chip Version: 1
Max socket num: 2
*******************************
IPU0log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 0
cls: 6, core: 7
cpu 933 sram 1010 ddr 983
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  750|  802|  885|  933|
max  v
IPU1log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 1
cls: 6, core: 7
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  759|  821|  909|  961|
max  v: |  750|  750|  753|  781
HSM0log=[1970-01-01 00:01:12.226][HSM][INFO][30] init start
[1970-01-01 00:01:12.226][HSM][INFO][38] init over
[00:01:12.236][info] succeed to do thirdparty dfx_pabuk init
[00:01:12.242][info] os_mem_system_init default pool done
[0
IMU0log=***
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | rail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_vo
IPU0log=: |  750|  750|  754|  775|  836|  922|  980|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:7
IPU1log=|  846|  938|  994|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:750 F:1950
avs-uncore V:750
HSM0log=0:01:12.248][info] addr is already in region
[00:01:12.251][info] succeed to do thirdparty otpc_pabuk init
[1970-01-01 00:01:12.256][HSM][INFO][31] select_region: 0xc11cb55b
[1970-01-01 00:01:12.262][HSM][INFO][67] spi_nor de
IMU0log=lt:1122 mV | pmu:MP2882
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_v
IPU0log=50 F:1950
avs-uncore V:750 F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
av
IPU1log= F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
avs-uncore V:840 F:2450
avs-
HSM0log=vice_id 0xff1a67c8
[1970-01-01 00:01:12.268][HSM][INFO][50] std_cmd readback 0x30220d8
[1970-01-01 00:01:12.274][HSM][INFO][72] saf_cmd 0x0 readback 0x9f5a0604
[1970-01-01 00:01:12.281][HSM][INFO][72] saf_cmd 0x1 readback 0x5
IMU0log=olt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_
IPU0log=s-uncore V:840 F:2450
avs-uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain
IPU1log=uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | r
HSM0log=b7e938
[1970-01-01 00:01:12.287][HSM][INFO][72] saf_cmd 0x2 readback 0x1
[1970-01-01 00:01:12.293][HSM][INFO][72] saf_cmd 0x3 readback 0x0
[1970-01-01 00:01:12.298][HSM][INFO][72] saf_cmd 0x4 readback 0x0
[00:01:12.305][info
IMU0log=volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus r
IPU0log=[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | p
IPU1log=ail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_volt:1122 mV | pmu:MP2882
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[0] volt =  906 mV
pwr domain
HSM0log=] succeed to do thirdparty boot_profile_driver init
[00:01:12.311][info] succeed to do thirdparty crypto_driver init
[00:01:12.316][info] succeed to do thirdparty period_driver init
[00:01:12.322][info]  start loading interna
IMU0log=eady.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait th
IPU0log=mu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pmbus:0x480c0000 ver:0x110
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
IPU1log=[9] volt = 1103 mV
=end=
w&h rd rail:0, 906
w&h rd rail:1, 1103
pwr domain[0] set volt  906 mV succ
pwr domain[9] set volt 1103 mV succ
volt post
pwr domain[0] volt =  906 mV
pwr domain[9] volt = 1103 mV
==end==
Totem[0] Core Bo
HSM0log=l task ...
[00:01:12.327][info]  task name is ccm_task
[00:01:12.331][info]  hm_dynamic_loadelf successfully!
[00:01:12.336][info] internal task[1] task_name=ccm_task load successfully
[00:01:12.342][info]  task name is upgr
IMU0log=e cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master I
IMU0log=1T1N1U skt:0 CfgBusDfxPreConfig finish

********Hello Huawei LiteOS********

IMU Firmware Version : B173V01
LiteOS Kernel Version : 5.10.0
Run on Socket[0] Die[3]
Chip Version: 1
Max socket num: 2
*******************************
IPU0log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 0
cls: 6, core: 7
cpu 933 sram 1010 ddr 983
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  750|  802|  885|  933|
max  v
IPU1log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 1
cls: 6, core: 7
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  759|  821|  909|  961|
max  v: |  750|  750|  753|  781
HSM0log=[1970-01-01 00:01:11.530][HSM][INFO][30] init start
[1970-01-01 00:01:11.530][HSM][INFO][38] init over
[00:01:11.540][info] succeed to do thirdparty dfx_pabuk init
[00:01:11.546][info] os_mem_system_init default pool done
[0
IMU0log=***
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | rail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_vo
IPU0log=: |  750|  750|  754|  775|  836|  922|  980|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:7
IPU1log=|  846|  938|  994|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:750 F:1950
avs-uncore V:750
HSM0log=0:01:11.552][info] addr is already in region
[00:01:11.555][info] succeed to do thirdparty otpc_pabuk init
[1970-01-01 00:01:11.560][HSM][INFO][31] select_region: 0xc11cb55b
[1970-01-01 00:01:11.566][HSM][INFO][67] spi_nor de
IMU0log=lt:1122 mV | pmu:MP2882
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_v
IPU0log=50 F:1950
avs-uncore V:750 F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
av
IPU1log= F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
avs-uncore V:840 F:2450
avs-
HSM0log=vice_id 0xff1a67c8
[1970-01-01 00:01:11.572][HSM][INFO][50] std_cmd readback 0x30220d8
[1970-01-01 00:01:11.578][HSM][INFO][72] saf_cmd 0x0 readback 0x9f5a0604
[1970-01-01 00:01:11.585][HSM][INFO][72] saf_cmd 0x1 readback 0x5
IMU0log=olt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_
IPU0log=s-uncore V:840 F:2450
avs-uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain
IPU1log=uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | r
HSM0log=b7e938
[1970-01-01 00:01:11.591][HSM][INFO][72] saf_cmd 0x2 readback 0x1
[1970-01-01 00:01:11.597][HSM][INFO][72] saf_cmd 0x3 readback 0x0
[1970-01-01 00:01:11.603][HSM][INFO][72] saf_cmd 0x4 readback 0x0
[00:01:11.609][info
IMU0log=volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus r
IPU0log=[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | p
IPU1log=ail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_volt:1122 mV | pmu:MP2882
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[0] volt =  906 mV
pwr domain
HSM0log=] succeed to do thirdparty boot_profile_driver init
[00:01:11.615][info] succeed to do thirdparty crypto_driver init
[00:01:11.620][info] succeed to do thirdparty period_driver init
[00:01:11.626][info]  start loading interna
IMU0log=eady.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait th
IPU0log=mu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pmbus:0x480c0000 ver:0x110
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
IPU1log=[9] volt = 1103 mV
=end=
w&h rd rail:0, 908
w&h rd rail:1, 1105
pwr domain[0] set volt  904 mV succ
pwr domain[9] set volt 1103 mV succ
volt post
pwr domain[0] volt =  906 mV
pwr domain[9] volt = 1103 mV
==end==
Totem[0] Core Bo
HSM0log=l task ...
[00:01:11.631][info]  task name is ccm_task
[00:01:11.635][info]  hm_dynamic_loadelf successfully!
[00:01:11.640][info] internal task[1] task_name=ccm_task load successfully
[00:01:11.646][info]  task name is upgr
IMU0log=e cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master I
IPU0log=
avsbus resync succ
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[2] volt =  906 mV
pwr domain[7] volt =  804 mV
pwr domain[4] volt =  804 mV
pwr domain[1] volt =  804 mV
=end=
w&h rd rail:
IPU1log=ot Vol [1029]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2,
HSM0log=ade_task
[00:01:11.651][info]  hm_dynamic_loadelf successfully!
[00:01:11.655][info] internal task[2] task_name=upgrade_task load successfully
[00:01:11.662][info] created task ccm_task success!
[00:01:11.667][info] created 
IMU0log=1T1N1U skt:0 CfgBusDfxPreConfig finish

********Hello Huawei LiteOS********

IMU Firmware Version : B173V01
LiteOS Kernel Version : 5.10.0
Run on Socket[0] Die[3]
Chip Version: 1
Max socket num: 2
*******************************
IPU0log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 0
cls: 6, core: 7
cpu 933 sram 1010 ddr 983
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  750|  802|  885|  933|
max  v
IPU1log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 1
cls: 6, core: 7
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  759|  821|  909|  961|
max  v: |  750|  750|  753|  781
HSM0log=[1970-01-01 00:01:12.118][HSM][INFO][30] init start
[1970-01-01 00:01:12.119][HSM][INFO][38] init over
[00:01:12.128][info] succeed to do thirdparty dfx_pabuk init
[00:01:12.134][info] os_mem_system_init default pool done
[0
IMU0log=***
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | rail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_vo
IPU0log=: |  750|  750|  754|  775|  836|  922|  980|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:7
IPU1log=|  846|  938|  994|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:750 F:1950
avs-uncore V:750
HSM0log=0:01:12.140][info] addr is already in region
[00:01:12.143][info] succeed to do thirdparty otpc_pabuk init
[1970-01-01 00:01:12.148][HSM][INFO][31] select_region: 0xc11cb55b
[1970-01-01 00:01:12.154][HSM][INFO][67] spi_nor de
IMU0log=lt:1122 mV | pmu:MP2882
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_v
IPU0log=50 F:1950
avs-uncore V:750 F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
av
IPU1log= F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
avs-uncore V:840 F:2450
avs-
HSM0log=vice_id 0xff1a67c8
[1970-01-01 00:01:12.161][HSM][INFO][50] std_cmd readback 0x30220d8
[1970-01-01 00:01:12.167][HSM][INFO][72] saf_cmd 0x0 readback 0x9f5a0604
[1970-01-01 00:01:12.173][HSM][INFO][72] saf_cmd 0x1 readback 0x5
IMU0log=olt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_
IPU0log=s-uncore V:840 F:2450
avs-uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain
IPU1log=uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | r
HSM0log=b7e938
[1970-01-01 00:01:12.179][HSM][INFO][72] saf_cmd 0x2 readback 0x1
[1970-01-01 00:01:12.185][HSM][INFO][72] saf_cmd 0x3 readback 0x0
[1970-01-01 00:01:12.191][HSM][INFO][72] saf_cmd 0x4 readback 0x0
[00:01:12.197][info
IMU0log=volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus r
IPU0log=[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | p
IPU1log=ail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_volt:1122 mV | pmu:MP2882
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[0] volt =  906 mV
pwr domain
HSM0log=] succeed to do thirdparty boot_profile_driver init
[00:01:12.203][info] succeed to do thirdparty crypto_driver init
[00:01:12.209][info] succeed to do thirdparty period_driver init
[00:01:12.214][info]  start loading interna
IMU0log=eady.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait th
IPU0log=mu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pmbus:0x480c0000 ver:0x110
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
IPU1log=[9] volt = 1103 mV
=end=
w&h rd rail:0, 906
w&h rd rail:1, 1103
pwr domain[0] set volt  904 mV succ
pwr domain[9] set volt 1103 mV succ
volt post
pwr domain[0] volt =  904 mV
pwr domain[9] volt = 1103 mV
==end==
Totem[0] Core Bo
HSM0log=l task ...
[00:01:12.219][info]  task name is ccm_task
[00:01:12.223][info]  hm_dynamic_loadelf successfully!
[00:01:12.228][info] internal task[1] task_name=ccm_task load successfully
[00:01:12.235][info]  task name is upgr
IMU0log=e cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master I
IPU0log=
avsbus resync succ
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[2] volt =  904 mV
pwr domain[7] volt =  802 mV
pwr domain[4] volt =  806 mV
pwr domain[1] volt =  806 mV
=end=
w&h rd rail:
IPU1log=ot Vol [1029]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2,
HSM0log=ade_task
[00:01:12.239][info]  hm_dynamic_loadelf successfully!
[00:01:12.244][info] internal task[2] task_name=upgrade_task load successfully
[00:01:12.251][info] created task ccm_task success!
[00:01:12.255][info] created 
IMU0log=mu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
cpu 0 entering scheduler
|--------------------------------------------------|
AtsPrint
|idx|lockCount| srcAddr| destAddr| addrLen|
|--
IPU0log=0, 904
w&h rd rail:1, 804
pwr domain[2] set volt  902 mV succ
pwr domain[7] set volt  802 mV succ
w&h rd rail:0, 806
w&h rd rail:1, 804
pwr domain[4] set volt  802 mV succ
pwr domain[1] set volt  804 mV succ
volt post
pwr domain
IPU1log= ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd8
HSM0log=task upgrade_task success!
[1970-01-01 00:01:12.260][HSM][INFO][54] Platform init 0x20250523 0x4e.
[1970-01-01 00:01:12.267][HSM][INFO][197] ccm start.
[1970-01-01 00:01:12.271][HSM][INFO][86] upgrade task init success.
[197
IMU0log=------------------------------------------------|
|  0|00000000|0x010500000|0x000110800000|0x00100000|
|  1|00000000|0x020000000|0x00001d000000|0x00800000|
|  2|00000000|0x020800000|0x000490000000|0x00100000|
|  3|00000000|0x020
IPU0log=[2] volt =  902 mV
pwr domain[7] volt =  800 mV
pwr domain[4] volt =  804 mV
pwr domain[1] volt =  804 mV
==end==
Totem[0] Core Boot Vol [1015]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0,
IPU1log=00, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
opposite dieId: 0, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 
HSM0log=0-01-01 00:01:12.277][HSM][INFO][95] upgrade recv cmd, 0x181.
[1970-01-01 00:01:12.283][HSM][INFO][103] upgrade res, 0x3a5aa5a3.
.
IMU0log=900000|0x000004000000|0x08000000|
|  4|00000000|0x028900000|0x000440580000|0x01000000|
|  5|00000000|0x029900000|0x000590000000|0x00100000|
|  6|00000000|0x029a00000|0x002000150000|0x00100000|
|  7|00000000|0x000000000|0x0000000
IPU0log= MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 
IPU1log=enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
hiboost task entry
boost wait SEF.
[INFO] mem used of task 'app_Task' is:0x2028, not zero when task being deleted
boost param OK.
Totem[0] Core[ 0] Freq Limit Low
HSM0log=
IMU0log=00000|0x00000000|
|  8|00000000|0x040000000|0x000000000000|0x08000000|
|  9|00000000|0x048000000|0x000000000000|0x08000000|
| 10|00000000|0x050000000|0x000000000000|0x08000000|
| 11|00000000|0x058000000|0x000000000000|0x08000000
IPU0log=0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
tsensor type
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Fr
HSM0log=
IMU0log=|
| 12|00000000|0x060000000|0x000000000000|0x08000000|
| 13|00000000|0x068000000|0x000000000000|0x08000000|
| 14|00000000|0x070000000|0x000000000000|0x08000000|
| 15|00000000|0x078000000|0x000490000000|0x08000000|
|-------------
IPU0log=: 3, ppuFormatK: 0x4da6, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b4,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 3, mask: fffffff8
tsensor type: 4, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=-------------------------------------|
=~=~=~=~=~=~=~=~=~=~= IMU Log @ 2026.6.1 7:59:36 =~=~=~=~=~=~=~=~=~=~=
[IMU] Watchdog Initialization done!
[RegisterInterruptSource]:[21] begin
Interrupt 32 register OK
Interrupt 34 regis
IPU0log=0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 4, mask: ffffffee
tsensor type: 5, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1

IPU1log= Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=ter OK
Interrupt 40 register OK
Interrupt 44 register OK
sram cnt 0x0, id = 43
Interrupt 43 register OK
Interrupt 36 register OK
Interrupt 57 register OK
sram cnt 0x0, id = 42
Interrupt 42 register OK
Interrupt 37 register OK
[R
IPU0log=tsensor: 5, mask: ffffffda
tsensor type: 6, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 6, mask: ffffff80
tsensor type: 7, ppuFormatK: 0x437a,
IPU1log=KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=egisterInterruptSource]:[39] end
IPMB initialization Start...
IPMB clock set done, prer = 0x18.
IPMB Rx FIFO clear empty.
IPMB initialization Done.
starting DFX Collect Task end
PowerTask Entry ...
Wait all vrd init done .
IPU0log= ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 7, mask: fffffffe
opposite dieId: 1, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
CPM max V[900]-
IPU1log= Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low
HSM0log=
IMU0log=..
All vrd init done, power task start
refresh domainId 0 Lsb 0x0
refresh domainId 9 Lsb 0x1
refresh domainId 2 Lsb 0x0
refresh domainId 7 Lsb 0x1
refresh domainId 4 Lsb 0x0
refresh domainId 1 Lsb 0x1
power sensor[0] | calib:512
IPU0log=F:2800
CPM min V[750]-F:1600
freq:2350, idx:9
cpm trim freq: 2600, idx: 4
cpm trim finish
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
recount hours 
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Fr
HSM0log=
IMU0log=0 | rshunt:1 | rshuntDiv:1000 | currLsb:1 | currLsbDiv:1000 | enableFlag:1
                | pwrLsb:25 | defPwr:25000 | minPwr:10000 | maxPwr:65000 | pwrFix:3400
                | manufacturerId: 0x5549 | dieId: 0x2260
power sen
IPU0log=0xb40 
hiboost task entry
boost wait SEF.
boost param OK.
Totem[0] Core[ 0] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[26
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=sor[0] init success
ScmiTaskEntry start.
[RegisterInterruptSource]:[21] begin
Interrupt 51 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 52 register OK
[RegisterInterruptSource]
IPU0log=00000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[12000
IPU1log= Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 53 register OK
[RegisterInterruptSource]:[39] end
[0.01.28.816]starting ras Init
RAS Setup Value get done!
INT_NUM_PER_SKT * HiGetSktNum() = 0x8
index = 0x0
RasIntRegis
IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Lim
IPU1log=KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=ter init 160 
index = 0x1
RasIntRegister init 172 
index = 0x2
RasIntRegister init 162 
index = 0x3
RasIntRegister init 174 
index = 0x4
RasIntRegister init 184 
index = 0x5
RasIntRegister init 196 
index = 0x6
RasIntRegister in
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IMU0log=1T1N1U skt:0 CfgBusDfxPreConfig finish

********Hello Huawei LiteOS********

IMU Firmware Version : B173V01
LiteOS Kernel Version : 5.10.0
Run on Socket[0] Die[3]
Chip Version: 1
Max socket num: 2
*******************************
IPU0log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 0
cls: 6, core: 7
cpu 933 sram 1010 ddr 983
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  750|  802|  885|  933|
max  v
IPU1log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 1
cls: 6, core: 7
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  759|  821|  909|  961|
max  v: |  750|  750|  753|  781
HSM0log=[1970-01-01 00:01:12.459][HSM][INFO][30] init start
[1970-01-01 00:01:12.459][HSM][INFO][38] init over
[00:01:12.469][info] succeed to do thirdparty dfx_pabuk init
[00:01:12.475][info] os_mem_system_init default pool done
[0
IMU0log=***
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | rail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_vo
IPU0log=: |  750|  750|  754|  775|  836|  922|  980|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:7
IPU1log=|  846|  938|  994|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:750 F:1950
avs-uncore V:750
HSM0log=0:01:12.481][info] addr is already in region
[00:01:12.484][info] succeed to do thirdparty otpc_pabuk init
[1970-01-01 00:01:12.489][HSM][INFO][31] select_region: 0xc11cb55b
[1970-01-01 00:01:12.495][HSM][INFO][67] spi_nor de
IMU0log=lt:1122 mV | pmu:MP2882
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_v
IPU0log=50 F:1950
avs-uncore V:750 F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
av
IPU1log= F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
avs-uncore V:840 F:2450
avs-
HSM0log=vice_id 0xff1a67c8
[1970-01-01 00:01:12.501][HSM][INFO][50] std_cmd readback 0x30220d8
[1970-01-01 00:01:12.507][HSM][INFO][72] saf_cmd 0x0 readback 0x9f5a0604
[1970-01-01 00:01:12.514][HSM][INFO][72] saf_cmd 0x1 readback 0x5
IMU0log=olt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_
IPU0log=s-uncore V:840 F:2450
avs-uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain
IPU1log=uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | r
HSM0log=b7e938
[1970-01-01 00:01:12.520][HSM][INFO][72] saf_cmd 0x2 readback 0x1
[1970-01-01 00:01:12.526][HSM][INFO][72] saf_cmd 0x3 readback 0x0
[1970-01-01 00:01:12.532][HSM][INFO][72] saf_cmd 0x4 readback 0x0
[00:01:12.538][info
IMU0log=volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus r
IPU0log=[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | p
IPU1log=ail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_volt:1122 mV | pmu:MP2882
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[0] volt =  908 mV
pwr domain
HSM0log=] succeed to do thirdparty boot_profile_driver init
[00:01:12.544][info] succeed to do thirdparty crypto_driver init
[00:01:12.549][info] succeed to do thirdparty period_driver init
[00:01:12.555][info]  start loading interna
IMU0log=eady.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait th
IPU0log=mu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pmbus:0x480c0000 ver:0x110
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
IPU1log=[9] volt = 1103 mV
=end=
w&h rd rail:0, 906
w&h rd rail:1, 1103
pwr domain[0] set volt  904 mV succ
pwr domain[9] set volt 1105 mV succ
volt post
pwr domain[0] volt =  904 mV
pwr domain[9] volt = 1103 mV
==end==
Totem[0] Core Bo
HSM0log=l task ...
[00:01:12.560][info]  task name is ccm_task
[00:01:12.564][info]  hm_dynamic_loadelf successfully!
[00:01:12.569][info] internal task[1] task_name=ccm_task load successfully
[00:01:12.575][info]  task name is upgr
IMU0log=e cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master I
IPU0log=
avsbus resync succ
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[2] volt =  904 mV
pwr domain[7] volt =  804 mV
pwr domain[4] volt =  806 mV
pwr domain[1] volt =  804 mV
=end=
w&h rd rail:
IPU1log=ot Vol [1029]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2,
HSM0log=ade_task
[00:01:12.579][info]  hm_dynamic_loadelf successfully!
[00:01:12.584][info] internal task[2] task_name=upgrade_task load successfully
[00:01:12.591][info] created task ccm_task success!
[00:01:12.596][info] created 
IMU0log=mu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
cpu 0 entering scheduler
|--------------------------------------------------|
AtsPrint
|idx|lockCount| srcAddr| destAddr| addrLen|
|--
IPU0log=0, 904
w&h rd rail:1, 804
pwr domain[2] set volt  902 mV succ
pwr domain[7] set volt  802 mV succ
w&h rd rail:0, 806
w&h rd rail:1, 804
pwr domain[4] set volt  804 mV succ
pwr domain[1] set volt  802 mV succ
volt post
pwr domain
IPU1log= ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd8
HSM0log=task upgrade_task success!
[1970-01-01 00:01:12.601][HSM][INFO][54] Platform init 0x20250523 0x4e.
[1970-01-01 00:01:12.607][HSM][INFO][197] ccm start.
[1970-01-01 00:01:12.612][HSM][INFO][86] upgrade task init success.
[197
IMU0log=------------------------------------------------|
|  0|00000000|0x010500000|0x000110800000|0x00100000|
|  1|00000000|0x020000000|0x00001d000000|0x00800000|
|  2|00000000|0x020800000|0x000490000000|0x00100000|
|  3|00000000|0x020
IPU0log=[2] volt =  904 mV
pwr domain[7] volt =  800 mV
pwr domain[4] volt =  804 mV
pwr domain[1] volt =  804 mV
==end==
Totem[0] Core Boot Vol [1015]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0,
IPU1log=00, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
opposite dieId: 0, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 
HSM0log=0-01-01 00:01:12.618][HSM][INFO][95] upgrade recv cmd, 0x181.
[1970-01-01 00:01:12.624][HSM][INFO][103] upgrade res, 0x3a5aa5a3.
.
IMU0log=900000|0x000004000000|0x08000000|
|  4|00000000|0x028900000|0x000440580000|0x01000000|
|  5|00000000|0x029900000|0x000590000000|0x00100000|
|  6|00000000|0x029a00000|0x002000150000|0x00100000|
|  7|00000000|0x000000000|0x0000000
IPU0log= MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 
IPU1log=enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
hiboost task entry
boost wait SEF.
[INFO] mem used of task 'app_Task' is:0x2028, not zero when task being deleted
boost param OK.
Totem[0] Core[ 0] Freq Limit Low
IMU0log=1T1N1U skt:0 CfgBusDfxPreConfig finish

********Hello Huawei LiteOS********

IMU Firmware Version : B173V01
LiteOS Kernel Version : 5.10.0
Run on Socket[0] Die[3]
Chip Version: 1
Max socket num: 2
*******************************
IPU0log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 0
cls: 6, core: 7
cpu 933 sram 1010 ddr 983
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  750|  802|  885|  933|
max  v
IPU1log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 1
cls: 6, core: 7
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  759|  821|  909|  961|
max  v: |  750|  750|  753|  781
HSM0log=[1970-01-01 00:01:00.974][HSM][INFO][30] init start
[1970-01-01 00:01:00.974][HSM][INFO][38] init over
[00:01:00.984][info] succeed to do thirdparty dfx_pabuk init
[00:01:00.990][info] os_mem_system_init default pool done
[0
IMU0log=***
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | rail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_vo
IPU0log=: |  750|  750|  754|  775|  836|  922|  980|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:7
IPU1log=|  846|  938|  994|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:750 F:1950
avs-uncore V:750
HSM0log=0:01:00.996][info] addr is already in region
[00:01:00.999][info] succeed to do thirdparty otpc_pabuk init
[1970-01-01 00:01:01.004][HSM][INFO][31] select_region: 0xc11cb55b
[1970-01-01 00:01:01.010][HSM][INFO][67] spi_nor de
IMU0log=lt:1122 mV | pmu:MP2882
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_v
IPU0log=50 F:1950
avs-uncore V:750 F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
av
IPU1log= F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
avs-uncore V:840 F:2450
avs-
HSM0log=vice_id 0xff1a67c8
[1970-01-01 00:01:01.016][HSM][INFO][50] std_cmd readback 0x30220d8
[1970-01-01 00:01:01.022][HSM][INFO][72] saf_cmd 0x0 readback 0x9f5a0604
[1970-01-01 00:01:01.029][HSM][INFO][72] saf_cmd 0x1 readback 0x5
IMU0log=olt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_
IPU0log=s-uncore V:840 F:2450
avs-uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain
IPU1log=uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | r
HSM0log=b7e938
[1970-01-01 00:01:01.035][HSM][INFO][72] saf_cmd 0x2 readback 0x1
[1970-01-01 00:01:01.041][HSM][INFO][72] saf_cmd 0x3 readback 0x0
[1970-01-01 00:01:01.047][HSM][INFO][72] saf_cmd 0x4 readback 0x0
[00:01:01.053][info
IMU0log=volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus r
IPU0log=[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | p
IPU1log=ail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_volt:1122 mV | pmu:MP2882
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[0] volt = 1035 mV
pwr domain
HSM0log=] succeed to do thirdparty boot_profile_driver init
[00:01:01.059][info] succeed to do thirdparty crypto_driver init
[00:01:01.065][info] succeed to do thirdparty period_driver init
[00:01:01.070][info]  start loading interna
IMU0log=eady.
1T1N1U skt:0 CfgBusDfxPreConfig finish

********Hello Huawei LiteOS********

IMU Firmware Version : B173V01
LiteOS Kernel Version : 5.10.0
Run on Socket[0] Die[3]
Chip Version: 1
Max socket num: 2
*************************
IPU0log=mu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pmbus:0x480c0000 ver:0x110
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
IPU1log=[9] volt = 1103 mV
=end=
w&h rd rail:0, 1035
w&h rd rail:1, 1103
pwr domain[0] set volt  906 mV succ
pwr domain[9] set volt 1103 mV succ
volt post
pwr domain[0] volt =  904 mV
pwr domain[9] volt = 1105 mV
==end==
Totem[0] Core B
HSM0log=l task ...
[00:01:01.075][info]  task name is ccm_task
[00:01:01.079][info]  hm_dynamic_loadelf successfully!
[00:01:01.084][info] internal task[1] task_name=ccm_task load successfully
[00:01:01.090][info]  task name is upgr
IMU0log=*********
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | rail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | 
IPU0log=
avsbus resync succ
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[2] volt = 1019 mV
pwr domain[7] volt =  802 mV
pwr domain[4] volt =  804 mV
pwr domain[1] volt =  802 mV
=end=
w&h rd rail:
IPU1log=oot Vol [1029]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2
HSM0log=ade_task
[00:01:01.095][info]  hm_dynamic_loadelf successfully!
[00:01:01.100][info] internal task[2] task_name=upgrade_task load successfully
[00:01:01.107][info] created task ccm_task success!
[00:01:01.111][info] created 
IMU0log=max_volt:1122 mV | pmu:MP2882
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV |
IPU0log=0, 1019
w&h rd rail:1, 802
pwr domain[2] set volt  902 mV succ
pwr domain[7] set volt  802 mV succ
w&h rd rail:0, 804
w&h rd rail:1, 802
pwr domain[4] set volt  804 mV succ
pwr domain[1] set volt  802 mV succ
volt post
pwr domai
IPU1log=, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd
HSM0log=task upgrade_task success!
[1970-01-01 00:01:01.116][HSM][INFO][54] Platform init 0x20250523 0x4e.
[1970-01-01 00:01:01.122][HSM][INFO][197] ccm start.
[1970-01-01 00:01:01.127][HSM][INFO][86] upgrade task init success.
[197
IMU0log= min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 
IPU0log=n[2] volt =  902 mV
pwr domain[7] volt =  800 mV
pwr domain[4] volt =  804 mV
pwr domain[1] volt =  802 mV
==end==
Totem[0] Core Boot Vol [1015]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0
IPU1log=800, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
opposite dieId: 0, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89
HSM0log=0-01-01 00:01:01.133][HSM][INFO][95] upgrade recv cmd, 0x181.
[1970-01-01 00:01:01.139][HSM][INFO][103] upgrade res, 0x3a5aa5a3.
.
IMU0log=| def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cf
IPU0log=, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor:
IPU1log= enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
hiboost task entry
boost wait SEF.
[INFO] mem used of task 'app_Task' is:0x2028, not zero when task being deleted
boost param OK.
Totem[0] Core[ 0] Freq Limit Lo
HSM0log=
IMU0log=gbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
cpu 0 entering scheduler
|--------------------------------------------------|
AtsPrint
|idx|lockCount| srcAddr| destAddr| addrLen|
|----------------
IPU0log= 0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
tsensor typ
IPU1log=w[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] F
HSM0log=
IMU0log=----------------------------------|
|  0|00000000|0x010500000|0x000110800000|0x00100000|
|  1|00000000|0x020000000|0x00001d000000|0x00800000|
|  2|00000000|0x020800000|0x000490000000|0x00100000|
|  3|00000000|0x020900000|0x00000
IPU0log=e: 3, ppuFormatK: 0x4da6, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b4,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 3, mask: fffffff8
tsensor type: 4, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB:
IPU1log=req Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0
HSM0log=
IMU0log=4000000|0x08000000|
|  4|00000000|0x028900000|0x000440580000|0x01000000|
|  5|00000000|0x029900000|0x000590000000|0x00100000|
|  6|00000000|0x029a00000|0x002000150000|0x00100000|
|  7|00000000|0x000000000|0x000000000000|0x000000
IPU0log= 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 4, mask: ffffffee
tsensor type: 5, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
IPU1log=] Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000
HSM0log=
IMU0log=00|
|  8|00000000|0x040000000|0x000000000000|0x08000000|
|  9|00000000|0x048000000|0x000000000000|0x08000000|
| 10|00000000|0x050000000|0x000000000000|0x08000000|
| 11|00000000|0x058000000|0x000000000000|0x08000000|
| 12|0000000
IPU0log=
tsensor: 5, mask: ffffffda
tsensor type: 6, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 6, mask: ffffff80
tsensor type: 7, ppuFormatK: 0x437a
IPU1log=]KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KH
HSM0log=
IMU0log=0|0x060000000|0x000000000000|0x08000000|
| 13|00000000|0x068000000|0x000000000000|0x08000000|
| 14|00000000|0x070000000|0x000000000000|0x08000000|
| 15|00000000|0x078000000|0x000490000000|0x08000000|
|---------------------------
IPU0log=, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 7, mask: fffffffe
opposite dieId: 1, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
CPM max V[900]
IPU1log=Z Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Lo
HSM0log=
IMU0log=-----------------------|
=~=~=~=~=~=~=~=~=~=~= IMU Log @ 2026.6.1 8:9:13 =~=~=~=~=~=~=~=~=~=~=
[IMU] Watchdog Initialization done!
[RegisterInterruptSource]:[21] begin
Interrupt 32 register OK
Interrupt 34 register OK
Interrup
IPU0log=-F:2800
CPM min V[750]-F:1600
freq:2350, idx:9
cpm trim freq: 2600, idx: 4
cpm trim finish
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
recount hours
IPU1log=w[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] F
HSM0log=
IMU0log=t 40 register OK
Interrupt 44 register OK
sram cnt 0x0, id = 43
Interrupt 43 register OK
Interrupt 36 register OK
Interrupt 57 register OK
sram cnt 0x0, id = 42
Interrupt 42 register OK
Interrupt 37 register OK
[RegisterInterrup
IPU0log= 0xb40 
hiboost task entry
boost wait SEF.
boost param OK.
Totem[0] Core[ 0] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[2
IPU1log=req Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0
HSM0log=
IMU0log=tSource]:[39] end
IPMB initialization Start...
IPMB clock set done, prer = 0x18.
IPMB Rx FIFO clear empty.
IPMB initialization Done.
starting DFX Collect Task end
PowerTask Entry ...
Wait all vrd init done ...
All vrd init
IPU0log=600000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[1200
IPU1log=] Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000
HSM0log=
IMU0log= done, power task start
refresh domainId 0 Lsb 0x0
refresh domainId 9 Lsb 0x1
refresh domainId 2 Lsb 0x0
refresh domainId 7 Lsb 0x1
refresh domainId 4 Lsb 0x0
refresh domainId 1 Lsb 0x1
power sensor[0] | calib:5120 | rshunt:1 | 
IPU0log=000]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Li
IPU1log=]KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KH
HSM0log=
IMU0log=rshuntDiv:1000 | currLsb:1 | currLsbDiv:1000 | enableFlag:1
                | pwrLsb:25 | defPwr:25000 | minPwr:10000 | maxPwr:65000 | pwrFix:3400
                | manufacturerId: 0x5549 | dieId: 0x2260
power sensor[0] init suc
IPU0log=mit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core
IPU1log=Z Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Lo
IMU0log=1T1N1U skt:0 CfgBusDfxPreConfig finish

********Hello Huawei LiteOS********

IMU Firmware Version : B173V01
LiteOS Kernel Version : 5.10.0
Run on Socket[0] Die[3]
Chip Version: 1
Max socket num: 2
*******************************
IPU0log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 0
cls: 6, core: 7
cpu 933 sram 1010 ddr 983
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  750|  802|  885|  933|
max  v
IPU1log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 1
cls: 6, core: 7
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  759|  821|  909|  961|
max  v: |  750|  750|  753|  781
HSM0log=[1970-01-01 00:01:11.706][HSM][INFO][30] init start
[1970-01-01 00:01:11.706][HSM][INFO][38] init over
[00:01:11.716][info] succeed to do thirdparty dfx_pabuk init
[00:01:11.721][info] os_mem_system_init default pool done
[0
IMU0log=***
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | rail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_vo
IPU0log=: |  750|  750|  754|  775|  836|  922|  980|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:7
IPU1log=|  846|  938|  994|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:750 F:1950
avs-uncore V:750
HSM0log=0:01:11.728][info] addr is already in region
[00:01:11.730][info] succeed to do thirdparty otpc_pabuk init
[1970-01-01 00:01:11.736][HSM][INFO][31] select_region: 0xc11cb55b
[1970-01-01 00:01:11.742][HSM][INFO][67] spi_nor de
IMU0log=lt:1122 mV | pmu:MP2882
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_v
IPU0log=50 F:1950
avs-uncore V:750 F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
av
IPU1log= F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
avs-uncore V:840 F:2450
avs-
HSM0log=vice_id 0xff1a67c8
[1970-01-01 00:01:11.748][HSM][INFO][50] std_cmd readback 0x30220d8
[1970-01-01 00:01:11.754][HSM][INFO][72] saf_cmd 0x0 readback 0x9f5a0604
[1970-01-01 00:01:11.760][HSM][INFO][72] saf_cmd 0x1 readback 0x5
IMU0log=olt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_
IPU0log=s-uncore V:840 F:2450
avs-uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain
IPU1log=uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | r
HSM0log=b7e938
[1970-01-01 00:01:11.767][HSM][INFO][72] saf_cmd 0x2 readback 0x1
[1970-01-01 00:01:11.772][HSM][INFO][72] saf_cmd 0x3 readback 0x0
[1970-01-01 00:01:11.778][HSM][INFO][72] saf_cmd 0x4 readback 0x0
[00:01:11.785][info
IMU0log=volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus r
IPU0log=[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | p
IPU1log=ail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_volt:1122 mV | pmu:MP2882
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[0] volt =  906 mV
pwr domain
HSM0log=] succeed to do thirdparty boot_profile_driver init
[00:01:11.790][info] succeed to do thirdparty crypto_driver init
[00:01:11.796][info] succeed to do thirdparty period_driver init
[00:01:11.802][info]  start loading interna
IMU0log=eady.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait th
IPU0log=mu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pmbus:0x480c0000 ver:0x110
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
IPU1log=[9] volt = 1105 mV
=end=
w&h rd rail:0, 906
w&h rd rail:1, 1103
pwr domain[0] set volt  904 mV succ
pwr domain[9] set volt 1103 mV succ
volt post
pwr domain[0] volt =  904 mV
pwr domain[9] volt = 1103 mV
==end==
Totem[0] Core Bo
HSM0log=l task ...
[00:01:11.807][info]  task name is ccm_task
[00:01:11.810][info]  hm_dynamic_loadelf successfully!
[00:01:11.815][info] internal task[1] task_name=ccm_task load successfully
[00:01:11.822][info]  task name is upgr
IMU0log=e cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master I
IPU0log=
avsbus resync succ
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[2] volt =  904 mV
pwr domain[7] volt =  804 mV
pwr domain[4] volt =  806 mV
pwr domain[1] volt =  804 mV
=end=
w&h rd rail:
IPU1log=ot Vol [1029]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2,
HSM0log=ade_task
[00:01:11.826][info]  hm_dynamic_loadelf successfully!
[00:01:11.831][info] internal task[2] task_name=upgrade_task load successfully
[00:01:11.838][info] created task ccm_task success!
[00:01:11.843][info] created 
IMU0log=mu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
cpu 0 entering scheduler
|--------------------------------------------------|
AtsPrint
|idx|lockCount| srcAddr| destAddr| addrLen|
|--
IPU0log=0, 904
w&h rd rail:1, 804
pwr domain[2] set volt  904 mV succ
pwr domain[7] set volt  802 mV succ
w&h rd rail:0, 806
w&h rd rail:1, 804
pwr domain[4] set volt  804 mV succ
pwr domain[1] set volt  802 mV succ
volt post
pwr domain
IPU1log= ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd8
HSM0log=task upgrade_task success!
[1970-01-01 00:01:11.848][HSM][INFO][54] Platform init 0x20250523 0x4e.
[1970-01-01 00:01:11.854][HSM][INFO][197] ccm start.
[1970-01-01 00:01:11.859][HSM][INFO][86] upgrade task init success.
[197
IMU0log=------------------------------------------------|
|  0|00000000|0x010500000|0x000110800000|0x00100000|
|  1|00000000|0x020000000|0x00001d000000|0x00800000|
|  2|00000000|0x020800000|0x000490000000|0x00100000|
|  3|00000000|0x020
IPU0log=[2] volt =  902 mV
pwr domain[7] volt =  800 mV
pwr domain[4] volt =  802 mV
pwr domain[1] volt =  802 mV
==end==
Totem[0] Core Boot Vol [1015]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0,
IPU1log=00, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
opposite dieId: 0, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 
HSM0log=0-01-01 00:01:11.864][HSM][INFO][95] upgrade recv cmd, 0x181.
[1970-01-01 00:01:11.870][HSM][INFO][103] upgrade res, 0x3a5aa5a3.
.
IMU0log=900000|0x000004000000|0x08000000|
|  4|00000000|0x028900000|0x000440580000|0x01000000|
|  5|00000000|0x029900000|0x000590000000|0x00100000|
|  6|00000000|0x029a00000|0x002000150000|0x00100000|
|  7|00000000|0x000000000|0x0000000
IPU0log= MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 
IPU1log=enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
hiboost task entry
boost wait SEF.
[INFO] mem used of task 'app_Task' is:0x2028, not zero when task being deleted
boost param OK.
Totem[0] Core[ 0] Freq Limit Low
HSM0log=
IMU0log=00000|0x00000000|
|  8|00000000|0x040000000|0x000000000000|0x08000000|
|  9|00000000|0x048000000|0x000000000000|0x08000000|
| 10|00000000|0x050000000|0x000000000000|0x08000000|
| 11|00000000|0x058000000|0x000000000000|0x08000000
IPU0log=0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
tsensor type
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Fr
HSM0log=
IMU0log=|
| 12|00000000|0x060000000|0x000000000000|0x08000000|
| 13|00000000|0x068000000|0x000000000000|0x08000000|
| 14|00000000|0x070000000|0x000000000000|0x08000000|
| 15|00000000|0x078000000|0x000490000000|0x08000000|
|-------------
IPU0log=: 3, ppuFormatK: 0x4da6, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b4,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 3, mask: fffffff8
tsensor type: 4, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=-------------------------------------|
=~=~=~=~=~=~=~=~=~=~= IMU Log @ 2026.6.1 8:16:13 =~=~=~=~=~=~=~=~=~=~=
[IMU] Watchdog Initialization done!
[RegisterInterruptSource]:[21] begin
Interrupt 32 register OK
Interrupt 34 regis
IPU0log=0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 4, mask: ffffffee
tsensor type: 5, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1

IPU1log= Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=ter OK
Interrupt 40 register OK
Interrupt 44 register OK
sram cnt 0x0, id = 43
Interrupt 43 register OK
Interrupt 36 register OK
Interrupt 57 register OK
sram cnt 0x0, id = 42
Interrupt 42 register OK
Interrupt 37 register OK
[R
IPU0log=tsensor: 5, mask: ffffffda
tsensor type: 6, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 6, mask: ffffff80
tsensor type: 7, ppuFormatK: 0x437a,
IPU1log=KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=egisterInterruptSource]:[39] end
IPMB initialization Start...
IPMB clock set done, prer = 0x18.
IPMB Rx FIFO clear empty.
IPMB initialization Done.
starting DFX Collect Task end
PowerTask Entry ...
Wait all vrd init done .
IPU0log= ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 7, mask: fffffffe
opposite dieId: 1, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
CPM max V[900]-
IPU1log= Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low
HSM0log=
IMU0log=..
All vrd init done, power task start
refresh domainId 0 Lsb 0x0
refresh domainId 9 Lsb 0x1
refresh domainId 2 Lsb 0x0
refresh domainId 7 Lsb 0x1
refresh domainId 4 Lsb 0x0
refresh domainId 1 Lsb 0x1
power sensor[0] | calib:512
IPU0log=F:2800
CPM min V[750]-F:1600
freq:2350, idx:9
cpm trim freq: 2600, idx: 4
cpm trim finish
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
recount hours 
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Fr
HSM0log=
IMU0log=0 | rshunt:1 | rshuntDiv:1000 | currLsb:1 | currLsbDiv:1000 | enableFlag:1
                | pwrLsb:25 | defPwr:25000 | minPwr:10000 | maxPwr:65000 | pwrFix:3400
                | manufacturerId: 0x5549 | dieId: 0x2260
power sen
IPU0log=0xb40 
hiboost task entry
boost wait SEF.
boost param OK.
Totem[0] Core[ 0] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[26
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=sor[0] init success
ScmiTaskEntry start.
[RegisterInterruptSource]:[21] begin
Interrupt 51 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 52 register OK
[RegisterInterruptSource]
IPU0log=00000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[12000
IPU1log= Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 53 register OK
[RegisterInterruptSource]:[39] end
[0.01.28.399]starting ras Init
RAS Setup Value get done!
INT_NUM_PER_SKT * HiGetSktNum() = 0x8
index = 0x0
RasIntRegis
IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Lim
IPU1log=KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=ter init 160 
index = 0x1
RasIntRegister init 172 
index = 0x2
RasIntRegister init 162 
index = 0x3
RasIntRegister init 174 
index = 0x4
RasIntRegister init 184 
index = 0x5
RasIntRegister init 196 
index = 0x6
RasIntRegister in
IMU0log=1T1N1U skt:0 CfgBusDfxPreConfig finish

********Hello Huawei LiteOS********

IMU Firmware Version : B173V01
LiteOS Kernel Version : 5.10.0
Run on Socket[0] Die[3]
Chip Version: 1
Max socket num: 2
*******************************
IPU0log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 0
cls: 6, core: 7
cpu 933 sram 1010 ddr 983
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  750|  802|  885|  933|
max  v
IPU1log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 1
cls: 6, core: 7
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  759|  821|  909|  961|
max  v: |  750|  750|  753|  781
HSM0log=[1970-01-01 00:01:11.347][HSM][INFO][30] init start
[1970-01-01 00:01:11.347][HSM][INFO][38] init over
[00:01:11.357][info] succeed to do thirdparty dfx_pabuk init
[00:01:11.362][info] os_mem_system_init default pool done
[0
IMU0log=***
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | rail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_vo
IPU0log=: |  750|  750|  754|  775|  836|  922|  980|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:7
IPU1log=|  846|  938|  994|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:750 F:1950
avs-uncore V:750
HSM0log=0:01:11.369][info] addr is already in region
[00:01:11.371][info] succeed to do thirdparty otpc_pabuk init
[1970-01-01 00:01:11.377][HSM][INFO][31] select_region: 0xc11cb55b
[1970-01-01 00:01:11.383][HSM][INFO][67] spi_nor de
IMU0log=lt:1122 mV | pmu:MP2882
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_v
IPU0log=50 F:1950
avs-uncore V:750 F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
av
IPU1log= F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
avs-uncore V:840 F:2450
avs-
HSM0log=vice_id 0xff1a67c8
[1970-01-01 00:01:11.389][HSM][INFO][50] std_cmd readback 0x30220d8
[1970-01-01 00:01:11.395][HSM][INFO][72] saf_cmd 0x0 readback 0x9f5a0604
[1970-01-01 00:01:11.401][HSM][INFO][72] saf_cmd 0x1 readback 0x5
IMU0log=olt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_
IPU0log=s-uncore V:840 F:2450
avs-uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain
IPU1log=uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | r
HSM0log=b7e938
[1970-01-01 00:01:11.408][HSM][INFO][72] saf_cmd 0x2 readback 0x1
[1970-01-01 00:01:11.413][HSM][INFO][72] saf_cmd 0x3 readback 0x0
[1970-01-01 00:01:11.419][HSM][INFO][72] saf_cmd 0x4 readback 0x0
[00:01:11.426][info
IMU0log=volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus r
IPU0log=[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | p
IPU1log=ail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_volt:1122 mV | pmu:MP2882
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[0] volt =  906 mV
pwr domain
HSM0log=] succeed to do thirdparty boot_profile_driver init
[00:01:11.431][info] succeed to do thirdparty crypto_driver init
[00:01:11.437][info] succeed to do thirdparty period_driver init
[00:01:11.443][info]  start loading interna
IMU0log=eady.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait th
IPU0log=mu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pmbus:0x480c0000 ver:0x110
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
IPU1log=[9] volt = 1103 mV
=end=
w&h rd rail:0, 908
w&h rd rail:1, 1105
pwr domain[0] set volt  906 mV succ
pwr domain[9] set volt 1103 mV succ
volt post
pwr domain[0] volt =  904 mV
pwr domain[9] volt = 1103 mV
==end==
Totem[0] Core Bo
HSM0log=l task ...
[00:01:11.448][info]  task name is ccm_task
[00:01:11.452][info]  hm_dynamic_loadelf successfully!
[00:01:11.456][info] internal task[1] task_name=ccm_task load successfully
[00:01:11.463][info]  task name is upgr
IMU0log=e cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master I
IPU0log=
avsbus resync succ
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[2] volt =  904 mV
pwr domain[7] volt =  804 mV
pwr domain[4] volt =  806 mV
pwr domain[1] volt =  804 mV
=end=
w&h rd rail:
IPU1log=ot Vol [1029]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2,
HSM0log=ade_task
[00:01:11.467][info]  hm_dynamic_loadelf successfully!
[00:01:11.472][info] internal task[2] task_name=upgrade_task load successfully
[00:01:11.479][info] created task ccm_task success!
[00:01:11.484][info] created 
IMU0log=mu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
cpu 0 entering scheduler
|--------------------------------------------------|
AtsPrint
|idx|lockCount| srcAddr| destAddr| addrLen|
|--
IPU0log=0, 906
w&h rd rail:1, 804
pwr domain[2] set volt  902 mV succ
pwr domain[7] set volt  802 mV succ
w&h rd rail:0, 806
w&h rd rail:1, 804
pwr domain[4] set volt  804 mV succ
pwr domain[1] set volt  804 mV succ
volt post
pwr domain
IPU1log= ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd8
HSM0log=task upgrade_task success!
[1970-01-01 00:01:11.489][HSM][INFO][54] Platform init 0x20250523 0x4e.
[1970-01-01 00:01:11.495][HSM][INFO][197] ccm start.
[1970-01-01 00:01:11.500][HSM][INFO][86] upgrade task init success.
[197
IMU0log=------------------------------------------------|
|  0|00000000|0x010500000|0x000110800000|0x00100000|
|  1|00000000|0x020000000|0x00001d000000|0x00800000|
|  2|00000000|0x020800000|0x000490000000|0x00100000|
|  3|00000000|0x020
IPU0log=[2] volt =  902 mV
pwr domain[7] volt =  800 mV
pwr domain[4] volt =  804 mV
pwr domain[1] volt =  802 mV
==end==
Totem[0] Core Boot Vol [1015]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0,
IPU1log=00, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
opposite dieId: 0, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 
HSM0log=0-01-01 00:01:11.506][HSM][INFO][95] upgrade recv cmd, 0x181.
[1970-01-01 00:01:11.511][HSM][INFO][103] upgrade res, 0x3a5aa5a3.
.
IMU0log=900000|0x000004000000|0x08000000|
|  4|00000000|0x028900000|0x000440580000|0x01000000|
|  5|00000000|0x029900000|0x000590000000|0x00100000|
|  6|00000000|0x029a00000|0x002000150000|0x00100000|
|  7|00000000|0x000000000|0x0000000
IPU0log= MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 
IPU1log=enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
hiboost task entry
boost wait SEF.
[INFO] mem used of task 'app_Task' is:0x2028, not zero when task being deleted
boost param OK.
Totem[0] Core[ 0] Freq Limit Low
HSM0log=
IMU0log=00000|0x00000000|
|  8|00000000|0x040000000|0x000000000000|0x08000000|
|  9|00000000|0x048000000|0x000000000000|0x08000000|
| 10|00000000|0x050000000|0x000000000000|0x08000000|
| 11|00000000|0x058000000|0x000000000000|0x08000000
IPU0log=0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
tsensor type
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Fr
HSM0log=
IMU0log=|
| 12|00000000|0x060000000|0x000000000000|0x08000000|
| 13|00000000|0x068000000|0x000000000000|0x08000000|
| 14|00000000|0x070000000|0x000000000000|0x08000000|
| 15|00000000|0x078000000|0x000490000000|0x08000000|
|-------------
IPU0log=: 3, ppuFormatK: 0x4da6, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b4,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 3, mask: fffffff8
tsensor type: 4, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=-------------------------------------|
=~=~=~=~=~=~=~=~=~=~= IMU Log @ 2026.6.1 8:26:26 =~=~=~=~=~=~=~=~=~=~=
[IMU] Watchdog Initialization done!
[RegisterInterruptSource]:[21] begin
Interrupt 32 register OK
Interrupt 34 regis
IPU0log=0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 4, mask: ffffffee
tsensor type: 5, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1

IPU1log= Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=ter OK
Interrupt 40 register OK
Interrupt 44 register OK
sram cnt 0x0, id = 43
Interrupt 43 register OK
Interrupt 36 register OK
Interrupt 57 register OK
sram cnt 0x0, id = 42
Interrupt 42 register OK
Interrupt 37 register OK
[R
IPU0log=tsensor: 5, mask: ffffffda
tsensor type: 6, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 6, mask: ffffff80
tsensor type: 7, ppuFormatK: 0x437a,
IPU1log=KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=egisterInterruptSource]:[39] end
IPMB initialization Start...
IPMB clock set done, prer = 0x18.
IPMB Rx FIFO clear empty.
IPMB initialization Done.
starting DFX Collect Task end
PowerTask Entry ...
Wait all vrd init done .
IPU0log= ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 7, mask: fffffffe
opposite dieId: 1, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
CPM max V[900]-
IPU1log= Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low
HSM0log=
IMU0log=..
All vrd init done, power task start
refresh domainId 0 Lsb 0x0
refresh domainId 9 Lsb 0x1
refresh domainId 2 Lsb 0x0
refresh domainId 7 Lsb 0x1
refresh domainId 4 Lsb 0x0
refresh domainId 1 Lsb 0x1
power sensor[0] | calib:512
IPU0log=F:2800
CPM min V[750]-F:1600
freq:2350, idx:9
cpm trim freq: 2600, idx: 4
cpm trim finish
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
recount hours 
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Fr
HSM0log=
IMU0log=0 | rshunt:1 | rshuntDiv:1000 | currLsb:1 | currLsbDiv:1000 | enableFlag:1
                | pwrLsb:25 | defPwr:25000 | minPwr:10000 | maxPwr:65000 | pwrFix:3400
                | manufacturerId: 0x5549 | dieId: 0x2260
power sen
IPU0log=0xb40 
hiboost task entry
boost wait SEF.
boost param OK.
Totem[0] Core[ 0] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[26
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=sor[0] init success
ScmiTaskEntry start.
[RegisterInterruptSource]:[21] begin
Interrupt 51 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 52 register OK
[RegisterInterruptSource]
IPU0log=00000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[12000
IPU1log= Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 53 register OK
[RegisterInterruptSource]:[39] end
[0.01.28.041]starting ras Init
RAS Setup Value get done!
INT_NUM_PER_SKT * HiGetSktNum() = 0x8
index = 0x0
RasIntRegis
IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Lim
IPU1log=KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=ter init 160 
index = 0x1
RasIntRegister init 172 
index = 0x2
RasIntRegister init 162 
index = 0x3
RasIntRegister init 174 
index = 0x4
RasIntRegister init 184 
index = 0x5
RasIntRegister init 196 
index = 0x6
RasIntRegister in
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IPU1log= Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low
HSM0log=
IMU0log=it 186 
index = 0x7
RasIntRegister init 198 
RasIntRegister init 161 
RasIntRegister init 173 
RasIntRegister init 185 
RasIntRegister init 197 
RasIntRegister init 284 
RasIntRegister init 314 
MceTableHeadInit start
starting C
IPU0log=14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
To
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
uncore max freq : 23
HSM0log=
IMU0log=e_Storm Contrl and Ras_Data_Update Task end
[0.01.28.123]starting ras end
[IMU][ERR] skt id 0
Ub init task start Entry ...
UbInitTask Entry ...
[RegisterInterruptSource]:[21] begin
Interrupt 167 register OK
[RegisterInterrupt
IPU0log=tem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[26
IPU1log=50 MHz

HSM0log=
IMU0log=Source]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 191 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 171 register OK
[RegisterInterruptSource]:[39] end
[RegisterI
IPU0log=00000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[12000
IPU1log=
HSM0log=
IMU0log=nterruptSource]:[21] begin
Interrupt 183 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 195 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin

IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Lim
IPU1log=
HSM0log=
IMU0log=Interrupt 207 register OK
[RegisterInterruptSource]:[39] end
Init heart-beat-task end
CS0 flash do not support sfdp!
Current flash device ID[0x61a67c8]!
System supported 1 Flash.
flash cs 0 Manufacture 0xc8, DeviceId 0x1a67, Ad
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IPU1log=
HSM0log=
IMU0log=drMode[0-3B,1-4B] 0x1:
    size 0x4000000, pagesize 0x100
    read  cmd 0x13, dummy byte 0x8
    write cmd 0x12, dummy byte 0x0
    erase4k cmd 0x21, erase64k byte 0xdc
sfc init end
firstUnMskExt0Int
ThermalDimmStart Entry ...

IPU0log=33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
To
IPU1log=
HSM0log=
IMU0log=wait ddr init done...
HacLowPowerStart Entry ...
Hello LiteOS...
Init ReportPcieMmioToBmcTaskEntry end
starting Fpc Isolation Task end
pwr cap[0]: 0, 67
pwr cap[1]: f, 27
pwr cap[2]: 1, 3
BMC_COLLECTION: bmc req last log!
[
IPU0log=tem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[26
IPU1log=
HSM0log=
IMU0log=IMU][ERR] [
IPU3log= no log data error!]
[0.01.59.405]DDR init done
[LOG]head = 0x0, tail = 0x1850, logSize = 0x1850
[IMU][ERR] HsmLogInit!
[IMU][ERR] HsmLogInit! TRUE
set apei done!
UbConfigData size is 64
UbConfigData 0 : 0
Ub
IPU0log=00000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
uncore max freq : 2350 MHz

IPU1log=
HSM0log=
IMU0log=ConfigData 1 : 0
UbConfigData 2 : 0
UbConfigData 3 : 1
UbConfigData 4 : 31
UbConfigData 5 : 1
UbConfigData 6 : 0
UbConfigData 7 : 32
UbConfigData 8 : 0
UbConfigData 9 : 1
UbConfigData 10 : 2
UbConfigData 11 : 0
UbConfigData 12 :
IPU0log=
IPU1log=
HSM0log=
IMU0log= 0
UbConfigData 13 : 1
UbConfigData 14 : 0
UbConfigData 15 : 0
UbConfigData 16 : 0
UbConfigData 17 : 0
UbConfigData 18 : 0
UbConfigData 19 : 0
UbConfigData 20 : 0
UbConfigData 21 : 0
UbConfigData 22 : 11
UbConfigData 23 : 0
UbCo
IPU0log=
IPU1log=
HSM0log=
IMU0log=nfigData 24 : 0
UbConfigData 25 : 0
UbConfigData 26 : 0
UbConfigData 27 : 0
UbConfigData 28 : 0
UbConfigData 29 : 0
UbConfigData 30 : 0
UbConfigData 31 : 0
UbConfigData 32 : 0
UbConfigData 33 : 0
UbConfigData 34 : 2
UbConfigData
IPU0log=
IPU1log=
HSM0log=
IMU0log= 35 : 1
UbConfigData 36 : 0
UbConfigData 37 : 0
UbConfigData 38 : 0
UbConfigData 39 : 0
UbConfigData 40 : 0
UbConfigData 41 : 0
UbConfigData 42 : 0
UbConfigData 43 : 0
UbConfigData 44 : 0
UbConfigData 45 : 0
UbConfigData 46 : 0

IPU0log=
IPU1log=
HSM0log=
IMU0log=UbConfigData 47 : 0
UbConfigData 48 : 0
UbConfigData 49 : 0
UbConfigData 50 : 0
UbConfigData 51 : 0
UbConfigData 52 : 0
UbConfigData 53 : 0
UbConfigData 54 : 0
UbConfigData 55 : 0
UbConfigData 56 : 0
UbConfigData 57 : 0
UbConfig
IPU0log=
IPU1log=
HSM0log=
IMU0log=Data 58 : 0
UbConfigData 59 : 0
UbConfigData 60 : 0
UbConfigData 61 : 0
UbConfigData 62 : 0
UbConfigData 63 : 0
UbConfigData 64 : 0
ClusterSwitch: 0, 0
ClusterMode: 0, 0
ControlMode: 0, 0
EnumMode: 1, 1
BodyMask: 31, 31
CcCtxCou
IPU0log=
IPU1log=
HSM0log=
IMU0log=nt: 256, 256
RcCtxCount: 32, 32
UbMemEntrySize: 128, 0
MctpSupport: 1, 1
SecureMode: 0, 0
PrimaryCna: 0, 0
Upi: 0, 0
EntityId: 0, 0
SlotId: 1, 1
SocketId: 2, 2
PortIndex: 0, 0
PortCna: 0, 0
CtrlCna: 11, 11
ImpBootFlag: 2, 2
ImuB
IPU0log=
IPU1log=
HSM0log=
IMU0log=ootFlag: 1, 1
SktId: 0 DieId:2, HCCS_LINK:2 PaId:2
SktId: 1 DieId:2, HCCS_LINK:0 PaId:0
CIS register: ID[0xc00007ff], owner[0x1000003], function[0x1045dd8c].
CIS register: ID[0xc0000002], owner[0x1000003], function[0x1045de2c].

IPU0log=
IPU1log=
HSM0log=
IMU0log=odf: can not find od file[config]
Do not get NII route table, disable NII Send function.
UbiosTaskStart Entry ...
UbiosTaskStart create task success
IMU ImpBootFlag: 0x2
skip IMP start config...
UbiosCisTask Entry ...
ddr ini
IPU0log=
IPU1log=
HSM0log=
IMU0log=t done, start thermal dimm task
======dimm status======
  chl[0] dimm0 1, dimm1 0
  chl[1] dimm0 0, dimm1 0
  chl[2] dimm0 0, dimm1 0
  chl[3] dimm0 0, dimm1 0
  chl[4] dimm0 0, dimm1 0
  chl[5] dimm0 0, dimm1 0
  chl[6] dimm0 0
IPU0log=
IPU1log=
HSM0log=
IMU0log=, dimm1 0
  chl[7] dimm0 0, dimm1 0
  chl[8] dimm0 0, dimm1 0
  chl[9] dimm0 0, dimm1 0
  chl[10] dimm0 0, dimm1 0
  chl[11] dimm0 0, dimm1 0
==========end==========
sktId[0] chl[0] registered, dimm mask = 0x1
======dimm status=
IPU0log=
IPU1log=
HSM0log=
IMU0log======
  chl[0] dimm0 1, dimm1 0
  chl[1] dimm0 0, dimm1 0
  chl[2] dimm0 0, dimm1 0
  chl[3] dimm0 0, dimm1 0
  chl[4] dimm0 0, dimm1 0
  chl[5] dimm0 0, dimm1 0
  chl[6] dimm0 0, dimm1 0
  chl[7] dimm0 0, dimm1 0
  chl[8] dimm0
IPU0log=
IPU1log=
HSM0log=
IMU0log= 0, dimm1 0
  chl[9] dimm0 0, dimm1 0
  chl[10] dimm0 0, dimm1 0
  chl[11] dimm0 0, dimm1 0
==========end==========
sktId[1] chl[0] registered, dimm mask = 0x1
=====dimm temp params=====
  temp_threshold      : temp_mid:85,85 | 
IPU0log=
IPU1log=
HSM0log=
IMU0log=temp_hi:95 | temp_cri:100
  is_thermal_thro_en  : 1
  is_aref_rate_auto   : 0
===========end============
[0.02.06.297]TF Heartbeat Start
[0.02.07.660]RECEIVE MEM SILK.
0: skt = 1 logic = 3 phy = 10 
1: skt = 1 logic = 2 phy = 4 
IPU0log=
IPU1log=
HSM0log=
IMU0log=
2: skt = 1 logic = 8 phy = 5 
3: skt = 1 logic = 0 phy = 8 
4: skt = 1 logic = 6 phy = 9 
5: skt = 0 logic = 7 phy = 1 
6: skt = 0 logic = 3 phy = 10 
7: skt = 0 logic = 9 phy = 11 
8: skt = 0 logic = 4 phy = 2 
9: skt = 0 logi
IPU0log=
IPU1log=
HSM0log=
IMU0log=c = 1 phy = 0 
10: skt = 0 logic = 11 phy = 7 
11: skt = 1 logic = 5 phy = 6 
12: skt = 1 logic = 11 phy = 7 
13: skt = 0 logic = 5 phy = 6 
14: skt = 0 logic = 0 phy = 8 
15: skt = 1 logic = 1 phy = 0 
16: skt = 1 logic = 7 phy
IPU0log=
IPU1log=
HSM0log=
IMU0log= = 1 
17: skt = 1 logic = 9 phy = 11 
18: skt = 0 logic = 6 phy = 9 
19: skt = 1 logic = 10 phy = 3 
20: skt = 0 logic = 2 phy = 4 
21: skt = 0 logic = 10 phy = 3 
22: skt = 1 logic = 4 phy = 2 
23: skt = 0 logic = 8 phy = 5 
ge
IPU0log=
IPU1log=
HSM0log=
IMU0log=t mem silk data length: 72
[0.02.10.692]PCIE INIT DONE.
[IMU][ERR] LOS_SemPend(g_pcieSemaphore, LOS_WAIT_FOREVER)
[RegisterInterruptSource]:[21] begin
Interrupt 258 register OK
[RegisterInterruptSource]:[39] end
[RegisterInter
IPU0log=
IPU1log=
HSM0log=
IMU0log=ruptSource]:[21] begin
Interrupt 262 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 266 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Inte
IPU0log=
IPU1log=
HSM0log=
IMU0log=rrupt 270 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 277 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 288 register OK
[Regis
IPU0log=
IPU1log=
HSM0log=
IMU0log=terInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 292 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 296 register OK
[RegisterInterruptSource]:[39] end
IPU0log=
IPU1log=
HSM0log=
IMU0log=
[RegisterInterruptSource]:[21] begin
Interrupt 300 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 307 register OK
[RegisterInterruptSource]:[39] end
pmt Init done

-----------
IPU0log=
IPU1log=
HSM0log=
IMU0log=------ROUTE TABLE------------------
entryCount = 3
----------------------------------------------
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize 
IPU0log=
IPU1log=
HSM0log=
IMU0log== 2, bdf = 0x9300
[No.1]:
eidRange = 1, startEid = 10, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x9100
[No.2]:
eidRange = 1, startEid = 11, port = 0, isStatic = 1,
IPU0log=
IPU1log=
HSM0log=
IMU0log= entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2100
----------------------------------------------
-----------------ROUTE TABLE------------------
entryCount = 4
------------------------------
IPU0log=
IPU1log=
HSM0log=
IMU0log=----------------
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x9300
[No.1]:
eidRange = 1, startEid = 10, port = 0, isStatic = 1, e
IPU0log=
IPU1log=
HSM0log=
IMU0log=ntryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x9100
[No.2]:
eidRange = 1, startEid = 11, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2
IPU0log=
IPU1log=
HSM0log=
IMU0log=100
[No.3]:
eidRange = 1, startEid = 12, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2500
----------------------------------------------
-----------------ROUTE TABL
IPU0log=
IPU1log=
HSM0log=
IMU0log=E------------------
entryCount = 4
----------------------------------------------
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x930
IPU0log=
IPU1log=
HSM0log=
IMU0log=0
[No.1]:
eidRange = 1, startEid = 10, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x9100
[No.2]:
eidRange = 1, startEid = 11, port = 0, isStatic = 1, entryType = 0, 
IPU0log=
IPU1log=
HSM0log=
IMU0log=
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2100
[No.3]:
eidRange = 1, startEid = 12, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2500
---------
IPU0log=
IPU1log=
HSM0log=
IMU0log=-------------------------------------

IPU0log=
IPU1log=
HSM0log=
IMU0log=1T1N1U skt:0 CfgBusDfxPreConfig finish

********Hello Huawei LiteOS********

IMU Firmware Version : B173V01
LiteOS Kernel Version : 5.10.0
Run on Socket[0] Die[3]
Chip Version: 1
Max socket num: 2
*******************************
IPU0log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 0
cls: 6, core: 7
cpu 933 sram 1010 ddr 983
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  750|  802|  885|  933|
max  v
IPU1log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 1
cls: 6, core: 7
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  759|  821|  909|  961|
max  v: |  750|  750|  753|  781
HSM0log=[1970-01-01 00:01:11.729][HSM][INFO][30] init start
[1970-01-01 00:01:11.729][HSM][INFO][38] init over
[00:01:11.739][info] succeed to do thirdparty dfx_pabuk init
[00:01:11.744][info] os_mem_system_init default pool done
[0
IMU0log=***
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | rail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_vo
IPU0log=: |  750|  750|  754|  775|  836|  922|  980|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:7
IPU1log=|  846|  938|  994|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:750 F:1950
avs-uncore V:750
HSM0log=0:01:11.751][info] addr is already in region
[00:01:11.753][info] succeed to do thirdparty otpc_pabuk init
[1970-01-01 00:01:11.759][HSM][INFO][31] select_region: 0xc11cb55b
[1970-01-01 00:01:11.765][HSM][INFO][67] spi_nor de
IMU0log=lt:1122 mV | pmu:MP2882
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_v
IPU0log=50 F:1950
avs-uncore V:750 F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
av
IPU1log= F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
avs-uncore V:840 F:2450
avs-
HSM0log=vice_id 0xff1a67c8
[1970-01-01 00:01:11.771][HSM][INFO][50] std_cmd readback 0x30220d8
[1970-01-01 00:01:11.777][HSM][INFO][72] saf_cmd 0x0 readback 0x9f5a0604
[1970-01-01 00:01:11.783][HSM][INFO][72] saf_cmd 0x1 readback 0x5
IMU0log=olt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_
IPU0log=s-uncore V:840 F:2450
avs-uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain
IPU1log=uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | r
HSM0log=b7e938
[1970-01-01 00:01:11.790][HSM][INFO][72] saf_cmd 0x2 readback 0x1
[1970-01-01 00:01:11.795][HSM][INFO][72] saf_cmd 0x3 readback 0x0
[1970-01-01 00:01:11.801][HSM][INFO][72] saf_cmd 0x4 readback 0x0
[00:01:11.808][info
IMU0log=volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus r
IPU0log=[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | p
IPU1log=ail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_volt:1122 mV | pmu:MP2882
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[0] volt =  906 mV
pwr domain
HSM0log=] succeed to do thirdparty boot_profile_driver init
[00:01:11.813][info] succeed to do thirdparty crypto_driver init
[00:01:11.819][info] succeed to do thirdparty period_driver init
[00:01:11.825][info]  start loading interna
IMU0log=eady.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait th
IPU0log=mu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pmbus:0x480c0000 ver:0x110
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
IPU1log=[9] volt = 1103 mV
=end=
w&h rd rail:0, 906
w&h rd rail:1, 1103
pwr domain[0] set volt  904 mV succ
pwr domain[9] set volt 1103 mV succ
volt post
pwr domain[0] volt =  904 mV
pwr domain[9] volt = 1103 mV
==end==
Totem[0] Core Bo
HSM0log=l task ...
[00:01:11.830][info]  task name is ccm_task
[00:01:11.833][info]  hm_dynamic_loadelf successfully!
[00:01:11.838][info] internal task[1] task_name=ccm_task load successfully
[00:01:11.845][info]  task name is upgr
IMU0log=e cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master I
IPU0log=
avsbus resync succ
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[2] volt =  904 mV
pwr domain[7] volt =  802 mV
pwr domain[4] volt =  806 mV
pwr domain[1] volt =  804 mV
=end=
w&h rd rail:
IPU1log=ot Vol [1029]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2,
HSM0log=ade_task
[00:01:11.849][info]  hm_dynamic_loadelf successfully!
[00:01:11.854][info] internal task[2] task_name=upgrade_task load successfully
[00:01:11.861][info] created task ccm_task success!
[00:01:11.866][info] created 
IMU0log=mu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
cpu 0 entering scheduler
|--------------------------------------------------|
AtsPrint
|idx|lockCount| srcAddr| destAddr| addrLen|
|--
IPU0log=0, 904
w&h rd rail:1, 804
pwr domain[2] set volt  902 mV succ
pwr domain[7] set volt  802 mV succ
w&h rd rail:0, 806
w&h rd rail:1, 806
pwr domain[4] set volt  804 mV succ
pwr domain[1] set volt  802 mV succ
volt post
pwr domain
IPU1log= ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd8
HSM0log=task upgrade_task success!
[1970-01-01 00:01:11.871][HSM][INFO][54] Platform init 0x20250523 0x4e.
[1970-01-01 00:01:11.877][HSM][INFO][197] ccm start.
[1970-01-01 00:01:11.882][HSM][INFO][86] upgrade task init success.
[197
IMU0log=------------------------------------------------|
|  0|00000000|0x010500000|0x000110800000|0x00100000|
|  1|00000000|0x020000000|0x00001d000000|0x00800000|
|  2|00000000|0x020800000|0x000490000000|0x00100000|
|  3|00000000|0x020
IPU0log=[2] volt =  902 mV
pwr domain[7] volt =  802 mV
pwr domain[4] volt =  802 mV
pwr domain[1] volt =  802 mV
==end==
Totem[0] Core Boot Vol [1015]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0,
IPU1log=00, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
opposite dieId: 0, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 
HSM0log=0-01-01 00:01:11.888][HSM][INFO][95] upgrade recv cmd, 0x181.
[1970-01-01 00:01:11.893][HSM][INFO][103] upgrade res, 0x3a5aa5a3.
.
IMU0log=900000|0x000004000000|0x08000000|
|  4|00000000|0x028900000|0x000440580000|0x01000000|
|  5|00000000|0x029900000|0x000590000000|0x00100000|
|  6|00000000|0x029a00000|0x002000150000|0x00100000|
|  7|00000000|0x000000000|0x0000000
IPU0log= MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 
IPU1log=enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
hiboost task entry
boost wait SEF.
[INFO] mem used of task 'app_Task' is:0x2028, not zero when task being deleted
boost param OK.
Totem[0] Core[ 0] Freq Limit Low
HSM0log=
IMU0log=00000|0x00000000|
|  8|00000000|0x040000000|0x000000000000|0x08000000|
|  9|00000000|0x048000000|0x000000000000|0x08000000|
| 10|00000000|0x050000000|0x000000000000|0x08000000|
| 11|00000000|0x058000000|0x000000000000|0x08000000
IPU0log=0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
tsensor type
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Fr
HSM0log=
IMU0log=|
| 12|00000000|0x060000000|0x000000000000|0x08000000|
| 13|00000000|0x068000000|0x000000000000|0x08000000|
| 14|00000000|0x070000000|0x000000000000|0x08000000|
| 15|00000000|0x078000000|0x000490000000|0x08000000|
|-------------
IPU0log=: 3, ppuFormatK: 0x4da6, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b4,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 3, mask: fffffff8
tsensor type: 4, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=-------------------------------------|
=~=~=~=~=~=~=~=~=~=~= IMU Log @ 2026.6.1 9:11:56 =~=~=~=~=~=~=~=~=~=~=
[IMU] Watchdog Initialization done!
[RegisterInterruptSource]:[21] begin
Interrupt 32 register OK
Interrupt 34 regis
IPU0log=0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 4, mask: ffffffee
tsensor type: 5, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1

IPU1log= Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=ter OK
Interrupt 40 register OK
Interrupt 44 register OK
sram cnt 0x0, id = 43
Interrupt 43 register OK
Interrupt 36 register OK
Interrupt 57 register OK
sram cnt 0x0, id = 42
Interrupt 42 register OK
Interrupt 37 register OK
[R
IPU0log=tsensor: 5, mask: ffffffda
tsensor type: 6, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 6, mask: ffffff80
tsensor type: 7, ppuFormatK: 0x437a,
IPU1log=KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=egisterInterruptSource]:[39] end
IPMB initialization Start...
IPMB clock set done, prer = 0x18.
IPMB Rx FIFO clear empty.
IPMB initialization Done.
starting DFX Collect Task end
PowerTask Entry ...
Wait all vrd init done .
IPU0log= ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 7, mask: fffffffe
opposite dieId: 1, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
CPM max V[900]-
IPU1log= Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low
HSM0log=
IMU0log=..
All vrd init done, power task start
refresh domainId 0 Lsb 0x0
refresh domainId 9 Lsb 0x1
refresh domainId 2 Lsb 0x0
refresh domainId 7 Lsb 0x1
refresh domainId 4 Lsb 0x0
refresh domainId 1 Lsb 0x1
power sensor[0] | calib:512
IPU0log=F:2800
CPM min V[750]-F:1600
freq:2350, idx:9
cpm trim freq: 2600, idx: 4
cpm trim finish
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
recount hours 
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Fr
HSM0log=
IMU0log=0 | rshunt:1 | rshuntDiv:1000 | currLsb:1 | currLsbDiv:1000 | enableFlag:1
                | pwrLsb:25 | defPwr:25000 | minPwr:10000 | maxPwr:65000 | pwrFix:3400
                | manufacturerId: 0x5549 | dieId: 0x2260
power sen
IPU0log=0xb40 
hiboost task entry
boost wait SEF.
boost param OK.
Totem[0] Core[ 0] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[26
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=sor[0] init success
ScmiTaskEntry start.
[RegisterInterruptSource]:[21] begin
Interrupt 51 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 52 register OK
[RegisterInterruptSource]
IPU0log=00000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[12000
IPU1log= Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 53 register OK
[RegisterInterruptSource]:[39] end
[0.01.28.427]starting ras Init
RAS Setup Value get done!
INT_NUM_PER_SKT * HiGetSktNum() = 0x8
index = 0x0
RasIntRegis
IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Lim
IPU1log=KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=ter init 160 
index = 0x1
RasIntRegister init 172 
index = 0x2
RasIntRegister init 162 
index = 0x3
RasIntRegister init 174 
index = 0x4
RasIntRegister init 184 
index = 0x5
RasIntRegister init 196 
index = 0x6
RasIntRegister in
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IPU1log= Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low
HSM0log=
IMU0log=it 186 
index = 0x7
RasIntRegister init 198 
RasIntRegister init 161 
RasIntRegister init 173 
RasIntRegister init 185 
RasIntRegister init 197 
RasIntRegister init 284 
RasIntRegister init 314 
MceTableHeadInit start
starting C
IPU0log=14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
To
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
uncore max freq : 23
HSM0log=
IMU0log=e_Storm Contrl and Ras_Data_Update Task end
[0.01.28.509]starting ras end
[IMU][ERR] skt id 0
Ub init task start Entry ...
UbInitTask Entry ...
[RegisterInterruptSource]:[21] begin
Interrupt 167 register OK
[RegisterInterrupt
IPU0log=tem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[26
IPU1log=50 MHz

HSM0log=
IMU0log=Source]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 191 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 171 register OK
[RegisterInterruptSource]:[39] end
[RegisterI
IPU0log=00000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[12000
IPU1log=
HSM0log=
IMU0log=nterruptSource]:[21] begin
Interrupt 183 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 195 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin

IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Lim
IPU1log=
HSM0log=
IMU0log=BMC_COLLECTION: bmc req last log!
[IMU][ERR] [
IPU3log= no log data error!]
Interrupt 207 register OK
[RegisterInterruptSource]:[39] end
Init heart-beat-task end
CS0 flash do not support sfdp!
Current flash device ID[0x61a67c8]
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IPU1log=
HSM0log=
IMU0log=!
System supported 1 Flash.
flash cs 0 Manufacture 0xc8, DeviceId 0x1a67, AddrMode[0-3B,1-4B] 0x1:
    size 0x4000000, pagesize 0x100
    read  cmd 0x13, dummy byte 0x8
    write cmd 0x12, dummy byte 0x0
    erase4k cmd 0x21, er
IPU0log=33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
To
IPU1log=
HSM0log=
IMU0log=ase64k byte 0xdc
sfc init end
firstUnMskExt0Int
ThermalDimmStart Entry ...
wait ddr init done...
HacLowPowerStart Entry ...
Hello LiteOS...
Init ReportPcieMmioToBmcTaskEntry end
starting Fpc Isolation Task end
pwr cap[0]: 0, 
IPU0log=tem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[26
IPU1log=
HSM0log=
IMU0log=67
pwr cap[1]: f, 27
pwr cap[2]: 1, 3
[0.01.59.830]DDR init done
[LOG]head = 0x0, tail = 0x1850, logSize = 0x1850
[IMU][ERR] HsmLogInit!
[IMU][ERR] HsmLogInit! TRUE
set apei done!
UbConfigData size is 64
UbConfigData 0 : 0
Ub
IPU0log=00000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
uncore max freq : 2350 MHz

IPU1log=
HSM0log=
IMU0log=ConfigData 1 : 0
UbConfigData 2 : 0
UbConfigData 3 : 1
UbConfigData 4 : 31
UbConfigData 5 : 1
UbConfigData 6 : 0
UbConfigData 7 : 32
UbConfigData 8 : 0
UbConfigData 9 : 1
UbConfigData 10 : 2
UbConfigData 11 : 0
UbConfigData 12 :
IPU0log=
IPU1log=
HSM0log=
IMU0log= 0
UbConfigData 13 : 1
UbConfigData 14 : 0
UbConfigData 15 : 0
UbConfigData 16 : 0
UbConfigData 17 : 0
UbConfigData 18 : 0
UbConfigData 19 : 0
UbConfigData 20 : 0
UbConfigData 21 : 0
UbConfigData 22 : 11
UbConfigData 23 : 0
UbCo
IPU0log=
IPU1log=
HSM0log=
IMU0log=nfigData 24 : 0
UbConfigData 25 : 0
UbConfigData 26 : 0
UbConfigData 27 : 0
UbConfigData 28 : 0
UbConfigData 29 : 0
UbConfigData 30 : 0
UbConfigData 31 : 0
UbConfigData 32 : 0
UbConfigData 33 : 0
UbConfigData 34 : 2
UbConfigData
IPU0log=
IPU1log=
HSM0log=
IMU0log= 35 : 1
UbConfigData 36 : 0
UbConfigData 37 : 0
UbConfigData 38 : 0
UbConfigData 39 : 0
UbConfigData 40 : 0
UbConfigData 41 : 0
UbConfigData 42 : 0
UbConfigData 43 : 0
UbConfigData 44 : 0
UbConfigData 45 : 0
UbConfigData 46 : 0

IPU0log=
IPU1log=
HSM0log=
IMU0log=UbConfigData 47 : 0
UbConfigData 48 : 0
UbConfigData 49 : 0
UbConfigData 50 : 0
UbConfigData 51 : 0
UbConfigData 52 : 0
UbConfigData 53 : 0
UbConfigData 54 : 0
UbConfigData 55 : 0
UbConfigData 56 : 0
UbConfigData 57 : 0
UbConfig
IPU0log=
IPU1log=
HSM0log=
IMU0log=Data 58 : 0
UbConfigData 59 : 0
UbConfigData 60 : 0
UbConfigData 61 : 0
UbConfigData 62 : 0
UbConfigData 63 : 0
UbConfigData 64 : 0
ClusterSwitch: 0, 0
ClusterMode: 0, 0
ControlMode: 0, 0
EnumMode: 1, 1
BodyMask: 31, 31
CcCtxCou
IPU0log=
IPU1log=
HSM0log=
IMU0log=nt: 256, 256
RcCtxCount: 32, 32
UbMemEntrySize: 128, 0
MctpSupport: 1, 1
SecureMode: 0, 0
PrimaryCna: 0, 0
Upi: 0, 0
EntityId: 0, 0
SlotId: 1, 1
SocketId: 2, 2
PortIndex: 0, 0
PortCna: 0, 0
CtrlCna: 11, 11
ImpBootFlag: 2, 2
ImuB
IPU0log=
IPU1log=
HSM0log=
IMU0log=ootFlag: 1, 1
SktId: 0 DieId:2, HCCS_LINK:2 PaId:2
SktId: 1 DieId:2, HCCS_LINK:0 PaId:0
CIS register: ID[0xc00007ff], owner[0x1000003], function[0x1045dd8c].
CIS register: ID[0xc0000002], owner[0x1000003], function[0x1045de2c].

IPU0log=
IPU1log=
HSM0log=
IMU0log=odf: can not find od file[config]
Do not get NII route table, disable NII Send function.
UbiosTaskStart Entry ...
UbiosTaskStart create task success
IMU ImpBootFlag: 0x2
skip IMP start config...
UbiosCisTask Entry ...
ddr ini
IPU0log=
IPU1log=
HSM0log=
IMU0log=t done, start thermal dimm task
======dimm status======
  chl[0] dimm0 1, dimm1 0
  chl[1] dimm0 0, dimm1 0
  chl[2] dimm0 0, dimm1 0
  chl[3] dimm0 0, dimm1 0
  chl[4] dimm0 0, dimm1 0
  chl[5] dimm0 0, dimm1 0
  chl[6] dimm0 0
IPU0log=
IPU1log=
HSM0log=
IMU0log=, dimm1 0
  chl[7] dimm0 0, dimm1 0
  chl[8] dimm0 0, dimm1 0
  chl[9] dimm0 0, dimm1 0
  chl[10] dimm0 0, dimm1 0
  chl[11] dimm0 0, dimm1 0
==========end==========
sktId[0] chl[0] registered, dimm mask = 0x1
======dimm status=
IPU0log=
IPU1log=
HSM0log=
IMU0log======
  chl[0] dimm0 1, dimm1 0
  chl[1] dimm0 0, dimm1 0
  chl[2] dimm0 0, dimm1 0
  chl[3] dimm0 0, dimm1 0
  chl[4] dimm0 0, dimm1 0
  chl[5] dimm0 0, dimm1 0
  chl[6] dimm0 0, dimm1 0
  chl[7] dimm0 0, dimm1 0
  chl[8] dimm0
IPU0log=
IPU1log=
HSM0log=
IMU0log= 0, dimm1 0
  chl[9] dimm0 0, dimm1 0
  chl[10] dimm0 0, dimm1 0
  chl[11] dimm0 0, dimm1 0
==========end==========
sktId[1] chl[0] registered, dimm mask = 0x1
=====dimm temp params=====
  temp_threshold      : temp_mid:85,85 | 
IPU0log=
IPU1log=
HSM0log=
IMU0log=temp_hi:95 | temp_cri:100
  is_thermal_thro_en  : 1
  is_aref_rate_auto   : 0
===========end============
[0.02.06.671]TF Heartbeat Start
[0.02.08.033]RECEIVE MEM SILK.
0: skt = 1 logic = 3 phy = 10 
1: skt = 1 logic = 2 phy = 4 
IPU0log=
IPU1log=
HSM0log=
IMU0log=
2: skt = 1 logic = 8 phy = 5 
3: skt = 1 logic = 0 phy = 8 
4: skt = 1 logic = 6 phy = 9 
5: skt = 0 logic = 7 phy = 1 
6: skt = 0 logic = 3 phy = 10 
7: skt = 0 logic = 9 phy = 11 
8: skt = 0 logic = 4 phy = 2 
9: skt = 0 logi
IPU0log=
IPU1log=
HSM0log=
IMU0log=c = 1 phy = 0 
10: skt = 0 logic = 11 phy = 7 
11: skt = 1 logic = 5 phy = 6 
12: skt = 1 logic = 11 phy = 7 
13: skt = 0 logic = 5 phy = 6 
14: skt = 0 logic = 0 phy = 8 
15: skt = 1 logic = 1 phy = 0 
16: skt = 1 logic = 7 phy
IPU0log=
IPU1log=
HSM0log=
IMU0log= = 1 
17: skt = 1 logic = 9 phy = 11 
18: skt = 0 logic = 6 phy = 9 
19: skt = 1 logic = 10 phy = 3 
20: skt = 0 logic = 2 phy = 4 
21: skt = 0 logic = 10 phy = 3 
22: skt = 1 logic = 4 phy = 2 
23: skt = 0 logic = 8 phy = 5 
ge
IPU0log=
IPU1log=
HSM0log=
IMU0log=t mem silk data length: 72
[0.02.11.074]PCIE INIT DONE.
[IMU][ERR] LOS_SemPend(g_pcieSemaphore, LOS_WAIT_FOREVER)
[RegisterInterruptSource]:[21] begin
Interrupt 258 register OK
[RegisterInterruptSource]:[39] end
[RegisterInter
IPU0log=
IPU1log=
HSM0log=
IMU0log=ruptSource]:[21] begin
Interrupt 262 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 266 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Inte
IPU0log=
IPU1log=
HSM0log=
IMU0log=rrupt 270 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 277 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 288 register OK
[Regis
IPU0log=
IPU1log=
HSM0log=
IMU0log=terInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 292 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 296 register OK
[RegisterInterruptSource]:[39] end
IPU0log=
IPU1log=
HSM0log=
IMU0log=
[RegisterInterruptSource]:[21] begin
Interrupt 300 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 307 register OK
[RegisterInterruptSource]:[39] end
pmt Init done

-----------
IPU0log=
IPU1log=
HSM0log=
IMU0log=------ROUTE TABLE------------------
entryCount = 3
----------------------------------------------
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize 
IPU0log=
IPU1log=
HSM0log=
IMU0log== 2, bdf = 0x9300
[No.1]:
eidRange = 1, startEid = 10, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x9100
[No.2]:
eidRange = 1, startEid = 11, port = 0, isStatic = 1,
IPU0log=
IPU1log=
HSM0log=
IMU0log= entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2100
----------------------------------------------
-----------------ROUTE TABLE------------------
entryCount = 4
------------------------------
IPU0log=
IPU1log=
HSM0log=
IMU0log=----------------
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x9300
[No.1]:
eidRange = 1, startEid = 10, port = 0, isStatic = 1, e
IPU0log=
IPU1log=
HSM0log=
IMU0log=ntryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x9100
[No.2]:
eidRange = 1, startEid = 11, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2
IPU0log=
IPU1log=
HSM0log=
IMU0log=100
[No.3]:
eidRange = 1, startEid = 12, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2500
----------------------------------------------
-----------------ROUTE TABL
IPU0log=
IPU1log=
HSM0log=
IMU0log=E------------------
entryCount = 4
----------------------------------------------
[No.0]:
eidRange = 1, startEid = 9, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x930
IPU0log=
IPU1log=
HSM0log=
IMU0log=0
[No.1]:
eidRange = 1, startEid = 10, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x9100
[No.2]:
eidRange = 1, startEid = 11, port = 0, isStatic = 1, entryType = 0, 
IPU0log=
IPU1log=
HSM0log=
IMU0log=
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2100
[No.3]:
eidRange = 1, startEid = 12, port = 0, isStatic = 1, entryType = 0, 
transportBinding = 2, mediaType = 15, addressSize = 2, bdf = 0x2500
---------
IPU0log=
IPU1log=
HSM0log=
IMU0log=-------------------------------------

IPU0log=
IPU1log=
HSM0log=
IMU0log=1T1N1U skt:0 CfgBusDfxPreConfig finish

********Hello Huawei LiteOS********

IMU Firmware Version : B173V01
LiteOS Kernel Version : 5.10.0
Run on Socket[0] Die[3]
Chip Version: 1
Max socket num: 2
*******************************
IPU0log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 0
cls: 6, core: 7
cpu 933 sram 1010 ddr 983
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  750|  802|  885|  933|
max  v
IPU1log=
********LiteOS********

IPU Firmware Version : B173V01
soktId: 0, dieId: 1
cls: 6, core: 7
core f: | 1700| 1800| 2000| 2100| 2300| 2500| 2600|
min  v: |  750|  750|  750|  759|  821|  909|  961|
max  v: |  750|  750|  753|  781
IMU0log=***
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | rail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_vo
IPU0log=: |  750|  750|  754|  775|  836|  922|  980|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:7
IPU1log=|  846|  938|  994|
avs-uncore V:750 F:1600
avs-uncore V:750 F:1650
avs-uncore V:750 F:1700
avs-uncore V:750 F:1750
avs-uncore V:750 F:1800
avs-uncore V:750 F:1850
avs-uncore V:750 F:1900
avs-uncore V:750 F:1950
avs-uncore V:750
HSM0log=[1970-01-01 00:01:12.646][HSM][INFO][30] init start
[1970-01-01 00:01:12.646][HSM][INFO][38] init over
[00:01:12.656][info] succeed to do thirdparty dfx_pabuk init
[00:01:12.661][info] os_mem_system_init default pool done
[0
IMU0log=lt:1122 mV | pmu:MP2882
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_v
IPU0log=50 F:1950
avs-uncore V:750 F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
av
IPU1log= F:2000
avs-uncore V:755 F:2050
avs-uncore V:760 F:2100
avs-uncore V:765 F:2150
avs-uncore V:770 F:2200
avs-uncore V:780 F:2250
avs-uncore V:790 F:2300
avs-uncore V:800 F:2350
avs-uncore V:820 F:2400
avs-uncore V:840 F:2450
avs-
HSM0log=0:01:12.668][info] addr is already in region
[00:01:12.670][info] succeed to do thirdparty otpc_pabuk init
[1970-01-01 00:01:12.676][HSM][INFO][31] select_region: 0xc11cb55b
[1970-01-01 00:01:12.682][HSM][INFO][67] spi_nor de
IMU0log=olt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_
IPU0log=s-uncore V:840 F:2450
avs-uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[2] TB_CORE_DVFS       | rail:0 | addr:0x46 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain
IPU1log=uncore V:860 F:2500
avs-uncore V:880 F:2550
avs-uncore V:900 F:2600
pwr domain[0] TA_CORE_DVFS       | rail:0 | addr:0x42 | def_volt: 900 mV | min_volt: 580 mV | max_volt:1200 mV | pmu:MP2882
pwr domain[9] DDRIO              | r
HSM0log=vice_id 0xff1a67c8
[1970-01-01 00:01:12.688][HSM][INFO][50] std_cmd readback 0x30220d8
[1970-01-01 00:01:12.694][HSM][INFO][72] saf_cmd 0x0 readback 0x9f5a0604
[1970-01-01 00:01:12.700][HSM][INFO][72] saf_cmd 0x1 readback 0x5
IMU0log=volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus r
IPU0log=[7] IO_NB_AVS          | rail:1 | addr:0x46 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pwr domain[4] UNCORE_DVFS        | rail:0 | addr:0x44 | def_volt: 800 mV | min_volt: 580 mV | max_volt:1200 mV | p
IPU1log=ail:1 | addr:0x42 | def_volt:1100 mV | min_volt:1078 mV | max_volt:1122 mV | pmu:MP2882
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[0] volt =  906 mV
pwr domain
HSM0log=b7e938
[1970-01-01 00:01:12.707][HSM][INFO][72] saf_cmd 0x2 readback 0x1
[1970-01-01 00:01:12.713][HSM][INFO][72] saf_cmd 0x3 readback 0x0
[1970-01-01 00:01:12.718][HSM][INFO][72] saf_cmd 0x4 readback 0x0
[00:01:12.725][info
IMU0log=eady.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait th
IPU0log=mu:MP2882
pwr domain[1] IO_NA_AVS          | rail:1 | addr:0x44 | def_volt: 800 mV | min_volt: 784 mV | max_volt: 816 mV | pmu:MP2882
pmbus:0x480c0000 ver:0x110
pmbus:0x47550000 ver:0x110
avsbus clk cfg:0x1919
avsbus resync succ
IPU1log=[9] volt = 1101 mV
=end=
w&h rd rail:0, 906
w&h rd rail:1, 1101
pwr domain[0] set volt  904 mV succ
pwr domain[9] set volt 1103 mV succ
volt post
pwr domain[0] volt =  904 mV
pwr domain[9] volt = 1103 mV
==end==
Totem[0] Core Bo
HSM0log=] succeed to do thirdparty boot_profile_driver init
[00:01:12.730][info] succeed to do thirdparty crypto_driver init
[00:01:12.736][info] succeed to do thirdparty period_driver init
[00:01:12.742][info]  start loading interna
IMU0log=e cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master I
IPU0log=
avsbus resync succ
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[2] volt =  904 mV
pwr domain[7] volt =  802 mV
pwr domain[4] volt =  804 mV
pwr domain[1] volt =  804 mV
=end=
w&h rd rail:
IPU1log=ot Vol [1029]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2,
HSM0log=l task ...
[00:01:12.747][info]  task name is ccm_task
[00:01:12.751][info]  hm_dynamic_loadelf successfully!
[00:01:12.755][info] internal task[1] task_name=ccm_task load successfully
[00:01:12.762][info]  task name is upgr
IMU0log=mu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
cpu 0 entering scheduler
|--------------------------------------------------|
AtsPrint
|idx|lockCount| srcAddr| destAddr| addrLen|
|--
IPU0log=0, 904
w&h rd rail:1, 804
pwr domain[2] set volt  902 mV succ
pwr domain[7] set volt  804 mV succ
w&h rd rail:0, 804
w&h rd rail:1, 804
pwr domain[4] set volt  804 mV succ
pwr domain[1] set volt  802 mV succ
volt post
pwr domain
IPU1log= ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd8
HSM0log=ade_task
[00:01:12.766][info]  hm_dynamic_loadelf successfully!
[00:01:12.771][info] internal task[2] task_name=upgrade_task load successfully
[00:01:12.778][info] created task ccm_task success!
[00:01:12.783][info] created 
IMU0log=------------------------------------------------|
|  0|00000000|0x010500000|0x000110800000|0x00100000|
|  1|00000000|0x020000000|0x00001d000000|0x00800000|
|  2|00000000|0x020800000|0x000490000000|0x00100000|
|  3|00000000|0x020
IPU0log=[2] volt =  902 mV
pwr domain[7] volt =  802 mV
pwr domain[4] volt =  802 mV
pwr domain[1] volt =  802 mV
==end==
Totem[0] Core Boot Vol [1015]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0,
IPU1log=00, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
opposite dieId: 0, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 
HSM0log=task upgrade_task success!
[1970-01-01 00:01:12.788][HSM][INFO][54] Platform init 0x20250523 0x4e.
[1970-01-01 00:01:12.794][HSM][INFO][197] ccm start.
[1970-01-01 00:01:12.799][HSM][INFO][86] upgrade task init success.
[197
IMU0log=900000|0x000004000000|0x08000000|
|  4|00000000|0x028900000|0x000440580000|0x01000000|
|  5|00000000|0x029900000|0x000590000000|0x00100000|
|  6|00000000|0x029a00000|0x002000150000|0x00100000|
|  7|00000000|0x000000000|0x0000000
IPU0log= MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 
IPU1log=enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
hiboost task entry
boost wait SEF.
[INFO] mem used of task 'app_Task' is:0x2028, not zero when task being deleted
boost param OK.
Totem[0] Core[ 0] Freq Limit Low
HSM0log=0-01-01 00:01:12.805][HSM][INFO][95] upgrade recv cmd, 0x181.
[1970-01-01 00:01:12.810][HSM][INFO][103] upgrade res, 0x3a5aa5a3.
.
IMU0log=00000|0x00000000|
|  8|00000000|0x040000000|0x000000000000|0x08000000|
|  9|00000000|0x048000000|0x000000000000|0x08000000|
| 10|00000000|0x050000000|0x000000000000|0x08000000|
| 11|00000000|0x058000000|0x000000000000|0x08000000
IPU0log=0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
tsensor type
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Fr
HSM0log=
IMU0log=|
| 12|00000000|0x060000000|0x000000000000|0x08000000|
| 13|00000000|0x068000000|0x000000000000|0x08000000|
| 14|00000000|0x070000000|0x000000000000|0x08000000|
| 15|00000000|0x078000000|0x000490000000|0x08000000|
|-------------
IPU0log=: 3, ppuFormatK: 0x4da6, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b4,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 3, mask: fffffff8
tsensor type: 4, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=-------------------------------------|
=~=~=~=~=~=~=~=~=~=~= IMU Log @ 2026.7.2 1:20:48 =~=~=~=~=~=~=~=~=~=~=
[IMU] Watchdog Initialization done!
[RegisterInterruptSource]:[21] begin
Interrupt 32 register OK
Interrupt 34 regis
IPU0log=0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 4, mask: ffffffee
tsensor type: 5, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1

IPU1log= Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=ter OK
Interrupt 40 register OK
Interrupt 44 register OK
sram cnt 0x0, id = 43
Interrupt 43 register OK
Interrupt 36 register OK
Interrupt 57 register OK
sram cnt 0x0, id = 42
Interrupt 42 register OK
Interrupt 37 register OK
[R
IPU0log=tsensor: 5, mask: ffffffda
tsensor type: 6, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 6, mask: ffffff80
tsensor type: 7, ppuFormatK: 0x437a,
IPU1log=KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=egisterInterruptSource]:[39] end
IPMB initialization Start...
IPMB clock set done, prer = 0x18.
IPMB Rx FIFO clear empty.
IPMB initialization Done.
starting DFX Collect Task end
PowerTask Entry ...
Wait all vrd init done .
IPU0log= ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 7, mask: fffffffe
opposite dieId: 1, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
CPM max V[900]-
IPU1log= Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low
HSM0log=
IMU0log=..
All vrd init done, power task start
refresh domainId 0 Lsb 0x0
refresh domainId 9 Lsb 0x1
refresh domainId 2 Lsb 0x0
refresh domainId 7 Lsb 0x1
refresh domainId 4 Lsb 0x0
refresh domainId 1 Lsb 0x1
power sensor[0] | calib:512
IPU0log=F:2800
CPM min V[750]-F:1600
freq:2350, idx:9
cpm trim freq: 2600, idx: 4
cpm trim finish
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
recount hours 
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[23] Fr
HSM0log=
IMU0log=0 | rshunt:1 | rshuntDiv:1000 | currLsb:1 | currLsbDiv:1000 | enableFlag:1
                | pwrLsb:25 | defPwr:25000 | minPwr:10000 | maxPwr:65000 | pwrFix:3400
                | manufacturerId: 0x5549 | dieId: 0x2260
power sen
IPU0log=0xe1c 
hiboost task entry
boost wait SEF.
boost param OK.
Totem[0] Core[ 0] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[26
IPU1log=eq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[25] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0]
HSM0log=
IMU0log=sor[0] init success
ScmiTaskEntry start.
[RegisterInterruptSource]:[21] begin
Interrupt 51 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 52 register OK
[RegisterInterruptSource]
IPU0log=00000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 4] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 6] Freq Limit Low[12000
IPU1log= Core[27] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[29] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2600000]
HSM0log=
IMU0log=:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 53 register OK
[RegisterInterruptSource]:[39] end
[0.01.29.343]starting ras Init
RAS Setup Value get done!
INT_NUM_PER_SKT * HiGetSktNum() = 0x8
index = 0x0
RasIntRegis
IPU0log=00]KHZ Up[2600000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 8] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[10] Freq Lim
IPU1log=KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[33] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=ter init 160 
index = 0x1
RasIntRegister init 172 
index = 0x2
RasIntRegister init 162 
index = 0x3
RasIntRegister init 174 
index = 0x4
RasIntRegister init 184 
index = 0x5
RasIntRegister init 196 
index = 0x6
RasIntRegister in
IPU0log=it Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[
IPU1log= Up[2600000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[38] Freq Limit Low
HSM0log=
IMU0log=it 186 
index = 0x7
RasIntRegister init 198 
RasIntRegister init 161 
RasIntRegister init 173 
RasIntRegister init 185 
RasIntRegister init 197 
RasIntRegister init 284 
RasIntRegister init 314 
MceTableHeadInit start
starting C
IPU0log=14] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
To
IPU1log=[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
uncore max freq : 23
HSM0log=
IMU0log=e_Storm Contrl and Ras_Data_Update Task end
[0.01.29.424]starting ras end
[IMU][ERR] skt id 0
Ub init task start Entry ...
UbInitTask Entry ...
[RegisterInterruptSource]:[21] begin
Interrupt 167 register OK
[RegisterInterrupt
IPU0log=tem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[19] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2600000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[26
IPU1log=50 MHz

HSM0log=
IMU0log=Source]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 191 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 171 register OK
[RegisterInterruptSource]:[39] end
[RegisterI
HSM0log=l task ...
[00:01:14.799][info]  task name is ccm_task
[00:01:14.803][info]  hm_dynamic_loadelf successfully!
[00:01:14.808][info] internal task[1] task_name=ccm_task load successfully
[00:01:14.814][info]  task name is upgr
IMU0log=e cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master I
IPU0log=
avsbus resync succ
avsbus clk cfg:0x1919
avsbus resync succ
avsbus resync succ
==volt boot==
pwr domain[2] volt =  906 mV
pwr domain[7] volt =  806 mV
pwr domain[4] volt =  804 mV
pwr domain[1] volt =  806 mV
=end=
w&h rd rail:
IPU1log=ot Vol [1052]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2,
HSM0log=ade_task
[00:01:14.818][info]  hm_dynamic_loadelf successfully!
[00:01:14.823][info] internal task[2] task_name=upgrade_task load successfully
[00:01:14.830][info] created task ccm_task success!
[00:01:14.835][info] created 
IMU0log=mu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
Master Imu wait the cfgbus ready.
send IMU_INIT_END to cpld.
cpu 0 entering scheduler
|-------------
IPU0log=0, 906
w&h rd rail:1, 804
pwr domain[2] set volt  904 mV succ
pwr domain[7] set volt  804 mV succ
w&h rd rail:0, 804
w&h rd rail:1, 806
pwr domain[4] set volt  802 mV succ
pwr domain[1] set volt  804 mV succ
volt post
pwr domain
IPU1log= ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd8
HSM0log=task upgrade_task success!
[1970-01-01 00:01:14.840][HSM][INFO][54] Platform init 0x20250523 0x4e.
[1970-01-01 00:01:14.846][HSM][INFO][197] ccm start.
[1970-01-01 00:01:14.851][HSM][INFO][86] upgrade task init success.
[197
IMU0log=-------------------------------------|
AtsPrint
|idx|lockCount| srcAddr| destAddr| addrLen|
|--------------------------------------------------|
|  0|00000000|0x010500000|0x000110800000|0x00100000|
|  1|00000000|0x020000000|0x00
IPU0log=[2] volt =  904 mV
pwr domain[7] volt =  804 mV
pwr domain[4] volt =  802 mV
pwr domain[1] volt =  804 mV
==end==
Totem[0] Core Boot Vol [1018]mv
wait mbist finish
mbist finish
tsensor type: 0, ppuFormatK: 0x437a, ArFactor: 0x0,
IPU1log=00, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
opposite dieId: 0, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 
HSM0log=0-01-01 00:01:14.857][HSM][INFO][95] upgrade recv cmd, 0x181.
[1970-01-01 00:01:14.863][HSM][INFO][103] upgrade res, 0x3a5aa5a3.
.
IMU0log=001d000000|0x00800000|
|  2|00000000|0x020800000|0x000490000000|0x00100000|
|  3|00000000|0x020900000|0x000004000000|0x08000000|
|  4|00000000|0x028900000|0x000440580000|0x01000000|
|  5|00000000|0x029900000|0x000590000000|0x001
IPU0log= MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 0, mask: fffff000
tsensor type: 2, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 
IPU1log=enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
hiboost task entry
boost wait SEF.
[INFO] mem used of task 'app_Task' is:0x2028, not zero when task being deleted
boost param OK.
Totem[0] Core[ 0] Freq Limit Low
HSM0log=
IMU0log=00000|
|  6|00000000|0x029a00000|0x002000150000|0x00100000|
|  7|00000000|0x000000000|0x000000000000|0x00000000|
|  8|00000000|0x040000000|0x000000000000|0x08000000|
|  9|00000000|0x048000000|0x000000000000|0x08000000|
| 10|0000
IPU0log=0x6, ReduceFactor2: 0x1
tsensor: 2, mask: fffffff8
tsensor type: 1, ppuFormatK: 0x4def, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b1,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 1, mask: ffffff80
tsensor type
IPU1log=[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[ 4] Fr
HSM0log=
IMU0log=0000|0x050000000|0x000000000000|0x08000000|
| 11|00000000|0x058000000|0x000000000000|0x08000000|
| 12|00000000|0x060000000|0x000000000000|0x08000000|
| 13|00000000|0x068000000|0x000000000000|0x08000000|
| 14|00000000|0x070000000
IPU0log=: 3, ppuFormatK: 0x4da6, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b4,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 3, mask: fffffff8
tsensor type: 4, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 
IPU1log=eq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[ 6] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0]
HSM0log=
IMU0log=|0x000000000000|0x08000000|
| 15|00000000|0x078000000|0x0028c8000000|0x08000000|
|--------------------------------------------------|
=~=~=~=~=~=~=~=~=~=~= IMU Log @ 2026.7.17 20:20:39 =~=~=~=~=~=~=~=~=~=~=
[IMU] Watchdog Initia
IPU0log=0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 4, mask: ffffffee
tsensor type: 5, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1

IPU1log= Core[ 8] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[10] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2300000]
HSM0log=
IMU0log=lization done!
[RegisterInterruptSource]:[21] begin
Interrupt 32 register OK
Interrupt 34 register OK
Interrupt 40 register OK
Interrupt 44 register OK
sram cnt 0x0, id = 43
Interrupt 43 register OK
Interrupt 36 register OK
In
IPU0log=tsensor: 5, mask: ffffffda
tsensor type: 6, ppuFormatK: 0x437a, ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 6, mask: ffffff80
tsensor type: 7, ppuFormatK: 0x437a,
IPU1log=KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[14] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=terrupt 57 register OK
sram cnt 0x0, id = 42
Interrupt 42 register OK
Interrupt 37 register OK
[RegisterInterruptSource]:[39] end
IPMB initialization Start...
IPMB clock set done, prer = 0x18.
IPMB Rx FIFO clear empty.
IPMB 
IPU0log= ArFactor: 0x0, MrFactor: 0x7,FormatB: 0xd800, FormatSub: 0x1b0,ReduceFactor: 0x6, ReduceFactor2: 0x1
tsensor: 7, mask: fffffffe
opposite dieId: 1, opposite periId: 0
data memory init, wait time: 8us.
LDO enabled
CPM max V[900]-
IPU1log= Up[2300000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[19] Freq Limit Low
HSM0log=
IMU0log=initialization Done.
starting DFX Collect Task end
PowerTask Entry ...
Wait all vrd init done ...
All vrd init done, power task start
refresh domainId 0 Lsb 0x0
refresh domainId 9 Lsb 0x1
refresh domainId 2 Lsb 0x0
refresh dom
IPU0log=F:2800
CPM min V[750]-F:1600
freq:2350, idx:9
cpm trim freq: 2600, idx: 4
cpm trim finish
[INFO] scmiId: 0, ch: 0 register succ
[INFO] Interrupt 89 enabled, ret: 0
cpu 0 entering scheduler
thermal soc task enabled
recount hours 
IPU1log=[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[23] Fr
HSM0log=
IMU0log=ainId 7 Lsb 0x1
refresh domainId 4 Lsb 0x0
refresh domainId 1 Lsb 0x1
power sensor[0] | calib:5120 | rshunt:1 | rshuntDiv:1000 | currLsb:1 | currLsbDiv:1000 | enableFlag:1
                | pwrLsb:25 | defPwr:25000 | minPwr:1000
IPU0log=0x7ec 
hiboost task entry
boost wait SEF.
boost param OK.
Totem[0] Core[ 0] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[ 1] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[ 2] Freq Limit Low[1200000]KHZ Up[23
IPU1log=eq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[25] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0]
HSM0log=
IMU0log=0 | maxPwr:65000 | pwrFix:-3400
                | manufacturerId: 0x5549 | dieId: 0x2260
power sensor[0] init success
ScmiTaskEntry start.
[RegisterInterruptSource]:[21] begin
Interrupt 51 register OK
[RegisterInterruptSource]:
IPU0log=00000]KHZ
Totem[0] Core[ 3] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[ 4] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[ 5] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[ 6] Freq Limit Low[12000
IPU1log= Core[27] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[29] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2300000]
HSM0log=
IMU0log=[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 52 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 53 register OK
[RegisterInterruptSource]:[39] end
[0.01.33.422]startin
IPU0log=00]KHZ Up[2300000]KHZ
Totem[0] Core[ 7] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[ 8] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[ 9] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[10] Freq Lim
IPU1log=KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[33] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ
HSM0log=
IMU0log=g ras Init
RAS Setup Value get done!
INT_NUM_PER_SKT * HiGetSktNum() = 0x8
index = 0x0
RasIntRegister init 160 
index = 0x1
RasIntRegister init 172 
index = 0x2
[0.01.33.436]Receive ras int[162]
First coalesce handler start
Type
IPU0log=it Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[11] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[12] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[13] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[
IPU1log= Up[2300000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[38] Freq Limit Low
HSM0log=
IMU0log=2 status = 0x0
Type1 status = 0x20000
Found error node[17], moduleId[0x51]
Secondary coalesce handler start
Type2 status = 0x0
Type1 status = 0x8
Found error node[3], moduleId[0x30]
-- RAS DUMP --
Skt[0] Nimbus[0] Module[UCMI] 

IPU0log=14] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[15] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[16] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[17] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
To
IPU1log=[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[42] Fr
HSM0log=
IMU0log=Error severity is RECOVERABLE[28001d0000]
ERR_MISC_00 = 0x00000010
memory copy failed!
Apei not ready
report common callback: success
Type0 status = 0x0
Type0 status = 0x0
ras int[162] end

RasIntRegister init 162 
index = 0x3
R
IPU0log=tem[0] Core[18] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[19] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[20] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[21] Freq Limit Low[1200000]KHZ Up[23
IPU1log=eq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[43] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[44] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[45] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0]
HSM0log=
IMU0log=asIntRegister init 174 
index = 0x4
RasIntRegister init 184 
index = 0x5
RasIntRegister init 196 
index = 0x6
[0.01.33.507]Receive ras int[186]
First coalesce handler start
Type2 status = 0x0
Type1 status = 0x20000
Found error n
IPU0log=00000]KHZ
Totem[0] Core[22] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[23] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[24] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[25] Freq Limit Low[12000
IPU1log= Core[46] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[47] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
get tdp value from Product! Tdp value per vdie : 220000 mW!
uncore max freq : 2350 MHz

HSM0log=
IMU0log=ode[17], moduleId[0x51]
Secondary coalesce handler start
Type2 status = 0x0
Type1 status = 0x8
Found error node[3], moduleId[0x30]
-- RAS DUMP --
Skt[1] Nimbus[0] Module[UCMI] 
Error severity is RECOVERABLE[68001d0000]
ERR_MISC_
IPU0log=00]KHZ Up[2300000]KHZ
Totem[0] Core[26] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[27] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[28] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[29] Freq Lim
IPU1log=
HSM0log=
IMU0log=00 = 0x00000010
memory copy failed!
Apei not ready
report common callback: success
Type0 status = 0x0
Type0 status = 0x0
ras int[186] end

RasIntRegister init 186 
index = 0x7
RasIntRegister init 198 
RasIntRegister init 161 
Ra
IPU0log=it Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[30] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[31] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[32] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[
IPU1log=
HSM0log=
IMU0log=sIntRegister init 173 
RasIntRegister init 185 
RasIntRegister init 197 
RasIntRegister init 284 
RasIntRegister init 314 
starting Ce_Storm Contrl and Ras_Data_Update Task end
MceTableHeadInit start
[0.01.33.589]starting ras en
IPU0log=33] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[34] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[35] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[36] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
To
IPU1log=
HSM0log=
IMU0log=d
[IMU][ERR] skt id 0
Ub init task start Entry ...
[RegisterInterruptSource]:[21] begin
UbInitTask Entry ...
Interrupt 167 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 191 re
IPU0log=tem[0] Core[37] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[38] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[39] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[40] Freq Limit Low[1200000]KHZ Up[23
IPU1log=
HSM0log=
IMU0log=gister OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 171 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 183 register OK
[RegisterInterrupt
IPU0log=00000]KHZ
Totem[0] Core[41] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[42] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[43] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[44] Freq Limit Low[12000
IPU1log=
HSM0log=
IMU0log=Source]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 195 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 207 register OK
[RegisterInterruptSource]:[39] end
Init heart
IPU0log=00]KHZ Up[2300000]KHZ
Totem[0] Core[45] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[46] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
Totem[0] Core[47] Freq Limit Low[1200000]KHZ Up[2300000]KHZ
get tdp value from Product
IPU1log=
HSM0log=
IMU0log=-beat-task end
CS0 flash do not support sfdp!
Current flash device ID[0x61a67c8]!
System supported 1 Flash.
flash cs 0 Manufacture 0xc8, DeviceId 0x1a67, AddrMode[0-3B,1-4B] 0x1:
    size 0x4000000, pagesize 0x100
    read  cmd 
IPU0log=! Tdp value per vdie : 220000 mW!
uncore max freq : 2350 MHz

IPU1log=
HSM0log=
IMU0log=0x13, dummy byte 0x8
    write cmd 0x12, dummy byte 0x0
    erase4k cmd 0x21, erase64k byte 0xdc
sfc init end
firstUnMskExt0Int
ThermalDimmStart Entry ...
wait ddr init done...
HacLowPowerStart Entry ...
Hello LiteOS...
Init 
IPU0log=
IPU1log=
HSM0log=
IMU0log=ReportPcieMmioToBmcTaskEntry end
starting Fpc Isolation Task end
[0.01.53.112]Receive ras int[162]
First coalesce handler start
Type2 status = 0x0
Type1 status = 0x20000
Found error node[17], moduleId[0x51]
Secondary coalesce ha
IPU0log=
IPU1log=
HSM0log=
IMU0log=ndler start
Type2 status = 0x0
Type1 status = 0x8
Found error node[3], moduleId[0x30]
-- RAS DUMP --
Skt[0] Nimbus[0] Module[UCMI] 
Error severity is RECOVERABLE[28001d0000]
ERR_MISC_00 = 0x00000010
Apei not ready
report common 
IPU0log=
IPU1log=
HSM0log=
IMU0log=callback: success
Type0 status = 0x0
Type0 status = 0x0
ras int[162] end

[0.02.44.016]DDR init done
[LOG]head = 0x0, tail = 0x1dc9, logSize = 0x1dc9
[IMU][ERR] HsmLogInit!
[IMU][ERR] HsmLogInit! TRUE
set apei done!
current_addr
IPU0log=
IPU1log=
HSM0log=
IMU0log= = 20 0
HEAD:
47 4c 45 4d 20 0 40 1 20 0 0 0 
ERR DATA:
0 30 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 81 0 0 0 0 0 0 0 0 
UbConfigData size is 64
UbConfigData 0 : 0
UbConfigData 1 : 0
UbConfigData 2 : 0
UbConfigData 3 : 1
UbConfigData
IPU0log=
IPU1log=
HSM0log=
IMU0log= 4 : 31
UbConfigData 5 : 1
UbConfigData 6 : 0
UbConfigData 7 : 32
UbConfigData 8 : 0
UbConfigData 9 : 1
UbConfigData 10 : 2
UbConfigData 11 : 0
UbConfigData 12 : 0
UbConfigData 13 : 1
UbConfigData 14 : 0
UbConfigData 15 : 0
UbCo
IPU0log=
IPU1log=
HSM0log=
IMU0log=nfigData 16 : 0
UbConfigData 17 : 0
UbConfigData 18 : 0
UbConfigData 19 : 0
UbConfigData 20 : 0
UbConfigData 21 : 0
UbConfigData 22 : 11
UbConfigData 23 : 0
UbConfigData 24 : 0
UbConfigData 25 : 0
UbConfigData 26 : 0
UbConfigDat
IPU0log=
IPU1log=
HSM0log=
IMU0log=a 27 : 0
UbConfigData 28 : 0
UbConfigData 29 : 0
UbConfigData 30 : 0
UbConfigData 31 : 0
UbConfigData 32 : 0
UbConfigData 33 : 0
UbConfigData 34 : 2
UbConfigData 35 : 1
UbConfigData 36 : 0
UbConfigData 37 : 0
UbConfigData 38 : 0
IPU0log=
IPU1log=
HSM0log=
IMU0log=
UbConfigData 39 : 0
UbConfigData 40 : 0
UbConfigData 41 : 0
UbConfigData 42 : 0
UbConfigData 43 : 0
UbConfigData 44 : 0
UbConfigData 45 : 0
UbConfigData 46 : 0
UbConfigData 47 : 0
UbConfigData 48 : 0
UbConfigData 49 : 0
UbConfi
IPU0log=
IPU1log=
HSM0log=
IMU0log=gData 50 : 0
UbConfigData 51 : 0
UbConfigData 52 : 0
UbConfigData 53 : 0
ddr init done, start thermal dimm task
======dimm status======
  chl[0] dimm0 1, dimm1 0
  chl[1] dimm0 0, dimm1 0
  chl[2] dimm0 0, dimm1 0
  chl[3] dimm0
IPU0log=
IPU1log=
HSM0log=
IMU0log= 0, dimm1 0
  chl[4] dimm0 0, dimm1 0
  chl[5] dimm0 0, dimm1 0
  chl[6] dimm0 0, dimm1 0
  chl[7] dimm0 0, dimm1 0
  chl[8] dimm0 0, dimm1 0
  chl[9] dimm0 0, dimm1 0
  chl[10] dimm0 0, dimm1 0
  chl[11] dimm0 0, dimm1 0
======
IPU0log=
IPU1log=
HSM0log=
IMU0log=====end==========
sktId[0] chl[0] registered, dimm mask = 0x1
======dimm status======
  chl[0] dimm0 1, dimm1 0
  chl[1] dimm0 0, dimm1 0
  chl[2] dimm0 0, dimm1 0
  chl[3] dimm0 0, dimm1 0
  chl[4] dimm0 0, dimm1 0
  chl[5] dim
IPU0log=
IPU1log=
HSM0log=
IMU0log=m0 0, dimm1 0
  chl[6] dimm0 0, dimm1 0
  chl[7] dimm0 0, dimm1 0
  chl[8] dimm0 0, dimm1 0
  chl[9] dimm0 0, dimm1 0
  chl[10] dimm0 0, dimm1 0
  chl[11] dimm0 0, dimm1 0
==========end==========
sktId[1] chl[0] registered, dimm
IPU0log=
IPU1log=
HSM0log=
IMU0log= mask = 0x1
=====dimm temp params=====
  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
  is_thermal_thro_en  : 1
  is_aref_rate_auto   : 1
===========end============
skt[0] chl[0] max_temp 35'C, aref_rate 0x5 
IPU0log=
IPU1log=
HSM0log=
IMU0log=--> 0x4
skt[1] chl[0] max_temp 37'C, aref_rate 0x5 --> 0x4
UbConfigData 54 : 0
UbConfigData 55 : 0
UbConfigData 56 : 0
UbConfigData 57 : 0
UbConfigData 58 : 0
UbConfigData 59 : 0
UbConfigData 60 : 0
UbConfigData 61 : 0
UbConfigD
IPU0log=
IPU1log=
HSM0log=
IMU0log=ata 62 : 0
UbConfigData 63 : 0
UbConfigData 64 : 0
ClusterSwitch: 0, 0
ClusterMode: 0, 0
ControlMode: 0, 0
EnumMode: 1, 1
BodyMask: 31, 31
CcCtxCount: 256, 256
RcCtxCount: 32, 32
UbMemEntrySize: 128, 0
MctpSupport: 1, 1
SecureMo
IPU0log=
IPU1log=
HSM0log=
IMU0log=de: 0, 0
PrimaryCna: 0, 0
Upi: 0, 0
EntityId: 0, 0
SlotId: 1, 1
SocketId: 2, 2
PortIndex: 0, 0
PortCna: 0, 0
CtrlCna: 11, 11
ImpBootFlag: 2, 2
ImuBootFlag: 1, 1
SktId: 0 DieId:2, HCCS_LINK:2 PaId:2
SktId: 1 DieId:2, HCCS_LINK:0 
IPU0log=
IPU1log=
HSM0log=
IMU0log=PaId:0
CIS register: ID[0xc00007ff], owner[0x1000003], function[0x1045df9c].
CIS register: ID[0xc0000002], owner[0x1000003], function[0x1045e03c].
odf: can not find od file[config]
Do not get NII route table, disable NII Send fu
IPU0log=
IPU1log=
HSM0log=
IMU0log=nction.
UbiosTaskStart Entry ...
UbiosTaskStart create task success
IMU ImpBootFlag: 0x2
skip IMP start config...
UbiosCisTask Entry ...

IPU0log=
IPU1log=
HSM0log=
IMU0log=[0.35.55.611]Receive ras int[162]
First coalesce handler start
Type2 status = 0x0
Type1 status = 0x20000
Found error node[17], moduleId[0x51]
Secondary coalesce handler start
Type2 status = 0x0
Type1 status = 0x8
Found error nod
IPU0log=
IPU1log=
HSM0log=
IMU0log=e[3], moduleId[0x30]
-- RAS DUMP --
Skt[0] Nimbus[0] Module[UCMI] 
Error severity is RECOVERABLE[28001d0000]
ERR_MISC_00 = 0x00000010
Apei not initialed
report common callback: success
CE/NFE happen, recount because the interval
IPU0log=
IPU1log=
HSM0log=
IMU0log= is over 60 seconds.
Type0 status = 0x0
Type0 status = 0x0
ras int[162] end

current_addr = 40 0
HEAD:
47 4c 45 4d 20 0 40 1 40 0 0 0 
ERR DATA:
0 30 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 81 0 0 0 0 0 0 0 0 
[0.35.56.334]TF Heartb
IPU0log=
IPU1log=
HSM0log=
IMU0log=eat Start
[0.35.56.345]Receive ras int[162]
First coalesce handler start
Type2 status = 0x0
Type1 status = 0x20000
Found error node[17], moduleId[0x51]
Secondary coalesce handler start
Type2 status = 0x0
Type1 status = 0x8
Found
IPU0log=
IPU1log=
HSM0log=
IMU0log= error node[3], moduleId[0x30]
-- RAS DUMP --
Skt[0] Nimbus[0] Module[UCMI] 
Error severity is RECOVERABLE[28001d0000]
ERR_MISC_00 = 0x00000010
Apei not initialed
report common callback: success
skt[0], die[2], coalesce[22], nod
IPU0log=
IPU1log=
HSM0log=
IMU0log=eId[3], err_type[1], err_count[2]
Type0 status = 0x0
Type0 status = 0x0
ras int[162] end

[0.35.56.570]Receive ras int[162]
First coalesce handler start
Type2 status = 0x0
Type1 status = 0x20000
Found error node[17], moduleId[0x
IPU0log=
IPU1log=
HSM0log=
IMU0log=51]
Secondary coalesce handler start
Type2 status = 0x0
Type1 status = 0x8
Found error node[3], moduleId[0x30]
-- RAS DUMP --
Skt[0] Nimbus[0] Module[UCMI] 
Error severity is RECOVERABLE[28001d0000]
ERR_MISC_00 = 0x00000010
Apei
IPU0log=
IPU1log=
HSM0log=
IMU0log= not initialed
report common callback: success
skt[0], die[2], coalesce[22], nodeId[3], err_type[1], err_count[3]
Type0 status = 0x0
Type0 status = 0x0
ras int[162] end

current_addr = 60 0
HEAD:
47 4c 45 4d 20 0 40 1 60 0 0 0 
IPU0log=
IPU1log=
HSM0log=
IMU0log=
ERR DATA:
0 30 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 81 0 0 0 0 0 0 0 0 
current_addr = 80 0
HEAD:
47 4c 45 4d 20 0 40 1 80 0 0 0 
ERR DATA:
0 30 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 81 0 0 0 0 0 0 0 0 

IPU0log=
IPU1log=
HSM0log=
IMU0log=[0.43.24.958]Receive ras int[162]
First coalesce handler start
Type2 status = 0x0
Type1 status = 0x20000
Found error node[17], moduleId[0x51]
Secondary coalesce handler start
Type2 status = 0x0
Type1 status = 0x8
Found error nod
IPU0log=
IPU1log=
HSM0log=
IMU0log=e[3], moduleId[0x30]
-- RAS DUMP --
Skt[0] Nimbus[0] Module[UCMI] 
Error severity is RECOVERABLE[28001d0000]
ERR_MISC_00 = 0x00000010
report to os
report common callback: success
CE/NFE happen, recount because the interval is o
IPU0log=
IPU1log=
HSM0log=
IMU0log=ver 60 seconds.
Type0 status = 0x0
Type0 status = 0x0
ras int[162] end

[0.43.25.190]Receive ras int[162]
First coalesce handler start
Type2 status = 0x0
Type1 status = 0x20000
Found error node[17], moduleId[0x51]
Secondary coa
IPU0log=
IPU1log=
HSM0log=
IMU0log=lesce handler start
Type2 status = 0x0
Type1 status = 0x8
Found error node[3], moduleId[0x30]
-- RAS DUMP --
Skt[0] Nimbus[0] Module[UCMI] 
Error severity is RECOVERABLE[28001d0000]
ERR_MISC_00 = 0x00000010
report to os
report 
IPU0log=
IPU1log=
HSM0log=
IMU0log=common callback: success
skt[0], die[2], coalesce[22], nodeId[3], err_type[1], err_count[2]
Type0 status = 0x0
Type0 status = 0x0
ras int[162] end

current_addr = a0 0
HEAD:
47 4c 45 4d 20 0 40 1 a0 0 0 0 
ERR DATA:
0 30 10 0
IPU0log=
IPU1log=
HSM0log=
IMU0log= 0 0 0 0 0 0 0 0 0 0 0 0 0 81 0 0 0 0 0 0 0 0 
current_addr = c0 0
HEAD:
47 4c 45 4d 20 0 40 1 c0 0 0 0 
ERR DATA:
0 30 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 81 0 0 0 0 0 0 0 0 
[0.43.58.448]Receive ras int[162]
First coalesce han
IPU0log=
IPU1log=
HSM0log=
IMU0log=dler start
Type2 status = 0x0
Type1 status = 0x20000
Found error node[17], moduleId[0x51]
Secondary coalesce handler start
Type2 status = 0x0
Type1 status = 0x8
Found error node[3], moduleId[0x30]
-- RAS DUMP --
Skt[0] Nimbus[0]
IPU0log=
IPU1log=
HSM0log=
IMU0log= Module[UCMI] 
Error severity is RECOVERABLE[28001d0000]
ERR_MISC_00 = 0x00000010
report to os
report common callback: success
skt[0], die[2], coalesce[22], nodeId[3], err_type[1], err_count[3]
Type0 status = 0x0
Type0 status =
IPU0log=
IPU1log=
HSM0log=
IMU0log= 0x0
ras int[162] end

[0.43.58.645]PCIE INIT DONE.
[IMU][ERR] LOS_SemPend(g_pcieSemaphore, LOS_WAIT_FOREVER)
[RegisterInterruptSource]:[21] begin
Interrupt 258 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterrupt
IPU0log=
IPU1log=
HSM0log=
IMU0log=Source]:[21] begin
Interrupt 262 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
Interrupt 266 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
[0.43.58
IPU0log=
IPU1log=
HSM0log=
IMU0log=.717]Receive ras int[162]
First coalesce handler start
Type2 status = 0x0
Type1 status = 0x20000
Found error node[17], moduleId[0x51]
Secondary coalesce handler start
Type2 status = 0x0
Type1 status = 0x8
Found error node[3], mo
IPU0log=
IPU1log=
HSM0log=
IMU0log=duleId[0x30]
-- RAS DUMP --
Skt[0] Nimbus[0] Module[UCMI] 
Error severity is RECOVERABLE[28001d0000]
ERR_MISC_00 = 0x00000010
report to os
report common callback: success
skt[0], die[2], coalesce[22], nodeId[3], err_type[1], er
IPU0log=
IPU1log=
HSM0log=
IMU0log=r_count[4]
Type0 status = 0x0
Type0 status = 0x0
ras int[162] end

Interrupt 270 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
current_addr = e0 0
HEAD:
47 4c 45 4d 20 0 Interrupt 277 reg
IPU0log=
IPU1log=
HSM0log=
IMU0log=ister OK
40 1 e0 0 0 0 [RegisterInterruptSource]:[39] end

ERR DATA:
0 [RegisterInterruptSource]:[21] begin
30 10 0 0 0 0 0 0 0 Interrupt 288 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] beg
IPU0log=
IPU1log=
HSM0log=
IMU0log=in
Interrupt 292 register OK
[RegisterInterruptSource]:[39] end
[RegisterInterruptSource]:[21] begin
0 0 0 0 0 0 0 81 0 Interrupt 296 register OK
0 0 0 0 0 [RegisterInterruptSource]:[39] end
0 0 
[RegisterInterruptSource]:[
IPU0log=
IPU1log=
HSM0log=
IMU0log=21] begin
Interrupt 300 register OK
[RegisterInterruptSource]:[39] end
current_addr = 0 1
HEAD:
[RegisterInterruptSource]:[21] begin
47 4c 45 4d 20 0 40 Interrupt 307 register OK
1 0 1 0 0 [RegisterInterruptSource]:[39] end
IPU0log=
IPU1log=
HSM0log=
IMU0log=
pmt Init done


ERR DATA:
0 30 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 81 0 0 0 0 0 0 0 0 

IPU0log=
IPU1log=
HSM0log=
IMU0log=[0.48.24.656]Receive ras int[162]
First coalesce handler start
Type2 status = 0x0
Type1 status = 0x20000
Found error node[17], moduleId[0x51]
Secondary coalesce handler start
Type2 status = 0x0
Type1 status = 0x8
Found error nod
IPU0log=
IPU1log=
HSM0log=
IMU0log=e[3], moduleId[0x30]
-- RAS DUMP --
Skt[0] Nimbus[0] Module[UCMI] 
Error severity is RECOVERABLE[28001d0000]
ERR_MISC_00 = 0x00000010
report to os
report common callback: success
CE/NFE happen, recount because the interval is o
IPU0log=
IPU1log=
HSM0log=
IMU0log=ver 60 seconds.
Type0 status = 0x0
Type0 status = 0x0
ras int[162] end

[0.48.25.159]Receive ras int[162]
First coalesce handler start
Type2 status = 0x0
Type1 status = 0x20000
Found error node[17], moduleId[0x51]
Secondary coa
IPU0log=
IPU1log=
HSM0log=
IMU0log=lesce handler start
Type2 status = 0x0
Type1 status = 0x8
Found error node[3], moduleId[0x30]
-- RAS DUMP --
Skt[0] Nimbus[0] Module[UCMI] 
Error severity is RECOVERABLE[28001d0000]
ERR_MISC_00 = 0x00000010
report to os
report 
IPU0log=
IPU1log=
HSM0log=
IMU0log=common callback: success
skt[0], die[2], coalesce[22], nodeId[3], err_type[1], err_count[2]
Type0 status = 0x0
Type0 status = 0x0
ras int[162] end

current_addr = 20 1
HEAD:
47 4c 45 4d 20 0 40 1 20 1 0 0 
ERR DATA:
0 30 10 0
IPU0log=
IPU1log=
HSM0log=
IMU0log= 0 0 0 0 0 0 0 0 0 0 0 0 0 81 0 0 0 0 0 0 0 0 
current_addr = 20 0
HEAD:
47 4c 45 4d 20 0 40 1 20 0 0 0 
ERR DATA:
0 30 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 81 0 0 0 0 0 0 0 0 

IPU0log=
IPU1log=
HSM0log=
IMU0log=[0.52.03.285]Receive ras int[162]
First coalesce handler start
Type2 status = 0x0
Type1 status = 0x20000
Found error node[17], moduleId[0x51]
Secondary coalesce handler start
Type2 status = 0x0
Type1 status = 0x8
Found error nod
IPU0log=
IPU1log=
HSM0log=
IMU0log=e[3], moduleId[0x30]
-- RAS DUMP --
Skt[0] Nimbus[0] Module[UCMI] 
Error severity is RECOVERABLE[28001d0000]
ERR_MISC_00 = 0x00000010
report to os
report common callback: success
CE/NFE happen, recount because the interval is o
IPU0log=
IPU1log=
HSM0log=
IMU0log=ver 60 seconds.
Type0 status = 0x0
Type0 status = 0x0
ras int[162] end

current_addr = 40 0
HEAD:
47 4c 45 4d 20 0 40 1 40 0 0 0 
ERR DATA:
0 30 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 81 0 0 0 0 0 0 0 0 

IPU0log=
IPU1log=
HSM0log=