IRQ                                                   COUNT     STAT  PENDING
SEC_ERR                                                   0        R        -
ADDR_ALIGN_ERR                                            0        R        -
ADDR_RSVD_ERR                                             0        R        -
SIZE_ERR                                                  0        R        -
CLK_PIPE_LOC                                              0        D        P
CLK_U2PHY_LOC                                             0        D        -
TIME_OUT                                                  0        R        -
CSR_LMI_RCH_SLVERR                                        0        R        -
CSR_LMI_WCH_SLVERR                                        0        R        -
CSR_LMI_RCH_DECERR                                        0        R        -
CSR_LMI_WCH_DECERR                                        0        R        -
CSR_LMI_RCH_TIMEOUT                                       0        D        -
CSR_LMI_WCH_TIMEOUT                                       0        R        -
USBC_AXI_RUSER_POISON_ERR                                 0        R        -
CSR_LMI_RCH_NULL_CMD                                      0        R        -
CSR_LMI_WCH_NULL_CMD                                      0        R        -
ERPU_ETRB_FIFO_FULL                                       0        R        -
ERPU_TRBNUM_SZERR                                         0        R        -
DEV_ERPU_EBSZ_ZERO_ERR                                    0        R        -
HOST_ERPU_ERSTSZ_ZERO_ERR                                 0        R        -
ERPU_TOPCSR_TARGET_INVALID                                0        R        -
DMA_WCH4_RSP_FIFO_UNDERFLOW                               0        R        -
DMA_WCH4_RSP_FIFO_OVERFLOW                                0        R        -
DMA_WCMD_SLOT_OVERFLOW                                    0        R        -
DMA_WCH3_RSP_FIFO_UNDERFLOW                               0        R        -
DMA_WCH3_RSP_FIFO_OVERFLOW                                0        R        -
DMA_WCH2_RSP_FIFO_UNDERFLOW                               0        R        -
DMA_WCH2_RSP_FIFO_OVERFLOW                                0        R        -
DMA_WCH1_RSP_FIFO_UNDERFLOW                               0        R        -
DMA_WCH1_RSP_FIFO_OVERFLOW                                0        R        -
DMA_WCH0_RSP_FIFO_UNDERFLOW                               0        R        -
DMA_WCH0_RSP_FIFO_OVERFLOW                                0        R        -
DMA_WRSP_ASYN_OVERFLOW                                    0        R        -
DMA_WDATA_ASYN_OVERFLOW                                   0        R        -
DMA_WCMD_ASYN_FIFO_OVERFLOW                               0        R        -
DMA_RCH4_SYNC_DATA_FIFO_UNDERFLOW                         0        R        -
DMA_RCH4_SYNC_DATA_FIFO_OVERFLOW                          0        R        -
DMA_RCH4_RCMD_SLOT_OVERFLOW                               0        R        -
DMA_RCH1_RCMD_SLOT_OVERFLOW                               0        R        -
DMA_RCH0_RCMD_SLOT_OVERFLOW                               0        R        -
DMA_RCH0_SYNC_DATA_FIFO_UNDERFLOW                         0        R        -
DMA_RCH0_SYNC_DATA_FIFO_OVERFLOW                          0        R        -
DMA_RCH123_DATA_FIFO_UNDERFLOW                            0        R        -
DMA_RCH123_DATA_FIFO_OVERFLOW                             0        R        -
DMA_RDATA_ASYN_OVERFLOW                                   0        R        -
DMA_RCMD_ASYN_OVERFLOW                                    0        R        -
MPI_BMU_ADDR_ERR                                          0        R        -
MPI_BMU_TIMEOUT_ALERT                                     0        R        -
EPQ_RADDR_ERR                                             0        D        -
EPQ_WADDR_ERR                                             0        R        -
RBUF_RADDR_ERR                                            0        R        -
RBUF_WADDR_ERR                                            0        R        -
WBUF_RADDR_ERR                                            0        R        -
WBUF_WADDR_ERR                                            0        R        -
RXFIFO_RADDR_ERR                                          0        R        -
RXFIFO_WADDR_ERR                                          0        R        -
TXFIFO_RADDR_ERR                                          0        R        -
TXFIFO_WADDR_ERR                                          0        R        -
BMU_RBUF_WADDR_ERR                                        0        R        -
BMU_RBUF_RADDR_ERR                                        0        R        -
BMU_WBUF_WADDR_ERR                                        0        R        -
BMU_WBUF_RADDR_ERR                                        0        R        -
BME_ERR                                                   0        R        -
SUSPEND_EVENT_HOLD_PULSE                                  0        R        -
ECC_MBIT_ERR_RAM4                                         0        R        -
ECC_MBIT_ERR_RAM3                                         0        R        -
ECC_MBIT_ERR_RAM2                                         0        R        -
ECC_MBIT_ERR_RAM1                                         0        R        -
ECC_MBIT_ERR_RAM0                                         0        R        -
CSR_ULPI_TX_PKT_TOUT                                      0        D        -
