02 mV
3>power domain[14] volt = 1203 mV
3>power domain[4] volt =  802 mV
3>power domain[11] volt =  904 mV
3>power domain[10] volt =  904 mV
3>power domain[16] volt = 1203 mV
3>power domain[2] volt = 1101 mV
3>power domain[3] volt =  949 mV
3>power domain[12] volt =  804 mV
3>power domain[6] volt = 1105 mV
3>===============end===============
3>the power sensor : manu id = 2peak, die id = TPA626
3>power sensor[0] init success
3>die[0] its[0] init done
3>die[0] its[1] init done
3>die[0] its[2] init done
3>die[0] its[3] init done
3>die[0] its[4] init done
3>die[0] its[5] init done
3>die[0] its[6] init done
3>die[0] its[7] init done
3>die[0] its[8] init done
3>die[0] its[9] init done
3>die[1] its[0] init done
3>die[1] its[1] init done
3>die[1] its[2] init done
3>die[1] its[3] init done
3>die[1] its[4] init done
3>die[1] its[5] init done
3>die[1] its[6] init done
3>die[1] its[7] init done
3>die[1] its[8] init done
3>die[1] its[9] init done
3>Totem[0] Core Boot Vol [1101]mv
3>Totem[0] Core Current Vol [1100]mv
3>Totem[1] Core Boot Vol [1103]mv
3>Totem[1] Core Current Vol [1100]mv
3>NA 1620V1a0
3>NB 1620V1a0
3>GetCoreBaseFreq [2500000KHZ]
3>GetCoreTurboFreq [2500000KHZ]
3>GetCustomClusterNum [10]
3>Ipu ACG Training Done!
3>AP Last Time:[0.00.01.720]
3>wait UEFI pll init...
3>done
3>acg trim start
3>core trim freq:2000, avs:0 volt:810mv
3>core trim freq:2000, avs:0 volt:810mv
3>core trim freq:2050, avs:1 volt:810mv
3>core trim freq:2050, avs:1 volt:810mv
3>core trim freq:2100, avs:2 volt:810mv
3>core trim freq:2100, avs:2 volt:810mv
3>core trim freq:2150, avs:3 volt:810mv
3>core trim freq:2150, avs:3 volt:810mv
3>core trim freq:2200, avs:4 volt:810mv
3>core trim freq:2200, avs:4 volt:811mv
3>core trim freq:2250, avs:5 volt:820mv
3>core trim freq:2250, avs:5 volt:824mv
3>core trim freq:2300, avs:6 volt:833mv
3>core trim freq:2300, avs:6 volt:836mv
3>core trim freq:2350, avs:7 volt:845mv
3>core trim freq:2350, avs:7 volt:849mv
3>core trim freq:2400, avs:8 volt:858mv
3>core trim freq:2400, avs:8 volt:862mv
3>core trim freq:2450, avs:9 volt:870mv
3>core trim freq:2450, avs:9 volt:874mv
3>core trim freq:2500, avs:10 volt:883mv
3>core trim freq:2500, avs:10 volt:887mv
3>core trim freq:2550, avs:11 volt:895mv
3>core trim freq:2550, avs:11 volt:900mv
3>core trim freq:2600, avs:12 volt:908mv
3>core trim freq:2600, avs:12 volt:912mv
3>core trim freq:2650, avs:13 volt:920mv
3>core trim freq:2650, avs:13 volt:925mv
3>core trim freq:2700, avs:14 volt:933mv
3>core trim freq:2700, avs:14 volt:938mv
3>core trim freq:2750, avs:15 volt:951mv
3>core trim freq:2750, avs:15 volt:956mv
3>core trim freq:2800, avs:16 volt:969mv
3>core trim freq:2800, avs:16 volt:974mv
3>core trim freq:2850, avs:17 volt:987mv
3>core trim freq:2850, avs:17 volt:992mv
3>core trim freq:2900, avs:18 volt:1005mv
3>core trim freq:2900, avs:18 volt:1011mv
3>core trim freq:2950, avs:19 volt:1022mv
3>core trim freq:2950, avs:19 volt:1028mv
3>core trim freq:3000, avs:20 volt:1039mv
3>core trim freq:3000, avs:20 volt:1045mv
3>core trim freq:3050, avs:21 volt:1053mv
3>core trim freq:3050, avs:21 volt:1058mv
3>core trim freq:3100, avs:22 volt:1067mv
3>core trim freq:3100, avs:22 volt:1072mv
3>acg trim end
3>LDO disabled
3>[TracePoint] type[  0] cmd[  2] data[  3]
3>Interrupt 423 register OK
3>Interrupt 430 register OK
3>[TracePoint] type[  0] cmd[  2] data[  4]
3>
3>cpu 0 entering scheduler
3>[TracePoint] type[  0] cmd[  3] data[  1]
3>add your ipu app init here!
3>IpuInterfaceTaskStart Entry ...
3>ipu interface task wait parameters from uefi...
3>thermal soc task enabled
3>AP Last Time:[0.00.41.050]
3>ThermalDimmStart Entry ...
3>wait ddr init done...
3>power task start...
3>[TracePoint] type[  0] cmd[  3] data[  2]
3>ufs task wait parameters from uefi...
3>AmuTaskStart Entry ... 
3>amu task wait parameters from uefi...
3>ThermalSiwStart Entry ...
3>ThermalSiwTask idle...
3>DemtTaskStart Entry ...
3>[TracePoint] type[  0] cmd[  3] data[  3]
3>HiBoostTaskStart Entry ...
3>HiBoost task enabled
3>Waiting for UEFI parameters...
3>[TracePoint] type[  0] cmd[  3] data[  4]
3>demt task wait parameters from uefi...
3>AgeTaskStart Entry ...
3>age task wait parameters from uefi...
3>[TracePoint] type[  0] cmd[  3] data[  5]
3>uefi parameters ready!
3>UFSProfile[0]
3>PowerPolicy[0] BenchMarkSelection[0]
3>ipu interface task wait ddr init done from uefi...
3>ufs task parameters from uefi ready
3>uncore domain[0] freq:2900
3>uncore domain[1] freq:2900
3>thermal soc task restore underclocking_en=1
3>ppu alert temp div init done
3>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
3>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
3>======sioe status======
3>TA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
3>TA_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
3>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
3>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
3>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
3>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
3>==========end==========
3>sioe init done
3>ufs task disabled
3>UEFI parameters ready
3>UncoreMaxFreq Set to [2900 MHZ]
3>get TDP from efuse success, value = 307500mw
3>target power set to [307500]mw, brd:[307500]
3>age task parameters from uefi ready
3>age task enabled
3>demt task parameters from uefi ready
0>uefi ddr init finish!
0>ipu interface task wait uefi end done from uefi...
0>ddr init done, start thermal dimm task
0>======dimm status======
0>  chl[0] dimm0 0, dimm1 0
0>  chl[1] dimm0 0, dimm1 0
0>  chl[2] dimm0 2, dimm1 0
0>  chl[3] dimm0 0, dimm1 0
0>  chl[4] dimm0 0, dimm1 0
0>  chl[5] dimm0 0, dimm1 0
0>  chl[6] dimm0 0, dimm1 0
0>  chl[7] dimm0 0, dimm1 0
0>==========end==========
0>chl[2] registered, dimm mask = 0x1
0>=====dimm temp params=====
0>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
0>  is_thermal_thro_en  : 1
0>  is_aref_rate_auto   : 1
0>===========end============
1>uefi ddr init finish!
1>ipu interface task wait uefi end done from uefi...
1>ddr init done, start thermal dimm task
1>======dimm status======
1>  chl[0] dimm0 0, dimm1 0
1>  chl[1] dimm0 0, dimm1 0
1>  chl[2] dimm0 0, dimm1 0
1>  chl[3] dimm0 0, dimm1 0
1>  chl[4] dimm0 0, dimm1 0
1>  chl[5] dimm0 0, dimm1 0
1>  chl[6] dimm0 0, dimm1 0
1>  chl[7] dimm0 0, dimm1 0
1>==========end==========
1>=====dimm temp params=====
1>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
1>  is_thermal_thro_en  : 1
1>  is_aref_rate_auto   : 1
1>===========end============
2>uefi ddr init finish!
2>ipu interface task wait uefi end done from uefi...
2>ddr init done, start thermal dimm task
2>======dimm status======
2>  chl[0] dimm0 0, dimm1 0
2>  chl[1] dimm0 0, dimm1 0
2>  chl[2] dimm0 2, dimm1 0
2>  chl[3] dimm0 0, dimm1 0
2>  chl[4] dimm0 0, dimm1 0
2>  chl[5] dimm0 0, dimm1 0
2>  chl[6] dimm0 0, dimm1 0
2>  chl[7] dimm0 0, dimm1 0
2>==========end==========
2>chl[2] registered, dimm mask = 0x1
2>=====dimm temp params=====
2>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
2>  is_thermal_thro_en  : 1
2>  is_aref_rate_auto   : 1
2>===========end============
3>uefi ddr init finish!
3>ipu interface task wait uefi end done from uefi...
3>ddr init done, start thermal dimm task
3>======dimm status======
3>  chl[0] dimm0 0, dimm1 0
3>  chl[1] dimm0 0, dimm1 0
3>  chl[2] dimm0 0, dimm1 0
3>  chl[3] dimm0 0, dimm1 0
3>  chl[4] dimm0 0, dimm1 0
3>  chl[5] dimm0 0, dimm1 0
3>  chl[6] dimm0 0, dimm1 0
3>  chl[7] dimm0 0, dimm1 0
3>==========end==========
3>=====dimm temp params=====
3>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
3>  is_thermal_thro_en  : 1
3>  is_aref_rate_auto   : 1
3>===========end============
[0.01.11.346]DDR Rreserved for IMU: len = 3e00000
[LOG]head = 0x0, tail = 0x4f35, logSize = 0x4f35
copy registry.json file success
Set component all release version to sram end.
ipcMsgSend success
[0.01.11.388]starting ras Init
nodeId = 0, dieId = 0, isSasExist = 0.
nodeId = 0, dieId = 2, isSasExist = 0.
nodeId = 1, dieId = 0, isSasExist = 0.
nodeId = 1, dieId = 2, isSasExist = 0.
nodeId = 2, dieId = 0, isSasExist = 0.
nodeId = 2, dieId = 2, isSasExist = 0.
nodeId = 3, dieId = 0, isSasExist = 0.
nodeId = 3, dieId = 2, isSasExist = 0.
Mce Table head exist!
RasIntRegister init 452 
RasIntRegister init 453 
RasIntRegister init 64 
RasIntRegister init 65 
RasIntRegister init 465 
RasIntRegister init 466 
RasIntRegister init 86 
RasIntRegister init 87 
RasIntRegister init 478 
RasIntRegister init 479 
RasIntRegister init 108 
RasIntRegister init 109 
RasIntRegister init 491 
RasIntRegister init 492 
RasIntRegister init 130 
RasIntRegister init 131 
RasIntRegister init 504 
RasIntRegister init 505 
RasIntRegister init 152 
RasIntRegister init 153 
RasIntRegister init 517 
RasIntRegister init 518 
RasIntRegister init 174 
RasIntRegister init 175 
RasIntRegister init 530 
RasIntRegister init 531 
RasIntRegister init 196 
RasIntRegister init 197 
RasIntRegister init 543 
RasIntRegister init 544 
RasIntRegister init 218 
RasIntRegister init 219 
RasIntRegister init 76 
RasIntRegister init 98 
RasIntRegister init 120 
RasIntRegister init 142 
RasIntRegister init 164 
RasIntRegister init 186 
RasIntRegister init 208 
RasIntRegister init 230 
[0.01.11.509]starting ras end


HSM_LOG:
[00:00:00.000][info] succeed to do thirdparty dfx_pabuk init
[00:00:00.000][info] succeed to do thirdparty crypto_driver init




HSM_LOG:
[00:00:00.010][info] os_mem_system_init default pool done
[00:00:00.016][info] succeed to do thirdparty otpc_pabuk init
[00:00

0>chl[2] max_temp 35'C, aref_rate 0x5 --> 0x4
2>chl[2] max_temp 35'C, aref_rate 0x5 --> 0x4


HSM_LOG:
:00.017][info] succeed to do thirdparty boot_profile_driver init
[00:00:00.017][info] succeed to do thirdparty measure_value_ma



HSM_LOG:
nage_driver init
[00:00:00.018][info] succeed to do thirdparty period_driver init
[00:00:00.018][info]  start loading internal



HSM_LOG:
 task ...
[00:00:00.018][info]  task name is ccm_task
[00:00:00.019][info]  hm_dynamic_loadelf successfully!
[00:00:00.019][i



HSM_LOG:
nfo] internal task[1] task_name=ccm_task load successfully
[00:00:00.020][info]  task name is upgrade_task
[00:00:00.020][info



HSM_LOG:
]  hm_dynamic_loadelf successfully!
[00:00:00.021][info] internal task[2] task_name=upgrade_task load successfully
[00:00:00.0



HSM_LOG:
22][info]  task name is hes_task
[00:00:00.022][info]  hm_dynamic_loadelf successfully!
[00:00:00.023][info] internal task[3] 



HSM_LOG:
task_name=hes_task load successfully
[00:00:00.024][info] created task ccm_task success!
[00:00:00.025][info] created task upg

[0.01.30.415][ERR]cmd not support! cmd = 0xd


HSM_LOG:
rade_task success!
[00:00:00.026][info] created task hes_task success!
[00:00:00.026][info] Init start.
[1970-01-01 00:00:00.



HSM_LOG:
027][HSM][INFO][54] Platform init 0x20250523 0x4e.

[1970-01-01 00:00:00.027][HSM][INFO][197] ccm start.

[1970-01-01 00:00:00



HSM_LOG:
.028][HSM][INFO][86] upgrade task init success.

[1970-01-01 00:00:00.028][HSM][INFO][95] upgrade recv cmd, 0x181.

[1970-01-0



HSM_LOG:
1 00:00:00.029][HSM][INFO][103] upgrade res, 0x3a5aa5a3.

[1970-01-01 00:00:00.030][HSM][INFO][75] hes tee_task_entry.

[1970-



HSM_LOG:
01-01 00:00:00.551][HSM][INFO][44] hes init success.

[00:00:00.551][info] Init over.


[0.01.40.689]TF Heartbeat Start
[0.01.45.321]PCIE INIT DONE.
g_mctpQueueCount(48) > tabCnt(42)
Interrupt 454 register OK
Interrupt 467 register OK
Interrupt 480 register OK
Interrupt 493 register OK
Interrupt 506 register OK
Interrupt 519 register OK
Interrupt 532 register OK
Interrupt 545 register OK
data = 0x0
pmt Init done

Add ep: bdf=5500 eid=9 epCnt=1 eid_alloc=a
Add ep: bdf=300 eid=a epCnt=1 eid_alloc=b
mctp task ok.
[0.02.16.455]Receive ras int[491]
First coalesce handler start
Type2 status = 0x0
Type1 status = 0x4
Found error node[2]
False alarm reporting!
Type0 status = 0x0
ras int[491] end

[0.02.44.561]BIOS POST END.
Create SetReportPcieMmioToBmc ok.
Start SetReportPcieMmioToBmc ok.
slotNum = 0x14
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[0] port:20  pcieSlotCtrl.data (after)0x4801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[1] port:24  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[2] port:26  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[3] port:32  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[4] port:0  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[5] port:24  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[6] port:26  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[7] port:20  pcieSlotCtrl.data (after)0x4801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[8] port:22  pcieSlotCtrl.data (after)0x4801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[9] port:24  pcieSlotCtrl.data (after)0x4801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[10] port:26  pcieSlotCtrl.data (after)0x4801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[11] port:32  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[12] port:34  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[13] port:36  pcieSlotCtrl.data (after)0x4801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[14] port:38  pcieSlotCtrl.data (after)0x4801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[15] port:0  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[16] port:12  pcieSlotCtrl.data (after)0x4801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[17] port:14  pcieSlotCtrl.data (after)0x4801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[18] port:16  pcieSlotCtrl.data (after)0x4801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[19] port:18  pcieSlotCtrl.data (after)0x4801c0.

1>uefi end finish!
1>ipu interface task exit!
1>amu task parameters from uefi ready
3>uefi end finish!
3>ipu interface task exit!
3>amu task parameters from uefi ready
0>uefi end finish!
0>ipu interface task exit!
0>amu task parameters from uefi ready
2>uefi end finish!
2>ipu interface task exit!
2>amu task parameters from uefi ready
Enter current value process
1>amu task activated
1>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
3>amu task activated
3>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
0>amu task activated
0>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
2>amu task activated
2>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
[0.07.44.560]IpmiCmdReportPcieMMIO start
[0.08.08.138]IpmiCmdReportPcieMMIO end
pool addr          pool size    used size     free size    max free node size   used node num     free node num      UsageWaterLine
---------------    --------     -------       --------     --------------       -------------      ------------      ------------
0x840908e708       0x204c0      0x1a010       0x6240       0x5ad0               0xd9               0x3                0x1a9f0        

********Hello Huawei LiteOS********

KpxxxxIMU Firmware Version : V32.70.0
LiteOS Kernel Version : 5.7.0
Run on ChipVersion[0] Node[0] Die[2]
build time : Feb 05 2026 20:30:00

**********************************

main core booting up...
start set affinity

mpidr = 0x81020000
sram ecc state: 0x0, sram ecc cnt: 0x0
[0.00.00.033]node 0 begins init all serdes.
BoardInfo->NodeNum 4.
BoardInfo->NodeId 0.
BoardInfo->InfoVersion 5.
BoardInfo->NASerdesSceneMode 3.
BoardInfo->NBSerdesSceneMode 3.
BoardInfo->HccsTopologyType 7.
BoardInfo->BoardId 0.
ChipVersionIsPro: 1.
BoardInfo Node 0, SerdesUseMode: 1 2 12 4 4 4 4  1 1 1 4 4 1 1 
BoardInfo Node 1, SerdesUseMode: 1 1 1 4 4 1 1  12 13 1 4 4 4 4 
BoardInfo Node 2, SerdesUseMode: 12 13 12 4 4 4 4  1 1 1 4 4 1 1 
BoardInfo Node 3, SerdesUseMode: 1 1 1 4 4 1 1  12 13 1 4 4 4 4 
BoardInfo Node 0, SerdesRxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 255 255 
BoardInfo Node 1, SerdesRxPolarityReverse: 255 255 255 0 0 255 255  0 0 0 0 0 0 0 
BoardInfo Node 2, SerdesRxPolarityReverse: 0 0 0 0 0 0 0  0 0 255 0 0 0 255 
BoardInfo Node 3, SerdesRxPolarityReverse: 255 255 255 0 0 0 0  0 0 255 0 0 0 0 
BoardInfo Node 0, SerdesTxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 255 255 
BoardInfo Node 1, SerdesTxPolarityReverse: 255 255 255 0 0 255 255  0 0 0 0 0 0 0 
BoardInfo Node 2, SerdesTxPolarityReverse: 0 0 0 0 0 0 0  0 0 255 0 0 0 0 
BoardInfo Node 3, SerdesTxPolarityReverse: 255 255 255 0 0 0 0  0 0 255 0 0 0 0 
serdessdk version: 2.0_5.0_20241203_imu
node_id 0, die 0, ind 0, usemode 1 begin serdes-init.
node_id 0, die 0, ind 1, usemode 2 begin serdes-init.
node_id 0, die 0, ind 2, usemode 12 begin serdes-init.
chip_id 0, die 0, ind 2, usemode 12 don't support, power down macro!
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
node_id 0, die 2, ind 0, usemode 1 begin serdes-init.
node_id 0, die 2, ind 1, usemode 1 begin serdes-init.
chip serdes init status:0x0.
[0.00.00.478]node 0 ends init all serdes.
link[0] freq_type:1 | peer_chip_type:1 | peer_node_id:1 | peer_link_id:6
link[1] freq_type:1 | peer_chip_type:1 | peer_node_id:1 | peer_link_id:7
link[2] freq_type:1 | peer_chip_type:1 | peer_node_id:1 | peer_link_id:4
link[3] freq_type:1 | peer_chip_type:1 | peer_node_id:1 | peer_link_id:5
link[4] freq_type:1 | peer_chip_type:1 | peer_node_id:3 | peer_link_id:0
link[5] freq_type:1 | peer_chip_type:1 | peer_node_id:2 | peer_link_id:4
register hccs done
nodeId 0, dieId 0, linkId 0, FFE info: fir_pre1 0, fir_main 63, fir_post1 0
node_id 0, die 0, ind 4, usemode 4 begin serdes-init.
nodeId 0, dieId 0, linkId 1, FFE info: fir_pre1 0, fir_main 63, fir_post1 0
node_id 0, die 0, ind 3, usemode 4 begin serdes-init.
nodeId 0, dieId 0, linkId 2, FFE info: fir_pre1 0, fir_main 63, fir_post1 0
node_id 0, die 0, ind 5, usemode 4 begin serdes-init.
nodeId 0, dieId 0, linkId 3, FFE info: fir_pre1 0, fir_main 63, fir_post1 0
node_id 0, die 0, ind 6, usemode 4 begin serdes-init.
node_id 0, die 2, ind 4, usemode 4 begin serdes-init.
node_id 0, die 2, ind 3, usemode 4 begin serdes-init.
hccs init start...
pa ring link down success
reset pa success
link[0] pcs init success
link[1] pcs init success
link[2] pcs init success
link[3] pcs init success
link[4] pcs init success
link[5] pcs init success
release reset pa success
link[0] macro adapt done (lane_mask=0xff) (0ms)
link[1] macro adapt done (lane_mask=0xff) (0ms)
link[2] macro adapt done (lane_mask=0xff) (0ms)
link[3] macro adapt done (lane_mask=0xff) (0ms)
link[4] macro adapt done (lane_mask=0xff) (0ms)
link[5] macro adapt done (lane_mask=0xff) (0ms)
link[0] pcs training success (10ms)
link[1] pcs training success (10ms)
link[2] pcs training success (10ms)
link[3] pcs training success (10ms)
link[4] pcs training success (10ms)
link[5] pcs training success (10ms)
link[0] training success (20ms)
link[1] training success (20ms)
link[2] training success (20ms)
link[3] training success (20ms)
link[4] training success (20ms)
link[5] training success (20ms)
link[0]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link[1]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link[2]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link[3]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link[4]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link[5]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link training success
pa[0] linkEn = 0xf
pa[0] allNodeLink0 = 0xf0
pa[0] allNodeLink1 = 0x0
pa[1] linkEn = 0x3
pa[1] allNodeLink0 = 0x1200
pa[1] allNodeLink1 = 0x0
pa init success
COM_PAID_INTLV_REG = 0xc
paid decode init success
pa[0] PA_PM_BASE_INFO = 0xff8421
pa[0] PA_PM_MAP_LINK_NUM = 0x2184
pa[1] PA_PM_BASE_INFO = 0x330021
pa[1] PA_PM_MAP_LINK_NUM = 0x11
hccs performace config success
pa ring link up success
hccs init done
hccs access test start
node[0] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[1] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[2] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[3] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[1] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
node[2] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
node[3] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
hccs access test success
======hccs status======
  node[0] mask: expected = 0x3f, link up = 0x3f, width reduction = 0x0, link down = 0x0
  node[1] mask: expected = 0xf3, link up = 0xf3, width reduction = 0x0, link down = 0x0
  node[2] mask: expected = 0x3f, link up = 0x3f, width reduction = 0x0, link down = 0x0
  node[3] mask: expected = 0xf3, link up = 0xf3, width reduction = 0x0, link down = 0x0
==========end==========
report hccs status success
node[0] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
LRDXSD_LOCK_OFFSET = 0x0
LRDXSD_ERRIMSK_OFFSET = 0x0
LRDXSD_DBG_OTIMSK_OFFSET = 0x0
LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
LRDXSD_DBG_EN_OFFSET = 0x1
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
ID[0x3a25c2]!
ID[0x0]!
[ERR]Don't support the flash, CS[1] ID[0x0]!!
sfdp detect, try to get dummy data from hboot1 first.
ID[0x3a25c2]!
flash 0 support sfdp.
Interrupt 423 register OK
Interrupt 425 register OK
Interrupt 427 register OK
Interrupt 429 register OK
Interrupt 430 register OK
Interrupt 431 register OK
Interrupt 436 register OK

cpu 0 entering scheduler
[IMU] Watchdog Initialization done!
ScmiTaskEntry start.
Interrupt 456 register OK
Interrupt 469 register OK
Interrupt 482 register OK
Interrupt 495 register OK
Interrupt 508 register OK
Interrupt 521 register OK
Interrupt 534 register OK
Interrupt 547 register OK
starting Fpc Isolation Task end
starting fdm Err Info Task end
starting Roce recovery Task end
starting Ce_Storm Contrl Task end
starting Ras_Data_Update Task end
power register ubios call id
Interrupt 459 register OK
Interrupt 472 register OK
Interrupt 485 register OK
Interrupt 498 register OK
Interrupt 511 register OK
Interrupt 524 register OK
Interrupt 537 register OK
Interrupt 550 register OK
[0.00.43.119]Real time now 2026.7.23 14:57:46
NIC CARD[0][0]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[0][1]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[1][0]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[1][1]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[2][0]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[2][1]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[3][0]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[3][1]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
Init heart-beat-task end
Init SeamlessUpdateTask end
pool addr          pool size    used size     free size    max free node size   used node num     free node num      UsageWaterLine
---------------    --------     -------       --------     --------------       -------------      ------------      ------------
0x840908e708       0x204c0      0x1a780       0x5ad0       0x5ad0               0x79               0x1                0x1a9f0        
Get Setup Config.
pwr cap[0]: 0, 63
pwr cap[1]: f, 27
pwr cap[2]: 1, 3
Node 0, Die 0 ImpState is 0 skip exec.
Node 0, Die 2 ImpState is 0 skip exec.
Node 1, Die 0 ImpState is 0 skip exec.
Node 1, Die 2 ImpState is 0 skip exec.
Node 2, Die 0 ImpState is 0 skip exec.
Node 2, Die 2 ImpState is 0 skip exec.
Node 3, Die 0 ImpState is 0 skip exec.
Node 3, Die 2 ImpState is 0 skip exec.
[0.02.38.127]DDR Rreserved for IMU: len = 3e00000
[LOG]head = 0x0, tail = 0x2b7a, logSize = 0x2b7a
copy registry.json file success
Set component all release version to sram end.
ipcMsgSend success
[0.02.38.166]starting ras Init
nodeId = 0, dieId = 0, isSasExist = 0.
nodeId = 0, dieId = 2, isSasExist = 0.
nodeId = 1, dieId = 0, isSasExist = 0.
nodeId = 1, dieId = 2, isSasExist = 0.
nodeId = 2, dieId = 0, isSasExist = 0.
nodeId = 2, dieId = 2, isSasExist = 0.
nodeId = 3, dieId = 0, isSasExist = 0.
nodeId = 3, dieId = 2, isSasExist = 0.
Mce Table head exist!
RasIntRegister init 452 
RasIntRegister init 453 
RasIntRegister init 64 
RasIntRegister init 65 
RasIntRegister init 465 
RasIntRegister init 466 
RasIntRegister init 86 
RasIntRegister init 87 
RasIntRegister init 478 
RasIntRegister init 479 
RasIntRegister init 108 
RasIntRegister init 109 
RasIntRegister init 491 
RasIntRegister init 492 
RasIntRegister init 130 
RasIntRegister init 131 
RasIntRegister init 504 
RasIntRegister init 505 
RasIntRegister init 152 
RasIntRegister init 153 
RasIntRegister init 517 
RasIntRegister init 518 
RasIntRegister init 174 
RasIntRegister init 175 
RasIntRegister init 530 
RasIntRegister init 531 
RasIntRegister init 196 
RasIntRegister init 197 
RasIntRegister init 543 
RasIntRegister init 544 
RasIntRegister init 218 
RasIntRegister init 219 
RasIntRegister init 76 
RasIntRegister init 98 
RasIntRegister init 120 
RasIntRegister init 142 
RasIntRegister init 164 
RasIntRegister init 186 
RasIntRegister init 208 
RasIntRegister init 230 
[0.02.38.287]starting ras end
[0.02.57.425][ERR]cmd not support! cmd = 0xd
[0.02.58.246]ext0 int trigger

********Hello Huawei LiteOS********

KpxxxxIMU Firmware Version : V32.70.0
LiteOS Kernel Version : 5.7.0
Run on ChipVersion[0] Node[0] Die[2]
build time : Feb 05 2026 20:30:00

**********************************

main core booting up...
start set affinity

mpidr = 0x81020000
sram ecc state: 0x0, sram ecc cnt: 0x0
[0.00.00.033]node 0 begins init all serdes.
BoardInfo->NodeNum 4.
BoardInfo->NodeId 0.
BoardInfo->InfoVersion 5.
BoardInfo->NASerdesSceneMode 3.
BoardInfo->NBSerdesSceneMode 3.
BoardInfo->HccsTopologyType 7.
BoardInfo->BoardId 0.
ChipVersionIsPro: 1.
BoardInfo Node 0, SerdesUseMode: 1 2 12 4 4 4 4  1 1 1 4 4 1 1 
BoardInfo Node 1, SerdesUseMode: 1 1 1 4 4 1 1  12 13 1 4 4 4 4 
BoardInfo Node 2, SerdesUseMode: 12 13 12 4 4 4 4  1 1 1 4 4 1 1 
BoardInfo Node 3, SerdesUseMode: 1 1 1 4 4 1 1  12 13 1 4 4 4 4 
BoardInfo Node 0, SerdesRxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 255 255 
BoardInfo Node 1, SerdesRxPolarityReverse: 255 255 255 0 0 255 255  0 0 0 0 0 0 0 
BoardInfo Node 2, SerdesRxPolarityReverse: 0 0 0 0 0 0 0  0 0 255 0 0 0 255 
BoardInfo Node 3, SerdesRxPolarityReverse: 255 255 255 0 0 0 0  0 0 255 0 0 0 0 
BoardInfo Node 0, SerdesTxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 255 255 
BoardInfo Node 1, SerdesTxPolarityReverse: 255 255 255 0 0 255 255  0 0 0 0 0 0 0 
BoardInfo Node 2, SerdesTxPolarityReverse: 0 0 0 0 0 0 0  0 0 255 0 0 0 0 
BoardInfo Node 3, SerdesTxPolarityReverse: 255 255 255 0 0 0 0  0 0 255 0 0 0 0 
serdessdk version: 2.0_5.0_20241203_imu
node_id 0, die 0, ind 0, usemode 1 begin serdes-init.
node_id 0, die 0, ind 1, usemode 2 begin serdes-init.
node_id 0, die 0, ind 2, usemode 12 begin serdes-init.
chip_id 0, die 0, ind 2, usemode 12 don't support, power down macro!
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
node_id 0, die 2, ind 0, usemode 1 begin serdes-init.
node_id 0, die 2, ind 1, usemode 1 begin serdes-init.
chip serdes init status:0x0.
[0.00.00.487]node 0 ends init all serdes.
link[0] freq_type:1 | peer_chip_type:1 | peer_node_id:1 | peer_link_id:6
link[1] freq_type:1 | peer_chip_type:1 | peer_node_id:1 | peer_link_id:7
link[2] freq_type:1 | peer_chip_type:1 | peer_node_id:1 | peer_link_id:4
link[3] freq_type:1 | peer_chip_type:1 | peer_node_id:1 | peer_link_id:5
link[4] freq_type:1 | peer_chip_type:1 | peer_node_id:3 | peer_link_id:0
link[5] freq_type:1 | peer_chip_type:1 | peer_node_id:2 | peer_link_id:4
register hccs done
nodeId 0, dieId 0, linkId 0, FFE info: fir_pre1 0, fir_main 63, fir_post1 0
node_id 0, die 0, ind 4, usemode 4 begin serdes-init.
nodeId 0, dieId 0, linkId 1, FFE info: fir_pre1 0, fir_main 63, fir_post1 0
node_id 0, die 0, ind 3, usemode 4 begin serdes-init.
nodeId 0, dieId 0, linkId 2, FFE info: fir_pre1 0, fir_main 63, fir_post1 0
node_id 0, die 0, ind 5, usemode 4 begin serdes-init.
nodeId 0, dieId 0, linkId 3, FFE info: fir_pre1 0, fir_main 63, fir_post1 0
node_id 0, die 0, ind 6, usemode 4 begin serdes-init.
node_id 0, die 2, ind 4, usemode 4 begin serdes-init.
node_id 0, die 2, ind 3, usemode 4 begin serdes-init.
hccs init start...
pa ring link down success
reset pa success
link[0] pcs init success
link[1] pcs init success
link[2] pcs init success
link[3] pcs init success
link[4] pcs init success
link[5] pcs init success
release reset pa success
link[0] macro adapt done (lane_mask=0xff) (0ms)
link[1] macro adapt done (lane_mask=0xff) (0ms)
link[2] macro adapt done (lane_mask=0xff) (0ms)
link[3] macro adapt done (lane_mask=0xff) (0ms)
link[4] macro adapt done (lane_mask=0xff) (0ms)
link[5] macro adapt done (lane_mask=0xff) (0ms)
link[0] pcs training success (10ms)
link[1] pcs training success (10ms)
link[2] pcs training success (10ms)
link[3] pcs training success (10ms)
link[4] pcs training success (10ms)
link[5] pcs training success (10ms)
link[0] training success (20ms)
link[1] training success (20ms)
link[2] training success (20ms)
link[3] training success (20ms)
link[4] training success (20ms)
link[5] training success (20ms)
link[0]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link[1]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link[2]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link[3]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link[4]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link[5]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link training success
pa[0] linkEn = 0xf
pa[0] allNodeLink0 = 0xf0
pa[0] allNodeLink1 = 0x0
pa[1] linkEn = 0x3
pa[1] allNodeLink0 = 0x1200
pa[1] allNodeLink1 = 0x0
pa init success
COM_PAID_INTLV_REG = 0xc
paid decode init success
pa[0] PA_PM_BASE_INFO = 0xff8421
pa[0] PA_PM_MAP_LINK_NUM = 0x2184
pa[1] PA_PM_BASE_INFO = 0x330021
pa[1] PA_PM_MAP_LINK_NUM = 0x11
hccs performace config success
pa ring link up success
hccs init done
hccs access test start
node[0] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[1] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[2] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[3] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[1] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
node[2] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
node[3] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
hccs access test success
======hccs status======
  node[0] mask: expected = 0x3f, link up = 0x3f, width reduction = 0x0, link down = 0x0
  node[1] mask: expected = 0xf3, link up = 0xf3, width reduction = 0x0, link down = 0x0
  node[2] mask: expected = 0x3f, link up = 0x3f, width reduction = 0x0, link down = 0x0
  node[3] mask: expected = 0xf3, link up = 0xf3, width reduction = 0x0, link down = 0x0
==========end==========
report hccs status success
node[0] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
LRDXSD_LOCK_OFFSET = 0x0
LRDXSD_ERRIMSK_OFFSET = 0x0
LRDXSD_DBG_OTIMSK_OFFSET = 0x0
LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
LRDXSD_DBG_EN_OFFSET = 0x1
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
ID[0xff3a25c2]!
ID[0xff000000]!
[ERR]Don't support the flash, CS[1] ID[0xff000000]!!
sfdp detect, try to get dummy data from hboot1 first.
ID[0xff3a25c2]!
flash 0 support sfdp.
Interrupt 423 register OK
Interrupt 425 register OK
Interrupt 427 register OK
Interrupt 429 register OK
Interrupt 430 register OK
Interrupt 431 register OK
Interrupt 436 register OK

cpu 0 entering scheduler
[IMU] Watchdog Initialization done!
ScmiTaskEntry start.
Interrupt 456 register OK
Interrupt 469 register OK
Interrupt 482 register OK
Interrupt 495 register OK
Interrupt 508 register OK
Interrupt 521 register OK
Interrupt 534 register OK
Interrupt 547 register OK
starting Fpc Isolation Task end
starting fdm Err Info Task end
starting Roce recovery Task end
starting Ce_Storm Contrl Task end
starting Ras_Data_Update Task end
power register ubios call id
Interrupt 459 register OK
Interrupt 472 register OK
Interrupt 485 register OK
Interrupt 498 register OK
Interrupt 511 register OK
Interrupt 524 register OK
Interrupt 537 register OK
Interrupt 550 register OK
[0.00.04.534]Real time now 2026.7.23 15:00:16
NIC CARD[0][0]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[0][1]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[1][0]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[1][1]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[2][0]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[2][1]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[3][0]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[3][1]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
Init heart-beat-task end
Init SeamlessUpdateTask end
pool addr          pool size    used size     free size    max free node size   used node num     free node num      UsageWaterLine
---------------    --------     -------       --------     --------------       -------------      ------------      ------------
0x840908e708       0x204c0      0x1a780       0x5ad0       0x5ad0               0x79               0x1                0x1a9f0        
Get Setup Config.
pwr cap[0]: 0, 63
pwr cap[1]: f, 27
pwr cap[2]: 1, 3
Node 0, Die 0 ImpState is 0 skip exec.
Node 0, Die 2 ImpState is 0 skip exec.
Node 1, Die 0 ImpState is 0 skip exec.
Node 1, Die 2 ImpState is 0 skip exec.
Node 2, Die 0 ImpState is 0 skip exec.
Node 2, Die 2 ImpState is 0 skip exec.
Node 3, Die 0 ImpState is 0 skip exec.
Node 3, Die 2 ImpState is 0 skip exec.
[0.00.20.758]DDR Rreserved for IMU: len = 3e00000
[LOG]head = 0x0, tail = 0x558f, logSize = 0x558f
copy registry.json file success
Set component all release version to sram end.
ipcMsgSend success
[0.00.20.798]starting ras Init
nodeId = 0, dieId = 0, isSasExist = 0.
nodeId = 0, dieId = 2, isSasExist = 0.
nodeId = 1, dieId = 0, isSasExist = 0.
nodeId = 1, dieId = 2, isSasExist = 0.
nodeId = 2, dieId = 0, isSasExist = 0.
nodeId = 2, dieId = 2, isSasExist = 0.
nodeId = 3, dieId = 0, isSasExist = 0.
nodeId = 3, dieId = 2, isSasExist = 0.
Mce Table head exist!
RasIntRegister init 452 
RasIntRegister init 453 
RasIntRegister init 64 
RasIntRegister init 65 
RasIntRegister init 465 
RasIntRegister init 466 
RasIntRegister init 86 
RasIntRegister init 87 
RasIntRegister init 478 
RasIntRegister init 479 
RasIntRegister init 108 
RasIntRegister init 109 
RasIntRegister init 491 
RasIntRegister init 492 
RasIntRegister init 130 
RasIntRegister init 131 
RasIntRegister init 504 
RasIntRegister init 505 
RasIntRegister init 152 
RasIntRegister init 153 
RasIntRegister init 517 
RasIntRegister init 518 
RasIntRegister init 174 
RasIntRegister init 175 
RasIntRegister init 530 
RasIntRegister init 531 
RasIntRegister init 196 
RasIntRegister init 197 
RasIntRegister init 543 
RasIntRegister init 544 
RasIntRegister init 218 
RasIntRegister init 219 
RasIntRegister init 76 
RasIntRegister init 98 
RasIntRegister init 120 
RasIntRegister init 142 
RasIntRegister init 164 
RasIntRegister init 186 
RasIntRegister init 208 
RasIntRegister init 230 
[0.00.20.919]starting ras end
[0.00.36.889][ERR]cmd not support! cmd = 0xd
[0.00.47.175]TF Heartbeat Start
[0.00.51.830]PCIE INIT DONE.
g_mctpQueueCount(48) > tabCnt(42)
Interrupt 454 register OK
Interrupt 467 register OK
Interrupt 480 register OK
Interrupt 493 register OK
Interrupt 506 register OK
Interrupt 519 register OK
Interrupt 532 register OK
Interrupt 545 register OK
data = 0x0
pmt Init done

Add ep: bdf=5500 eid=9 epCnt=1 eid_alloc=a
Add ep: bdf=300 eid=a epCnt=1 eid_alloc=b
mctp task ok.
[0.01.26.589]Receive ras int[530]
First coalesce handler start
Type2 status = 0x0
Type1 status = 0x4
Found error node[2]
False alarm reporting!
Type0 status = 0x0
ras int[530] end

[0.01.26.653]Receive ras int[491]
First coalesce handler start
Type2 status = 0x0
Type1 status = 0x4
Found error node[2]
False alarm reporting!
Type0 status = 0x0
ras int[491] end

[0.02.52.161]BIOS POST END.
Create SetReportPcieMmioToBmc ok.
Start SetReportPcieMmioToBmc ok.
slotNum = 0x14
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[0] port:20  pcieSlotCtrl.data (after)0x4801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[1] port:24  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[2] port:26  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[3] port:32  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[4] port:0  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[5] port:24  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[6] port:26  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[7] port:20  pcieSlotCtrl.data (after)0x4801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[8] port:22  pcieSlotCtrl.data (after)0x4801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[9] port:24  pcieSlotCtrl.data (after)0x4801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[10] port:26  pcieSlotCtrl.data (after)0x4801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[11] port:32  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[12] port:34  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[13] port:36  pcieSlotCtrl.data (after)0x4801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[14] port:38  pcieSlotCtrl.data (after)0x4801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[15] port:0  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[16] port:12  pcieSlotCtrl.data (after)0x4801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[17] port:14  pcieSlotCtrl.data (after)0x4801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[18] port:16  pcieSlotCtrl.data (after)0x4801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[19] port:18  pcieSlotCtrl.data (after)0x4801c0.

Enter current value process


HSM_LOG:
[00:00:00.000][info] succeed to do thirdparty dfx_pabuk init
[00:00:00.000][info] succeed to do thirdparty crypto_driver init


v TB[ 908]mv
0>[2650]MHZ -> Vol TA[ 922]mv TB[ 920]mv
0>[2700]MHZ -> Vol TA[ 935]mv TB[ 933]mv
0>[2750]MHZ -> Vol TA[ 953]mv TB[ 950]mv
0>[2800]MHZ -> Vol TA[ 971]mv TB[ 968]mv
0>[2850]MHZ -> Vol TA[ 989]mv TB[ 986]mv
0>[2900]MHZ -> Vol TA[1007]mv TB[1004]mv
0>[2950]MHZ -> Vol TA[1024]mv TB[1021]mv
0>[3000]MHZ -> Vol TA[1041]mv TB[1038]mv
0>[3050]MHZ -> Vol TA[1054]mv TB[1052]mv
0>[3100]MHZ -> Vol TA[1068]mv TB[1066]mv
0>Uncore VF curve:
0>Uncore [   0]MHZ -> Vol [ 810]mv
0>Uncore [ 100]MHZ -> Vol [ 810]mv
0>Uncore [ 200]MHZ -> Vol [ 810]mv
0>Uncore [ 300]MHZ -> Vol [ 810]mv
0>Uncore [ 400]MHZ -> Vol [ 810]mv
0>Uncore [ 500]MHZ -> Vol [ 810]mv
0>Uncore [ 600]MHZ -> Vol [ 810]mv
0>Uncore [ 700]MHZ -> Vol [ 810]mv
0>Uncore [ 800]MHZ -> Vol [ 810]mv
0>Uncore [ 900]MHZ -> Vol [ 810]mv
0>Uncore [1000]MHZ -> Vol [ 810]mv
0>Uncore [1100]MHZ -> Vol [ 810]mv
0>Uncore [1200]MHZ -> Vol [ 810]mv
0>Uncore [1300]MHZ -> Vol [ 810]mv
0>Uncore [1400]MHZ -> Vol [ 810]mv
0>Uncore [1500]MHZ -> Vol [ 810]mv
0>Uncore [1600]MHZ -> Vol [ 810]mv
0>Uncore [1700]MHZ -> Vol [ 810]mv
0>Uncore [1800]MHZ -> Vol [ 810]mv
0>Uncore [1900]MHZ -> Vol [ 810]mv
0>Uncore [2000]MHZ -> Vol [ 810]mv
0>Uncore [2100]MHZ -> Vol [ 810]mv
0>Uncore [2200]MHZ -> Vol [ 812]mv
0>Uncore [2300]MHZ -> Vol [ 829]mv
0>Uncore [2400]MHZ -> Vol [ 846]mv
0>Uncore [2500]MHZ -> Vol [ 863]mv
0>Uncore [2600]MHZ -> Vol [ 883]mv
0>Uncore [2700]MHZ -> Vol [ 903]mv
0>Uncore [2800]MHZ -> Vol [ 923]mv
0>Uncore [2900]MHZ -> Vol [ 944]mv
0>Uncore [3000]MHZ -> Vol [1100]mv
0>[TracePoint] type[  0] cmd[  1] data[  6]
0>[TracePoint] type[  0] cmd[  1] data[  7]
0>
********Hello Huawei LiteOS********

KpxxxxIPU Firmware Version : V32.70.0
LiteOS Kernel Version : 5.7.0
0>Run on ChipVersion[0] Node[0] Die[0]
0>build time : Feb 05 2026 20:30:00

0>**********************************
0>
main core booting up...
0>start set affinity
0>
mpidr = 0x81000000
0>sram ecc state: 0x0, sram ecc cnt: 0x0
0>[TracePoint] type[  0] cmd[  2] data[  1]
0>[TracePoint] type[  0] cmd[  2] data[  2]
0>LRDXSD_LOCK_OFFSET = 0x0
0>LRDXSD_ERRIMSK_OFFSET = 0x0
0>LRDXSD_DBG_OTIMSK_OFFSET = 0x0
0>LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
0>LRDXSD_DBG_EN_OFFSET = 0x1
0>======tsensor params======
0>  is_trimmed       : 1
0>  underclocking_en : 1
0>===========end============
0>soc tsensor init done
0>========vrd info from cpld========
0>vrd_id | u64                | pmbus_en | avsbus_en | loop | pmbus_id | pmbus_addr | avs_sw | pmbus_sw | addr_9545 | domain_type | die_mask | reserved
0>  00   | 0x0001000100002017 | 0x1      | 0x1       | 0x1  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0100   | 0x0
0>  01   | 0x000001060000201b | 0x1      | 0x1       | 0x2  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x6         | 0x0001   | 0x0
0>  02   | 0x0003000300002715 | 0x1      | 0x0       | 0x1  | 0x1      | 0x27       | 0x0    | 0x0      | 0x0       | 0x3         | 0x0300   | 0x0
0>  03   | 0x0003000400002719 | 0x1      | 0x0       | 0x2  | 0x1      | 0x27       | 0x0    | 0x0      | 0x0       | 0x4         | 0x0300   | 0x0
0>  04   | 0x0002000100002027 | 0x1      | 0x1       | 0x1  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0200   | 0x0
0>  05   | 0x000300020000202b | 0x1      | 0x1       | 0x2  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x2         | 0x0300   | 0x0
0>  06   | 0x0000020a00002725 | 0x1      | 0x0       | 0x1  | 0x2      | 0x27       | 0x0    | 0x0      | 0x0       | 0xa         | 0x0002   | 0x0
0>  07   | 0x0000020500002729 | 0x1      | 0x0       | 0x2  | 0x2      | 0x27       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0002   | 0x0
0>  08   | 0x0000020600002a25 | 0x1      | 0x0       | 0x1  | 0x2      | 0x2a       | 0x0    | 0x0      | 0x0       | 0x6         | 0x0002   | 0x0
0>  09   | 0x0000010a00002a29 | 0x1      | 0x0       | 0x2  | 0x2      | 0x2a       | 0x0    | 0x0      | 0x0       | 0xa         | 0x0001   | 0x0
0>================end===============
0>=============vrd info=============
0>power domain num: 10
0>power domain[00] id:0 | CORE_DVFS_TA       | PMBus NA | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
0>power domain[01] id:10 | IO_DVDD09_NA       | PMBus NA | cap:0x3 | rail:1 | addr:0x20 | def_volt: 900 mV | min_volt: 700 mV | max_volt: 900 mV
0>power domain[02] id:1 | DDR_VDD            | PMBus NA | cap:0x1 | rail:0 | addr:0x27 | def_volt: 800 mV | min_volt: 760 mV | max_volt: 840 mV
0>power domain[03] id:6 | DDR_VDDQ           | PMBus NA | cap:0x1 | rail:1 | addr:0x27 | def_volt:1100 mV | min_volt:1000 mV | max_volt:1200 mV
0>power domain[04] id:2 | CORE_DVFS_TB       | PMBus NB | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
0>power domain[05] id:3 | UNCORE_DVFS        | PMBus NB | cap:0x3 | rail:1 | addr:0x20 | def_volt: 944 mV | min_volt: 750 mV | max_volt:1100 mV
0>power domain[06] id:15 | NB_AVDD_SDS        | PMBus NB | cap:0x1 | rail:0 | addr:0x27 | def_volt:1200 mV | min_volt:1164 mV | max_volt:1236 mV
0>power domain[07] id:5 | IO_DVDD_NB         | PMBus NB | cap:0x1 | rail:1 | addr:0x27 | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
0>power domain[08] id:11 | IO_DVDD09_NB       | PMBus NB | cap:0x1 | rail:0 | addr:0x2a | def_volt: 900 mV | min_volt: 700 mV | max_volt: 900 mV
0>power domain[09] id:13 | NA_AVDD_SDS        | PMBus NB | cap:0x1 | rail:1 | addr:0x2a | def_volt:1200 mV | min_volt:1164 mV | max_volt:1236 mV
0>================end===============
0>pmbus[0] init done
0>pmbus[1] init done
0>power domain[0] CORE_DVFS_TA       | NA PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
0>power domain[10] IO_DVDD09_NA       | NA PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 900 mV | pmu:MP2882
0>power domain[1] DDR_VDD            | NA PMBus        | rail:0 | addr:0x27 | def_volt: 800 mV | pmu:MP2882
0>power domain[6] DDR_VDDQ           | NA PMBus        | rail:1 | addr:0x27 | def_volt:1100 mV | pmu:MP2882
0>power domain[2] CORE_DVFS_TB       | NB PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
0>power domain[3] UNCORE_DVFS        | NB PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 944 mV | pmu:MP2882
0>power domain[15] NB_AVDD_SDS        | NB PMBus        | rail:0 | addr:0x27 | def_volt:1200 mV | pmu:MP2882
0>power domain[5] IO_DVDD_NB         | NB PMBus        | rail:1 | addr:0x27 | def_volt: 800 mV | pmu:MP2882
0>power domain[11] IO_DVDD09_NB       | NB PMBus        | rail:0 | addr:0x2a | def_volt: 900 mV | pmu:MP2882
0>power domain[13] NA_AVDD_SDS        | NB PMBus        | rail:1 | addr:0x2a | def_volt:1200 mV | pmu:MP2882
0>power domain[0] CORE_DVFS_TA       is transferred to AVSBus mode
0>power domain[10] IO_DVDD09_NA       is transferred to AVSBus mode
0>power domain[2] CORE_DVFS_TB       is transferred to AVSBus mode
0>power domain[3] UNCORE_DVFS        is transferred to AVSBus mode
0>avsbus resync success
0>avsbus[0] init done
0>avsbus resync success
0>avsbus[1] init done
0>============volt boot============
0>power domain[0] volt =  880 mV
0>power domain[10] volt =  906 mV
0>power domain[1] volt =  806 mV
0>power domain[6] volt = 1105 mV
0>power domain[2] volt =  888 mV
0>power domain[3] volt =  949 mV
0>power domain[15] volt = 1205 mV
0>power domain[5] volt =  804 mV
0>power domain[11] volt =  906 mV
0>power domain[13] volt = 1206 mV
0>===============end===============
0>--w&h rd rail:0, 880, CORE_DVFS_TA
0>--w&h rd rail:1, 900, CORE_DVFS_TA
0>power domain[0] set volt --> 1097 mV success
0>--w&h rd rail:0, 886, CORE_DVFS_TB
0>--w&h rd rail:1, 949, CORE_DVFS_TB
0>power domain[2] set volt --> 1103 mV success
0>power domain[3] set volt -->  951 mV success
0>============volt post============
0>power domain[0] volt = 1097 mV
0>power domain[10] volt =  904 mV
0>power domain[1] volt =  806 mV
0>power domain[6] volt = 1105 mV
0>power domain[2] volt = 1105 mV
0>power domain[3] volt =  951 mV
0>power domain[15] volt = 1205 mV
0>power domain[5] volt =  804 mV
0>power domain[11] volt =  908 mV
0>power domain[13] volt = 1205 mV
0>===============end===============
0>die[0] its[0] init done
0>die[0] its[1] init done
0>die[0] its[2] init done
0>die[0] its[3] init done
0>die[0] its[4] init done
0>die[0] its[5] init done
0>die[0] its[6] init done
0>die[0] its[7] init done
0>die[0] its[8] init done
0>die[0] its[9] init done
0>die[1] its[0] init done
0>die[1] its[1] init done
0>die[1] its[2] init done
0>die[1] its[3] init done
0>die[1] its[4] init done
0>die[1] its[5] init done
0>die[1] its[6] init done
0>die[1] its[7] init done
0>die[1] its[8] init done
0>die[1] its[9] init done
0>Totem[0] Core Boot Vol [1097]mv
0>Totem[0] Core Current Vol [1100]mv
0>Totem[1] Core Boot Vol [1105]mv
0>Totem[1] Core Current Vol [1100]mv
0>NA 1620V1a0
0>NB 1620V1a0
0>GetCoreBaseFreq [2500000KHZ]
0>GetCoreTurboFreq [2500000KHZ]
0>GetCustomClusterNum [10]
0>Ipu ACG Training Done!
0>AP Last Time:[0.00.01.895]
0>wait UEFI pll init...
0>done
0>acg trim start
0>core trim freq:2000, avs:0 volt:810mv
0>core trim freq:2000, avs:0 volt:810mv
0>core trim freq:2050, avs:1 volt:810mv
0>core trim freq:2050, avs:1 volt:810mv
0>core trim freq:2100, avs:2 volt:810mv
0>core trim freq:2100, avs:2 volt:810mv
0>core trim freq:2150, avs:3 volt:810mv
0>core trim freq:2150, avs:3 volt:810mv
0>core trim freq:2200, avs:4 volt:810mv
0>core trim freq:2200, avs:4 volt:810mv
0>core trim freq:2250, avs:5 volt:821mv
0>core trim freq:2250, avs:5 volt:820mv
0>core trim freq:2300, avs:6 volt:834mv
0>core trim freq:2300, avs:6 volt:833mv
0>core trim freq:2350, avs:7 volt:847mv
0>core trim freq:2350, avs:7 volt:845mv
0>core trim freq:2400, avs:8 volt:859mv
0>core trim freq:2400, avs:8 volt:858mv
0>core trim freq:2450, avs:9 volt:872mv
0>core trim freq:2450, avs:9 volt:870mv
0>core trim freq:2500, avs:10 volt:884mv
0>core trim freq:2500, avs:10 volt:883mv
0>core trim freq:2550, avs:11 volt:897mv
0>core trim freq:2550, avs:11 volt:895mv
0>core trim freq:2600, avs:12 volt:909mv
0>core trim freq:2600, avs:12 volt:908mv
0>core trim freq:2650, avs:13 volt:922mv
0>core trim freq:2650, avs:13 volt:920mv
0>core trim freq:2700, avs:14 volt:935mv
0>core trim freq:2700, avs:14 volt:933mv
0>core trim freq:2750, avs:15 volt:953mv
0>core trim freq:2750, avs:15 volt:950mv
0>core trim freq:2800, avs:16 volt:971mv
0>core trim freq:2800, avs:16 volt:968mv
0>core trim freq:2850, avs:17 volt:989mv
0>core trim freq:2850, avs:17 volt:986mv
0>core trim freq:2900, avs:18 volt:1007mv
0>core trim freq:2900, avs:18 volt:1004mv
0>core trim freq:2950, avs:19 volt:1024mv
0>core trim freq:2950, avs:19 volt:1021mv
0>core trim freq:3000, avs:20 volt:1041mv
0>core trim freq:3000, avs:20 volt:1038mv
0>core trim freq:3050, avs:21 volt:1054mv
0>core trim freq:3050, avs:21 volt:1052mv
0>core trim freq:3100, avs:22 volt:1068mv
0>core trim freq:3100, avs:22 volt:1066mv
0>acg trim end
0>LDO disabled
0>[TracePoint] type[  0] cmd[  2] data[  3]
0>Interrupt 423 register OK
0>Interrupt 430 register OK
0>[TracePoint] type[  0] cmd[  2] data[  4]
0>
0>cpu 0 entering scheduler
0>[TracePoint] type[  0] cmd[  3] data[  1]
0>add your ipu app init here!
0>IpuInterfaceTaskStart Entry ...
0>ipu interface task wait parameters from uefi...
0>thermal soc task enabled
0>AP Last Time:[0.00.07.143]
0>ThermalDimmStart Entry ...
0>wait ddr init done...
0>power task start...
0>[TracePoint] type[  0] cmd[  3] data[  2]
0>ufs task wait parameters from uefi...
0>AmuTaskStart Entry ... 
0>amu task wait parameters from uefi...
0>ThermalSiwStart Entry ...
0>ThermalSiwTask idle...
0>DemtTaskStart Entry ...
0>[TracePoint] type[  0] cmd[  3] data[  3]
0>demt task wait parameters from uefi...
0>HiBoostTaskStart Entry ...
0>HiBoost task enabled
0>Waiting for UEFI parameters...
0>[TracePoint] type[  0] cmd[  3] data[  4]
0>AgeTaskStart Entry ...
0>age task wait parameters from uefi...
0>[TracePoint] type[  0] cmd[  3] data[  5]
0>uefi parameters ready!
0>UFSProfile[0]
0>PowerPolicy[2] BenchMarkSelection[0]
0>ipu interface task wait ddr init done from uefi...
0>ufs task parameters from uefi ready
0>uncore domain[0] freq:2900
0>uncore domain[1] freq:2900
0>thermal soc task restore underclocking_en=1
0>ppu alert temp div init done
0>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
0>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
0>======sioe status======
0>TA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TA_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TA_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TA_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
0>TA_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
0>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
0>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
0>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
0>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
0>==========end==========
0>sioe init done
0>ufs task enabled
0>--> UFS profile[0]
0>UEFI parameters ready
0>UncoreMaxFreq Set to [2900 MHZ]
0>get TDP from efuse success, value = 307500mw
0>target power set to [307500]mw, brd:[307500]
0>demt task parameters from uefi ready
0>age task parameters from uefi ready
0>age task enabled
0>uefi ddr init finish!
0>ipu interface task wait uefi end done from uefi...
0>ddr init done, start thermal dimm task
0>======dimm status======
0>  chl[0] dimm0 0, dimm1 0
0>  chl[1] dimm0 0, dimm1 0
0>  chl[2] dimm0 2, dimm1 0
0>  chl[3] dimm0 0, dimm1 0
0>  chl[4] dimm0 0, dimm1 0
0>  chl[5] dimm0 0, dimm1 0
0>  chl[6] dimm0 0, dimm1 0
0>  chl[7] dimm0 0, dimm1 0
0>==========end==========
0>chl[2] registered, dimm mask = 0x1
0>=====dimm temp params=====
0>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
0>  is_thermal_thro_en  : 1
0>  is_aref_rate_auto   : 1
0>===========end============
0>chl[2] max_temp 42'C, aref_rate 0x5 --> 0x4
0>uefi end finish!
0>ipu interface task exit!
0>amu task parameters from uefi ready
0>amu task activated
0>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
810]mv
1>Uncore [ 100]MHZ -> Vol [ 810]mv
1>Uncore [ 200]MHZ -> Vol [ 810]mv
1>Uncore [ 300]MHZ -> Vol [ 810]mv
1>Uncore [ 400]MHZ -> Vol [ 810]mv
1>Uncore [ 500]MHZ -> Vol [ 810]mv
1>Uncore [ 600]MHZ -> Vol [ 810]mv
1>Uncore [ 700]MHZ -> Vol [ 810]mv
1>Uncore [ 800]MHZ -> Vol [ 810]mv
1>Uncore [ 900]MHZ -> Vol [ 810]mv
1>Uncore [1000]MHZ -> Vol [ 810]mv
1>Uncore [1100]MHZ -> Vol [ 810]mv
1>Uncore [1200]MHZ -> Vol [ 810]mv
1>Uncore [1300]MHZ -> Vol [ 810]mv
1>Uncore [1400]MHZ -> Vol [ 810]mv
1>Uncore [1500]MHZ -> Vol [ 810]mv
1>Uncore [1600]MHZ -> Vol [ 810]mv
1>Uncore [1700]MHZ -> Vol [ 810]mv
1>Uncore [1800]MHZ -> Vol [ 810]mv
1>Uncore [1900]MHZ -> Vol [ 810]mv
1>Uncore [2000]MHZ -> Vol [ 810]mv
1>Uncore [2100]MHZ -> Vol [ 810]mv
1>Uncore [2200]MHZ -> Vol [ 814]mv
1>Uncore [2300]MHZ -> Vol [ 831]mv
1>Uncore [2400]MHZ -> Vol [ 848]mv
1>Uncore [2500]MHZ -> Vol [ 866]mv
1>Uncore [2600]MHZ -> Vol [ 886]mv
1>Uncore [2700]MHZ -> Vol [ 907]mv
1>Uncore [2800]MHZ -> Vol [ 927]mv
1>Uncore [2900]MHZ -> Vol [ 948]mv
1>Uncore [3000]MHZ -> Vol [1100]mv
1>[TracePoint] type[  0] cmd[  1] data[  6]
1>[TracePoint] type[  0] cmd[  1] data[  7]
1>
********Hello Huawei LiteOS********

KpxxxxIPU Firmware Version : V32.70.0
LiteOS Kernel Version : 5.7.0
1>Run on ChipVersion[0] Node[1] Die[0]
1>build time : Feb 05 2026 20:30:00

1>**********************************
1>
main core booting up...
1>start set affinity
1>
mpidr = 0x81040000
1>sram ecc state: 0x0, sram ecc cnt: 0x0
1>[TracePoint] type[  0] cmd[  2] data[  1]
1>[TracePoint] type[  0] cmd[  2] data[  2]
1>LRDXSD_LOCK_OFFSET = 0x0
1>LRDXSD_ERRIMSK_OFFSET = 0x0
1>LRDXSD_DBG_OTIMSK_OFFSET = 0x0
1>LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
1>LRDXSD_DBG_EN_OFFSET = 0x1
1>======tsensor params======
1>  is_trimmed       : 1
1>  underclocking_en : 1
1>===========end============
1>soc tsensor init done
1>========vrd info from cpld========
1>vrd_id | u64                | pmbus_en | avsbus_en | loop | pmbus_id | pmbus_addr | avs_sw | pmbus_sw | addr_9545 | domain_type | die_mask | reserved
1>  00   | 0x0001000100002017 | 0x1      | 0x1       | 0x1  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0100   | 0x0
1>  01   | 0x000300030000201b | 0x1      | 0x1       | 0x2  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x3         | 0x0300   | 0x0
1>  02   | 0x0000010a00002715 | 0x1      | 0x0       | 0x1  | 0x1      | 0x27       | 0x0    | 0x0      | 0x0       | 0xa         | 0x0001   | 0x0
1>  03   | 0x0000010500002719 | 0x1      | 0x0       | 0x2  | 0x1      | 0x27       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0001   | 0x0
1>  04   | 0x0000020600002a15 | 0x1      | 0x0       | 0x1  | 0x1      | 0x2a       | 0x0    | 0x0      | 0x0       | 0x6         | 0x0002   | 0x0
1>  05   | 0x0000010600002a19 | 0x1      | 0x0       | 0x2  | 0x1      | 0x2a       | 0x0    | 0x0      | 0x0       | 0x6         | 0x0001   | 0x0
1>  06   | 0x0000020a00002f15 | 0x1      | 0x0       | 0x1  | 0x1      | 0x2f       | 0x0    | 0x0      | 0x0       | 0xa         | 0x0002   | 0x0
1>  07   | 0x0002000100002027 | 0x1      | 0x1       | 0x1  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0200   | 0x0
1>  08   | 0x000300020000202b | 0x1      | 0x1       | 0x2  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x2         | 0x0300   | 0x0
1>  09   | 0x0000030500002725 | 0x1      | 0x0       | 0x1  | 0x2      | 0x27       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0003   | 0x0
1>  10   | 0x0003000400002729 | 0x1      | 0x0       | 0x2  | 0x2      | 0x27       | 0x0    | 0x0      | 0x0       | 0x4         | 0x0300   | 0x0
1>================end===============
1>=============vrd info=============
1>power domain num: 11
1>power domain[00] id:0 | CORE_DVFS_TA       | PMBus NA | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
1>power domain[01] id:1 | DDR_VDD            | PMBus NA | cap:0x3 | rail:1 | addr:0x20 | def_volt: 800 mV | min_volt: 760 mV | max_volt: 840 mV
1>power domain[02] id:14 | NA_AVDD_SDS        | PMBus NA | cap:0x1 | rail:0 | addr:0x27 | def_volt:1200 mV | min_volt:1164 mV | max_volt:1236 mV
1>power domain[03] id:4 | IO_DVDD_NA         | PMBus NA | cap:0x1 | rail:1 | addr:0x27 | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
1>power domain[04] id:11 | IO_DVDD09_NB       | PMBus NA | cap:0x1 | rail:0 | addr:0x2a | def_volt: 900 mV | min_volt: 700 mV | max_volt: 900 mV
1>power domain[05] id:10 | IO_DVDD09_NA       | PMBus NA | cap:0x1 | rail:1 | addr:0x2a | def_volt: 900 mV | min_volt: 700 mV | max_volt: 900 mV
1>power domain[06] id:16 | NB_AVDD_SDS        | PMBus NA | cap:0x1 | rail:0 | addr:0x2f | def_volt:1200 mV | min_volt:1164 mV | max_volt:1236 mV
1>power domain[07] id:2 | CORE_DVFS_TB       | PMBus NB | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
1>power domain[08] id:3 | UNCORE_DVFS        | PMBus NB | cap:0x3 | rail:1 | addr:0x20 | def_volt: 948 mV | min_volt: 750 mV | max_volt:1100 mV
1>power domain[09] id:12 | IO_DVDD_NANB       | PMBus NB | cap:0x1 | rail:0 | addr:0x27 | def_volt: 800 mV | min_volt: 750 mV | max_volt: 900 mV
1>power domain[10] id:6 | DDR_VDDQ           | PMBus NB | cap:0x1 | rail:1 | addr:0x27 | def_volt:1100 mV | min_volt:1000 mV | max_volt:1200 mV
1>================end===============
1>pmbus[0] init done
1>pmbus[1] init done
1>power domain[0] CORE_DVFS_TA       | NA PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
1>power domain[1] DDR_VDD            | NA PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 800 mV | pmu:MP2882
1>power domain[14] NA_AVDD_SDS        | NA PMBus        | rail:0 | addr:0x27 | def_volt:1200 mV | pmu:MP2882
1>power domain[4] IO_DVDD_NA         | NA PMBus        | rail:1 | addr:0x27 | def_volt: 800 mV | pmu:MP2882
1>power domain[11] IO_DVDD09_NB       | NA PMBus        | rail:0 | addr:0x2a | def_volt: 900 mV | pmu:MP2882
1>power domain[10] IO_DVDD09_NA       | NA PMBus        | rail:1 | addr:0x2a | def_volt: 900 mV | pmu:MP2882
1>power domain[16] NB_AVDD_SDS        | NA PMBus        | rail:0 | addr:0x2f | def_volt:1200 mV | pmu:MP2882
1>power domain[2] CORE_DVFS_TB       | NB PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
1>power domain[3] UNCORE_DVFS        | NB PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 948 mV | pmu:MP2882
1>power domain[12] IO_DVDD_NANB       | NB PMBus        | rail:0 | addr:0x27 | def_volt: 800 mV | pmu:MP2882
1>power domain[6] DDR_VDDQ           | NB PMBus        | rail:1 | addr:0x27 | def_volt:1100 mV | pmu:MP2882
1>power domain[0] CORE_DVFS_TA       is transferred to AVSBus mode
1>power domain[1] DDR_VDD            is transferred to AVSBus mode
1>power domain[2] CORE_DVFS_TB       is transferred to AVSBus mode
1>power domain[3] UNCORE_DVFS        is transferred to AVSBus mode
1>avsbus resync success
1>avsbus[0] init done
1>avsbus resync success
1>avsbus[1] init done
1>============volt boot============
1>power domain[0] volt =  892 mV
1>power domain[1] volt =  804 mV
1>power domain[14] volt = 1205 mV
1>power domain[4] volt =  806 mV
1>power domain[11] volt =  906 mV
1>power domain[10] volt =  904 mV
1>power domain[16] volt = 1203 mV
1>power domain[2] volt =  886 mV
1>power domain[3] volt =  816 mV
1>power domain[12] volt =  806 mV
1>power domain[6] volt = 1105 mV
1>===============end===============
1>--w&h rd rail:0, 892, CORE_DVFS_TA
1>--w&h rd rail:1, 800, CORE_DVFS_TA
1>power domain[0] set volt --> 1103 mV success
1>--w&h rd rail:0, 888, CORE_DVFS_TB
1>--w&h rd rail:1, 814, CORE_DVFS_TB
1>power domain[2] set volt --> 1097 mV success
1>power domain[3] set volt -->  953 mV success
1>============volt post============
1>power domain[0] volt = 1103 mV
1>power domain[1] volt =  804 mV
1>power domain[14] volt = 1203 mV
1>power domain[4] volt =  806 mV
1>power domain[11] volt =  904 mV
1>power domain[10] volt =  904 mV
1>power domain[16] volt = 1203 mV
1>power domain[2] volt = 1097 mV
1>power domain[3] volt =  953 mV
1>power domain[12] volt =  808 mV
1>power domain[6] volt = 1105 mV
1>===============end===============
1>the power sensor : manu id = 2peak, die id = TPA626
1>power sensor[0] init success
1>die[0] its[0] init done
1>die[0] its[1] init done
1>die[0] its[2] init done
1>die[0] its[3] init done
1>die[0] its[4] init done
1>die[0] its[5] init done
1>die[0] its[6] init done
1>die[0] its[7] init done
1>die[0] its[8] init done
1>die[0] its[9] init done
1>die[1] its[0] init done
1>die[1] its[1] init done
1>die[1] its[2] init done
1>die[1] its[3] init done
1>die[1] its[4] init done
1>die[1] its[5] init done
1>die[1] its[6] init done
1>die[1] its[7] init done
1>die[1] its[8] init done
1>die[1] its[9] init done
1>Totem[0] Core Boot Vol [1103]mv
1>Totem[0] Core Current Vol [1100]mv
1>Totem[1] Core Boot Vol [1097]mv
1>Totem[1] Core Current Vol [1100]mv
1>NA 1620V1a0
1>NB 1620V1a0
1>GetCoreBaseFreq [2500000KHZ]
1>GetCoreTurboFreq [2500000KHZ]
1>GetCustomClusterNum [10]
1>Ipu ACG Training Done!
1>AP Last Time:[0.00.01.522]
1>wait UEFI pll init...
1>done
1>acg trim start
1>core trim freq:2000, avs:0 volt:810mv
1>core trim freq:2000, avs:0 volt:810mv
1>core trim freq:2050, avs:1 volt:810mv
1>core trim freq:2050, avs:1 volt:810mv
1>core trim freq:2100, avs:2 volt:810mv
1>core trim freq:2100, avs:2 volt:810mv
1>core trim freq:2150, avs:3 volt:810mv
1>core trim freq:2150, avs:3 volt:810mv
1>core trim freq:2200, avs:4 volt:814mv
1>core trim freq:2200, avs:4 volt:812mv
1>core trim freq:2250, avs:5 volt:826mv
1>core trim freq:2250, avs:5 volt:825mv
1>core trim freq:2300, avs:6 volt:839mv
1>core trim freq:2300, avs:6 volt:838mv
1>core trim freq:2350, avs:7 volt:852mv
1>core trim freq:2350, avs:7 volt:851mv
1>core trim freq:2400, avs:8 volt:865mv
1>core trim freq:2400, avs:8 volt:863mv
1>core trim freq:2450, avs:9 volt:878mv
1>core trim freq:2450, avs:9 volt:876mv
1>core trim freq:2500, avs:10 volt:890mv
1>core trim freq:2500, avs:10 volt:889mv
1>core trim freq:2550, avs:11 volt:903mv
1>core trim freq:2550, avs:11 volt:901mv
1>core trim freq:2600, avs:12 volt:916mv
1>core trim freq:2600, avs:12 volt:914mv
1>core trim freq:2650, avs:13 volt:929mv
1>core trim freq:2650, avs:13 volt:927mv
1>core trim freq:2700, avs:14 volt:942mv
1>core trim freq:2700, avs:14 volt:940mv
1>core trim freq:2750, avs:15 volt:960mv
1>core trim freq:2750, avs:15 volt:958mv
1>core trim freq:2800, avs:16 volt:978mv
1>core trim freq:2800, avs:16 volt:976mv
1>core trim freq:2850, avs:17 volt:996mv
1>core trim freq:2850, avs:17 volt:994mv
1>core trim freq:2900, avs:18 volt:1015mv
1>core trim freq:2900, avs:18 volt:1012mv
1>core trim freq:2950, avs:19 volt:1032mv
1>core trim freq:2950, avs:19 volt:1029mv
1>core trim freq:3000, avs:20 volt:1050mv
1>core trim freq:3000, avs:20 volt:1047mv
1>core trim freq:3050, avs:21 volt:1063mv
1>core trim freq:3050, avs:21 volt:1060mv
1>core trim freq:3100, avs:22 volt:1076mv
1>core trim freq:3100, avs:22 volt:1074mv
1>acg trim end
1>LDO disabled
1>[TracePoint] type[  0] cmd[  2] data[  3]
1>Interrupt 423 register OK
1>Interrupt 430 register OK
1>[TracePoint] type[  0] cmd[  2] data[  4]
1>
1>cpu 0 entering scheduler
1>[TracePoint] type[  0] cmd[  3] data[  1]
1>add your ipu app init here!
1>IpuInterfaceTaskStart Entry ...
1>ipu interface task wait parameters from uefi...
1>thermal soc task enabled
1>AP Last Time:[0.00.07.144]
1>ThermalDimmStart Entry ...
1>wait ddr init done...
1>power task start...
1>[TracePoint] type[  0] cmd[  3] data[  2]
1>ufs task wait parameters from uefi...
1>AmuTaskStart Entry ... 
1>amu task wait parameters from uefi...
1>ThermalSiwStart Entry ...
1>ThermalSiwTask idle...
1>DemtTaskStart Entry ...
1>[TracePoint] type[  0] cmd[  3] data[  3]
1>HiBoostTaskStart Entry ...
1>HiBoost task enabled
1>Waiting for UEFI parameters...
1>[TracePoint] type[  0] cmd[  3] data[  4]
1>demt task wait parameters from uefi...
1>AgeTaskStart Entry ...
1>age task wait parameters from uefi...
1>[TracePoint] type[  0] cmd[  3] data[  5]
1>uefi parameters ready!
1>UFSProfile[0]
1>PowerPolicy[2] BenchMarkSelection[0]
1>ipu interface task wait ddr init done from uefi...
1>ufs task parameters from uefi ready
1>uncore domain[0] freq:2900
1>uncore domain[1] freq:2900
1>thermal soc task restore underclocking_en=1
1>ppu alert temp div init done
1>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
1>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
1>======sioe status======
1>TA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TA_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TA_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TA_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
1>TA_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
1>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
1>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
1>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
1>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
1>==========end==========
1>sioe init done
1>ufs task enabled
1>--> UFS profile[0]
1>UEFI parameters ready
1>UncoreMaxFreq Set to [2900 MHZ]
1>get TDP from efuse success, value = 307500mw
1>target power set to [307500]mw, brd:[307500]
1>age task parameters from uefi ready
1>demt task parameters from uefi ready
1>age task enabled
1>uefi ddr init finish!
1>ipu interface task wait uefi end done from uefi...
1>ddr init done, start thermal dimm task
1>======dimm status======
1>  chl[0] dimm0 0, dimm1 0
1>  chl[1] dimm0 0, dimm1 0
1>  chl[2] dimm0 0, dimm1 0
1>  chl[3] dimm0 0, dimm1 0
1>  chl[4] dimm0 0, dimm1 0
1>  chl[5] dimm0 0, dimm1 0
1>  chl[6] dimm0 0, dimm1 0
1>  chl[7] dimm0 0, dimm1 0
1>==========end==========
1>=====dimm temp params=====
1>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
1>  is_thermal_thro_en  : 1
1>  is_aref_rate_auto   : 1
1>===========end============
1>uefi end finish!
1>ipu interface task exit!
1>amu task parameters from uefi ready
1>amu task activated
1>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
v TB[ 915]mv
2>[2650]MHZ -> Vol TA[ 930]mv TB[ 928]mv
2>[2700]MHZ -> Vol TA[ 943]mv TB[ 941]mv
2>[2750]MHZ -> Vol TA[ 961]mv TB[ 959]mv
2>[2800]MHZ -> Vol TA[ 979]mv TB[ 977]mv
2>[2850]MHZ -> Vol TA[ 997]mv TB[ 995]mv
2>[2900]MHZ -> Vol TA[1016]mv TB[1014]mv
2>[2950]MHZ -> Vol TA[1033]mv TB[1031]mv
2>[3000]MHZ -> Vol TA[1051]mv TB[1049]mv
2>[3050]MHZ -> Vol TA[1064]mv TB[1062]mv
2>[3100]MHZ -> Vol TA[1077]mv TB[1075]mv
2>Uncore VF curve:
2>Uncore [   0]MHZ -> Vol [ 810]mv
2>Uncore [ 100]MHZ -> Vol [ 810]mv
2>Uncore [ 200]MHZ -> Vol [ 810]mv
2>Uncore [ 300]MHZ -> Vol [ 810]mv
2>Uncore [ 400]MHZ -> Vol [ 810]mv
2>Uncore [ 500]MHZ -> Vol [ 810]mv
2>Uncore [ 600]MHZ -> Vol [ 810]mv
2>Uncore [ 700]MHZ -> Vol [ 810]mv
2>Uncore [ 800]MHZ -> Vol [ 810]mv
2>Uncore [ 900]MHZ -> Vol [ 810]mv
2>Uncore [1000]MHZ -> Vol [ 810]mv
2>Uncore [1100]MHZ -> Vol [ 810]mv
2>Uncore [1200]MHZ -> Vol [ 810]mv
2>Uncore [1300]MHZ -> Vol [ 810]mv
2>Uncore [1400]MHZ -> Vol [ 810]mv
2>Uncore [1500]MHZ -> Vol [ 810]mv
2>Uncore [1600]MHZ -> Vol [ 810]mv
2>Uncore [1700]MHZ -> Vol [ 810]mv
2>Uncore [1800]MHZ -> Vol [ 810]mv
2>Uncore [1900]MHZ -> Vol [ 810]mv
2>Uncore [2000]MHZ -> Vol [ 810]mv
2>Uncore [2100]MHZ -> Vol [ 810]mv
2>Uncore [2200]MHZ -> Vol [ 811]mv
2>Uncore [2300]MHZ -> Vol [ 828]mv
2>Uncore [2400]MHZ -> Vol [ 845]mv
2>Uncore [2500]MHZ -> Vol [ 862]mv
2>Uncore [2600]MHZ -> Vol [ 882]mv
2>Uncore [2700]MHZ -> Vol [ 902]mv
2>Uncore [2800]MHZ -> Vol [ 922]mv
2>Uncore [2900]MHZ -> Vol [ 943]mv
2>Uncore [3000]MHZ -> Vol [1100]mv
2>[TracePoint] type[  0] cmd[  1] data[  6]
2>[TracePoint] type[  0] cmd[  1] data[  7]
2>
********Hello Huawei LiteOS********

KpxxxxIPU Firmware Version : V32.70.0
LiteOS Kernel Version : 5.7.0
2>Run on ChipVersion[0] Node[2] Die[0]
2>build time : Feb 05 2026 20:30:00

2>**********************************
2>
main core booting up...
2>start set affinity
2>
mpidr = 0x81080000
2>sram ecc state: 0x0, sram ecc cnt: 0x0
2>[TracePoint] type[  0] cmd[  2] data[  1]
2>[TracePoint] type[  0] cmd[  2] data[  2]
2>LRDXSD_LOCK_OFFSET = 0x0
2>LRDXSD_ERRIMSK_OFFSET = 0x0
2>LRDXSD_DBG_OTIMSK_OFFSET = 0x0
2>LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
2>LRDXSD_DBG_EN_OFFSET = 0x1
2>======tsensor params======
2>  is_trimmed       : 1
2>  underclocking_en : 1
2>===========end============
2>soc tsensor init done
2>========vrd info from cpld========
2>vrd_id | u64                | pmbus_en | avsbus_en | loop | pmbus_id | pmbus_addr | avs_sw | pmbus_sw | addr_9545 | domain_type | die_mask | reserved
2>  00   | 0x0001000100002017 | 0x1      | 0x1       | 0x1  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0100   | 0x0
2>  01   | 0x000001060000201b | 0x1      | 0x1       | 0x2  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x6         | 0x0001   | 0x0
2>  02   | 0x0003000300002715 | 0x1      | 0x0       | 0x1  | 0x1      | 0x27       | 0x0    | 0x0      | 0x0       | 0x3         | 0x0300   | 0x0
2>  03   | 0x0003000400002719 | 0x1      | 0x0       | 0x2  | 0x1      | 0x27       | 0x0    | 0x0      | 0x0       | 0x4         | 0x0300   | 0x0
2>  04   | 0x0002000100002027 | 0x1      | 0x1       | 0x1  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0200   | 0x0
2>  05   | 0x000300020000202b | 0x1      | 0x1       | 0x2  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x2         | 0x0300   | 0x0
2>  06   | 0x0000020a00002725 | 0x1      | 0x0       | 0x1  | 0x2      | 0x27       | 0x0    | 0x0      | 0x0       | 0xa         | 0x0002   | 0x0
2>  07   | 0x0000020500002729 | 0x1      | 0x0       | 0x2  | 0x2      | 0x27       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0002   | 0x0
2>  08   | 0x0000020600002a25 | 0x1      | 0x0       | 0x1  | 0x2      | 0x2a       | 0x0    | 0x0      | 0x0       | 0x6         | 0x0002   | 0x0
2>  09   | 0x0000010a00002a29 | 0x1      | 0x0       | 0x2  | 0x2      | 0x2a       | 0x0    | 0x0      | 0x0       | 0xa         | 0x0001   | 0x0
2>================end===============
2>=============vrd info=============
2>power domain num: 10
2>power domain[00] id:0 | CORE_DVFS_TA       | PMBus NA | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
2>power domain[01] id:10 | IO_DVDD09_NA       | PMBus NA | cap:0x3 | rail:1 | addr:0x20 | def_volt: 900 mV | min_volt: 700 mV | max_volt: 900 mV
2>power domain[02] id:1 | DDR_VDD            | PMBus NA | cap:0x1 | rail:0 | addr:0x27 | def_volt: 800 mV | min_volt: 760 mV | max_volt: 840 mV
2>power domain[03] id:6 | DDR_VDDQ           | PMBus NA | cap:0x1 | rail:1 | addr:0x27 | def_volt:1100 mV | min_volt:1000 mV | max_volt:1200 mV
2>power domain[04] id:2 | CORE_DVFS_TB       | PMBus NB | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
2>power domain[05] id:3 | UNCORE_DVFS        | PMBus NB | cap:0x3 | rail:1 | addr:0x20 | def_volt: 943 mV | min_volt: 750 mV | max_volt:1100 mV
2>power domain[06] id:15 | NB_AVDD_SDS        | PMBus NB | cap:0x1 | rail:0 | addr:0x27 | def_volt:1200 mV | min_volt:1164 mV | max_volt:1236 mV
2>power domain[07] id:5 | IO_DVDD_NB         | PMBus NB | cap:0x1 | rail:1 | addr:0x27 | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
2>power domain[08] id:11 | IO_DVDD09_NB       | PMBus NB | cap:0x1 | rail:0 | addr:0x2a | def_volt: 900 mV | min_volt: 700 mV | max_volt: 900 mV
2>power domain[09] id:13 | NA_AVDD_SDS        | PMBus NB | cap:0x1 | rail:1 | addr:0x2a | def_volt:1200 mV | min_volt:1164 mV | max_volt:1236 mV
2>================end===============
2>pmbus[0] init done
2>pmbus[1] init done
2>power domain[0] CORE_DVFS_TA       | NA PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
2>power domain[10] IO_DVDD09_NA       | NA PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 900 mV | pmu:MP2882
2>power domain[1] DDR_VDD            | NA PMBus        | rail:0 | addr:0x27 | def_volt: 800 mV | pmu:MP2882
2>power domain[6] DDR_VDDQ           | NA PMBus        | rail:1 | addr:0x27 | def_volt:1100 mV | pmu:MP2882
2>power domain[2] CORE_DVFS_TB       | NB PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
2>power domain[3] UNCORE_DVFS        | NB PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 943 mV | pmu:MP2882
2>power domain[15] NB_AVDD_SDS        | NB PMBus        | rail:0 | addr:0x27 | def_volt:1200 mV | pmu:MP2882
2>power domain[5] IO_DVDD_NB         | NB PMBus        | rail:1 | addr:0x27 | def_volt: 800 mV | pmu:MP2882
2>power domain[11] IO_DVDD09_NB       | NB PMBus        | rail:0 | addr:0x2a | def_volt: 900 mV | pmu:MP2882
2>power domain[13] NA_AVDD_SDS        | NB PMBus        | rail:1 | addr:0x2a | def_volt:1200 mV | pmu:MP2882
2>power domain[0] CORE_DVFS_TA       is transferred to AVSBus mode
2>power domain[10] IO_DVDD09_NA       is transferred to AVSBus mode
2>power domain[2] CORE_DVFS_TB       is transferred to AVSBus mode
2>power domain[3] UNCORE_DVFS        is transferred to AVSBus mode
2>avsbus resync success
2>avsbus[0] init done
2>avsbus resync success
2>avsbus[1] init done
2>============volt boot============
2>power domain[0] volt =  894 mV
2>power domain[10] volt =  904 mV
2>power domain[1] volt =  806 mV
2>power domain[6] volt = 1105 mV
2>power domain[2] volt =  896 mV
2>power domain[3] volt =  814 mV
2>power domain[15] volt = 1208 mV
2>power domain[5] volt =  806 mV
2>power domain[11] volt =  906 mV
2>power domain[13] volt = 1203 mV
2>===============end===============
2>--w&h rd rail:0, 896, CORE_DVFS_TA
2>--w&h rd rail:1, 900, CORE_DVFS_TA
2>power domain[0] set volt --> 1105 mV success
2>--w&h rd rail:0, 896, CORE_DVFS_TB
2>--w&h rd rail:1, 812, CORE_DVFS_TB
2>power domain[2] set volt --> 1107 mV success
2>power domain[3] set volt -->  947 mV success
2>============volt post============
2>power domain[0] volt = 1103 mV
2>power domain[10] volt =  902 mV
2>power domain[1] volt =  806 mV
2>power domain[6] volt = 1103 mV
2>power domain[2] volt = 1107 mV
2>power domain[3] volt =  949 mV
2>power domain[15] volt = 1206 mV
2>power domain[5] volt =  804 mV
2>power domain[11] volt =  906 mV
2>power domain[13] volt = 1205 mV
2>===============end===============
2>die[0] its[0] init done
2>die[0] its[1] init done
2>die[0] its[2] init done
2>die[0] its[3] init done
2>die[0] its[4] init done
2>die[0] its[5] init done
2>die[0] its[6] init done
2>die[0] its[7] init done
2>die[0] its[8] init done
2>die[0] its[9] init done
2>die[1] its[0] init done
2>die[1] its[1] init done
2>die[1] its[2] init done
2>die[1] its[3] init done
2>die[1] its[4] init done
2>die[1] its[5] init done
2>die[1] its[6] init done
2>die[1] its[7] init done
2>die[1] its[8] init done
2>die[1] its[9] init done
2>Totem[0] Core Boot Vol [1103]mv
2>Totem[0] Core Current Vol [1100]mv
2>Totem[1] Core Boot Vol [1107]mv
2>Totem[1] Core Current Vol [1100]mv
2>NA 1620V1a0
2>NB 1620V1a0
2>GetCoreBaseFreq [2500000KHZ]
2>GetCoreTurboFreq [2500000KHZ]
2>GetCustomClusterNum [10]
2>Ipu ACG Training Done!
2>AP Last Time:[0.00.01.468]
2>wait UEFI pll init...
2>done
2>acg trim start
2>core trim freq:2000, avs:0 volt:810mv
2>core trim freq:2000, avs:0 volt:810mv
2>core trim freq:2050, avs:1 volt:810mv
2>core trim freq:2050, avs:1 volt:810mv
2>core trim freq:2100, avs:2 volt:810mv
2>core trim freq:2100, avs:2 volt:810mv
2>core trim freq:2150, avs:3 volt:810mv
2>core trim freq:2150, avs:3 volt:810mv
2>core trim freq:2200, avs:4 volt:814mv
2>core trim freq:2200, avs:4 volt:813mv
2>core trim freq:2250, avs:5 volt:827mv
2>core trim freq:2250, avs:5 volt:825mv
2>core trim freq:2300, avs:6 volt:840mv
2>core trim freq:2300, avs:6 volt:838mv
2>core trim freq:2350, avs:7 volt:853mv
2>core trim freq:2350, avs:7 volt:851mv
2>core trim freq:2400, avs:8 volt:865mv
2>core trim freq:2400, avs:8 volt:864mv
2>core trim freq:2450, avs:9 volt:878mv
2>core trim freq:2450, avs:9 volt:877mv
2>core trim freq:2500, avs:10 volt:891mv
2>core trim freq:2500, avs:10 volt:889mv
2>core trim freq:2550, avs:11 volt:904mv
2>core trim freq:2550, avs:11 volt:902mv
2>core trim freq:2600, avs:12 volt:917mv
2>core trim freq:2600, avs:12 volt:915mv
2>core trim freq:2650, avs:13 volt:930mv
2>core trim freq:2650, avs:13 volt:928mv
2>core trim freq:2700, avs:14 volt:943mv
2>core trim freq:2700, avs:14 volt:941mv
2>core trim freq:2750, avs:15 volt:961mv
2>core trim freq:2750, avs:15 volt:959mv
2>core trim freq:2800, avs:16 volt:979mv
2>core trim freq:2800, avs:16 volt:977mv
2>core trim freq:2850, avs:17 volt:997mv
2>core trim freq:2850, avs:17 volt:995mv
2>core trim freq:2900, avs:18 volt:1016mv
2>core trim freq:2900, avs:18 volt:1014mv
2>core trim freq:2950, avs:19 volt:1033mv
2>core trim freq:2950, avs:19 volt:1031mv
2>core trim freq:3000, avs:20 volt:1051mv
2>core trim freq:3000, avs:20 volt:1049mv
2>core trim freq:3050, avs:21 volt:1064mv
2>core trim freq:3050, avs:21 volt:1062mv
2>core trim freq:3100, avs:22 volt:1077mv
2>core trim freq:3100, avs:22 volt:1075mv
2>acg trim end
2>LDO disabled
2>[TracePoint] type[  0] cmd[  2] data[  3]
2>Interrupt 423 register OK
2>Interrupt 430 register OK
2>[TracePoint] type[  0] cmd[  2] data[  4]
2>
2>cpu 0 entering scheduler
2>[TracePoint] type[  0] cmd[  3] data[  1]
2>add your ipu app init here!
2>IpuInterfaceTaskStart Entry ...
2>ipu interface task wait parameters from uefi...
2>thermal soc task enabled
2>AP Last Time:[0.00.07.217]
2>ThermalDimmStart Entry ...
2>wait ddr init done...
2>power task start...
2>[TracePoint] type[  0] cmd[  3] data[  2]
2>ufs task wait parameters from uefi...
2>AmuTaskStart Entry ... 
2>amu task wait parameters from uefi...
2>ThermalSiwStart Entry ...
2>ThermalSiwTask idle...
2>DemtTaskStart Entry ...
2>[TracePoint] type[  0] cmd[  3] data[  3]
2>demt task wait parameters from uefi...
2>HiBoostTaskStart Entry ...
2>HiBoost task enabled
2>Waiting for UEFI parameters...
2>[TracePoint] type[  0] cmd[  3] data[  4]
2>AgeTaskStart Entry ...
2>age task wait parameters from uefi...
2>[TracePoint] type[  0] cmd[  3] data[  5]
2>uefi parameters ready!
2>UFSProfile[0]
2>PowerPolicy[2] BenchMarkSelection[0]
2>ipu interface task wait ddr init done from uefi...
2>ufs task parameters from uefi ready
2>uncore domain[0] freq:2900
2>uncore domain[1] freq:2900
2>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
2>thermal soc task restore underclocking_en=1
2>ppu alert temp div init done
2>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
2>======sioe status======
2>TA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
2>TA_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
2>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
2>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
2>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
2>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
2>==========end==========
2>sioe init done
2>ufs task enabled
2>--> UFS profile[0]
2>UEFI parameters ready
2>UncoreMaxFreq Set to [2900 MHZ]
2>get TDP from efuse success, value = 307500mw
2>target power set to [307500]mw, brd:[307500]
2>demt task parameters from uefi ready
2>age task parameters from uefi ready
2>age task enabled
2>uefi ddr init finish!
2>ipu interface task wait uefi end done from uefi...
2>ddr init done, start thermal dimm task
2>======dimm status======
2>  chl[0] dimm0 0, dimm1 0
2>  chl[1] dimm0 0, dimm1 0
2>  chl[2] dimm0 2, dimm1 0
2>  chl[3] dimm0 0, dimm1 0
2>  chl[4] dimm0 0, dimm1 0
2>  chl[5] dimm0 0, dimm1 0
2>  chl[6] dimm0 0, dimm1 0
2>  chl[7] dimm0 0, dimm1 0
2>==========end==========
2>chl[2] registered, dimm mask = 0x1
2>=====dimm temp params=====
2>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
2>  is_thermal_thro_en  : 1
2>  is_aref_rate_auto   : 1
2>===========end============
2>chl[2] max_temp 46'C, aref_rate 0x5 --> 0x4
2>uefi end finish!
2>ipu interface task exit!
2>amu task parameters from uefi ready
2>amu task activated
2>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
810]mv
3>Uncore [ 100]MHZ -> Vol [ 810]mv
3>Uncore [ 200]MHZ -> Vol [ 810]mv
3>Uncore [ 300]MHZ -> Vol [ 810]mv
3>Uncore [ 400]MHZ -> Vol [ 810]mv
3>Uncore [ 500]MHZ -> Vol [ 810]mv
3>Uncore [ 600]MHZ -> Vol [ 810]mv
3>Uncore [ 700]MHZ -> Vol [ 810]mv
3>Uncore [ 800]MHZ -> Vol [ 810]mv
3>Uncore [ 900]MHZ -> Vol [ 810]mv
3>Uncore [1000]MHZ -> Vol [ 810]mv
3>Uncore [1100]MHZ -> Vol [ 810]mv
3>Uncore [1200]MHZ -> Vol [ 810]mv
3>Uncore [1300]MHZ -> Vol [ 810]mv
3>Uncore [1400]MHZ -> Vol [ 810]mv
3>Uncore [1500]MHZ -> Vol [ 810]mv
3>Uncore [1600]MHZ -> Vol [ 810]mv
3>Uncore [1700]MHZ -> Vol [ 810]mv
3>Uncore [1800]MHZ -> Vol [ 810]mv
3>Uncore [1900]MHZ -> Vol [ 810]mv
3>Uncore [2000]MHZ -> Vol [ 810]mv
3>Uncore [2100]MHZ -> Vol [ 810]mv
3>Uncore [2200]MHZ -> Vol [ 811]mv
3>Uncore [2300]MHZ -> Vol [ 828]mv
3>Uncore [2400]MHZ -> Vol [ 845]mv
3>Uncore [2500]MHZ -> Vol [ 862]mv
3>Uncore [2600]MHZ -> Vol [ 882]mv
3>Uncore [2700]MHZ -> Vol [ 902]mv
3>Uncore [2800]MHZ -> Vol [ 922]mv
3>Uncore [2900]MHZ -> Vol [ 943]mv
3>Uncore [3000]MHZ -> Vol [1100]mv
3>[TracePoint] type[  0] cmd[  1] data[  6]
3>[TracePoint] type[  0] cmd[  1] data[  7]
3>
********Hello Huawei LiteOS********

KpxxxxIPU Firmware Version : V32.70.0
LiteOS Kernel Version : 5.7.0
3>Run on ChipVersion[0] Node[3] Die[0]
3>build time : Feb 05 2026 20:30:00

3>**********************************
3>
main core booting up...
3>start set affinity
3>
mpidr = 0x810c0000
3>sram ecc state: 0x0, sram ecc cnt: 0x0
3>[TracePoint] type[  0] cmd[  2] data[  1]
3>[TracePoint] type[  0] cmd[  2] data[  2]
3>LRDXSD_LOCK_OFFSET = 0x0
3>LRDXSD_ERRIMSK_OFFSET = 0x0
3>LRDXSD_DBG_OTIMSK_OFFSET = 0x0
3>LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
3>LRDXSD_DBG_EN_OFFSET = 0x1
3>======tsensor params======
3>  is_trimmed       : 1
3>  underclocking_en : 1
3>===========end============
3>soc tsensor init done
3>========vrd info from cpld========
3>vrd_id | u64                | pmbus_en | avsbus_en | loop | pmbus_id | pmbus_addr | avs_sw | pmbus_sw | addr_9545 | domain_type | die_mask | reserved
3>  00   | 0x0001000100002017 | 0x1      | 0x1       | 0x1  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0100   | 0x0
3>  01   | 0x000300030000201b | 0x1      | 0x1       | 0x2  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x3         | 0x0300   | 0x0
3>  02   | 0x0000010a00002715 | 0x1      | 0x0       | 0x1  | 0x1      | 0x27       | 0x0    | 0x0      | 0x0       | 0xa         | 0x0001   | 0x0
3>  03   | 0x0000010500002719 | 0x1      | 0x0       | 0x2  | 0x1      | 0x27       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0001   | 0x0
3>  04   | 0x0000020600002a15 | 0x1      | 0x0       | 0x1  | 0x1      | 0x2a       | 0x0    | 0x0      | 0x0       | 0x6         | 0x0002   | 0x0
3>  05   | 0x0000010600002a19 | 0x1      | 0x0       | 0x2  | 0x1      | 0x2a       | 0x0    | 0x0      | 0x0       | 0x6         | 0x0001   | 0x0
3>  06   | 0x0000020a00002f15 | 0x1      | 0x0       | 0x1  | 0x1      | 0x2f       | 0x0    | 0x0      | 0x0       | 0xa         | 0x0002   | 0x0
3>  07   | 0x0002000100002027 | 0x1      | 0x1       | 0x1  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0200   | 0x0
3>  08   | 0x000300020000202b | 0x1      | 0x1       | 0x2  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x2         | 0x0300   | 0x0
3>  09   | 0x0000030500002725 | 0x1      | 0x0       | 0x1  | 0x2      | 0x27       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0003   | 0x0
3>  10   | 0x0003000400002729 | 0x1      | 0x0       | 0x2  | 0x2      | 0x27       | 0x0    | 0x0      | 0x0       | 0x4         | 0x0300   | 0x0
3>================end===============
3>=============vrd info=============
3>power domain num: 11
3>power domain[00] id:0 | CORE_DVFS_TA       | PMBus NA | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
3>power domain[01] id:1 | DDR_VDD            | PMBus NA | cap:0x3 | rail:1 | addr:0x20 | def_volt: 800 mV | min_volt: 760 mV | max_volt: 840 mV
3>power domain[02] id:14 | NA_AVDD_SDS        | PMBus NA | cap:0x1 | rail:0 | addr:0x27 | def_volt:1200 mV | min_volt:1164 mV | max_volt:1236 mV
3>power domain[03] id:4 | IO_DVDD_NA         | PMBus NA | cap:0x1 | rail:1 | addr:0x27 | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
3>power domain[04] id:11 | IO_DVDD09_NB       | PMBus NA | cap:0x1 | rail:0 | addr:0x2a | def_volt: 900 mV | min_volt: 700 mV | max_volt: 900 mV
3>power domain[05] id:10 | IO_DVDD09_NA       | PMBus NA | cap:0x1 | rail:1 | addr:0x2a | def_volt: 900 mV | min_volt: 700 mV | max_volt: 900 mV
3>power domain[06] id:16 | NB_AVDD_SDS        | PMBus NA | cap:0x1 | rail:0 | addr:0x2f | def_volt:1200 mV | min_volt:1164 mV | max_volt:1236 mV
3>power domain[07] id:2 | CORE_DVFS_TB       | PMBus NB | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
3>power domain[08] id:3 | UNCORE_DVFS        | PMBus NB | cap:0x3 | rail:1 | addr:0x20 | def_volt: 943 mV | min_volt: 750 mV | max_volt:1100 mV
3>power domain[09] id:12 | IO_DVDD_NANB       | PMBus NB | cap:0x1 | rail:0 | addr:0x27 | def_volt: 800 mV | min_volt: 750 mV | max_volt: 900 mV
3>power domain[10] id:6 | DDR_VDDQ           | PMBus NB | cap:0x1 | rail:1 | addr:0x27 | def_volt:1100 mV | min_volt:1000 mV | max_volt:1200 mV
3>================end===============
3>pmbus[0] init done
3>pmbus[1] init done
3>power domain[0] CORE_DVFS_TA       | NA PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
3>power domain[1] DDR_VDD            | NA PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 800 mV | pmu:MP2882
3>power domain[14] NA_AVDD_SDS        | NA PMBus        | rail:0 | addr:0x27 | def_volt:1200 mV | pmu:MP2882
3>power domain[4] IO_DVDD_NA         | NA PMBus        | rail:1 | addr:0x27 | def_volt: 800 mV | pmu:MP2882
3>power domain[11] IO_DVDD09_NB       | NA PMBus        | rail:0 | addr:0x2a | def_volt: 900 mV | pmu:MP2882
3>power domain[10] IO_DVDD09_NA       | NA PMBus        | rail:1 | addr:0x2a | def_volt: 900 mV | pmu:MP2882
3>power domain[16] NB_AVDD_SDS        | NA PMBus        | rail:0 | addr:0x2f | def_volt:1200 mV | pmu:MP2882
3>power domain[2] CORE_DVFS_TB       | NB PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
3>power domain[3] UNCORE_DVFS        | NB PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 943 mV | pmu:MP2882
3>power domain[12] IO_DVDD_NANB       | NB PMBus        | rail:0 | addr:0x27 | def_volt: 800 mV | pmu:MP2882
3>power domain[6] DDR_VDDQ           | NB PMBus        | rail:1 | addr:0x27 | def_volt:1100 mV | pmu:MP2882
3>power domain[0] CORE_DVFS_TA       is transferred to AVSBus mode
3>power domain[1] DDR_VDD            is transferred to AVSBus mode
3>power domain[2] CORE_DVFS_TB       is transferred to AVSBus mode
3>power domain[3] UNCORE_DVFS        is transferred to AVSBus mode
3>avsbus resync success
3>avsbus[0] init done
3>avsbus resync success
3>avsbus[1] init done
3>============volt boot============
3>power domain[0] volt =  886 mV
3>power domain[1] volt =  802 mV
3>power domain[14] volt = 1203 mV
3>power domain[4] volt =  802 mV
3>power domain[11] volt =  904 mV
3>power domain[10] volt =  904 mV
3>power domain[16] volt = 1205 mV
3>power domain[2] volt =  890 mV
3>power domain[3] volt =  814 mV
3>power domain[12] volt =  804 mV
3>power domain[6] volt = 1105 mV
3>===============end===============
3>--w&h rd rail:0, 886, CORE_DVFS_TA
3>--w&h rd rail:1, 800, CORE_DVFS_TA
3>power domain[0] set volt --> 1101 mV success
3>--w&h rd rail:0, 890, CORE_DVFS_TB
3>--w&h rd rail:1, 814, CORE_DVFS_TB
3>power domain[2] set volt --> 1101 mV success
3>power domain[3] set volt -->  949 mV success
3>============volt post============
3>power domain[0] volt = 1103 mV
3>power domain[1] volt =  802 mV
3>power domain[14] volt = 1203 mV
3>power domain[4] volt =  804 mV
3>power domain[11] volt =  906 mV
3>power domain[10] volt =  902 mV
3>power domain[16] volt = 1205 mV
3>power domain[2] volt = 1103 mV
3>power domain[3] volt =  949 mV
3>power domain[12] volt =  804 mV
3>power domain[6] volt = 1105 mV
3>===============end===============
3>the power sensor : manu id = 2peak, die id = TPA626
3>power sensor[0] init success
3>die[0] its[0] init done
3>die[0] its[1] init done
3>die[0] its[2] init done
3>die[0] its[3] init done
3>die[0] its[4] init done
3>die[0] its[5] init done
3>die[0] its[6] init done
3>die[0] its[7] init done
3>die[0] its[8] init done
3>die[0] its[9] init done
3>die[1] its[0] init done
3>die[1] its[1] init done
3>die[1] its[2] init done
3>die[1] its[3] init done
3>die[1] its[4] init done
3>die[1] its[5] init done
3>die[1] its[6] init done
3>die[1] its[7] init done
3>die[1] its[8] init done
3>die[1] its[9] init done
3>Totem[0] Core Boot Vol [1103]mv
3>Totem[0] Core Current Vol [1100]mv
3>Totem[1] Core Boot Vol [1101]mv
3>Totem[1] Core Current Vol [1100]mv
3>NA 1620V1a0
3>NB 1620V1a0
3>GetCoreBaseFreq [2500000KHZ]
3>GetCoreTurboFreq [2500000KHZ]
3>GetCustomClusterNum [10]
3>Ipu ACG Training Done!
3>AP Last Time:[0.00.01.521]
3>wait UEFI pll init...
3>done
3>acg trim start
3>core trim freq:2000, avs:0 volt:810mv
3>core trim freq:2000, avs:0 volt:810mv
3>core trim freq:2050, avs:1 volt:810mv
3>core trim freq:2050, avs:1 volt:810mv
3>core trim freq:2100, avs:2 volt:810mv
3>core trim freq:2100, avs:2 volt:810mv
3>core trim freq:2150, avs:3 volt:810mv
3>core trim freq:2150, avs:3 volt:810mv
3>core trim freq:2200, avs:4 volt:810mv
3>core trim freq:2200, avs:4 volt:811mv
3>core trim freq:2250, avs:5 volt:820mv
3>core trim freq:2250, avs:5 volt:824mv
3>core trim freq:2300, avs:6 volt:833mv
3>core trim freq:2300, avs:6 volt:836mv
3>core trim freq:2350, avs:7 volt:845mv
3>core trim freq:2350, avs:7 volt:849mv
3>core trim freq:2400, avs:8 volt:858mv
3>core trim freq:2400, avs:8 volt:862mv
3>core trim freq:2450, avs:9 volt:870mv
3>core trim freq:2450, avs:9 volt:874mv
3>core trim freq:2500, avs:10 volt:883mv
3>core trim freq:2500, avs:10 volt:887mv
3>core trim freq:2550, avs:11 volt:895mv
3>core trim freq:2550, avs:11 volt:900mv
3>core trim freq:2600, avs:12 volt:908mv
3>core trim freq:2600, avs:12 volt:912mv
3>core trim freq:2650, avs:13 volt:920mv
3>core trim freq:2650, avs:13 volt:925mv
3>core trim freq:2700, avs:14 volt:933mv
3>core trim freq:2700, avs:14 volt:938mv
3>core trim freq:2750, avs:15 volt:951mv
3>core trim freq:2750, avs:15 volt:956mv
3>core trim freq:2800, avs:16 volt:969mv
3>core trim freq:2800, avs:16 volt:974mv
3>core trim freq:2850, avs:17 volt:987mv
3>core trim freq:2850, avs:17 volt:992mv
3>core trim freq:2900, avs:18 volt:1005mv
3>core trim freq:2900, avs:18 volt:1011mv
3>core trim freq:2950, avs:19 volt:1022mv
3>core trim freq:2950, avs:19 volt:1028mv
3>core trim freq:3000, avs:20 volt:1039mv
3>core trim freq:3000, avs:20 volt:1045mv
3>core trim freq:3050, avs:21 volt:1053mv
3>core trim freq:3050, avs:21 volt:1058mv
3>core trim freq:3100, avs:22 volt:1067mv
3>core trim freq:3100, avs:22 volt:1072mv
3>acg trim end
3>LDO disabled
3>[TracePoint] type[  0] cmd[  2] data[  3]
3>Interrupt 423 register OK
3>Interrupt 430 register OK
3>[TracePoint] type[  0] cmd[  2] data[  4]
3>
3>cpu 0 entering scheduler
3>[TracePoint] type[  0] cmd[  3] data[  1]
3>add your ipu app init here!
3>IpuInterfaceTaskStart Entry ...
3>ipu interface task wait parameters from uefi...
3>thermal soc task enabled
3>AP Last Time:[0.00.07.205]
3>ThermalDimmStart Entry ...
3>wait ddr init done...
3>power task start...
3>[TracePoint] type[  0] cmd[  3] data[  2]
3>ufs task wait parameters from uefi...
3>AmuTaskStart Entry ... 
3>amu task wait parameters from uefi...
3>ThermalSiwStart Entry ...
3>ThermalSiwTask idle...
3>DemtTaskStart Entry ...
3>[TracePoint] type[  0] cmd[  3] data[  3]
3>HiBoostTaskStart Entry ...
3>HiBoost task enabled
3>Waiting for UEFI parameters...
3>[TracePoint] type[  0] cmd[  3] data[  4]
3>demt task wait parameters from uefi...
3>AgeTaskStart Entry ...
3>age task wait parameters from uefi...
3>[TracePoint] type[  0] cmd[  3] data[  5]
3>uefi parameters ready!
3>UFSProfile[0]
3>PowerPolicy[2] BenchMarkSelection[0]
3>ipu interface task wait ddr init done from uefi...
3>ufs task parameters from uefi ready
3>uncore domain[0] freq:2900
3>uncore domain[1] freq:2900
3>thermal soc task restore underclocking_en=1
3>ppu alert temp div init done
3>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
3>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
3>======sioe status======
3>TA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
3>TA_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
3>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
3>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
3>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
3>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
3>==========end==========
3>sioe init done
3>ufs task enabled
3>--> UFS profile[0]
3>UEFI parameters ready
3>UncoreMaxFreq Set to [2900 MHZ]
3>get TDP from efuse success, value = 307500mw
3>target power set to [307500]mw, brd:[307500]
3>age task parameters from uefi ready
3>demt task parameters from uefi ready
3>age task enabled
3>uefi ddr init finish!
3>ipu interface task wait uefi end done from uefi...
3>ddr init done, start thermal dimm task
3>======dimm status======
3>  chl[0] dimm0 0, dimm1 0
3>  chl[1] dimm0 0, dimm1 0
3>  chl[2] dimm0 0, dimm1 0
3>  chl[3] dimm0 0, dimm1 0
3>  chl[4] dimm0 0, dimm1 0
3>  chl[5] dimm0 0, dimm1 0
3>  chl[6] dimm0 0, dimm1 0
3>  chl[7] dimm0 0, dimm1 0
3>==========end==========
3>=====dimm temp params=====
3>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
3>  is_thermal_thro_en  : 1
3>  is_aref_rate_auto   : 1
3>===========end============
3>uefi end finish!
3>ipu interface task exit!
3>amu task parameters from uefi ready
3>amu task activated
3>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!


HSM_LOG:
[00:00:00.010][info] os_mem_system_init default pool done
[00:00:00.016][info] succeed to do thirdparty otpc_pabuk init
[00:00



HSM_LOG:
:00.017][info] succeed to do thirdparty boot_profile_driver init
[00:00:00.017][info] succeed to do thirdparty measure_value_ma



HSM_LOG:
nage_driver init
[00:00:00.018][info] succeed to do thirdparty period_driver init
[00:00:00.018][info]  start loading internal



HSM_LOG:
 task ...
[00:00:00.018][info]  task name is ccm_task
[00:00:00.019][info]  hm_dynamic_loadelf successfully!
[00:00:00.019][i



HSM_LOG:
nfo] internal task[1] task_name=ccm_task load successfully
[00:00:00.020][info]  task name is upgrade_task
[00:00:00.020][info



HSM_LOG:
]  hm_dynamic_loadelf successfully!
[00:00:00.021][info] internal task[2] task_name=upgrade_task load successfully
[00:00:00.0



HSM_LOG:
22][info]  task name is hes_task
[00:00:00.022][info]  hm_dynamic_loadelf successfully!
[00:00:00.023][info] internal task[3] 



HSM_LOG:
task_name=hes_task load successfully
[00r init
[00:00:00.018][info] s



HSM_LOG:
ucceed to do thirdparty period_driver init
[00:00:00.018][info]  start loading internal task ...
[00:00:00.018][info]  task na



HSM_LOG:
me is ccm_task
[00:00:00.019][info]  hm_dynamic_loadelf successfully!
[00:00:00.019][info] internal task[1] task_name=ccm_task



HSM_LOG:
 load successfully
[00:00:00.020][info]  task name is upgrade_task
[00:00:00.020][info]  hm_dynamic_loadelf successfully!
[00



HSM_LOG:
:00:00.021][info] internal task[2] task_name=upgrade_task load successfully
[00:00:00.022][info]  task name is hes_task
[00:00



HSM_LOG:
:00.022][info]  hm_dynamic_loadelf successfully!
[00:00:00.023][info] internal task[3] task_name=hes_task load successfully
[0



HSM_LOG:
0:00:00.024][info] created task ccm_task success!
[00:00:00.025][info] created task upgrade_task success!
[00:00:00.026][info]



HSM_LOG:
 created task hes_task success!
[00:00:00.026][info] Init start.
[1970-01-01 00:00:00.027][HSM][INFO][54] Platform init 0x2025



HSM_LOG:
0523 0x4e.

[1970-01-01 00:00:00.027][HSM][INFO][197] ccm start.

[1970-01-01 00:00:00.028][HSM][INFO][86] upgrade task init s



HSM_LOG:
uccess.

[1970-01-01 00:00:00.028][HSM][INFO][95] upgrade recv cmd, 0x181.

[1970-01-01 00:00:00.029][HSM][INFO][103] upgrade 



HSM_LOG:
res, 0x3a5aa5a3.

[1970-01-01 00:00:00.030][HSM][INFO][75] hes tee_task_entry.

[1970-01-01 00:00:00.550][HSM][INFO][44] hes i



HSM_LOG:
nit success.

[00:00:00.551][info] Init over.
[1970-01-01 00:00:16.762][HSM][INFO][281] -------------1------------

.

[0.07.52.160]IpmiCmdReportPcieMMIO start
[0.08.15.739]IpmiCmdReportPcieMMIO end
pool addr          pool size    used size     free size    max free node size   used node num     free node num      UsageWaterLine
---------------    --------     -------       --------     --------------       -------------      ------------      ------------
0x840908e708       0x204c0      0x1a010       0x6240       0x5ad0               0xd9               0x3                0x1a9f0        
[14.54.18.833]ext0 int trigger

********Hello Huawei LiteOS********

KpxxxxIMU Firmware Version : V32.70.0
LiteOS Kernel Version : 5.7.0
Run on ChipVersion[0] Node[0] Die[2]
build time : Feb 05 2026 20:30:00

**********************************

main core booting up...
start set affinity

mpidr = 0x81020000
sram ecc state: 0x0, sram ecc cnt: 0x0
[0.00.00.033]node 0 begins init all serdes.
BoardInfo->NodeNum 4.
BoardInfo->NodeId 0.
BoardInfo->InfoVersion 5.
BoardInfo->NASerdesSceneMode 3.
BoardInfo->NBSerdesSceneMode 3.
BoardInfo->HccsTopologyType 7.
BoardInfo->BoardId 0.
ChipVersionIsPro: 1.
BoardInfo Node 0, SerdesUseMode: 1 2 12 4 4 4 4  1 1 1 4 4 1 1 
BoardInfo Node 1, SerdesUseMode: 1 1 1 4 4 1 1  12 13 1 4 4 4 4 
BoardInfo Node 2, SerdesUseMode: 12 13 12 4 4 4 4  1 1 1 4 4 1 1 
BoardInfo Node 3, SerdesUseMode: 1 1 1 4 4 1 1  12 13 1 4 4 4 4 
BoardInfo Node 0, SerdesRxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 255 255 
BoardInfo Node 1, SerdesRxPolarityReverse: 255 255 255 0 0 255 255  0 0 0 0 0 0 0 
BoardInfo Node 2, SerdesRxPolarityReverse: 0 0 0 0 0 0 0  0 0 255 0 0 0 255 
BoardInfo Node 3, SerdesRxPolarityReverse: 255 255 255 0 0 0 0  0 0 255 0 0 0 0 
BoardInfo Node 0, SerdesTxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 255 255 
BoardInfo Node 1, SerdesTxPolarityReverse: 255 255 255 0 0 255 255  0 0 0 0 0 0 0 
BoardInfo Node 2, SerdesTxPolarityReverse: 0 0 0 0 0 0 0  0 0 255 0 0 0 0 
BoardInfo Node 3, SerdesTxPolarityReverse: 255 255 255 0 0 0 0  0 0 255 0 0 0 0 
serdessdk version: 2.0_5.0_20241203_imu
node_id 0, die 0, ind 0, usemode 1 begin serdes-init.
node_id 0, die 0, ind 1, usemode 2 begin serdes-init.
node_id 0, die 0, ind 2, usemode 12 begin serdes-init.
chip_id 0, die 0, ind 2, usemode 12 don't support, power down macro!
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
node_id 0, die 2, ind 0, usemode 1 begin serdes-init.
node_id 0, die 2, ind 1, usemode 1 begin serdes-init.
chip serdes init status:0x0.
[0.00.00.484]node 0 ends init all serdes.
link[0] freq_type:1 | peer_chip_type:1 | peer_node_id:1 | peer_link_id:6
link[1] freq_type:1 | peer_chip_type:1 | peer_node_id:1 | peer_link_id:7
link[2] freq_type:1 | peer_chip_type:1 | peer_node_id:1 | peer_link_id:4
link[3] freq_type:1 | peer_chip_type:1 | peer_node_id:1 | peer_link_id:5
link[4] freq_type:1 | peer_chip_type:1 | peer_node_id:3 | peer_link_id:0
link[5] freq_type:1 | peer_chip_type:1 | peer_node_id:2 | peer_link_id:4
register hccs done
nodeId 0, dieId 0, linkId 0, FFE info: fir_pre1 0, fir_main 63, fir_post1 0
node_id 0, die 0, ind 4, usemode 4 begin serdes-init.
nodeId 0, dieId 0, linkId 1, FFE info: fir_pre1 0, fir_main 63, fir_post1 0
node_id 0, die 0, ind 3, usemode 4 begin serdes-init.
nodeId 0, dieId 0, linkId 2, FFE info: fir_pre1 0, fir_main 63, fir_post1 0
node_id 0, die 0, ind 5, usemode 4 begin serdes-init.
nodeId 0, dieId 0, linkId 3, FFE info: fir_pre1 0, fir_main 63, fir_post1 0
node_id 0, die 0, ind 6, usemode 4 begin serdes-init.
node_id 0, die 2, ind 4, usemode 4 begin serdes-init.
node_id 0, die 2, ind 3, usemode 4 begin serdes-init.
hccs init start...
pa ring link down success
reset pa success
link[0] pcs init success
link[1] pcs init success
link[2] pcs init success
link[3] pcs init success
link[4] pcs init success
link[5] pcs init success
release reset pa success
link[0] macro adapt done (lane_mask=0xff) (0ms)
link[1] macro adapt done (lane_mask=0xff) (0ms)
link[2] macro adapt done (lane_mask=0xff) (0ms)
link[3] macro adapt done (lane_mask=0xff) (0ms)
link[4] macro adapt done (lane_mask=0xff) (0ms)
link[5] macro adapt done (lane_mask=0xff) (0ms)
link[0] pcs training success (10ms)
link[1] pcs training success (10ms)
link[2] pcs training success (10ms)
link[3] pcs training success (10ms)
link[4] pcs training success (10ms)
link[5] pcs training success (10ms)
link[0] training success (20ms)
link[1] training success (20ms)
link[2] training success (20ms)
link[3] training success (20ms)
link[4] training success (20ms)
link[5] training success (20ms)
link[0]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link[1]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link[2]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link[3]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link[4]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link[5]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link training success
pa[0] linkEn = 0xf
pa[0] allNodeLink0 = 0xf0
pa[0] allNodeLink1 = 0x0
pa[1] linkEn = 0x3
pa[1] allNodeLink0 = 0x1200
pa[1] allNodeLink1 = 0x0
pa init success
COM_PAID_INTLV_REG = 0xc
paid decode init success
pa[0] PA_PM_BASE_INFO = 0xff8421
pa[0] PA_PM_MAP_LINK_NUM = 0x2184
pa[1] PA_PM_BASE_INFO = 0x330021
pa[1] PA_PM_MAP_LINK_NUM = 0x11
hccs performace config success
pa ring link up success
hccs init done
hccs access test start
node[0] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[1] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[2] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[3] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[1] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
node[2] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
node[3] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
hccs access test success
======hccs status======
  node[0] mask: expected = 0x3f, link up = 0x3f, width reduction = 0x0, link down = 0x0
  node[1] mask: expected = 0xf3, link up = 0xf3, width reduction = 0x0, link down = 0x0
  node[2] mask: expected = 0x3f, link up = 0x3f, width reduction = 0x0, link down = 0x0
  node[3] mask: expected = 0xf3, link up = 0xf3, width reduction = 0x0, link down = 0x0
==========end==========
report hccs status success
node[0] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
LRDXSD_LOCK_OFFSET = 0x0
LRDXSD_ERRIMSK_OFFSET = 0x0
LRDXSD_DBG_OTIMSK_OFFSET = 0x0
LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
LRDXSD_DBG_EN_OFFSET = 0x1
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
ID[0xff3a25c2]!
ID[0xff000000]!
[ERR]Don't support the flash, CS[1] ID[0xff000000]!!
sfdp detect, try to get dummy data from hboot1 first.
ID[0xff3a25c2]!
flash 0 support sfdp.
Interrupt 423 register OK
Interrupt 425 register OK
Interrupt 427 register OK
Interrupt 429 register OK
Interrupt 430 register OK
Interrupt 431 register OK
Interrupt 436 register OK

cpu 0 entering scheduler
[IMU] Watchdog Initialization done!
ScmiTaskEntry start.
Interrupt 456 register OK
Interrupt 469 register OK
Interrupt 482 register OK
Interrupt 495 register OK
Interrupt 508 register OK
Interrupt 521 register OK
Interrupt 534 register OK
Interrupt 547 register OK
starting Fpc Isolation Task end
starting fdm Err Info Task end
starting Roce recovery Task end
starting Ce_Storm Contrl Task end
starting Ras_Data_Update Task end
power register ubios call id
Interrupt 459 register OK
Interrupt 472 register OK
Interrupt 485 register OK
Interrupt 498 register OK
Interrupt 511 register OK
Interrupt 524 register OK
Interrupt 537 register OK
Interrupt 550 register OK
[0.00.04.526]Real time now 2026.7.24 05:54:45
NIC CARD[0][0]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[0][1]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[1][0]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[1][1]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[2][0]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[2][1]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[3][0]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[3][1]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
Init heart-beat-task end
Init SeamlessUpdateTask end
pool addr          pool size    used size     free size    max free node size   used node num     free node num      UsageWaterLine
---------------    --------     -------       --------     --------------       -------------      ------------      ------------
0x840908e708       0x204c0      0x1a780       0x5ad0       0x5ad0               0x79               0x1                0x1a9f0        
Get Setup Config.
pwr cap[0]: 0, 63
pwr cap[1]: f, 27
pwr cap[2]: 1, 3
Node 0, Die 0 ImpState is 0 skip exec.
Node 0, Die 2 ImpState is 0 skip exec.
Node 1, Die 0 ImpState is 0 skip exec.
Node 1, Die 2 ImpState is 0 skip exec.
Node 2, Die 0 ImpState is 0 skip exec.
Node 2, Die 2 ImpState is 0 skip exec.
Node 3, Die 0 ImpState is 0 skip exec.
Node 3, Die 2 ImpState is 0 skip exec.
[0.00.21.055]DDR Rreserved for IMU: len = 3e00000
[LOG]head = 0x159ec, tail = 0x17dd2, logSize = 0x23e6
copy registry.json file success
Set component all release version to sram end.
ipcMsgSend success
[0.00.21.095]starting ras Init
nodeId = 0, dieId = 0, isSasExist = 0.
nodeId = 0, dieId = 2, isSasExist = 0.
nodeId = 1, dieId = 0, isSasExist = 0.
nodeId = 1, dieId = 2, isSasExist = 0.
nodeId = 2, dieId = 0, isSasExist = 0.
nodeId = 2, dieId = 2, isSasExist = 0.
nodeId = 3, dieId = 0, isSasExist = 0.
nodeId = 3, dieId = 2, isSasExist = 0.
Mce Table head exist!
RasIntRegister init 452 
RasIntRegister init 453 
RasIntRegister init 64 
RasIntRegister init 65 
RasIntRegister init 465 
RasIntRegister init 466 
RasIntRegister init 86 
RasIntRegister init 87 
RasIntRegister init 478 
RasIntRegister init 479 
RasIntRegister init 108 
RasIntRegister init 109 
RasIntRegister init 491 
RasIntRegister init 492 
RasIntRegister init 130 
RasIntRegister init 131 
RasIntRegister init 504 
RasIntRegister init 505 
RasIntRegister init 152 
RasIntRegister init 153 
RasIntRegister init 517 
RasIntRegister init 518 
RasIntRegister init 174 
RasIntRegister init 175 
RasIntRegister init 530 
RasIntRegister init 531 
RasIntRegister init 196 
RasIntRegister init 197 
RasIntRegister init 543 
RasIntRegister init 544 
RasIntRegister init 218 
RasIntRegister init 219 
RasIntRegister init 76 
RasIntRegister init 98 
RasIntRegister init 120 
RasIntRegister init 142 
RasIntRegister init 164 
RasIntRegister init 186 
RasIntRegister init 208 
RasIntRegister init 230 
[0.00.21.216]starting ras end
[0.00.37.751][ERR]cmd not support! cmd = 0xd
[0.00.38.225]ext0 int trigger

********Hello Huawei LiteOS********

KpxxxxIMU Firmware Version : V32.70.0
LiteOS Kernel Version : 5.7.0
Run on ChipVersion[0] Node[0] Die[2]
build time : Feb 05 2026 20:30:00

**********************************

main core booting up...
start set affinity

mpidr = 0x81020000
sram ecc state: 0x0, sram ecc cnt: 0x0
[0.00.00.033]node 0 begins init all serdes.
BoardInfo->NodeNum 4.
BoardInfo->NodeId 0.
BoardInfo->InfoVersion 5.
BoardInfo->NASerdesSceneMode 3.
BoardInfo->NBSerdesSceneMode 3.
BoardInfo->HccsTopologyType 7.
BoardInfo->BoardId 0.
ChipVersionIsPro: 1.
BoardInfo Node 0, SerdesUseMode: 1 2 12 4 4 4 4  1 1 1 4 4 1 1 
BoardInfo Node 1, SerdesUseMode: 1 1 1 4 4 1 1  12 13 1 4 4 4 4 
BoardInfo Node 2, SerdesUseMode: 12 13 12 4 4 4 4  1 1 1 4 4 1 1 
BoardInfo Node 3, SerdesUseMode: 1 1 1 4 4 1 1  12 13 1 4 4 4 4 
BoardInfo Node 0, SerdesRxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 255 255 
BoardInfo Node 1, SerdesRxPolarityReverse: 255 255 255 0 0 255 255  0 0 0 0 0 0 0 
BoardInfo Node 2, SerdesRxPolarityReverse: 0 0 0 0 0 0 0  0 0 255 0 0 0 255 
BoardInfo Node 3, SerdesRxPolarityReverse: 255 255 255 0 0 0 0  0 0 255 0 0 0 0 
BoardInfo Node 0, SerdesTxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 255 255 
BoardInfo Node 1, SerdesTxPolarityReverse: 255 255 255 0 0 255 255  0 0 0 0 0 0 0 
BoardInfo Node 2, SerdesTxPolarityReverse: 0 0 0 0 0 0 0  0 0 255 0 0 0 0 
BoardInfo Node 3, SerdesTxPolarityReverse: 255 255 255 0 0 0 0  0 0 255 0 0 0 0 
serdessdk version: 2.0_5.0_20241203_imu
node_id 0, die 0, ind 0, usemode 1 begin serdes-init.
node_id 0, die 0, ind 1, usemode 2 begin serdes-init.
node_id 0, die 0, ind 2, usemode 12 begin serdes-init.
chip_id 0, die 0, ind 2, usemode 12 don't support, power down macro!
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
node_id 0, die 2, ind 0, usemode 1 begin serdes-init.
node_id 0, die 2, ind 1, usemode 1 begin serdes-init.
chip serdes init status:0x0.
[0.00.00.486]node 0 ends init all serdes.
link[0] freq_type:1 | peer_chip_type:1 | peer_node_id:1 | peer_link_id:6
link[1] freq_type:1 | peer_chip_type:1 | peer_node_id:1 | peer_link_id:7
link[2] freq_type:1 | peer_chip_type:1 | peer_node_id:1 | peer_link_id:4
link[3] freq_type:1 | peer_chip_type:1 | peer_node_id:1 | peer_link_id:5
link[4] freq_type:1 | peer_chip_type:1 | peer_node_id:3 | peer_link_id:0
link[5] freq_type:1 | peer_chip_type:1 | peer_node_id:2 | peer_link_id:4
register hccs done
nodeId 0, dieId 0, linkId 0, FFE info: fir_pre1 0, fir_main 63, fir_post1 0
node_id 0, die 0, ind 4, usemode 4 begin serdes-init.
nodeId 0, dieId 0, linkId 1, FFE info: fir_pre1 0, fir_main 63, fir_post1 0
node_id 0, die 0, ind 3, usemode 4 begin serdes-init.
nodeId 0, dieId 0, linkId 2, FFE info: fir_pre1 0, fir_main 63, fir_post1 0
node_id 0, die 0, ind 5, usemode 4 begin serdes-init.
nodeId 0, dieId 0, linkId 3, FFE info: fir_pre1 0, fir_main 63, fir_post1 0
node_id 0, die 0, ind 6, usemode 4 begin serdes-init.
node_id 0, die 2, ind 4, usemode 4 begin serdes-init.
node_id 0, die 2, ind 3, usemode 4 begin serdes-init.
hccs init start...
pa ring link down success
reset pa success
link[0] pcs init success
link[1] pcs init success
link[2] pcs init success
link[3] pcs init success
link[4] pcs init success
link[5] pcs init success
release reset pa success
link[0] macro adapt done (lane_mask=0xff) (0ms)
link[1] macro adapt done (lane_mask=0xff) (0ms)
link[2] macro adapt done (lane_mask=0xff) (0ms)
link[3] macro adapt done (lane_mask=0xff) (0ms)
link[4] macro adapt done (lane_mask=0xff) (0ms)
link[5] macro adapt done (lane_mask=0xff) (0ms)
link[0] pcs training success (10ms)
link[1] pcs training success (10ms)
link[2] pcs training success (10ms)
link[3] pcs training success (10ms)
link[4] pcs training success (10ms)
link[5] pcs training success (10ms)
link[0] training success (20ms)
link[1] training success (20ms)
link[2] training success (20ms)
link[3] training success (20ms)
link[4] training success (20ms)
link[5] training success (20ms)
link[0]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link[1]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link[2]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link[3]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link[4]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link[5]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link training success
pa[0] linkEn = 0xf
pa[0] allNodeLink0 = 0xf0
pa[0] allNodeLink1 = 0x0
pa[1] linkEn = 0x3
pa[1] allNodeLink0 = 0x1200
pa[1] allNodeLink1 = 0x0
pa init success
COM_PAID_INTLV_REG = 0xc
paid decode init success
pa[0] PA_PM_BASE_INFO = 0xff8421
pa[0] PA_PM_MAP_LINK_NUM = 0x2184
pa[1] PA_PM_BASE_INFO = 0x330021
pa[1] PA_PM_MAP_LINK_NUM = 0x11
hccs performace config success
pa ring link up success
hccs init done
hccs access test start
node[0] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[1] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[2] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[3] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[1] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
node[2] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
node[3] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
hccs access test success
======hccs status======
  node[0] mask: expected = 0x3f, link up = 0x3f, width reduction = 0x0, link down = 0x0
  node[1] mask: expected = 0xf3, link up = 0xf3, width reduction = 0x0, link down = 0x0
  node[2] mask: expected = 0x3f, link up = 0x3f, width reduction = 0x0, link down = 0x0
  node[3] mask: expected = 0xf3, link up = 0xf3, width reduction = 0x0, link down = 0x0
==========end==========
report hccs status success
node[0] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
LRDXSD_LOCK_OFFSET = 0x0
LRDXSD_ERRIMSK_OFFSET = 0x0
LRDXSD_DBG_OTIMSK_OFFSET = 0x0
LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
LRDXSD_DBG_EN_OFFSET = 0x1
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
ID[0xff3a25c2]!
ID[0xff000000]!
[ERR]Don't support the flash, CS[1] ID[0xff000000]!!
sfdp detect, try to get dummy data from hboot1 first.
ID[0xff3a25c2]!
flash 0 support sfdp.
Interrupt 423 register OK
Interrupt 425 register OK
Interrupt 427 register OK
Interrupt 429 register OK
Interrupt 430 register OK
Interrupt 431 register OK
Interrupt 436 register OK

cpu 0 entering scheduler
[IMU] Watchdog Initialization done!
ScmiTaskEntry start.
Interrupt 456 register OK
Interrupt 469 register OK
Interrupt 482 register OK
Interrupt 495 register OK
Interrupt 508 register OK
Interrupt 521 register OK
Interrupt 534 register OK
Interrupt 547 register OK
starting Fpc Isolation Task end
starting fdm Err Info Task end
starting Roce recovery Task end
starting Ce_Storm Contrl Task end
starting Ras_Data_Update Task end
power register ubios call id
Interrupt 459 register OK
Interrupt 472 register OK
Interrupt 485 register OK
Interrupt 498 register OK
Interrupt 511 register OK
Interrupt 524 register OK
Interrupt 537 register OK
Interrupt 550 register OK
[0.00.04.528]Real time now 2026.7.24 05:55:34
NIC CARD[0][0]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[0][1]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[1][0]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[1][1]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[2][0]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[2][1]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[3][0]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[3][1]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
Init heart-beat-task end
Init SeamlessUpdateTask end
pool addr          pool size    used size     free size    max free node size   used node num     free node num      UsageWaterLine
---------------    --------     -------       --------     --------------       -------------      ------------      ------------
0x840908e708       0x204c0      0x1a780       0x5ad0       0x5ad0               0x79               0x1                0x1a9f0        
Get Setup Config.
pwr cap[0]: 0, 63
pwr cap[1]: f, 27
pwr cap[2]: 1, 3
Node 0, Die 0 ImpState is 0 skip exec.
Node 0, Die 2 ImpState is 0 skip exec.
Node 1, Die 0 ImpState is 0 skip exec.
Node 1, Die 2 ImpState is 0 skip exec.
Node 2, Die 0 ImpState is 0 skip exec.
Node 2, Die 2 ImpState is 0 skip exec.
Node 3, Die 0 ImpState is 0 skip exec.
Node 3, Die 2 ImpState is 0 skip exec.
[0.00.20.781]DDR Rreserved for IMU: len = 3e00000
[LOG]head = 0x159ec, tail = 0x1a7ec, logSize = 0x4e00
copy registry.json file success
Set component all release version to sram end.
ipcMsgSend success
[0.00.20.821]starting ras Init
nodeId = 0, dieId = 0, isSasExist = 0.
nodeId = 0, dieId = 2, isSasExist = 0.
nodeId = 1, dieId = 0, isSasExist = 0.
nodeId = 1, dieId = 2, isSasExist = 0.
nodeId = 2, dieId = 0, isSasExist = 0.
nodeId = 2, dieId = 2, isSasExist = 0.
nodeId = 3, dieId = 0, isSasExist = 0.
nodeId = 3, dieId = 2, isSasExist = 0.
Mce Table head exist!
RasIntRegister init 452 
RasIntRegister init 453 
RasIntRegister init 64 
RasIntRegister init 65 
RasIntRegister init 465 
RasIntRegister init 466 
RasIntRegister init 86 
RasIntRegister init 87 
RasIntRegister init 478 
RasIntRegister init 479 
RasIntRegister init 108 
RasIntRegister init 109 
RasIntRegister init 491 
RasIntRegister init 492 
RasIntRegister init 130 
RasIntRegister init 131 
RasIntRegister init 504 
RasIntRegister init 505 
RasIntRegister init 152 
RasIntRegister init 153 
RasIntRegister init 517 
RasIntRegister init 518 
RasIntRegister init 174 
RasIntRegister init 175 
RasIntRegister init 530 
RasIntRegister init 531 
RasIntRegister init 196 
RasIntRegister init 197 
RasIntRegister init 543 
RasIntRegister init 544 
RasIntRegister init 218 
RasIntRegister init 219 
RasIntRegister init 76 
RasIntRegister init 98 
RasIntRegister init 120 
RasIntRegister init 142 
RasIntRegister init 164 
RasIntRegister init 186 
RasIntRegister init 208 
RasIntRegister init 230 
[0.00.20.942]starting ras end
[0.00.37.593][ERR]cmd not support! cmd = 0xd
[0.00.47.835]TF Heartbeat Start
[0.00.52.492]PCIE INIT DONE.
g_mctpQueueCount(48) > tabCnt(42)
Interrupt 454 register OK
Interrupt 467 register OK
Interrupt 480 register OK
Interrupt 493 register OK
Interrupt 506 register OK
Interrupt 519 register OK
Interrupt 532 register OK
Interrupt 545 register OK
data = 0x0
pmt Init done

Add ep: bdf=5500 eid=9 epCnt=1 eid_alloc=a
Add ep: bdf=300 eid=a epCnt=1 eid_alloc=b
mctp task ok.
[0.01.26.586]Receive ras int[491]
First coalesce handler start
Type2 status = 0x0
Type1 status = 0x4
Found error node[2]
False alarm reporting!
Type0 status = 0x0
ras int[491] end

[0.01.57.178]BIOS POST END.
Create SetReportPcieMmioToBmc ok.
Start SetReportPcieMmioToBmc ok.
slotNum = 0x14
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[0] port:20  pcieSlotCtrl.data (after)0x4801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[1] port:24  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[2] port:26  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[3] port:32  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[4] port:0  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[5] port:24  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[6] port:26  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[7] port:20  pcieSlotCtrl.data (after)0x4801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[8] port:22  pcieSlotCtrl.data (after)0x4801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[9] port:24  pcieSlotCtrl.data (after)0x4801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[10] port:26  pcieSlotCtrl.data (after)0x4801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[11] port:32  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[12] port:34  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[13] port:36  pcieSlotCtrl.data (after)0x4801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[14] port:38  pcieSlotCtrl.data (after)0x4801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[15] port:0  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[16] port:12  pcieSlotCtrl.data (after)0x4801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[17] port:14  pcieSlotCtrl.data (after)0x4801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[18] port:16  pcieSlotCtrl.data (after)0x4801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[19] port:18  pcieSlotCtrl.data (after)0x4801c0.

Enter current value process


HSM_LOG:
[00:00:00.000][info] succeed to do thirdparty dfx_pabuk init
[00:00:00.000][info] succeed to do thirdparty crypto_driver init


v TB[ 908]mv
0>[2650]MHZ -> Vol TA[ 922]mv TB[ 920]mv
0>[2700]MHZ -> Vol TA[ 935]mv TB[ 933]mv
0>[2750]MHZ -> Vol TA[ 953]mv TB[ 950]mv
0>[2800]MHZ -> Vol TA[ 971]mv TB[ 968]mv
0>[2850]MHZ -> Vol TA[ 989]mv TB[ 986]mv
0>[2900]MHZ -> Vol TA[1007]mv TB[1004]mv
0>[2950]MHZ -> Vol TA[1024]mv TB[1021]mv
0>[3000]MHZ -> Vol TA[1041]mv TB[1038]mv
0>[3050]MHZ -> Vol TA[1054]mv TB[1052]mv
0>[3100]MHZ -> Vol TA[1068]mv TB[1066]mv
0>Uncore VF curve:
0>Uncore [   0]MHZ -> Vol [ 810]mv
0>Uncore [ 100]MHZ -> Vol [ 810]mv
0>Uncore [ 200]MHZ -> Vol [ 810]mv
0>Uncore [ 300]MHZ -> Vol [ 810]mv
0>Uncore [ 400]MHZ -> Vol [ 810]mv
0>Uncore [ 500]MHZ -> Vol [ 810]mv
0>Uncore [ 600]MHZ -> Vol [ 810]mv
0>Uncore [ 700]MHZ -> Vol [ 810]mv
0>Uncore [ 800]MHZ -> Vol [ 810]mv
0>Uncore [ 900]MHZ -> Vol [ 810]mv
0>Uncore [1000]MHZ -> Vol [ 810]mv
0>Uncore [1100]MHZ -> Vol [ 810]mv
0>Uncore [1200]MHZ -> Vol [ 810]mv
0>Uncore [1300]MHZ -> Vol [ 810]mv
0>Uncore [1400]MHZ -> Vol [ 810]mv
0>Uncore [1500]MHZ -> Vol [ 810]mv
0>Uncore [1600]MHZ -> Vol [ 810]mv
0>Uncore [1700]MHZ -> Vol [ 810]mv
0>Uncore [1800]MHZ -> Vol [ 810]mv
0>Uncore [1900]MHZ -> Vol [ 810]mv
0>Uncore [2000]MHZ -> Vol [ 810]mv
0>Uncore [2100]MHZ -> Vol [ 810]mv
0>Uncore [2200]MHZ -> Vol [ 812]mv
0>Uncore [2300]MHZ -> Vol [ 829]mv
0>Uncore [2400]MHZ -> Vol [ 846]mv
0>Uncore [2500]MHZ -> Vol [ 863]mv
0>Uncore [2600]MHZ -> Vol [ 883]mv
0>Uncore [2700]MHZ -> Vol [ 903]mv
0>Uncore [2800]MHZ -> Vol [ 923]mv
0>Uncore [2900]MHZ -> Vol [ 944]mv
0>Uncore [3000]MHZ -> Vol [1100]mv
0>[TracePoint] type[  0] cmd[  1] data[  6]
0>[TracePoint] type[  0] cmd[  1] data[  7]
0>
********Hello Huawei LiteOS********

KpxxxxIPU Firmware Version : V32.70.0
LiteOS Kernel Version : 5.7.0
0>Run on ChipVersion[0] Node[0] Die[0]
0>build time : Feb 05 2026 20:30:00

0>**********************************
0>
main core booting up...
0>start set affinity
0>
mpidr = 0x81000000
0>sram ecc state: 0x0, sram ecc cnt: 0x0
0>[TracePoint] type[  0] cmd[  2] data[  1]
0>[TracePoint] type[  0] cmd[  2] data[  2]
0>LRDXSD_LOCK_OFFSET = 0x0
0>LRDXSD_ERRIMSK_OFFSET = 0x0
0>LRDXSD_DBG_OTIMSK_OFFSET = 0x0
0>LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
0>LRDXSD_DBG_EN_OFFSET = 0x1
0>======tsensor params======
0>  is_trimmed       : 1
0>  underclocking_en : 1
0>===========end============
0>soc tsensor init done
0>========vrd info from cpld========
0>vrd_id | u64                | pmbus_en | avsbus_en | loop | pmbus_id | pmbus_addr | avs_sw | pmbus_sw | addr_9545 | domain_type | die_mask | reserved
0>  00   | 0x0001000100002017 | 0x1      | 0x1       | 0x1  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0100   | 0x0
0>  01   | 0x000001060000201b | 0x1      | 0x1       | 0x2  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x6         | 0x0001   | 0x0
0>  02   | 0x0003000300002715 | 0x1      | 0x0       | 0x1  | 0x1      | 0x27       | 0x0    | 0x0      | 0x0       | 0x3         | 0x0300   | 0x0
0>  03   | 0x0003000400002719 | 0x1      | 0x0       | 0x2  | 0x1      | 0x27       | 0x0    | 0x0      | 0x0       | 0x4         | 0x0300   | 0x0
0>  04   | 0x0002000100002027 | 0x1      | 0x1       | 0x1  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0200   | 0x0
0>  05   | 0x000300020000202b | 0x1      | 0x1       | 0x2  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x2         | 0x0300   | 0x0
0>  06   | 0x0000020a00002725 | 0x1      | 0x0       | 0x1  | 0x2      | 0x27       | 0x0    | 0x0      | 0x0       | 0xa         | 0x0002   | 0x0
0>  07   | 0x0000020500002729 | 0x1      | 0x0       | 0x2  | 0x2      | 0x27       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0002   | 0x0
0>  08   | 0x0000020600002a25 | 0x1      | 0x0       | 0x1  | 0x2      | 0x2a       | 0x0    | 0x0      | 0x0       | 0x6         | 0x0002   | 0x0
0>  09   | 0x0000010a00002a29 | 0x1      | 0x0       | 0x2  | 0x2      | 0x2a       | 0x0    | 0x0      | 0x0       | 0xa         | 0x0001   | 0x0
0>================end===============
0>=============vrd info=============
0>power domain num: 10
0>power domain[00] id:0 | CORE_DVFS_TA       | PMBus NA | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
0>power domain[01] id:10 | IO_DVDD09_NA       | PMBus NA | cap:0x3 | rail:1 | addr:0x20 | def_volt: 900 mV | min_volt: 700 mV | max_volt: 900 mV
0>power domain[02] id:1 | DDR_VDD            | PMBus NA | cap:0x1 | rail:0 | addr:0x27 | def_volt: 800 mV | min_volt: 760 mV | max_volt: 840 mV
0>power domain[03] id:6 | DDR_VDDQ           | PMBus NA | cap:0x1 | rail:1 | addr:0x27 | def_volt:1100 mV | min_volt:1000 mV | max_volt:1200 mV
0>power domain[04] id:2 | CORE_DVFS_TB       | PMBus NB | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
0>power domain[05] id:3 | UNCORE_DVFS        | PMBus NB | cap:0x3 | rail:1 | addr:0x20 | def_volt: 944 mV | min_volt: 750 mV | max_volt:1100 mV
0>power domain[06] id:15 | NB_AVDD_SDS        | PMBus NB | cap:0x1 | rail:0 | addr:0x27 | def_volt:1200 mV | min_volt:1164 mV | max_volt:1236 mV
0>power domain[07] id:5 | IO_DVDD_NB         | PMBus NB | cap:0x1 | rail:1 | addr:0x27 | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
0>power domain[08] id:11 | IO_DVDD09_NB       | PMBus NB | cap:0x1 | rail:0 | addr:0x2a | def_volt: 900 mV | min_volt: 700 mV | max_volt: 900 mV
0>power domain[09] id:13 | NA_AVDD_SDS        | PMBus NB | cap:0x1 | rail:1 | addr:0x2a | def_volt:1200 mV | min_volt:1164 mV | max_volt:1236 mV
0>================end===============
0>pmbus[0] init done
0>pmbus[1] init done
0>power domain[0] CORE_DVFS_TA       | NA PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
0>power domain[10] IO_DVDD09_NA       | NA PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 900 mV | pmu:MP2882
0>power domain[1] DDR_VDD            | NA PMBus        | rail:0 | addr:0x27 | def_volt: 800 mV | pmu:MP2882
0>power domain[6] DDR_VDDQ           | NA PMBus        | rail:1 | addr:0x27 | def_volt:1100 mV | pmu:MP2882
0>power domain[2] CORE_DVFS_TB       | NB PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
0>power domain[3] UNCORE_DVFS        | NB PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 944 mV | pmu:MP2882
0>power domain[15] NB_AVDD_SDS        | NB PMBus        | rail:0 | addr:0x27 | def_volt:1200 mV | pmu:MP2882
0>power domain[5] IO_DVDD_NB         | NB PMBus        | rail:1 | addr:0x27 | def_volt: 800 mV | pmu:MP2882
0>power domain[11] IO_DVDD09_NB       | NB PMBus        | rail:0 | addr:0x2a | def_volt: 900 mV | pmu:MP2882
0>power domain[13] NA_AVDD_SDS        | NB PMBus        | rail:1 | addr:0x2a | def_volt:1200 mV | pmu:MP2882
0>power domain[0] CORE_DVFS_TA       is transferred to AVSBus mode
0>power domain[10] IO_DVDD09_NA       is transferred to AVSBus mode
0>power domain[2] CORE_DVFS_TB       is transferred to AVSBus mode
0>power domain[3] UNCORE_DVFS        is transferred to AVSBus mode
0>avsbus resync success
0>avsbus[0] init done
0>avsbus resync success
0>avsbus[1] init done
0>============volt boot============
0>power domain[0] volt =  882 mV
0>power domain[10] volt =  904 mV
0>power domain[1] volt =  806 mV
0>power domain[6] volt = 1105 mV
0>power domain[2] volt =  888 mV
0>power domain[3] volt =  949 mV
0>power domain[15] volt = 1206 mV
0>power domain[5] volt =  806 mV
0>power domain[11] volt =  906 mV
0>power domain[13] volt = 1205 mV
0>===============end===============
0>--w&h rd rail:0, 880, CORE_DVFS_TA
0>--w&h rd rail:1, 900, CORE_DVFS_TA
0>power domain[0] set volt --> 1097 mV success
0>--w&h rd rail:0, 886, CORE_DVFS_TB
0>--w&h rd rail:1, 949, CORE_DVFS_TB
0>power domain[2] set volt --> 1103 mV success
0>power domain[3] set volt -->  949 mV success
0>============volt post============
0>power domain[0] volt = 1097 mV
0>power domain[10] volt =  904 mV
0>power domain[1] volt =  806 mV
0>power domain[6] volt = 1105 mV
0>power domain[2] volt = 1105 mV
0>power domain[3] volt =  951 mV
0>power domain[15] volt = 1205 mV
0>power domain[5] volt =  806 mV
0>power domain[11] volt =  908 mV
0>power domain[13] volt = 1206 mV
0>===============end===============
0>die[0] its[0] init done
0>die[0] its[1] init done
0>die[0] its[2] init done
0>die[0] its[3] init done
0>die[0] its[4] init done
0>die[0] its[5] init done
0>die[0] its[6] init done
0>die[0] its[7] init done
0>die[0] its[8] init done
0>die[0] its[9] init done
0>die[1] its[0] init done
0>die[1] its[1] init done
0>die[1] its[2] init done
0>die[1] its[3] init done
0>die[1] its[4] init done
0>die[1] its[5] init done
0>die[1] its[6] init done
0>die[1] its[7] init done
0>die[1] its[8] init done
0>die[1] its[9] init done
0>Totem[0] Core Boot Vol [1097]mv
0>Totem[0] Core Current Vol [1100]mv
0>Totem[1] Core Boot Vol [1103]mv
0>Totem[1] Core Current Vol [1100]mv
0>NA 1620V1a0
0>NB 1620V1a0
0>GetCoreBaseFreq [2500000KHZ]
0>GetCoreTurboFreq [2500000KHZ]
0>GetCustomClusterNum [10]
0>Ipu ACG Training Done!
0>AP Last Time:[0.00.01.922]
0>wait UEFI pll init...
0>done
0>acg trim start
0>core trim freq:2000, avs:0 volt:810mv
0>core trim freq:2000, avs:0 volt:810mv
0>core trim freq:2050, avs:1 volt:810mv
0>core trim freq:2050, avs:1 volt:810mv
0>core trim freq:2100, avs:2 volt:810mvSYNC, QDR, SIO_PLL, is_cdr=0
0>TA_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
0>TA_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
0>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
0>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
0>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
0>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
0>==========end==========
0>sioe init done
0>ufs task enabled
0>--> UFS profile[0]
0>UEFI parameters ready
0>UncoreMaxFreq Set to [2900 MHZ]
0>get TDP from efuse success, value = 307500mw
0>target power set to [307500]mw, brd:[307500]
0>demt task parameters from uefi ready
0>age task parameters from uefi ready
0>age task enabled
0>uefi ddr init finish!
0>ipu interface task wait uefi end done from uefi...
0>ddr init done, start thermal dimm task
0>======dimm status======
0>  chl[0] dimm0 0, dimm1 0
0>  chl[1] dimm0 0, dimm1 0
0>  chl[2] dimm0 2, dimm1 0
0>  chl[3] dimm0 0, dimm1 0
0>  chl[4] dimm0 0, dimm1 0
0>  chl[5] dimm0 0, dimm1 0
0>  chl[6] dimm0 0, dimm1 0
0>  chl[7] dimm0 0, dimm1 0
0>==========end==========
0>chl[2] registered, dimm mask = 0x1
0>=====dimm temp params=====
0>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
0>  is_thermal_thro_en  : 1
0>  is_aref_rate_auto   : 1
0>===========end============
0>chl[2] max_temp 47'C, aref_rate 0x5 --> 0x4
0>uefi end finish!
0>ipu interface task exit!
0>amu task parameters from uefi ready
0>amu task activated
0>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
810]mv
1>Uncore [ 100]MHZ -> Vol [ 810]mv
1>Uncore [ 200]MHZ -> Vol [ 810]mv
1>Uncore [ 300]MHZ -> Vol [ 810]mv
1>Uncore [ 400]MHZ -> Vol [ 810]mv
1>Uncore [ 500]MHZ -> Vol [ 810]mv
1>Uncore [ 600]MHZ -> Vol [ 810]mv
1>Uncore [ 700]MHZ -> Vol [ 810]mv
1>Uncore [ 800]MHZ -> Vol [ 810]mv
1>Uncore [ 900]MHZ -> Vol [ 810]mv
1>Uncore [1000]MHZ -> Vol [ 810]mv
1>Uncore [1100]MHZ -> Vol [ 810]mv
1>Uncore [1200]MHZ -> Vol [ 810]mv
1>Uncore [1300]MHZ -> Vol [ 810]mv
1>Uncore [1400]MHZ -> Vol [ 810]mv
1>Uncore [1500]MHZ -> Vol [ 810]mv
1>Uncore [1600]MHZ -> Vol [ 810]mv
1>Uncore [1700]MHZ -> Vol [ 810]mv
1>Uncore [1800]MHZ -> Vol [ 810]mv
1>Uncore [1900]MHZ -> Vol [ 810]mv
1>Uncore [2000]MHZ -> Vol [ 810]mv
1>Uncore [2100]MHZ -> Vol [ 810]mv
1>Uncore [2200]MHZ -> Vol [ 814]mv
1>Uncore [2300]MHZ -> Vol [ 831]mv
1>Uncore [2400]MHZ -> Vol [ 848]mv
1>Uncore [2500]MHZ -> Vol [ 866]mv
1>Uncore [2600]MHZ -> Vol [ 886]mv
1>Uncore [2700]MHZ -> Vol [ 907]mv
1>Uncore [2800]MHZ -> Vol [ 927]mv
1>Uncore [2900]MHZ -> Vol [ 948]mv
1>Uncore [3000]MHZ -> Vol [1100]mv
1>[TracePoint] type[  0] cmd[  1] data[  6]
1>[TracePoint] type[  0] cmd[  1] data[  7]
1>
********Hello Huawei LiteOS********

KpxxxxIPU Firmware Version : V32.70.0
LiteOS Kernel Version : 5.7.0
1>Run on ChipVersion[0] Node[1] Die[0]
1>build time : Feb 05 2026 20:30:00

1>**********************************
1>
main core booting up...
1>start set affinity
1>
mpidr = 0x81040000
1>sram ecc state: 0x0, sram ecc cnt: 0x0
1>[TracePoint] type[  0] cmd[  2] data[  1]
1>[TracePoint] type[  0] cmd[  2] data[  2]
1>LRDXSD_LOCK_OFFSET = 0x0
1>LRDXSD_ERRIMSK_OFFSET = 0x0
1>LRDXSD_DBG_OTIMSK_OFFSET = 0x0
1>LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
1>LRDXSD_DBG_EN_OFFSET = 0x1
1>======tsensor params======
1>  is_trimmed       : 1
1>  underclocking_en : 1
1>===========end============
1>soc tsensor init done
1>========vrd info from cpld========
1>vrd_id | u64                | pmbus_en | avsbus_en | loop | pmbus_id | pmbus_addr | avs_sw | pmbus_sw | addr_9545 | domain_type | die_mask | reserved
1>  00   | 0x0001000100002017 | 0x1      | 0x1       | 0x1  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0100   | 0x0
1>  01   | 0x000300030000201b | 0x1      | 0x1       | 0x2  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x3         | 0x0300   | 0x0
1>  02   | 0x0000010a00002715 | 0x1      | 0x0       | 0x1  | 0x1      | 0x27       | 0x0    | 0x0      | 0x0       | 0xa         | 0x0001   | 0x0
1>  03   | 0x0000010500002719 | 0x1      | 0x0       | 0x2  | 0x1      | 0x27       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0001   | 0x0
1>  04   | 0x0000020600002a15 | 0x1      | 0x0       | 0x1  | 0x1      | 0x2a       | 0x0    | 0x0      | 0x0       | 0x6         | 0x0002   | 0x0
1>  05   | 0x0000010600002a19 | 0x1      | 0x0       | 0x2  | 0x1      | 0x2a       | 0x0    | 0x0      | 0x0       | 0x6         | 0x0001   | 0x0
1>  06   | 0x0000020a00002f15 | 0x1      | 0x0       | 0x1  | 0x1      | 0x2f       | 0x0    | 0x0      | 0x0       | 0xa         | 0x0002   | 0x0
1>  07   | 0x0002000100002027 | 0x1      | 0x1       | 0x1  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0200   | 0x0
1>  08   | 0x000300020000202b | 0x1      | 0x1       | 0x2  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x2         | 0x0300   | 0x0
1>  09   | 0x0000030500002725 | 0x1      | 0x0       | 0x1  | 0x2      | 0x27       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0003   | 0x0
1>  10   | 0x0003000400002729 | 0x1      | 0x0       | 0x2  | 0x2      | 0x27       | 0x0    | 0x0      | 0x0       | 0x4         | 0x0300   | 0x0
1>================end===============
1>=============vrd info=============
1>power domain num: 11
1>power domain[00] id:0 | CORE_DVFS_TA       | PMBus NA | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
1>power domain[01] id:1 | DDR_VDD            | PMBus NA | cap:0x3 | rail:1 | addr:0x20 | def_volt: 800 mV | min_volt: 760 mV | max_volt: 840 mV
1>power domain[02] id:14 | NA_AVDD_SDS        | PMBus NA | cap:0x1 | rail:0 | addr:0x27 | def_volt:1200 mV | min_volt:1164 mV | max_volt:1236 mV
1>power domain[03] id:4 | IO_DVDD_NA         | PMBus NA | cap:0x1 | rail:1 | addr:0x27 | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
1>power domain[04] id:11 | IO_DVDD09_NB       | PMBus NA | cap:0x1 | rail:0 | addr:0x2a | def_volt: 900 mV | min_volt: 700 mV | max_volt: 900 mV
1>power domain[05] id:10 | IO_DVDD09_NA       | PMBus NA | cap:0x1 | rail:1 | addr:0x2a | def_volt: 900 mV | min_volt: 700 mV | max_volt: 900 mV
1>power domain[06] id:16 | NB_AVDD_SDS        | PMBus NA | cap:0x1 | rail:0 | addr:0x2f | def_volt:1200 mV | min_volt:1164 mV | max_volt:1236 mV
1>power domain[07] id:2 | CORE_DVFS_TB       | PMBus NB | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
1>power domain[08] id:3 | UNCORE_DVFS        | PMBus NB | cap:0x3 | rail:1 | addr:0x20 | def_volt: 948 mV | min_volt: 750 mV | max_volt:1100 mV
1>power domain[09] id:12 | IO_DVDD_NANB       | PMBus NB | cap:0x1 | rail:0 | addr:0x27 | def_volt: 800 mV | min_volt: 750 mV | max_volt: 900 mV
1>power domain[10] id:6 | DDR_VDDQ           | PMBus NB | cap:0x1 | rail:1 | addr:0x27 | def_volt:1100 mV | min_volt:1000 mV | max_volt:1200 mV
1>================end===============
1>pmbus[0] init done
1>pmbus[1] init done
1>power domain[0] CORE_DVFS_TA       | NA PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
1>power domain[1] DDR_VDD            | NA PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 800 mV | pmu:MP2882
1>power domain[14] NA_AVDD_SDS        | NA PMBus        | rail:0 | addr:0x27 | def_volt:1200 mV | pmu:MP2882
1>power domain[4] IO_DVDD_NA         | NA PMBus        | rail:1 | addr:0x27 | def_volt: 800 mV | pmu:MP2882
1>power domain[11] IO_DVDD09_NB       | NA PMBus        | rail:0 | addr:0x2a | def_volt: 900 mV | pmu:MP2882
1>power domain[10] IO_DVDD09_NA       | NA PMBus        | rail:1 | addr:0x2a | def_volt: 900 mV | pmu:MP2882
1>power domain[16] NB_AVDD_SDS        | NA PMBus        | rail:0 | addr:0x2f | def_volt:1200 mV | pmu:MP2882
1>power domain[2] CORE_DVFS_TB       | NB PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
1>power domain[3] UNCORE_DVFS        | NB PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 948 mV | pmu:MP2882
1>power domain[12] IO_DVDD_NANB       | NB PMBus        | rail:0 | addr:0x27 | def_volt: 800 mV | pmu:MP2882
1>power domain[6] DDR_VDDQ           | NB PMBus        | rail:1 | addr:0x27 | def_volt:1100 mV | pmu:MP2882
1>power domain[0] CORE_DVFS_TA       is transferred to AVSBus mode
1>power domain[1] DDR_VDD            is transferred to AVSBus mode
1>power domain[2] CORE_DVFS_TB       is transferred to AVSBus mode
1>power domain[3] UNCORE_DVFS        is transferred to AVSBus mode
1>avsbus resync success
1>avsbus[0] init done
1>avsbus resync success
1>avsbus[1] init done
1>============volt boot============
1>power domain[0] volt =  892 mV
1>power domain[1] volt =  804 mV
1>power domain[14] volt = 1205 mV
1>power domain[4] volt =  806 mV
1>power domain[11] volt =  906 mV
1>power domain[10] volt =  904 mV
1>power domain[16] volt = 1203 mV
1>power domain[2] volt =  886 mV
1>power domain[3] volt =  816 mV
1>power domain[12] volt =  808 mV
1>power domain[6] volt = 1105 mV
1>===============end===============
1>--w&h rd rail:0, 892, CORE_DVFS_TA
1>--w&h rd rail:1, 800, CORE_DVFS_TA
1>power domain[0] set volt --> 1105 mV success
1>--w&h rd rail:0, 888, CORE_DVFS_TB
1>--w&h rd rail:1, 816, CORE_DVFS_TB
1>power domain[2] set volt --> 1097 mV success
1>power domain[3] set volt -->  953 mV success
1>============volt post============
1>power domain[0] volt = 1103 mV
1>power domain[1] volt =  804 mV
1>power domain[14] volt = 1205 mV
1>power domain[4] volt =  806 mV
1>power domain[11] volt =  904 mV
1>power domain[10] volt =  904 mV
1>power domain[16] volt = 1203 mV
1>power domain[2] volt = 1097 mV
1>power domain[3] volt =  953 mV
1>power domain[12] volt =  808 mV
1>power domain[6] volt = 1105 mV
1>===============end===============
1>the power sensor : manu id = 2peak, die id = TPA626
1>power sensor[0] init success
1>die[0] its[0] init done
1>die[0] its[1] init done
1>die[0] its[2] init done
1>die[0] its[3] init done
1>die[0] its[4] init done
1>die[0] its[5] init done
1>die[0] its[6] init done
1>die[0] its[7] init done
1>die[0] its[8] init done
1>die[0] its[9] init done
1>die[1] its[0] init done
1>die[1] its[1] init done
1>die[1] its[2] init done
1>die[1] its[3] init done
1>die[1] its[4] init done
1>die[1] its[5] init done
1>die[1] its[6] init done
1>die[1] its[7] init done
1>die[1] its[8] init done
1>die[1] its[9] init done
1>Totem[0] Core Boot Vol [1103]mv
1>Totem[0] Core Current Vol [1100]mv
1>Totem[1] Core Boot Vol [1099]mv
1>Totem[1] Core Current Vol [1100]mv
1>NA 1620V1a0
1>NB 1620V1a0
1>GetCoreBaseFreq [2500000KHZ]
1>GetCoreTurboFreq [2500000KHZ]
1>GetCustomClusterNum [10]
1>Ipu ACG Training Done!
1>AP Last Time:[0.00.01.522]
1>wait UEFI pll init...
1>done
1>acg trim start
1>core trim freq:2000, avs:0 volt:810mv
1>core trim freq:2000, avs:0 volt:810mv
1>core trim freq:2050, avs:1 volt:810mv
1>core trim freq:2050, avs:1 volt:810mv
1>core trim freq:2100, avs:2 volt:810mv
1>core trim freq:2100, avs:2 volt:810mv
1>core trim freq:2150, avs:3 volt:810mv
1>core trim freq:2150, avs:3 volt:810mv
1>core trim freq:2200, avs:4 volt:814mv
1>core trim freq:2200, avs:4 volt:812mv
1>core trim freq:2250, avs:5 volt:826mv
1>core trim freq:2250, avs:5 volt:825mv
1>core trim freq:2300, avs:6 volt:839mv
1>core trim freq:2300, avs:6 volt:838mv
1>core trim freq:2350, avs:7 volt:852mv
1>core trim freq:2350, avs:7 volt:851mv
1>core trim freq:2400, avs:8 volt:865mv
1>core trim freq:2400, avs:8 volt:863mv
1>core trim freq:2450, avs:9 volt:878mv
1>core trim freq:2450, avs:9 volt:876mv
1>core trim freq:2500, avs:10 volt:890mv
1>core trim freq:2500, avs:10 volt:889mv
1>core trim freq:2550, avs:11 volt:903mv
1>core trim freq:2550, avs:11 volt:901mv
1>core trim freq:2600, avs:12 volt:916mv
1>core trim freq:2600, avs:12 volt:914mv
1>core trim freq:2650, avs:13 volt:929mv
1>core trim freq:2650, avs:13 volt:927mv
1>core trim freq:2700, avs:14 volt:942mv
1>core trim freq:2700, avs:14 volt:940mv
1>core trim freq:2750, avs:15 volt:960mv
1>core trim freq:2750, avs:15 volt:958mv
1>core trim freq:2800, avs:16 volt:978mv
1>core trim freq:2800, avs:16 volt:976mv
1>core trim freq:2850, avs:17 volt:996mv
1>core trim freq:2850, avs:17 volt:994mv
1>core trim freq:2900, avs:18 volt:1015mv
1>core trim freq:2900, avs:18 volt:1012mv
1>core trim freq:2950, avs:19 volt:1032mv
1>core trim freq:2950, avs:19 volt:1029mv
1>core trim freq:3000, avs:20 volt:1050mv
1>core trim freq:3000, avs:20 volt:1047mv
1>core trim freq:3050, avs:21 volt:1063mv
1>core trim freq:3050, avs:21 volt:1060mv
1>core trim freq:3100, avs:22 volt:1076mv
1>core trim freq:3100, avs:22 volt:1074mv
1>acg trim end
1>LDO disabled
1>[TracePoint] type[  0] cmd[  2] data[  3]
1>Interrupt 423 register OK
1>Interrupt 430 register OK
1>[TracePoint] type[  0] cmd[  2] data[  4]
1>
1>cpu 0 entering scheduler
1>[TracePoint] type[  0] cmd[  3] data[  1]
1>add your ipu app init here!
1>IpuInterfaceTaskStart Entry ...
1>ipu interface task wait parameters from uefi...
1>thermal soc task enabled
1>AP Last Time:[0.00.07.247]
1>ThermalDimmStart Entry ...
1>wait ddr init done...
1>power task start...
1>[TracePoint] type[  0] cmd[  3] data[  2]
1>ufs task wait parameters from uefi...
1>AmuTaskStart Entry ... 
1>amu task wait parameters from uefi...
1>ThermalSiwStart Entry ...
1>ThermalSiwTask idle...
1>DemtTaskStart Entry ...
1>[TracePoint] type[  0] cmd[  3] data[  3]
1>HiBoostTaskStart Entry ...
1>HiBoost task enabled
1>Waiting for UEFI parameters...
1>[TracePoint] type[  0] cmd[  3] data[  4]
1>demt task wait parameters from uefi...
1>AgeTaskStart Entry ...
1>age task wait parameters from uefi...
1>[TracePoint] type[  0] cmd[  3] data[  5]
1>uefi parameters ready!
1>UFSProfile[0]
1>PowerPolicy[2] BenchMarkSelection[0]
1>ipu interface task wait ddr init done from uefi...
1>ufs task parameters from uefi ready
1>uncore domain[0] freq:2900
1>uncore domain[1] freq:2900
1>thermal soc task restore underclocking_en=1
1>ppu alert temp div init done
1>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
1>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
1>======sioe status======
1>TA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TA_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TA_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TA_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
1>TA_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
1>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
1>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
1>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
1>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
1>==========end==========
1>sioe init done
1>ufs task enabled
1>--> UFS profile[0]
1>UEFI parameters ready
1>UncoreMaxFreq Set to [2900 MHZ]
1>get TDP from efuse success, value = 307500mw
1>target power set to [307500]mw, brd:[307500]
1>age task parameters from uefi ready
1>demt task parameters from uefi ready
1>age task enabled
1>uefi ddr init finish!
1>ipu interface task wait uefi end done from uefi...
1>ddr init done, start thermal dimm task
1>======dimm status======
1>  chl[0] dimm0 0, dimm1 0
1>  chl[1] dimm0 0, dimm1 0
1>  chl[2] dimm0 0, dimm1 0
1>  chl[3] dimm0 0, dimm1 0
1>  chl[4] dimm0 0, dimm1 0
1>  chl[5] dimm0 0, dimm1 0
1>  chl[6] dimm0 0, dimm1 0
1>  chl[7] dimm0 0, dimm1 0
1>==========end==========
1>=====dimm temp params=====
1>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
1>  is_thermal_thro_en  : 1
1>  is_aref_rate_auto   : 1
1>===========end============
1>uefi end finish!
1>ipu interface task exit!
1>amu task parameters from uefi ready
1>amu task activated
1>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
v TB[ 915]mv
2>[2650]MHZ -> Vol TA[ 930]mv TB[ 928]mv
2>[2700]MHZ -> Vol TA[ 943]mv TB[ 941]mv
2>[2750]MHZ -> Vol TA[ 961]mv TB[ 959]mv
2>[2800]MHZ -> Vol TA[ 979]mv TB[ 977]mv
2>[2850]MHZ -> Vol TA[ 997]mv TB[ 995]mv
2>[2900]MHZ -> Vol TA[1016]mv TB[1014]mv
2>[2950]MHZ -> Vol TA[1033]mv TB[1031]mv
2>[3000]MHZ -> Vol TA[1051]mv TB[1049]mv
2>[3050]MHZ -> Vol TA[1064]mv TB[1062]mv
2>[3100]MHZ -> Vol TA[1077]mv TB[1075]mv
2>Uncore VF curve:
2>Uncore [   0]MHZ -> Vol [ 810]mv
2>Uncore [ 100]MHZ -> Vol [ 810]mv
2>Uncore [ 200]MHZ -> Vol [ 810]mv
2>Uncore [ 300]MHZ -> Vol [ 810]mv
2>Uncore [ 400]MHZ -> Vol [ 810]mv
2>Uncore [ 500]MHZ -> Vol [ 810]mv
2>Uncore [ 600]MHZ -> Vol [ 810]mv
2>Uncore [ 700]MHZ -> Vol [ 810]mv
2>Uncore [ 800]MHZ -> Vol [ 810]mv
2>Uncore [ 900]MHZ -> Vol [ 810]mv
2>Uncore [1000]MHZ -> Vol [ 810]mv
2>Uncore [1100]MHZ -> Vol [ 810]mv
2>Uncore [1200]MHZ -> Vol [ 810]mv
2>Uncore [1300]MHZ -> Vol [ 810]mv
2>Uncore [1400]MHZ -> Vol [ 810]mv
2>Uncore [1500]MHZ -> Vol [ 810]mv
2>Uncore [1600]MHZ -> Vol [ 810]mv
2>Uncore [1700]MHZ -> Vol [ 810]mv
2>Uncore [1800]MHZ -> Vol [ 810]mv
2>Uncore [1900]MHZ -> Vol [ 810]mv
2>Uncore [2000]MHZ -> Vol [ 810]mv
2>Uncore [2100]MHZ -> Vol [ 810]mv
2>Uncore [2200]MHZ -> Vol [ 811]mv
2>Uncore [2300]MHZ -> Vol [ 828]mv
2>Uncore [2400]MHZ -> Vol [ 845]mv
2>Uncore [2500]MHZ -> Vol [ 862]mv
2>Uncore [2600]MHZ -> Vol [ 882]mv
2>Uncore [2700]MHZ -> Vol [ 902]mv
2>Uncore [2800]MHZ -> Vol [ 922]mv
2>Uncore [2900]MHZ -> Vol [ 943]mv
2>Uncore [3000]MHZ -> Vol [1100]mv
2>[TracePoint] type[  0] cmd[  1] data[  6]
2>[TracePoint] type[  0] cmd[  1] data[  7]
2>
********Hello Huawei LiteOS********

KpxxxxIPU Firmware Version : V32.70.0
LiteOS Kernel Version : 5.7.0
2>Run on ChipVersion[0] Node[2] Die[0]
2>build time : Feb 05 2026 20:30:00

2>**********************************
2>
main core booting up...
2>start set affinity
2>
mpidr = 0x81080000
2>sram ecc state: 0x0, sram ecc cnt: 0x0
2>[TracePoint] type[  0] cmd[  2] data[  1]
2>[TracePoint] type[  0] cmd[  2] data[  2]
2>LRDXSD_LOCK_OFFSET = 0x0
2>LRDXSD_ERRIMSK_OFFSET = 0x0
2>LRDXSD_DBG_OTIMSK_OFFSET = 0x0
2>LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
2>LRDXSD_DBG_EN_OFFSET = 0x1
2>======tsensor params======
2>  is_trimmed       : 1
2>  underclocking_en : 1
2>===========end============
2>soc tsensor init done
2>========vrd info from cpld========
2>vrd_id | u64                | pmbus_en | avsbus_en | loop | pmbus_id | pmbus_addr | avs_sw | pmbus_sw | addr_9545 | domain_type | die_mask | reserved
2>  00   | 0x0001000100002017 | 0x1      | 0x1       | 0x1  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0100   | 0x0
2>  01   | 0x000001060000201b | 0x1      | 0x1       | 0x2  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x6         | 0x0001   | 0x0
2>  02   | 0x0003000300002715 | 0x1      | 0x0       | 0x1  | 0x1      | 0x27       | 0x0    | 0x0      | 0x0       | 0x3         | 0x0300   | 0x0
2>  03   | 0x0003000400002719 | 0x1      | 0x0       | 0x2  | 0x1      | 0x27       | 0x0    | 0x0      | 0x0       | 0x4         | 0x0300   | 0x0
2>  04   | 0x0002000100002027 | 0x1      | 0x1       | 0x1  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0200   | 0x0
2>  05   | 0x000300020000202b | 0x1      | 0x1       | 0x2  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x2         | 0x0300   | 0x0
2>  06   | 0x0000020a00002725 | 0x1      | 0x0       | 0x1  | 0x2      | 0x27       | 0x0    | 0x0      | 0x0       | 0xa         | 0x0002   | 0x0
2>  07   | 0x0000020500002729 | 0x1      | 0x0       | 0x2  | 0x2      | 0x27       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0002   | 0x0
2>  08   | 0x0000020600002a25 | 0x1      | 0x0       | 0x1  | 0x2      | 0x2a       | 0x0    | 0x0      | 0x0       | 0x6         | 0x0002   | 0x0
2>  09   | 0x0000010a00002a29 | 0x1      | 0x0       | 0x2  | 0x2      | 0x2a       | 0x0    | 0x0      | 0x0       | 0xa         | 0x0001   | 0x0
2>================end===============
2>=============vrd info=============
2>power domain num: 10
2>power domain[00] id:0 | CORE_DVFS_TA       | PMBus NA | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
2>power domain[01] id:10 | IO_DVDD09_NA       | PMBus NA | cap:0x3 | rail:1 | addr:0x20 | def_volt: 900 mV | min_volt: 700 mV | max_volt: 900 mV
2>power domain[02] id:1 | DDR_VDD            | PMBus NA | cap:0x1 | rail:0 | addr:0x27 | def_volt: 800 mV | min_volt: 760 mV | max_volt: 840 mV
2>power domain[03] id:6 | DDR_VDDQ           | PMBus NA | cap:0x1 | rail:1 | addr:0x27 | def_volt:1100 mV | min_volt:1000 mV | max_volt:1200 mV
2>power domain[04] id:2 | CORE_DVFS_TB       | PMBus NB | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
2>power domain[05] id:3 | UNCORE_DVFS        | PMBus NB | cap:0x3 | rail:1 | addr:0x20 | def_volt: 943 mV | min_volt: 750 mV | max_volt:1100 mV
2>power domain[06] id:15 | NB_AVDD_SDS        | PMBus NB | cap:0x1 | rail:0 | addr:0x27 | def_volt:1200 mV | min_volt:1164 mV | max_volt:1236 mV
2>power domain[07] id:5 | IO_DVDD_NB         | PMBus NB | cap:0x1 | rail:1 | addr:0x27 | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
2>power domain[08] id:11 | IO_DVDD09_NB       | PMBus NB | cap:0x1 | rail:0 | addr:0x2a | def_volt: 900 mV | min_volt: 700 mV | max_volt: 900 mV
2>power domain[09] id:13 | NA_AVDD_SDS        | PMBus NB | cap:0x1 | rail:1 | addr:0x2a | def_volt:1200 mV | min_volt:1164 mV | max_volt:1236 mV
2>================end===============
2>pmbus[0] init done
2>pmbus[1] init done
2>power domain[0] CORE_DVFS_TA       | NA PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
2>power domain[10] IO_DVDD09_NA       | NA PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 900 mV | pmu:MP2882
2>power domain[1] DDR_VDD            | NA PMBus        | rail:0 | addr:0x27 | def_volt: 800 mV | pmu:MP2882
2>power domain[6] DDR_VDDQ           | NA PMBus        | rail:1 | addr:0x27 | def_volt:1100 mV | pmu:MP2882
2>power domain[2] CORE_DVFS_TB       | NB PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
2>power domain[3] UNCORE_DVFS        | NB PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 943 mV | pmu:MP2882
2>power domain[15] NB_AVDD_SDS        | NB PMBus        | rail:0 | addr:0x27 | def_volt:1200 mV | pmu:MP2882
2>power domain[5] IO_DVDD_NB         | NB PMBus        | rail:1 | addr:0x27 | def_volt: 800 mV | pmu:MP2882
2>power domain[11] IO_DVDD09_NB       | NB PMBus        | rail:0 | addr:0x2a | def_volt: 900 mV | pmu:MP2882
2>power domain[13] NA_AVDD_SDS        | NB PMBus        | rail:1 | addr:0x2a | def_volt:1200 mV | pmu:MP2882
2>power domain[0] CORE_DVFS_TA       is transferred to AVSBus mode
2>power domain[10] IO_DVDD09_NA       is transferred to AVSBus mode
2>power domain[2] CORE_DVFS_TB       is transferred to AVSBus mode
2>power domain[3] UNCORE_DVFS        is transferred to AVSBus mode
2>avsbus resync success
2>avsbus[0] init done
2>avsbus resync success
2>avsbus[1] init done
2>============volt boot============
2>power domain[0] volt =  896 mV
2>power domain[10] volt =  904 mV
2>power domain[1] volt =  806 mV
2>power domain[6] volt = 1105 mV
2>power domain[2] volt =  898 mV
2>power domain[3] volt =  814 mV
2>power domain[15] volt = 1206 mV
2>power domain[5] volt =  806 mV
2>power domain[11] volt =  906 mV
2>power domain[13] volt = 1205 mV
2>===============end===============
2>--w&h rd rail:0, 896, CORE_DVFS_TA
2>--w&h rd rail:1, 900, CORE_DVFS_TA
2>power domain[0] set volt --> 1105 mV success
2>--w&h rd rail:0, 896, CORE_DVFS_TB
2>--w&h rd rail:1, 814, CORE_DVFS_TB
2>power domain[2] set volt --> 1109 mV success
2>power domain[3] set volt -->  949 mV success
2>============volt post============
2>power domain[0] volt = 1103 mV
2>power domain[10] volt =  904 mV
2>power domain[1] volt =  806 mV
2>power domain[6] volt = 1105 mV
2>power domain[2] volt = 1109 mV
2>power domain[3] volt =  947 mV
2>power domain[15] volt = 1206 mV
2>power domain[5] volt =  806 mV
2>power domain[11] volt =  906 mV
2>power domain[13] volt = 1205 mV
2>===============end===============
2>die[0] its[0] init done
2>die[0] its[1] init done
2>die[0] its[2] init done
2>die[0] its[3] init done
2>die[0] its[4] init done
2>die[0] its[5] init done
2>die[0] its[6] init done
2>die[0] its[7] init done
2>die[0] its[8] init done
2>die[0] its[9] init done
2>die[1] its[0] init done
2>die[1] its[1] init done
2>die[1] its[2] init done
2>die[1] its[3] init done
2>die[1] its[4] init done
2>die[1] its[5] init done
2>die[1] its[6] init done
2>die[1] its[7] init done
2>die[1] its[8] init done
2>die[1] its[9] init done
2>Totem[0] Core Boot Vol [1103]mv
2>Totem[0] Core Current Vol [1100]mv
2>Totem[1] Core Boot Vol [1109]mv
2>Totem[1] Core Current Vol [1100]mv
2>NA 1620V1a0
2>NB 1620V1a0
2>GetCoreBaseFreq [2500000KHZ]
2>GetCoreTurboFreq [2500000KHZ]
2>GetCustomClusterNum [10]
2>Ipu ACG Training Done!
2>AP Last Time:[0.00.01.469]
2>wait UEFI pll init...
2>done
2>acg trim start
2>core trim freq:2000, avs:0 volt:810mv
2>core trim freq:2000, avs:0 volt:810mv
2>core trim freq:2050, avs:1 volt:810mv
2>core trim freq:2050, avs:1 volt:810mv
2>core trim freq:2100, avs:2 volt:810mv
2>core trim freq:2100, avs:2 volt:810mv
2>core trim freq:2150, avs:3 volt:810mv
2>core trim freq:2150, avs:3 volt:810mv
2>core trim freq:2200, avs:4 volt:814mv
2>core trim freq:2200, avs:4 volt:813mv
2>core trim freq:2250, avs:5 volt:827mv
2>core trim freq:2250, avs:5 volt:825mv
2>core trim freq:2300, avs:6 volt:840mv
2>core trim freq:2300, avs:6 volt:838mv
2>core trim freq:2350, avs:7 volt:853mv
2>core trim freq:2350, avs:7 volt:851mv
2>core trim freq:2400, avs:8 volt:865mv
2>core trim freq:2400, avs:8 volt:864mv
2>core trim freq:2450, avs:9 volt:878mv
2>core trim freq:2450, avs:9 volt:877mv
2>core trim freq:2500, avs:10 volt:891mv
2>core trim freq:2500, avs:10 volt:889mv
2>core trim freq:2550, avs:11 volt:904mv
2>core trim freq:2550, avs:11 volt:902mv
2>core trim freq:2600, avs:12 volt:917mv
2>core trim freq:2600, avs:12 volt:915mv
2>core trim freq:2650, avs:13 volt:930mv
2>core trim freq:2650, avs:13 volt:928mv
2>core trim freq:2700, avs:14 volt:943mv
2>core trim freq:2700, avs:14 volt:941mv
2>core trim freq:2750, avs:15 volt:961mv
2>core trim freq:2750, avs:15 volt:959mv
2>core trim freq:2800, avs:16 volt:979mv
2>core trim freq:2800, avs:16 volt:977mv
2>core trim freq:2850, avs:17 volt:997mv
2>core trim freq:2850, avs:17 volt:995mv
2>core trim freq:2900, avs:18 volt:1016mv
2>core trim freq:2900, avs:18 volt:1014mv
2>core trim freq:2950, avs:19 volt:1033mv
2>core trim freq:2950, avs:19 volt:1031mv
2>core trim freq:3000, avs:20 volt:1051mv
2>core trim freq:3000, avs:20 volt:1049mv
2>core trim freq:3050, avs:21 volt:1064mv
2>core trim freq:3050, avs:21 volt:1062mv
2>core trim freq:3100, avs:22 volt:1077mv
2>core trim freq:3100, avs:22 volt:1075mv
2>acg trim end
2>LDO disabled
2>[TracePoint] type[  0] cmd[  2] data[  3]
2>Interrupt 423 register OK
2>Interrupt 430 register OK
2>[TracePoint] type[  0] cmd[  2] data[  4]
2>
2>cpu 0 entering scheduler
2>[TracePoint] type[  0] cmd[  3] data[  1]
2>add your ipu app init here!
2>IpuInterfaceTaskStart Entry ...
2>ipu interface task wait parameters from uefi...
2>thermal soc task enabled
2>AP Last Time:[0.00.07.216]
2>ThermalDimmStart Entry ...
2>wait ddr init done...
2>power task start...
2>[TracePoint] type[  0] cmd[  3] data[  2]
2>ufs task wait parameters from uefi...
2>AmuTaskStart Entry ... 
2>amu task wait parameters from uefi...
2>ThermalSiwStart Entry ...
2>ThermalSiwTask idle...
2>DemtTaskStart Entry ...
2>[TracePoint] type[  0] cmd[  3] data[  3]
2>demt task wait parameters from uefi...
2>HiBoostTaskStart Entry ...
2>HiBoost task enabled
2>Waiting for UEFI parameters...
2>[TracePoint] type[  0] cmd[  3] data[  4]
2>AgeTaskStart Entry ...
2>age task wait parameters from uefi...
2>[TracePoint] type[  0] cmd[  3] data[  5]
2>uefi parameters ready!
2>UFSProfile[0]
2>PowerPolicy[2] BenchMarkSelection[0]
2>ipu interface task wait ddr init done from uefi...
2>ufs task parameters from uefi ready
2>uncore domain[0] freq:2900
2>uncore domain[1] freq:2900
2>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
2>thermal soc task restore underclocking_en=1
2>ppu alert temp div init done
2>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
2>======sioe status======
2>TA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
2>TA_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
2>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
2>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
2>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
2>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
2>==========end==========
2>sioe init done
2>ufs task enabled
2>--> UFS profile[0]
2>UEFI parameters ready
2>UncoreMaxFreq Set to [2900 MHZ]
2>get TDP from efuse success, value = 307500mw
2>target power set to [307500]mw, brd:[307500]
2>demt task parameters from uefi ready
2>age task parameters from uefi ready
2>age task enabled
2>uefi ddr init finish!
2>ipu interface task wait uefi end done from uefi...
2>ddr init done, start thermal dimm task
2>======dimm status======
2>  chl[0] dimm0 0, dimm1 0
2>  chl[1] dimm0 0, dimm1 0
2>  chl[2] dimm0 2, dimm1 0
2>  chl[3] dimm0 0, dimm1 0
2>  chl[4] dimm0 0, dimm1 0
2>  chl[5] dimm0 0, dimm1 0
2>  chl[6] dimm0 0, dimm1 0
2>  chl[7] dimm0 0, dimm1 0
2>==========end==========
2>chl[2] registered, dimm mask = 0x1
2>=====dimm temp params=====
2>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
2>  is_thermal_thro_en  : 1
2>  is_aref_rate_auto   : 1
2>===========end============
2>chl[2] max_temp 55'C, aref_rate 0x5 --> 0x4
2>uefi end finish!
2>ipu interface task exit!
2>amu task parameters from uefi ready
2>amu task activated
2>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
810]mv
3>Uncore [ 100]MHZ -> Vol [ 810]mv
3>Uncore [ 200]MHZ -> Vol [ 810]mv
3>Uncore [ 300]MHZ -> Vol [ 810]mv
3>Uncore [ 400]MHZ -> Vol [ 810]mv
3>Uncore [ 500]MHZ -> Vol [ 810]mv
3>Uncore [ 600]MHZ -> Vol [ 810]mv
3>Uncore [ 700]MHZ -> Vol [ 810]mv
3>Uncore [ 800]MHZ -> Vol [ 810]mv
3>Uncore [ 900]MHZ -> Vol [ 810]mv
3>Uncore [1000]MHZ -> Vol [ 810]mv
3>Uncore [1100]MHZ -> Vol [ 810]mv
3>Uncore [1200]MHZ -> Vol [ 810]mv
3>Uncore [1300]MHZ -> Vol [ 810]mv
3>Uncore [1400]MHZ -> Vol [ 810]mv
3>Uncore [1500]MHZ -> Vol [ 810]mv
3>Uncore [1600]MHZ -> Vol [ 810]mv
3>Uncore [1700]MHZ -> Vol [ 810]mv
3>Uncore [1800]MHZ -> Vol [ 810]mv
3>Uncore [1900]MHZ -> Vol [ 810]mv
3>Uncore [2000]MHZ -> Vol [ 810]mv
3>Uncore [2100]MHZ -> Vol [ 810]mv
3>Uncore [2200]MHZ -> Vol [ 811]mv
3>Uncore [2300]MHZ -> Vol [ 828]mv
3>Uncore [2400]MHZ -> Vol [ 845]mv
3>Uncore [2500]MHZ -> Vol [ 862]mv
3>Uncore [2600]MHZ -> Vol [ 882]mv
3>Uncore [2700]MHZ -> Vol [ 902]mv
3>Uncore [2800]MHZ -> Vol [ 922]mv
3>Uncore [2900]MHZ -> Vol [ 943]mv
3>Uncore [3000]MHZ -> Vol [1100]mv
3>[TracePoint] type[  0] cmd[  1] data[  6]
3>[TracePoint] type[  0] cmd[  1] data[  7]
3>
********Hello Huawei LiteOS********

KpxxxxIPU Firmware Version : V32.70.0
LiteOS Kernel Version : 5.7.0
3>Run on ChipVersion[0] Node[3] Die[0]
3>build time : Feb 05 2026 20:30:00

3>**********************************
3>
main core booting up...
3>start set affinity
3>
mpidr = 0x810c0000
3>sram ecc state: 0x0, sram ecc cnt: 0x0
3>[TracePoint] type[  0] cmd[  2] data[  1]
3>[TracePoint] type[  0] cmd[  2] data[  2]
3>LRDXSD_LOCK_OFFSET = 0x0
3>LRDXSD_ERRIMSK_OFFSET = 0x0
3>LRDXSD_DBG_OTIMSK_OFFSET = 0x0
3>LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
3>LRDXSD_DBG_EN_OFFSET = 0x1
3>======tsensor params======
3>  is_trimmed       : 1
3>  underclocking_en : 1
3>===========end============
3>soc tsensor init done
3>========vrd info from cpld========
3>vrd_id | u64                | pmbus_en | avsbus_en | loop | pmbus_id | pmbus_addr | avs_sw | pmbus_sw | addr_9545 | domain_type | die_mask | reserved
3>  00   | 0x0001000100002017 | 0x1      | 0x1       | 0x1  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0100   | 0x0
3>  01   | 0x000300030000201b | 0x1      | 0x1       | 0x2  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x3         | 0x0300   | 0x0
3>  02   | 0x0000010a00002715 | 0x1      | 0x0       | 0x1  | 0x1      | 0x27       | 0x0    | 0x0      | 0x0       | 0xa         | 0x0001   | 0x0
3>  03   | 0x0000010500002719 | 0x1      | 0x0       | 0x2  | 0x1      | 0x27       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0001   | 0x0
3>  04   | 0x0000020600002a15 | 0x1      | 0x0       | 0x1  | 0x1      | 0x2a       | 0x0    | 0x0      | 0x0       | 0x6         | 0x0002   | 0x0
3>  05   | 0x0000010600002a19 | 0x1      | 0x0       | 0x2  | 0x1      | 0x2a       | 0x0    | 0x0      | 0x0       | 0x6         | 0x0001   | 0x0
3>  06   | 0x0000020a00002f15 | 0x1      | 0x0       | 0x1  | 0x1      | 0x2f       | 0x0    | 0x0      | 0x0       | 0xa         | 0x0002   | 0x0
3>  07   | 0x0002000100002027 | 0x1      | 0x1       | 0x1  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0200   | 0x0
3>  08   | 0x000300020000202b | 0x1      | 0x1       | 0x2  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x2         | 0x0300   | 0x0
3>  09   | 0x0000030500002725 | 0x1      | 0x0       | 0x1  | 0x2      | 0x27       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0003   | 0x0
3>  10   | 0x0003000400002729 | 0x1      | 0x0       | 0x2  | 0x2      | 0x27       | 0x0    | 0x0      | 0x0       | 0x4         | 0x0300   | 0x0
3>================end===============
3>=============vrd info=============
3>power domain num: 11
3>power domain[00] id:0 | CORE_DVFS_TA       | PMBus NA | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
3>power domain[01] id:1 | DDR_VDD            | PMBus NA | cap:0x3 | rail:1 | addr:0x20 | def_volt: 800 mV | min_volt: 760 mV | max_volt: 840 mV
3>power domain[02] id:14 | NA_AVDD_SDS        | PMBus NA | cap:0x1 | rail:0 | addr:0x27 | def_volt:1200 mV | min_volt:1164 mV | max_volt:1236 mV
3>power domain[03] id:4 | IO_DVDD_NA         | PMBus NA | cap:0x1 | rail:1 | addr:0x27 | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
3>power domain[04] id:11 | IO_DVDD09_NB       | PMBus NA | cap:0x1 | rail:0 | addr:0x2a | def_volt: 900 mV | min_volt: 700 mV | max_volt: 900 mV
3>power domain[05] id:10 | IO_DVDD09_NA       | PMBus NA | cap:0x1 | rail:1 | addr:0x2a | def_volt: 900 mV | min_volt: 700 mV | max_volt: 900 mV
3>power domain[06] id:16 | NB_AVDD_SDS        | PMBus NA | cap:0x1 | rail:0 | addr:0x2f | def_volt:1200 mV | min_volt:1164 mV | max_volt:1236 mV
3>power domain[07] id:2 | CORE_DVFS_TB       | PMBus NB | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
3>power domain[08] id:3 | UNCORE_DVFS        | PMBus NB | cap:0x3 | rail:1 | addr:0x20 | def_volt: 943 mV | min_volt: 750 mV | max_volt:1100 mV
3>power domain[09] id:12 | IO_DVDD_NANB       | PMBus NB | cap:0x1 | rail:0 | addr:0x27 | def_volt: 800 mV | min_volt: 750 mV | max_volt: 900 mV
3>power domain[10] id:6 | DDR_VDDQ           | PMBus NB | cap:0x1 | rail:1 | addr:0x27 | def_volt:1100 mV | min_volt:1000 mV | max_volt:1200 mV
3>================end===============
3>pmbus[0] init done
3>pmbus[1] init done
3>power domain[0] CORE_DVFS_TA       | NA PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
3>power domain[1] DDR_VDD            | NA PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 800 mV | pmu:MP2882
3>power domain[14] NA_AVDD_SDS        | NA PMBus        | rail:0 | addr:0x27 | def_volt:1200 mV | pmu:MP2882
3>power domain[4] IO_DVDD_NA         | NA PMBus        | rail:1 | addr:0x27 | def_volt: 800 mV | pmu:MP2882
3>power domain[11] IO_DVDD09_NB       | NA PMBus        | rail:0 | addr:0x2a | def_volt: 900 mV | pmu:MP2882
3>power domain[10] IO_DVDD09_NA       | NA PMBus        | rail:1 | addr:0x2a | def_volt: 900 mV | pmu:MP2882
3>power domain[16] NB_AVDD_SDS        | NA PMBus        | rail:0 | addr:0x2f | def_volt:1200 mV | pmu:MP2882
3>power domain[2] CORE_DVFS_TB       | NB PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
3>power domain[3] UNCORE_DVFS        | NB PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 943 mV | pmu:MP2882
3>power domain[12] IO_DVDD_NANB       | NB PMBus        | rail:0 | addr:0x27 | def_volt: 800 mV | pmu:MP2882
3>power domain[6] DDR_VDDQ           | NB PMBus        | rail:1 | addr:0x27 | def_volt:1100 mV | pmu:MP2882
3>power domain[0] CORE_DVFS_TA       is transferred to AVSBus mode
3>power domain[1] DDR_VDD            is transferred to AVSBus mode
3>power domain[2] CORE_DVFS_TB       is transferred to AVSBus mode
3>power domain[3] UNCORE_DVFS        is transferred to AVSBus mode
3>avsbus resync success
3>avsbus[0] init done
3>avsbus resync success
3>avsbus[1] init done
3>============volt boot============
3>power domain[0] volt =  886 mV
3>power domain[1] volt =  804 mV
3>power domain[14] volt = 1203 mV
3>power domain[4] volt =  804 mV
3>power domain[11] volt =  906 mV
3>power domain[10] volt =  904 mV
3>power domain[16] volt = 1205 mV
3>power domain[2] volt =  890 mV
3>power domain[3] volt =  816 mV
3>power domain[12] volt =  806 mV
3>power domain[6] volt = 1105 mV
3>===============end===============
3>--w&h rd rail:0, 886, CORE_DVFS_TA
3>--w&h rd rail:1, 800, CORE_DVFS_TA
3>power domain[0] set volt --> 1101 mV success
3>--w&h rd rail:0, 890, CORE_DVFS_TB
3>--w&h rd rail:1, 818, CORE_DVFS_TB
3>power domain[2] set volt --> 1101 mV success
3>power domain[3] set volt -->  949 mV success
3>============volt post============
3>power domain[0] volt = 1103 mV
3>power domain[1] volt =  802 mV
3>power domain[14] volt = 1201 mV
3>power domain[4] volt =  804 mV
3>power domain[11] volt =  906 mV
3>power domain[10] volt =  906 mV
3>power domain[16] volt = 1205 mV
3>power domain[2] volt = 1103 mV
3>power domain[3] volt =  949 mV
3>power domain[12] volt =  806 mV
3>power domain[6] volt = 1105 mV
3>===============end===============
3>the power sensor : manu id = 2peak, die id = TPA626
3>power sensor[0] init success
3>die[0] its[0] init done
3>die[0] its[1] init done
3>die[0] its[2] init done
3>die[0] its[3] init done
3>die[0] its[4] init done
3>die[0] its[5] init done
3>die[0] its[6] init done
3>die[0] its[7] init done
3>die[0] its[8] init done
3>die[0] its[9] init done
3>die[1] its[0] init done
3>die[1] its[1] init done
3>die[1] its[2] init done
3>die[1] its[3] init done
3>die[1] its[4] init done
3>die[1] its[5] init done
3>die[1] its[6] init done
3>die[1] its[7] init done
3>die[1] its[8] init done
3>die[1] its[9] init done
3>Totem[0] Core Boot Vol [1103]mv
3>Totem[0] Core Current Vol [1100]mv
3>Totem[1] Core Boot Vol [1103]mv
3>Totem[1] Core Current Vol [1100]mv
3>NA 1620V1a0
3>NB 1620V1a0
3>GetCoreBaseFreq [2500000KHZ]
3>GetCoreTurboFreq [2500000KHZ]
3>GetCustomClusterNum [10]
3>Ipu ACG Training Done!
3>AP Last Time:[0.00.01.521]
3>wait UEFI pll init...
3>done
3>acg trim start
3>core trim freq:2000, avs:0 volt:810mv
3>core trim freq:2000, avs:0 volt:810mv
3>core trim freq:2050, avs:1 volt:810mv
3>core trim freq:2050, avs:1 volt:810mv
3>core trim freq:2100, avs:2 volt:810mv
3>core trim freq:2100, avs:2 volt:810mv
3>core trim freq:2150, avs:3 volt:810mv
3>core trim freq:2150, avs:3 volt:810mv
3>core trim freq:2200, avs:4 volt:810mv
3>core trim freq:2200, avs:4 volt:811mv
3>core trim freq:2250, avs:5 volt:820mv
3>core trim freq:2250, avs:5 volt:824mv
3>core trim freq:2300, avs:6 volt:833mv
3>core trim freq:2300, avs:6 volt:836mv
3>core trim freq:2350, avs:7 volt:845mv
3>core trim freq:2350, avs:7 volt:849mv
3>core trim freq:2400, avs:8 volt:858mv
3>core trim freq:2400, avs:8 volt:862mv
3>core trim freq:2450, avs:9 volt:870mv
3>core trim freq:2450, avs:9 volt:874mv
3>core trim freq:2500, avs:10 volt:883mv
3>core trim freq:2500, avs:10 volt:887mv
3>core trim freq:2550, avs:11 volt:895mv
3>core trim freq:2550, avs:11 volt:900mv
3>core trim freq:2600, avs:12 volt:908mv
3>core trim freq:2600, avs:12 volt:912mv
3>core trim freq:2650, avs:13 volt:920mv
3>core trim freq:2650, avs:13 volt:925mv
3>core trim freq:2700, avs:14 volt:933mv
3>core trim freq:2700, avs:14 volt:938mv
3>core trim freq:2750, avs:15 volt:951mv
3>core trim freq:2750, avs:15 volt:956mv
3>core trim freq:2800, avs:16 volt:969mv
3>core trim freq:2800, avs:16 volt:974mv
3>core trim freq:2850, avs:17 volt:987mv
3>core trim freq:2850, avs:17 volt:992mv
3>core trim freq:2900, avs:18 volt:1005mv
3>core trim freq:2900, avs:18 volt:1011mv
3>core trim freq:2950, avs:19 volt:1022mv
3>core trim freq:2950, avs:19 volt:1028mv
3>core trim freq:3000, avs:20 volt:1039mv
3>core trim freq:3000, avs:20 volt:1045mv
3>core trim freq:3050, avs:21 volt:1053mv
3>core trim freq:3050, avs:21 volt:1058mv
3>core trim freq:3100, avs:22 volt:1067mv
3>core trim freq:3100, avs:22 volt:1072mv
3>acg trim end
3>LDO disabled
3>[TracePoint] type[  0] cmd[  2] data[  3]
3>Interrupt 423 register OK
3>Interrupt 430 register OK
3>[TracePoint] type[  0] cmd[  2] data[  4]
3>
3>cpu 0 entering scheduler
3>[TracePoint] type[  0] cmd[  3] data[  1]
3>add your ipu app init here!
3>IpuInterfaceTaskStart Entry ...
3>ipu interface task wait parameters from uefi...
3>thermal soc task enabled
3>AP Last Time:[0.00.07.301]
3>ThermalDimmStart Entry ...
3>wait ddr init done...
3>power task start...
3>[TracePoint] type[  0] cmd[  3] data[  2]
3>ufs task wait parameters from uefi...
3>AmuTaskStart Entry ... 
3>amu task wait parameters from uefi...
3>ThermalSiwStart Entry ...
3>ThermalSiwTask idle...
3>DemtTaskStart Entry ...
3>[TracePoint] type[  0] cmd[  3] data[  3]
3>HiBoostTaskStart Entry ...
3>HiBoost task enabled
3>Waiting for UEFI parameters...
3>[TracePoint] type[  0] cmd[  3] data[  4]
3>demt task wait parameters from uefi...
3>AgeTaskStart Entry ...
3>age task wait parameters from uefi...
3>[TracePoint] type[  0] cmd[  3] data[  5]
3>uefi parameters ready!
3>UFSProfile[0]
3>PowerPolicy[2] BenchMarkSelection[0]
3>ipu interface task wait ddr init done from uefi...
3>ufs task parameters from uefi ready
3>uncore domain[0] freq:2900
3>uncore domain[1] freq:2900
3>thermal soc task restore underclocking_en=1
3>ppu alert temp div init done
3>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
3>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
3>======sioe status======
3>TA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
3>TA_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
3>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
3>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
3>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
3>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
3>==========end==========
3>sioe init done
3>ufs task enabled
3>--> UFS profile[0]
3>UEFI parameters ready
3>UncoreMaxFreq Set to [2900 MHZ]
3>get TDP from efuse success, value = 307500mw
3>target power set to [307500]mw, brd:[307500]
3>age task parameters from uefi ready
3>demt task parameters from uefi ready
3>age task enabled
3>uefi ddr init finish!
3>ipu interface task wait uefi end done from uefi...
3>ddr init done, start thermal dimm task
3>======dimm status======
3>  chl[0] dimm0 0, dimm1 0
3>  chl[1] dimm0 0, dimm1 0
3>  chl[2] dimm0 0, dimm1 0
3>  chl[3] dimm0 0, dimm1 0
3>  chl[4] dimm0 0, dimm1 0
3>  chl[5] dimm0 0, dimm1 0
3>  chl[6] dimm0 0, dimm1 0
3>  chl[7] dimm0 0, dimm1 0
3>==========end==========
3>=====dimm temp params=====
3>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
3>  is_thermal_thro_en  : 1
3>  is_aref_rate_auto   : 1
3>===========end============
3>uefi end finish!
3>ipu interface task exit!
3>amu task parameters from uefi ready
3>amu task activated
3>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!


HSM_LOG:
[00:00:00.010][info] os_mem_system_init default pool done
[00:00:00.016][info] succeed to do thirdparty otpc_pabuk init
[00:00



HSM_LOG:
:00.017][info] succeed to do thirdparty boot_profile_driver init
[00:00:00.017][info] succeed to do thirdparty measure_value_ma



HSM_LOG:
nage_driver init
[00:00:00.018][info] succeed to do thirdparty period_driver init
[00:00:00.018][info]  start loading internal



HSM_LOG:
 task ...
[00:00:00.018][info]  task name is ccm_task
[00:00:00.019][info]  hm_dynamic_loadelf successfully!
[00:00:00.019][i



HSM_LOG:
nfo] internal task[1] task_name=ccm_task load successfully
[00:00:00.020][info]  task name is upgrade_task
[00:00:00.020][info



HSM_LOG:
]  hm_dynamic_loadelf successfully!
[00:00:00.021][info] internal task[2] task_name=upgrade_task load successfully
[00:00:00.0



HSM_LOG:
22][info]  task name is hes_task
[00:00:00.022][info]  hm_dynamic_loadelf successfully!
[00:00:00.023][info] internal task[3] 



HSM_LOG:
task_name=hes_task load successfully
[00:00:00.024][info] created task ccm_task success!
[00:00:00.025][info] created task upg



HSM_LOG:
rade_task success!
[00:00:00.026][info] created task hes_task success!
[00:00:00.026][info] Init start.
[1970-01-01 00:00:00.



HSM_LOG:
027][HSM][INFO][54] Platform init 0x20250523 0x4e.

[1970-01-01 00:00:00.027][HSM][INFO][197] ccm start.

[1970-01-01 00:00:00



HSM_LOG:
.028][HSM][INFO][86] upgrade task init success.

[1970-01-01 00:00:00.028][HSM][INFO][95] upgrade recv cmd, 0x181.

[1970-01-0



HSM_LOG:
1 00:00:00.029][HSM][INFO][103] upgrade res, 0x3a5aa5a3.

[1970-01-01 00:00:00.030][HSM][INFO][75] hes tee_task_entry.

[1970-



HSM_LOG:
01-01 00:00:00.550][HSM][INFO][44] hes init success.

[00:00:00.550][info] Init over.
[1970-01-01 00:00:17.062][HSM][INFO][281



HSM_LOG:
] -------------2------------

.[00:00:00.000][info] succeed to do thirdparty dfx_pabuk init
[00:00:00.000][info] succeed to do



HSM_LOG:
 thirdparty crypto_driver init
[00:00:00.010][info] os_mem_system_init default pool done
[00:00:00.016][info] succeed to do th



HSM_LOG:
irdparty otpc_pabuk init
[00:00:00.017][info] succeed to do thirdparty boot_profile_driver init
[00:00:00.017][info] succeed t



HSM_LOG:
o do thirdparty measure_value_manage_driver init
[00:00:00.018][info] succeed to do thirdparty period_driver init
[00:00:00.01



HSM_LOG:
8][info]  start loading internal task ...
[00:00:00.018][info]  task name is ccm_task
[00:00:00.019][info]  hm_dynamic_loadelf



HSM_LOG:
 successfully!
[00:00:00.019][info] internal task[1] task_name=ccm_task load successfully
[00:00:00.020][info]  task name is u



HSM_LOG:
pgrade_task
[00:00:00.020][info]  hm_dynamic_loadelf successfully!
[00:00:00.021][info] internal task[2] task_name=upgrade_tas



HSM_LOG:
k load successfully
[00:00:00.022][info]  task name is hes_task
[00:00:00.022][info]  hm_dynamic_loadelf successfully!
[00:00



HSM_LOG:
:00.023][info] internal task[3] task_name=hes_task load successfully
[00:00:00.024][info] created task ccm_task success!
[00:0



HSM_LOG:
0:00.025][info] created task upgrade_task success!
[00:00:00.026][info] created task hes_task success!
[00:00:00.026][info] In



HSM_LOG:
it start.
[1970-01-01 00:00:00.027][HSM][INFO][54] Platform init 0x20250523 0x4e.

[1970-01-01 00:00:00.027][HSM][INFO][197] c



HSM_LOG:
cm start.

[1970-01-01 00:00:00.028][HSM][INFO][86] upgrade task init success.

[1970-01-01 00:00:00.028][HSM][INFO][95] upgra



HSM_LOG:
de recv cmd, 0x181.

[1970-01-01 00:00:00.029][HSM][INFO][103] upgrade res, 0x3a5aa5a3.

[1970-01-01 00:00:00.030][HSM][INFO][



HSM_LOG:
75] hes tee_task_entry.

[1970-01-01 00:00:00.551][HSM][INFO][44] hes init success.

[00:00:00.552][info] Init over.
[1970-01



HSM_LOG:
-01 00:00:16.784][HSM][INFO][281] -------------3------------

.

[0.06.57.178]IpmiCmdReportPcieMMIO start
[0.07.20.743]IpmiCmdReportPcieMMIO end
pool addr          pool size    used size     free size    max free node size   used node num     free node num      UsageWaterLine
---------------    --------     -------       --------     --------------       -------------      ------------      ------------
0x840908e708       0x204c0      0x1a010       0x6240       0x5ad0               0xd9               0x3                0x1a9f0        
]mv
3>[ 500]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 550]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 600]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 650]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 700]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 750]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 800]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 850]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 900]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 950]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1000]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1050]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1100]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1150]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1200]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1250]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1300]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1350]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1400]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1450]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1500]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1550]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1600]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1650]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1700]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1750]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1800]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1850]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1900]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1950]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2000]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2050]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2100]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2150]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2200]MHZ -> Vol TA[ 810]mv TB[ 811]mv
3>[2250]MHZ -> Vol TA[ 820]mv TB[ 824]mv
3>[2300]MHZ -> Vol TA[ 833]mv TB[ 836]mv
3>[2350]MHZ -> Vol TA[ 845]mv TB[ 849]mv
3>[2400]MHZ -> Vol TA[ 858]mv TB[ 862]mv
3>[2450]MHZ -> Vol TA[ 870]mv TB[ 874]mv
3>[2500]MHZ -> Vol TA[ 883]mv TB[ 887]mv
3>[2550]MHZ -> Vol TA[ 895]mv TB[ 900]mv
3>[2600]MHZ -> Vol TA[ 908]mv TB[ 912]mv
3>[2650]MHZ -> Vol TA[ 920]mv TB[ 925]mv
3>[2700]MHZ -> Vol TA[ 933]mv TB[ 938]mv
3>[2750]MHZ -> Vol TA[ 951]mv TB[ 956]mv
3>[2800]MHZ -> Vol TA[ 969]mv TB[ 974]mv
3>[2850]MHZ -> Vol TA[ 987]mv TB[ 992]mv
3>[2900]MHZ -> Vol TA[1005]mv TB[1011]mv
3>[2950]MHZ -> Vol TA[1022]mv TB[1028]mv
3>[3000]MHZ -> Vol TA[1039]mv TB[1045]mv
3>[3050]MHZ -> Vol TA[1053]mv TB[1058]mv
3>[3100]MHZ -> Vol TA[1067]mv TB[1072]mv
3>Uncore VF curve:
3>Uncore [   0]MHZ -> Vol [ 810]mv
3>Uncore [ 100]MHZ -> Vol [ 810]mv
3>Uncore [ 200]MHZ -> Vol [ 810]mv
3>Uncore [ 300]MHZ -> Vol [ 810]mv
3>Uncore [ 400]MHZ -> Vol [ 810]mv
3>Uncore [ 500]MHZ -> Vol [ 810]mv
3>Uncore [ 600]MHZ -> Vol [ 810]mv
3>Uncore [ 700]MHZ -> Vol [ 810]mv
3>Uncore [ 800]MHZ -> Vol [ 810]mv
3>Uncore [ 900]MHZ -> Vol [ 810]mv
3>Uncore [1000]MHZ -> Vol [ 810]mv
3>Uncore [1100]MHZ -> Vol [ 810]mv
3>Uncore [1200]MHZ -> Vol [ 810]mv
3>Uncore [1300]MHZ -> Vol [ 810]mv
3>Uncore [1400]MHZ -> Vol [ 810]mv
3>Uncore [1500]MHZ -> Vol [ 810]mv
3>Uncore [1600]MHZ -> Vol [ 810]mv
3>Uncore [1700]MHZ -> Vol [ 810]mv
3>Uncore [1800]MHZ -> Vol [ 810]mv
3>Uncore [1900]MHZ -> Vol [ 810]mv
3>Uncore [2000]MHZ -> Vol [ 810]mv
3>Uncore [2100]MHZ -> Vol [ 810]mv
3>Uncore [2200]MHZ -> Vol [ 811]mv
3>Uncore [2300]MHZ -> Vol [ 828]mv
3>Uncore [2400]MHZ -> Vol [ 845]mv
3>Uncore [2500]MHZ -> Vol [ 862]mv
3>Uncore [2600]MHZ -> Vol [ 882]mv
3>Uncore [2700]MHZ -> Vol [ 902]mv
3>Uncore [2800]MHZ -> Vol [ 922]mv
3>Uncore [2900]MHZ -> Vol [ 943]mv
3>Uncore [3000]MHZ -> Vol [1100]mv
3>[TracePoint] type[  0] cmd[  1] data[  6]
3>[TracePoint] type[  0] cmd[  1] data[  7]
3>
********Hello Huawei LiteOS********

KpxxxxIPU Firmware Version : V32.70.0
LiteOS Kernel Version : 5.7.0
3>Run on ChipVersion[0] Node[3] Die[0]
3>build time : Feb 05 2026 20:30:00

3>**********************************
3>
main core booting up...
3>start set affinity
3>
mpidr = 0x810c0000
3>sram ecc state: 0x0, sram ecc cnt: 0x0
3>[TracePoint] type[  0] cmd[  2] data[  1]
3>[TracePoint] type[  0] cmd[  2] data[  2]
3>LRDXSD_LOCK_OFFSET = 0x0
3>LRDXSD_ERRIMSK_OFFSET = 0x0
3>LRDXSD_DBG_OTIMSK_OFFSET = 0x0
3>LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
3>LRDXSD_DBG_EN_OFFSET = 0x1
3>======tsensor params======
3>  is_trimmed       : 1
3>  underclocking_en : 1
3>===========end============
3>soc tsensor init done
3>========vrd info from cpld========
3>vrd_id | u64                | pmbus_en | avsbus_en | loop | pmbus_id | pmbus_addr | avs_sw | pmbus_sw | addr_9545 | domain_type | die_mask | reserved
3>  00   | 0x0001000100002017 | 0x1      | 0x1       | 0x1  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0100   | 0x0
3>  01   | 0x000300030000201b | 0x1      | 0x1       | 0x2  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x3         | 0x0300   | 0x0
3>  02   | 0x0000010a00002715 | 0x1      | 0x0       | 0x1  | 0x1      | 0x27       | 0x0    | 0x0      | 0x0       | 0xa         | 0x0001   | 0x0
3>  03   | 0x0000010500002719 | 0x1      | 0x0       | 0x2  | 0x1      | 0x27       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0001   | 0x0
3>  04   | 0x0000020600002a15 | 0x1      | 0x0       | 0x1  | 0x1      | 0x2a       | 0x0    | 0x0      | 0x0       | 0x6         | 0x0002   | 0x0
3>  05   | 0x0000010600002a19 | 0x1      | 0x0       | 0x2  | 0x1      | 0x2a       | 0x0    | 0x0      | 0x0       | 0x6         | 0x0001   | 0x0
3>  06   | 0x0000020a00002f15 | 0x1      | 0x0       | 0x1  | 0x1      | 0x2f       | 0x0    | 0x0      | 0x0       | 0xa         | 0x0002   | 0x0
3>  07   | 0x0002000100002027 | 0x1      | 0x1       | 0x1  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0200   | 0x0
3>  08   | 0x000300020000202b | 0x1      | 0x1       | 0x2  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x2         | 0x0300   | 0x0
3>  09   | 0x0000030500002725 | 0x1      | 0x0       | 0x1  | 0x2      | 0x27       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0003   | 0x0
3>  10   | 0x0003000400002729 | 0x1      | 0x0       | 0x2  | 0x2      | 0x27       | 0x0    | 0x0      | 0x0       | 0x4         | 0x0300   | 0x0
3>================end===============
3>=============vrd info=============
3>power domain num: 11
3>power domain[00] id:0 | CORE_DVFS_TA       | PMBus NA | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
3>power domain[01] id:1 | DDR_VDD            | PMBus NA | cap:0x3 | rail:1 | addr:0x20 | def_volt: 800 mV | min_volt: 760 mV | max_volt: 840 mV
3>power domain[02] id:14 | NA_AVDD_SDS        | PMBus NA | cap:0x1 | rail:0 | addr:0x27 | def_volt:1200 mV | min_volt:1164 mV | max_volt:1236 mV
3>power domain[03] id:4 | IO_DVDD_NA         | PMBus NA | cap:0x1 | rail:1 | addr:0x27 | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
3>power domain[04] id:11 | IO_DVDD09_NB       | PMBus NA | cap:0x1 | rail:0 | addr:0x2a | def_volt: 900 mV | min_volt: 700 mV | max_volt: 900 mV
3>power domain[05] id:10 | IO_DVDD09_NA       | PMBus NA | cap:0x1 | rail:1 | addr:0x2a | def_volt: 900 mV | min_volt: 700 mV | max_volt: 900 mV
3>power domain[06] id:16 | NB_AVDD_SDS        | PMBus NA | cap:0x1 | rail:0 | addr:0x2f | def_volt:1200 mV | min_volt:1164 mV | max_volt:1236 mV
3>power domain[07] id:2 | CORE_DVFS_TB       | PMBus NB | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
3>power domain[08] id:3 | UNCORE_DVFS        | PMBus NB | cap:0x3 | rail:1 | addr:0x20 | def_volt: 943 mV | min_volt: 750 mV | max_volt:1100 mV
3>power domain[09] id:12 | IO_DVDD_NANB       | PMBus NB | cap:0x1 | rail:0 | addr:0x27 | def_volt: 800 mV | min_volt: 750 mV | max_volt: 900 mV
3>power domain[10] id:6 | DDR_VDDQ           | PMBus NB | cap:0x1 | rail:1 | addr:0x27 | def_volt:1100 mV | min_volt:1000 mV | max_volt:1200 mV
3>================end===============
3>pmbus[0] init done
3>pmbus[1] init done
3>power domain[0] CORE_DVFS_TA       | NA PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
3>power domain[1] DDR_VDD            | NA PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 800 mV | pmu:MP2882
3>power domain[14] NA_AVDD_SDS        | NA PMBus        | rail:0 | addr:0x27 | def_volt:1200 mV | pmu:MP2882
3>power domain[4] IO_DVDD_NA         | NA PMBus        | rail:1 | addr:0x27 | def_volt: 800 mV | pmu:MP2882
3>power domain[11] IO_DVDD09_NB       | NA PMBus        | rail:0 | addr:0x2a | def_volt: 900 mV | pmu:MP2882
3>power domain[10] IO_DVDD09_NA       | NA PMBus        | rail:1 | addr:0x2a | def_volt: 900 mV | pmu:MP2882
3>power domain[16] NB_AVDD_SDS        | NA PMBus        | rail:0 | addr:0x2f | def_volt:1200 mV | pmu:MP2882
3>power domain[2] CORE_DVFS_TB       | NB PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
3>power domain[3] UNCORE_DVFS        | NB PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 943 mV | pmu:MP2882
3>power domain[12] IO_DVDD_NANB       | NB PMBus        | rail:0 | addr:0x27 | def_volt: 800 mV | pmu:MP2882
3>power domain[6] DDR_VDDQ           | NB PMBus        | rail:1 | addr:0x27 | def_volt:1100 mV | pmu:MP2882
3>power domain[0] CORE_DVFS_TA       is transferred to AVSBus mode
3>power domain[1] DDR_VDD            is transferred to AVSBus mode
3>power domain[2] CORE_DVFS_TB       is transferred to AVSBus mode
3>power domain[3] UNCORE_DVFS        is transferred to AVSBus mode
3>avsbus resync success
3>avsbus[0] init done
3>avsbus resync success
3>avsbus[1] init done
3>============volt boot============
3>power domain[0] volt = 1103 mV
3>power domain[1] volt =  804 mV
3>power domain[14] volt = 1201 mV
3>power domain[4] volt =  804 mV
3>power domain[11] volt =  904 mV
3>power domain[10] volt =  902 mV
3>power domain[16] volt = 1205 mV
3>power domain[2] volt = 1103 mV
3>power domain[3] volt = 1007 mV
3>power domain[12] volt =  804 mV
3>power domain[6] volt = 1105 mV
3>===============end===============
3>--w&h rd rail:0, 1101, CORE_DVFS_TA
3>--w&h rd rail:1, 800, CORE_DVFS_TA
3>power domain[0] set volt --> 1103 mV success
3>--w&h rd rail:0, 1101, CORE_DVFS_TB
3>--w&h rd rail:1, 1007, CORE_DVFS_TB
3>power domain[2] set volt --> 1101 mV success
3>power domain[3] set volt -->  949 mV success
3>============volt post============
3>power domain[0] volt = 1103 mV
3>power domain[1] volt =  802 mV
3>power domain[14] volt = 1201 mV
3>power domain[4] volt =  804 mV
3>power domain[11] volt =  906 mV
3>power domain[10] volt =  902 mV
3>power domain[16] volt = 1203 mV
3>power domain[2] volt = 1103 mV
3>power domain[3] volt =  949 mV
3>power domain[12] volt =  804 mV
3>power domain[6] volt = 1105 mV
3>===============end===============
3>the power sensor : manu id = 2peak, die id = TPA626
3>power sensor[0] init success
3>die[0] its[0] init done
3>die[0] its[1] init done
3>die[0] its[2] init done
3>die[0] its[3] init done
3>die[0] its[4] init done
3>die[0] its[5] init done
3>die[0] its[6] init done
3>die[0] its[7] init done
3>die[0] its[8] init done
3>die[0] its[9] init done
3>die[1] its[0] init done
3>die[1] its[1] init done
3>die[1] its[2] init done
3>die[1] its[3] init done
3>die[1] its[4] init done
3>die[1] its[5] init done
3>die[1] its[6] init done
3>die[1] its[7] init done
3>die[1] its[8] init done
3>die[1] its[9] init done
3>Totem[0] Core Boot Vol [1103]mv
3>Totem[0] Core Current Vol [1100]mv
3>Totem[1] Core Boot Vol [1103]mv
3>Totem[1] Core Current Vol [1100]mv
3>NA 1620V1a0
3>NB 1620V1a0
3>GetCoreBaseFreq [2500000KHZ]
3>GetCoreTurboFreq [2500000KHZ]
3>GetCustomClusterNum [10]
3>Ipu ACG Training Done!
3>AP Last Time:[0.00.01.725]
3>wait UEFI pll init...
3>done
3>acg trim start
3>core trim freq:2000, avs:0 volt:810mv
3>core trim freq:2000, avs:0 volt:810mv
3>core trim freq:2050, avs:1 volt:810mv
3>core trim freq:2050, avs:1 volt:810mv
3>core trim freq:2100, avs:2 volt:810mv
3>core trim freq:2100, avs:2 volt:810mv
3>core trim freq:2150, avs:3 volt:810mv
3>core trim freq:2150, avs:3 volt:810mv
3>core trim freq:2200, avs:4 volt:810mv
3>core trim freq:2200, avs:4 volt:811mv
3>core trim freq:2250, avs:5 volt:820mv
3>core trim freq:2250, avs:5 volt:824mv
3>core trim freq:2300, avs:6 volt:833mv
3>core trim freq:2300, avs:6 volt:836mv
3>core trim freq:2350, avs:7 volt:845mv
3>core trim freq:2350, avs:7 volt:849mv
3>core trim freq:2400, avs:8 volt:858mv
3>core trim freq:2400, avs:8 volt:862mv
3>core trim freq:2450, avs:9 volt:870mv
3>core trim freq:2450, avs:9 volt:874mv
3>core trim freq:2500, avs:10 volt:883mv
3>core trim freq:2500, avs:10 volt:887mv
3>core trim freq:2550, avs:11 volt:895mv
3>core trim freq:2550, avs:11 volt:900mv
3>core trim freq:2600, avs:12 volt:908mv
3>core trim freq:2600, avs:12 volt:912mv
3>core trim freq:2650, avs:13 volt:920mv
3>core trim freq:2650, avs:13 volt:925mv
3>core trim freq:2700, avs:14 volt:933mv
3>core trim freq:2700, avs:14 volt:938mv
3>core trim freq:2750, avs:15 volt:951mv
3>core trim freq:2750, avs:15 volt:956mv
3>core trim freq:2800, avs:16 volt:969mv
3>core trim freq:2800, avs:16 volt:974mv
3>core trim freq:2850, avs:17 volt:987mv
3>core trim freq:2850, avs:17 volt:992mv
3>core trim freq:2900, avs:18 volt:1005mv
3>core trim freq:2900, avs:18 volt:1011mv
3>core trim freq:2950, avs:19 volt:1022mv
3>core trim freq:2950, avs:19 volt:1028mv
3>core trim freq:3000, avs:20 volt:1039mv
3>core trim freq:3000, avs:20 volt:1045mv
3>core trim freq:3050, avs:21 volt:1053mv
3>core trim freq:3050, avs:21 volt:1058mv
3>core trim freq:3100, avs:22 volt:1067mv
3>core trim freq:3100, avs:22 volt:1072mv
3>acg trim end
3>LDO disabled
3>[TracePoint] type[  0] cmd[  2] data[  3]
3>Interrupt 423 register OK
3>Interrupt 430 register OK
3>[TracePoint] type[  0] cmd[  2] data[  4]
3>
3>cpu 0 entering scheduler
3>[TracePoint] type[  0] cmd[  3] data[  1]
3>add your ipu app init here!
3>IpuInterfaceTaskStart Entry ...
3>ipu interface task wait parameters from uefi...
3>thermal soc task enabled
3>AP Last Time:[0.00.41.163]
3>ThermalDimmStart Entry ...
3>wait ddr init done...
3>power task start...
3>[TracePoint] type[  0] cmd[  3] data[  2]
3>ufs task wait parameters from uefi...
3>AmuTaskStart Entry ... 
3>amu task wait parameters from uefi...
3>ThermalSiwStart Entry ...
3>ThermalSiwTask idle...
3>DemtTaskStart Entry ...
3>[TracePoint] type[  0] cmd[  3] data[  3]
3>HiBoostTaskStart Entry ...
3>HiBoost task enabled
3>Waiting for UEFI parameters...
3>[TracePoint] type[  0] cmd[  3] data[  4]
3>demt task wait parameters from uefi...
3>AgeTaskStart Entry ...
3>age task wait parameters from uefi...
3>[TracePoint] type[  0] cmd[  3] data[  5]
Get Setup Config.
pwr cap[0]: 0, 63
pwr cap[1]: f, 27
0>uefi parameters ready!
0>UFSProfile[0]
0>PowerPolicy[2] BenchMarkSelection[0]
0>ipu interface task wait ddr init done from uefi...
0>thermal soc task restore underclocking_en=1
0>ppu alert temp div init done
0>ufs task parameters from uefi ready
0>uncore domain[0] freq:2900
0>uncore domain[1] freq:2900
0>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
0>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
0>======sioe status======
0>TA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TA_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TA_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TA_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
0>TA_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
0>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
0>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
0>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
0>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
0>==========end==========
0>sioe init done
0>ufs task enabled
0>--> UFS profile[0]
0>UEFI parameters ready
0>UncoreMaxFreq Set to [2900 MHZ]
0>get TDP from efuse success, value = 307500mw
0>target power set to [307500]mw, brd:[307500]
0>demt task parameters from uefi ready
0>age task parameters from uefi ready
0>age task enabled
1>uefi parameters ready!
1>UFSProfile[0]
1>PowerPolicy[2] BenchMarkSelection[0]
1>ipu interface task wait ddr init done from uefi...
1>ufs task parameters from uefi ready
1>uncore domain[0] freq:2900
1>uncore domain[1] freq:2900
1>thermal soc task restore underclocking_en=1
1>ppu alert temp div init done
1>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
1>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
1>======sioe status======
1>TA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TA_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TA_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TA_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
1>TA_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
1>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
1>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
1>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
1>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
1>==========end==========
1>sioe init done
1>ufs task enabled
1>--> UFS profile[0]
1>UEFI parameters ready
1>UncoreMaxFreq Set to [2900 MHZ]
1>get TDP from efuse success, value = 307500mw
1>target power set to [307500]mw, brd:[307500]
1>age task parameters from uefi ready
1>age task enabled
1>demt task parameters from uefi ready
2>uefi parameters ready!
2>UFSProfile[0]
2>PowerPolicy[2] BenchMarkSelection[0]
2>ipu interface task wait ddr init done from uefi...
2>ufs task parameters from uefi ready
2>uncore domain[0] freq:2900
2>uncore domain[1] freq:2900
2>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
2>thermal soc task restore underclocking_en=1
2>ppu alert temp div init done
2>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
2>======sioe status======
2>TA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
2>TA_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
2>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
2>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
2>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
2>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
2>==========end==========
2>sioe init done
2>ufs task enabled
2>--> UFS profile[0]
2>UEFI parameters ready
2>UncoreMaxFreq Set to [2900 MHZ]
2>get TDP from efuse success, value = 307500mw
2>target power set to [307500]mw, brd:[307500]
2>demt task parameters from uefi ready
2>age task parameters from uefi ready
2>age task enabled
3>uefi parameters ready!
3>UFSProfile[0]
3>PowerPolicy[2] BenchMarkSelection[0]
3>ipu interface task wait ddr init done from uefi...
3>ufs task parameters from uefi ready
3>uncore domain[0] freq:2900
3>uncore domain[1] freq:2900
3>thermal soc task restore underclocking_en=1
3>ppu alert temp div init done
3>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
3>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
3>======sioe status======
3>TA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
3>TA_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
3>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
3>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
3>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
3>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
3>==========end==========
3>sioe init done
3>ufs task enabled
3>--> UFS profile[0]
3>UEFI parameters ready
3>UncoreMaxFreq Set to [2900 MHZ]
3>get TDP from efuse success, value = 307500mw
3>target power set to [307500]mw, brd:[307500]
3>age task parameters from uefi ready
3>age task enabled
3>demt task parameters from uefi ready
pwr cap[2]: 1, 3
Node 0, Die 0 ImpState is 0 skip exec.
Node 0, Die 2 ImpState is 0 skip exec.
Node 1, Die 0 ImpState is 0 skip exec.
Node 1, Die 2 ImpState is 0 skip exec.
Node 2, Die 0 ImpState is 0 skip exec.
Node 2, Die 2 ImpState is 0 skip exec.
Node 3, Die 0 ImpState is 0 skip exec.
Node 3, Die 2 ImpState is 0 skip exec.
0>uefi ddr init finish!
0>ipu interface task wait uefi end done from uefi...
0>ddr init done, start thermal dimm task
0>======dimm status======
1>uefi ddr init finish!
1>ipu interface task wait uefi end done from uefi...
2>uefi ddr init finish!
2>ipu interface task wait uefi end done from uefi...
2>ddr init done, start thermal dimm task
2>======dimm status======
2>  chl[0] dimm0 0, dimm1 0
2>  chl[1] dimm0 0, dimm1 0
2>  chl[2] dimm0 2, dimm1 0
2>  chl[3] dimm0 0, dimm1 0
2>  chl[4] dimm0 0, dimm1 0
3>uefi ddr init finish!
3>ipu interface task wait uefi end done from uefi...
[0.01.10.452]DDR Rreserved for IMU: len = 3e00000
[LOG]head = 0x0, tail = 0x4a70, logSize = 0x4a70
copy registry.json file success
Set component all release version to sram end.
ipcMsgSend success
[0.01.10.574]starting ras Init
nodeId = 0, dieId = 0, isSasExist = 0.
nodeId = 0, dieId = 2, isSasExist = 0.
nodeId = 1, dieId = 0, isSasExist = 0.
nodeId = 1, dieId = 2, isSasExist = 0.
nodeId = 2, dieId = 0, isSasExist = 0.
nodeId = 2, dieId = 2, isSasExist = 0.
nodeId = 3, dieId = 0, isSasExist = 0.
nodeId = 3, dieId = 2, isSasExist = 0.
Mce Table head exist!
RasIntRegister init 452 
RasIntRegister init 453 
RasIntRegister init 64 
RasIntRegister init 65 
RasIntRegister init 465 
RasIntRegister init 466 
RasIntRegister init 86 
RasIntRegister init 87 
RasIntRegister init 478 
RasIntRegister init 479 
RasIntRegister init 108 
RasIntRegister init 109 
RasIntRegister init 491 
RasIntRegister init 492 
RasIntRegister init 130 
RasIntRegister init 131 
RasIntRegister init 504 
RasIntRegister init 505 
RasIntRegister init 152 
RasIntRegister init 153 
RasIntRegister init 517 
RasIntRegister init 518 
RasIntRegister init 174 
RasIntRegister init 175 
RasIntRegister init 530 
RasIntRegister init 531 
RasIntRegister init 196 
RasIntRegister init 197 
RasIntRegister init 543 
RasIntRegister init 544 
RasIntRegister init 218 
RasIntRegister init 219 
RasIntRegister init 76 
RasIntRegister init 98 
RasIntRegister init 120 
RasIntRegister init 142 
RasIntRegister init 164 
RasIntRegister init 186 
RasIntRegister init 208 
RasIntRegister init 230 
[0.01.10.693]starting ras end


HSM_LOG:
[00:00:00.000][info] succeed to do thirdparty dfx_pabuk init
[00:00:00.000][info] succeed to do thirdparty crypto_driver init


0>  chl[0] dimm0 0, dimm1 0
0>  chl[1] dimm0 0, dimm1 0
0>  chl[2] dimm0 2, dimm1 0
0>  chl[3] dimm0 0, dimm1 0
0>  chl[4] dimm0 0, dimm1 0
0>  chl[5] dimm0 0, dimm1 0
0>  chl[6] dimm0 0, dimm1 0
0>  chl[7] dimm0 0, dimm1 0
0>==========end==========
0>chl[2] registered, dimm mask = 0x1
0>=====dimm temp params=====
0>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
0>  is_thermal_thro_en  : 1
0>  is_aref_rate_auto   : 1
0>===========end============
1>ddr init done, start thermal dimm task
1>======dimm status======
1>  chl[0] dimm0 0, dimm1 0
1>  chl[1] dimm0 0, dimm1 0
1>  chl[2] dimm0 0, dimm1 0
1>  chl[3] dimm0 0, dimm1 0
1>  chl[4] dimm0 0, dimm1 0
1>  chl[5] dimm0 0, dimm1 0
1>  chl[6] dimm0 0, dimm1 0
1>  chl[7] dimm0 0, dimm1 0
1>==========end==========
1>=====dimm temp params=====
1>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
1>  is_thermal_thro_en  : 1
1>  is_aref_rate_auto   : 1
1>===========end============
2>  chl[5] dimm0 0, dimm1 0
2>  chl[6] dimm0 0, dimm1 0
2>  chl[7] dimm0 0, dimm1 0
2>==========end==========
2>chl[2] registered, dimm mask = 0x1
2>=====dimm temp params=====
2>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
2>  is_thermal_thro_en  : 1
2>  is_aref_rate_auto   : 1
2>===========end============
3>ddr init done, start thermal dimm task
3>======dimm status======
3>  chl[0] dimm0 0, dimm1 0
3>  chl[1] dimm0 0, dimm1 0
3>  chl[2] dimm0 0, dimm1 0
3>  chl[3] dimm0 0, dimm1 0
3>  chl[4] dimm0 0, dimm1 0
3>  chl[5] dimm0 0, dimm1 0
3>  chl[6] dimm0 0, dimm1 0
3>  chl[7] dimm0 0, dimm1 0
3>==========end==========
3>=====dimm temp params=====
3>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
3>  is_thermal_thro_en  : 1
3>  is_aref_rate_auto   : 1
3>===========end============


HSM_LOG:
[00:00:00.010][info] os_mem_system_init default pool done
[00:00:00.016][info] succeed to do thirdparty otpc_pabuk init
[00:00

0>chl[2] max_temp 34'C, aref_rate 0x5 --> 0x4
2>chl[2] max_temp 35'C, aref_rate 0x5 --> 0x4


HSM_LOG:
:00.017][info] succeed to do thirdparty boot_profile_driver init
[00:00:00.017][info] succeed to do thirdparty measure_value_ma



HSM_LOG:
nage_driver init
[00:00:00.018][info] succeed to do thirdparty period_driver init
[00:00:00.018][info]  start loading internal



HSM_LOG:
 task ...
[00:00:00.018][info]  task name is ccm_task
[00:00:00.019][info]  hm_dynamic_loadelf successfully!
[00:00:00.019][i



HSM_LOG:
nfo] internal task[1] task_name=ccm_task load successfully
[00:00:00.020][info]  task name is upgrade_task
[00:00:00.020][info



HSM_LOG:
]  hm_dynamic_loadelf successfully!
[00:00:00.021][info] internal task[2] task_name=upgrade_task load successfully
[00:00:00.0



HSM_LOG:
22][info]  task name is hes_task
[00:00:00.022][info]  hm_dynamic_loadelf successfully!
[00:00:00.023][info] internal task[3] 



HSM_LOG:
task_name=hes_task load successfully
[00:00:00.024][info] created task ccm_task success!
[00:00:00.025][info] created task upg



HSM_LOG:
rade_task success!
[00:00:00.026][info] created task hes_task success!
[00:00:00.026][info] Init start.
[1970-01-01 00:00:00.

[0.01.31.571][ERR]cmd not support! cmd = 0xd


HSM_LOG:
027][HSM][INFO][54] Platform init 0x20250523 0x4e.

[1970-01-01 00:00:00.027][HSM][INFO][197] ccm start.

[1970-01-01 00:00:00



HSM_LOG:
.028][HSM][INFO][86] upgrade task init success.

[1970-01-01 00:00:00.028][HSM][INFO][95] upgrade recv cmd, 0x181.

[1970-01-0



HSM_LOG:
1 00:00:00.029][HSM][INFO][103] upgrade res, 0x3a5aa5a3.

[1970-01-01 00:00:00.030][HSM][INFO][75] hes tee_task_entry.

[1970-



HSM_LOG:
01-01 00:00:00.550][HSM][INFO][44] hes init success.

[00:00:00.550][info] Init over.


[0.01.41.832]TF Heartbeat Start
[0.01.46.460]PCIE INIT DONE.
g_mctpQueueCount(48) > tabCnt(42)
Interrupt 454 register OK
Interrupt 467 register OK
Interrupt 480 register OK
Interrupt 493 register OK
Interrupt 506 register OK
Interrupt 519 register OK
Interrupt 532 register OK
Interrupt 545 register OK
data = 0x0
pmt Init done

Add ep: bdf=5500 eid=9 epCnt=1 eid_alloc=a
Add ep: bdf=300 eid=a epCnt=1 eid_alloc=b
mctp task ok.
[0.02.23.695]Receive ras int[491]
First coalesce handler start
Type2 status = 0x0
Type1 status = 0x4
Found error node[2]
False alarm reporting!
Type0 status = 0x0
ras int[491] end

[0.02.52.456]BIOS POST END.
Create SetReportPcieMmioToBmc ok.
Start SetReportPcieMmioToBmc ok.
slotNum = 0x14
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[0] port:20  pcieSlotCtrl.data (after)0x4801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[1] port:24  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[2] port:26  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[3] port:32  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[4] port:0  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[5] port:24  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[6] port:26  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[7] port:20  pcieSlotCtrl.data (after)0x4801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[8] port:22  pcieSlotCtrl.data (after)0x4801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[9] port:24  pcieSlotCtrl.data (after)0x4801c0.

1>uefi end finish!
1>ipu interface task exit!
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[10] port:26  pcieSlotCtrl.data (after)0x4801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[11] port:32  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[12] port:34  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[13] port:36  pcieSlotCtrl.data (after)0x4801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[14] port:38  pcieSlotCtrl.data (after)0x4801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[15] port:0  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[16] port:12  pcieSlotCtrl.data (after)0x4801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[17] port:14  pcieSlotCtrl.data (after)0x4801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[18] port:16  pcieSlotCtrl.data (after)0x4801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[19] port:18  pcieSlotCtrl.data (after)0x4801c0.

Enter current value process
0>uefi end finish!
0>ipu interface task exit!
0>amu task parameters from uefi ready
1>amu task parameters from uefi ready
2>uefi end finish!
2>ipu interface task exit!
2>amu task parameters from uefi ready
3>uefi end finish!
3>ipu interface task exit!
3>amu task parameters from uefi ready
2>amu task activated
2>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
0>amu task activated
0>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
1>amu task activated
1>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
3>amu task activated
3>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
[0.07.52.455]IpmiCmdReportPcieMMIO start
[0.08.16.046]IpmiCmdReportPcieMMIO end
pool addr          pool size    used size     free size    max free node size   used node num     free node num      UsageWaterLine
---------------    --------     -------       --------     --------------       -------------      ------------      ------------
0x840908e708       0x204c0      0x1a010       0x6240       0x5ad0               0xd9               0x3                0x1a9f0        
 domain[11] volt =  906 mV
2>power domain[13] volt = 1203 mV
2>===============end===============
2>--w&h rd rail:0, 1105, CORE_DVFS_TA
2>--w&h rd rail:1, 900, CORE_DVFS_TA
2>power domain[0] set volt --> 1105 mV success
2>--w&h rd rail:0, 1107, CORE_DVFS_TB
2>--w&h rd rail:1, 1007, CORE_DVFS_TB
2>power domain[2] set volt --> 1107 mV success
2>power domain[3] set volt -->  949 mV success
2>============volt post============
2>power domain[0] volt = 1105 mV
2>power domain[10] volt =  904 mV
2>power domain[1] volt =  804 mV
2>power domain[6] volt = 1103 mV
2>power domain[2] volt = 1107 mV
2>power domain[3] volt =  949 mV
2>power domain[15] volt = 1206 mV
2>power domain[5] volt =  804 mV
2>power domain[11] volt =  904 mV
2>power domain[13] volt = 1205 mV
2>===============end===============
2>die[0] its[0] init done
2>die[0] its[1] init done
2>die[0] its[2] init done
2>die[0] its[3] init done
2>die[0] its[4] init done
2>die[0] its[5] init done
2>die[0] its[6] init done
2>die[0] its[7] init done
2>die[0] its[8] init done
2>die[0] its[9] init done
2>die[1] its[0] init done
2>die[1] its[1] init done
2>die[1] its[2] init done
2>die[1] its[3] init done
2>die[1] its[4] init done
2>die[1] its[5] init done
2>die[1] its[6] init done
2>die[1] its[7] init done
2>die[1] its[8] init done
2>die[1] its[9] init done
2>Totem[0] Core Boot Vol [1105]mv
2>Totem[0] Core Current Vol [1100]mv
2>Totem[1] Core Boot Vol [1107]mv
2>avs:8 volt:864mv
2>core trim freq:2450, avs:9 volt:878mv
2>core trim freq:2450, avs:9 volt:877mv
2>core trim freq:2500, avs:10 volt:891mv
2>core trim freq:2500, avs:10 volt:889mv
2>core trim freq:2550, avs:11 volt:904mv
2>core trim freq:2550, avs:11 volt:902mv
2>core trim freq:2600, avs:12 volt:917mv
2>core trim freq:2600, avs:12 volt:915mv
2>core trim freq:2650, avs:13 volt:930mv
2>core trim freq:2650, avs:13 volt:928mv
2>core trim freq:2700, avs:14 volt:943mv
2>core trim freq:2700, avs:14 volt:941mv
2>core trim freq:2750, avs:15 volt:961mv
2>core trim freq:2750, avs:15 volt:959mv
2>core trim freq:2800, avs:16 volt:979mv
2>core trim freq:2800, avs:16 volt:977mv
2>core trim freq:2850, avs:17 volt:997mv
2>core trim freq:2850, avs:17 volt:995mv
2>core trim freq:2900, avs:18 volt:1016mv
2>core trim freq:2900, avs:18 volt:1014mv
2>core trim freq:2950, avs:19 volt:1033mv
2>core trim freq:2950, avs:19 volt:1031mv
2>core trim freq:3000, avs:20 volt:1051mv
2>core trim freq:3000, avs:20 volt:1049mv
2>core trim freq:3050, avs:21 volt:1064mv
2>core trim freq:3050, avs:21 volt:1062mv
2>core trim freq:3100, avs:22 volt:1077mv
2>core trim freq:3100, avs:22 volt:1075mv
2>acg trim end
2>LDO disabled
2>[TracePoint] type[  0] cmd[  2] data[  3]
2>Interrupt 423 register OK
2>Interrupt 430 register OK
2>[TracePoint] type[  0] cmd[  2] data[  4]
2>
2>cpu 0 entering scheduler
2>[TracePoint] type[  0] cmd[  3] data[  1]
2>add your ipu app init here!
2>IpuInterfaceTaskStart Entry ...
2>ipu interface task wait parameters from uefi...
2>thermal soc task enabled
2>AP Last Time:[0.00.41.050]
2>ThermalDimmStart Entry ...
2>wait ddr init done...
2>power task start...
2>[TracePoint] type[  0] cmd[  3] data[  2]
2>ufs task wait parameters from uefi...
2>AmuTaskStart Entry ... 
2>amu task wait parameters from uefi...
2>ThermalSiwStart Entry ...
2>ThermalSiwTask idle...
2>DemtTaskStart Entry ...
2>[TracePoint] type[  0] cmd[  3] data[  3]
2>demt task wait parameters from uefi...
2>HiBoostTaskStart Entry ...
2>HiBoost task enabled
2>Waiting for UEFI parameters...
2>[TracePoint] type[  0] cmd[  3] data[  4]
2>AgeTaskStart Entry ...
2>age task wait parameters from uefi...
2>[TracePoint] type[  0] cmd[  3] data[  5]
2>uefi parameters ready!
2>UFSProfile[0]
2>PowerPolicy[2] BenchMarkSelection[0]
2>thermal soc task restore underclocking_en=1
2>ppu alert temp div init done
2>ufs task parameters from uefi ready
2>uncore domain[0] freq:2900
2>uncore domain[1] freq:2900
2>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
2>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
2>======sioe status======
2>TA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
2>TA_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
2>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
2>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
2>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
2>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
2>==========end==========
2>sioe init done
2>ufs task enabled
2>--> UFS profile[0]
2>ipu interface task wait ddr init done from uefi...
2>UEFI parameters ready
2>UncoreMaxFreq Set to [2900 MHZ]
2>get TDP from efuse success, value = 307500mw
2>target power set to [307500]mw, brd:[307500]
2>demt task parameters from uefi ready
2>age task parameters from uefi ready
2>age task enabled
]mv
3>[2550]MHZ -> Vol TA[ 895]mv TB[ 900]mv
3>[2600]MHZ -> Vol TA[ 908]mv TB[ 912]mv
3>[2650]MHZ -> Vol TA[ 920]mv TB[ 925]mv
3>[2700]MHZ -> Vol TA[ 933]mv TB[ 938]mv
3>[2750]MHZ -> Vol TA[ 951]mv TB[ 956]mv
3>[2800]MHZ -> Vol TA[ 969]mv TB[ 974]mv
3>[2850]MHZ -> Vol TA[ 987]mv TB[ 992]mv
3>[2900]MHZ -> Vol TA[1005]mv TB[1011]mv
3>[2950]MHZ -> Vol TA[1022]mv TB[1028]mv
3>[3000]MHZ -> Vol TA[1039]mv TB[1045]mv
3>[3050]MHZ -> Vol TA[1053]mv TB[1058]mv
3>[3100]MHZ -> Vol TA[1067]mv TB[1072]mv
3>Uncore VF curve:
3>Uncore [   0]MHZ -> Vol [ 810]mv
3>Uncore [ 100]MHZ -> Vol [ 810]mv
3>Uncore [ 200]MHZ -> Vol [ 810]mv
3>Uncore [ 300]MHZ -> Vol [ 810]mv
3>Uncore [ 400]MHZ -> Vol [ 810]mv
3>Uncore [ 500]MHZ -> Vol [ 810]mv
3>Uncore [ 600]MHZ -> Vol [ 810]mv
3>Uncore [ 700]MHZ -> Vol [ 810]mv
3>Uncore [ 800]MHZ -> Vol [ 810]mv
3>Uncore [ 900]MHZ -> Vol [ 810]mv
3>Uncore [1000]MHZ -> Vol [ 810]mv
3>Uncore [1100]MHZ -> Vol [ 810]mv
3>Uncore [1200]MHZ -> Vol [ 810]mv
3>Uncore [1300]MHZ -> Vol [ 810]mv
3>Uncore [1400]MHZ -> Vol [ 810]mv
3>Uncore [1500]MHZ -> Vol [ 810]mv
3>Uncore [1600]MHZ -> Vol [ 810]mv
3>Uncore [1700]MHZ -> Vol [ 810]mv
3>Uncore [1800]MHZ -> Vol [ 810]mv
3>Uncore [1900]MHZ -> Vol [ 810]mv
3>Uncore [2000]MHZ -> Vol [ 810]mv
3>Uncore [2100]MHZ -> Vol [ 810]mv
3>Uncore [2200]MHZ -> Vol [ 811]mv
3>Uncore [2300]MHZ -> Vol [ 828]mv
3>Uncore [2400]MHZ -> Vol [ 845]mv
3>Uncore [2500]MHZ -> Vol [ 862]mv
3>Uncore [2600]MHZ -> Vol [ 882]mv
3>Uncore [2700]MHZ -> Vol [ 902]mv
3>Uncore [2800]MHZ -> Vol [ 922]mv
3>Uncore [2900]MHZ -> Vol [ 943]mv
3>Uncore [3000]MHZ -> Vol [1100]mv
3>[TracePoint] type[  0] cmd[  1] data[  6]
3>[TracePoint] type[  0] cmd[  1] data[  7]
3>
********Hello Huawei LiteOS********

KpxxxxIPU Firmware Version : V32.70.0
LiteOS Kernel Version : 5.7.0
3>Run on ChipVersion[0] Node[3] Die[0]
3>build time : Feb 05 2026 20:30:00

3>**********************************
3>
main core booting up...
3>start set affinity
3>
mpidr = 0x810c0000
3>sram ecc state: 0x0, sram ecc cnt: 0x0
3>[TracePoint] type[  0] cmd[  2] data[  1]
3>[TracePoint] type[  0] cmd[  2] data[  2]
3>LRDXSD_LOCK_OFFSET = 0x0
3>LRDXSD_ERRIMSK_OFFSET = 0x0
3>LRDXSD_DBG_OTIMSK_OFFSET = 0x0
3>LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
3>LRDXSD_DBG_EN_OFFSET = 0x1
3>======tsensor params======
3>  is_trimmed       : 1
3>  underclocking_en : 1
3>===========end============
3>[ERR]3>die[0] cluster[0] remote & local tsensor init failed
3>[ERR]3>die[0] cluster[3] remote & local tsensor init failed
3>[ERR]3>die[0] cluster[9] remote & local tsensor init failed
3>soc tsensor init done
3>========vrd info from cpld========
3>vrd_id | u64                | pmbus_en | avsbus_en | loop | pmbus_id | pmbus_addr | avs_sw | pmbus_sw | addr_9545 | domain_type | die_mask | reserved
3>  00   | 0x0001000100002017 | 0x1      | 0x1       | 0x1  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0100   | 0x0
3>  01   | 0x000300030000201b | 0x1      | 0x1       | 0x2  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x3         | 0x0300   | 0x0
3>  02   | 0x0000010a00002715 | 0x1      | 0x0       | 0x1  | 0x1      | 0x27       | 0x0    | 0x0      | 0x0       | 0xa         | 0x0001   | 0x0
3>  03   | 0x0000010500002719 | 0x1      | 0x0       | 0x2  | 0x1      | 0x27       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0001   | 0x0
3>  04   | 0x0000020600002a15 | 0x1      | 0x0       | 0x1  | 0x1      | 0x2a       | 0x0    | 0x0      | 0x0       | 0x6         | 0x0002   | 0x0
3>  05   | 0x0000010600002a19 | 0x1      | 0x0       | 0x2  | 0x1      | 0x2a       | 0x0    | 0x0      | 0x0       | 0x6         | 0x0001   | 0x0
3>  06   | 0x0000020a00002f15 | 0x1      | 0x0       | 0x1  | 0x1      | 0x2f       | 0x0    | 0x0      | 0x0       | 0xa         | 0x0002   | 0x0
3>  07   | 0x0002000100002027 | 0x1      | 0x1       | 0x1  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0200   | 0x0
3>  08   | 0x000300020000202b | 0x1      | 0x1       | 0x2  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x2         | 0x0300   | 0x0
3>  09   | 0x0000030500002725 | 0x1      | 0x0       | 0x1  | 0x2      | 0x27       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0003   | 0x0
3>  10   | 0x0003000400002729 | 0x1      | 0x0       | 0x2  | 0x2      | 0x27       | 0x0    | 0x0      | 0x0       | 0x4         | 0x0300   | 0x0
3>================end===============
3>=============vrd info=============
3>power domain num: 11
3>power domain[00] id:0 | CORE_DVFS_TA       | PMBus NA | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
3>power domain[01] id:1 | DDR_VDD            | PMBus NA | cap:0x3 | rail:1 | addr:0x20 | def_volt: 800 mV | min_volt: 760 mV | max_volt: 840 mV
3>power domain[02] id:14 | NA_AVDD_SDS        | PMBus NA | cap:0x1 | rail:0 | addr:0x27 | def_volt:1200 mV | min_volt:1164 mV | max_volt:1236 mV
3>power domain[03] id:4 | IO_DVDD_NA         | PMBus NA | cap:0x1 | rail:1 | addr:0x27 | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
3>power domain[04] id:11 | IO_DVDD09_NB       | PMBus NA | cap:0x1 | rail:0 | addr:0x2a | def_volt: 900 mV | min_volt: 700 mV | max_volt: 900 mV
3>power domain[05] id:10 | IO_DVDD09_NA       | PMBus NA | cap:0x1 | rail:1 | addr:0x2a | def_volt: 900 mV | min_volt: 700 mV | max_volt: 900 mV
3>power domain[06] id:16 | NB_AVDD_SDS        | PMBus NA | cap:0x1 | rail:0 | addr:0x2f | def_volt:1200 mV | min_volt:1164 mV | max_volt:1236 mV
3>power domain[07] id:2 | CORE_DVFS_TB       | PMBus NB | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
3>power domain[08] id:3 | UNCORE_DVFS        | PMBus NB | cap:0x3 | rail:1 | addr:0x20 | def_volt: 943 mV | min_volt: 750 mV | max_volt:1100 mV
3>power domain[09] id:12 | IO_DVDD_NANB       | PMBus NB | cap:0x1 | rail:0 | addr:0x27 | def_volt: 800 mV | min_volt: 750 mV | max_volt: 900 mV
3>power domain[10] id:6 | DDR_VDDQ           | PMBus NB | cap:0x1 | rail:1 | addr:0x27 | def_volt:1100 mV | min_volt:1000 mV | max_volt:1200 mV
3>================end===============
3>pmbus[0] init done
3>pmbus[1] init done
3>power domain[0] CORE_DVFS_TA       | NA PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
3>power domain[1] DDR_VDD            | NA PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 800 mV | pmu:MP2882
3>power domain[14] NA_AVDD_SDS        | NA PMBus        | rail:0 | addr:0x27 | def_volt:1200 mV | pmu:MP2882
3>power domain[4] IO_DVDD_NA         | NA PMBus        | rail:1 | addr:0x27 | def_volt: 800 mV | pmu:MP2882
3>power domain[11] IO_DVDD09_NB       | NA PMBus        | rail:0 | addr:0x2a | def_volt: 900 mV | pmu:MP2882
3>power domain[10] IO_DVDD09_NA       | NA PMBus        | rail:1 | addr:0x2a | def_volt: 900 mV | pmu:MP2882
3>power domain[16] NB_AVDD_SDS        | NA PMBus        | rail:0 | addr:0x2f | def_volt:1200 mV | pmu:MP2882
3>power domain[2] CORE_DVFS_TB       | NB PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
3>power domain[3] UNCORE_DVFS        | NB PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 943 mV | pmu:MP2882
3>power domain[12] IO_DVDD_NANB       | NB PMBus        | rail:0 | addr:0x27 | def_volt: 800 mV | pmu:MP2882
3>power domain[6] DDR_VDDQ           | NB PMBus        | rail:1 | addr:0x27 | def_volt:1100 mV | pmu:MP2882
3>power domain[0] CORE_DVFS_TA       is transferred to AVSBus mode
3>power domain[1] DDR_VDD            is transferred to AVSBus mode
3>power domain[2] CORE_DVFS_TB       is transferred to AVSBus mode
3>power domain[3] UNCORE_DVFS        is transferred to AVSBus mode
3>avsbus resync success
3>avsbus[0] init done
3>avsbus resync success
3>avsbus[1] init done
3>============volt boot============
3>power domain[0] volt = 1101 mV
3>power domain[1] volt =  804 mV
3>power domain[14] volt = 1201 mV
3>power domain[4] volt =  802 mV
3>power domain[11] volt =  904 mV
3>power domain[10] volt =  904 mV
3>power domain[16] volt = 1205 mV
3>power domain[2] volt = 1103 mV
3>power domain[3] volt = 1007 mV
3>power domain[12] volt =  806 mV
3>power domain[6] volt = 1105 mV
3>===============end===============
3>--w&h rd rail:0, 1103, CORE_DVFS_TA
3>--w&h rd rail:1, 800, CORE_DVFS_TA
3>power domain[0] set volt --> 1103 mV success
3>--w&h rd rail:0, 1103, CORE_DVFS_TB
3>--w&h rd rail:1, 1007, CORE_DVFS_TB
3>power domain[2] set volt --> 1101 mV success
3>power domain[3] set volt -->  949 mV success
3>============volt post============
3>power domain[0] volt = 1103 mV
3>power domain[1] volt =  802 mV
3>power domain[14] volt = 1203 mV
3>power domain[4] volt =  802 mV
3>power domain[11] volt =  904 mV
3>power domain[10] volt =  902 mV
3>power domain[16] volt = 1203 mV
3>power domain[2] volt = 1103 mV
3>power domain[3] volt =  947 mV
3>power domain[12] volt =  804 mV
3>power domain[6] volt = 1105 mV
3>===============end===============
3>the power sensor : manu id = 2peak, die id = TPA626
3>power sensor[0] init success
3>die[0] its[0] init done
3>die[0] its[1] init done
3>die[0] its[2] init done
3>die[0] its[3] init done
3>die[0] its[4] init done
3>die[0] its[5] init done
3>die[0] its[6] init done
3>die[0] its[7] init done
3>die[0] its[8] init done
3>die[0] its[9] init done
3>die[1] its[0] init done
3>die[1] its[1] init done
3>die[1] its[2] init done
3>die[1] its[3] init done
3>die[1] its[4] init done
3>die[1] its[5] init done
3>die[1] its[6] init done
3>die[1] its[7] init done
3>die[1] its[8] init done
3>die[1] its[9] init done
3>Totem[0] Core Boot Vol [1103]mv
3>Totem[0] Core Current Vol [1100]mv
3>Totem[1] Core Boot Vol [1103]mv
3>Totem[1] Core Current Vol [1100]mv
3>NA 1620V1a0
3>NB 1620V1a0
3>GetCoreBaseFreq [2500000KHZ]
3>GetCoreTurboFreq [2500000KHZ]
3>GetCustomClusterNum [10]
3>Ipu ACG Training Done!
3>AP Last Time:[0.00.01.736]
3>wait UEFI pll init...
3>done
3>acg trim start
3>core trim freq:2000, avs:0 volt:810mv
3>core trim freq:2000, avs:0 volt:810mv
3>core trim freq:2050, avs:1 volt:810mv
3>core trim freq:2050, avs:1 volt:810mv
3>core trim freq:2100, avs:2 volt:810mv
3>core trim freq:2100, avs:2 volt:810mv
3>core trim freq:2150, avs:3 volt:810mv
3>core trim freq:2150, avs:3 volt:810mv
3>core trim freq:2200, avs:4 volt:810mv
3>core trim freq:2200, avs:4 volt:811mv
3>core trim freq:2250, avs:5 volt:820mv
3>core trim freq:2250, avs:5 volt:824mv
3>core trim freq:2300, avs:6 volt:833mv
3>core trim freq:2300, avs:6 volt:836mv
3>core trim freq:2350, avs:7 volt:845mv
3>core trim freq:2350, avs:7 volt:849mv
3>core trim freq:2400, avs:8 volt:858mv
3>core trim freq:2400, avs:8 volt:862mv
3>core trim freq:2450, avs:9 volt:870mv
3>core trim freq:2450, avs:9 volt:874mv
3>core trim freq:2500, avs:10 volt:883mv
3>core trim freq:2500, avs:10 volt:887mv
3>core trim freq:2550, avs:11 volt:895mv
3>core trim freq:2550, avs:11 volt:900mv
3>core trim freq:2600, avs:12 volt:908mv
3>core trim freq:2600, avs:12 volt:912mv
3>core trim freq:2650, avs:13 volt:920mv
3>core trim freq:2650, avs:13 volt:925mv
3>core trim freq:2700, avs:14 volt:933mv
3>core trim freq:2700, avs:14 volt:938mv
3>core trim freq:2750, avs:15 volt:951mv
3>core trim freq:2750, avs:15 volt:956mv
3>core trim freq:2800, avs:16 volt:969mv
3>core trim freq:2800, avs:16 volt:974mv
3>core trim freq:2850, avs:17 volt:987mv
3>core trim freq:2850, avs:17 volt:992mv
3>core trim freq:2900, avs:18 volt:1005mv
3>core trim freq:2900, avs:18 volt:1011mv
3>core trim freq:2950, avs:19 volt:1022mv
3>core trim freq:2950, avs:19 volt:1028mv
3>core trim freq:3000, avs:20 volt:1039mv
3>core trim freq:3000, avs:20 volt:1045mv
3>core trim freq:3050, avs:21 volt:1053mv
3>core trim freq:3050, avs:21 volt:1058mv
3>core trim freq:3100, avs:22 volt:1067mv
3>core trim freq:3100, avs:22 volt:1072mv
3>acg trim end
3>LDO disabled
3>[TracePoint] type[  0] cmd[  2] data[  3]
3>Interrupt 423 register OK
3>Interrupt 430 register OK
3>[TracePoint] type[  0] cmd[  2] data[  4]
3>
3>cpu 0 entering scheduler
3>[TracePoint] type[  0] cmd[  3] data[  1]
3>add your ipu app init here!
3>IpuInterfaceTaskStart Entry ...
3>ipu interface task wait parameters from uefi...
3>thermal soc task enabled
3>AP Last Time:[0.00.41.067]
3>ThermalDimmStart Entry ...
3>wait ddr init done...
3>power task start...
3>[TracePoint] type[  0] cmd[  3] data[  2]
3>ufs task wait parameters from uefi...
3>AmuTaskStart Entry ... 
3>amu task wait parameters from uefi...
3>ThermalSiwStart Entry ...
3>ThermalSiwTask idle...
3>DemtTaskStart Entry ...
3>[TracePoint] type[  0] cmd[  3] data[  3]
3>HiBoostTaskStart Entry ...
3>HiBoost task enabled
3>Waiting for UEFI parameters...
3>[TracePoint] type[  0] cmd[  3] data[  4]
3>demt task wait parameters from uefi...
3>AgeTaskStart Entry ...
3>age task wait parameters from uefi...
3>[TracePoint] type[  0] cmd[  3] data[  5]
3>uefi parameters ready!
3>UFSProfile[0]
3>PowerPolicy[2] BenchMarkSelection[0]
3>ipu interface task wait ddr init done from uefi...
3>ufs task parameters from uefi ready
3>uncore domain[0] freq:2900
3>uncore domain[1] freq:2900
3>thermal soc task restore underclocking_en=1
3>ppu alert temp div init done
3>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
3>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
3>======sioe status======
3>TA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
3>TA_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
3>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
3>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
3>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
3>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
3>==========end==========
3>sioe init done
3>ufs task enabled
3>--> UFS profile[0]
3>UEFI parameters ready
3>UncoreMaxFreq Set to [2900 MHZ]
3>get TDP from efuse success, value = 307500mw
3>target power set to [307500]mw, brd:[307500]
3>age task parameters from uefi ready
3>age task enabled
3>demt task parameters from uefi ready
0>uefi ddr init finish!
0>ipu interface task wait uefi end done from uefi...
0>ddr init done, start thermal dimm task
0>======dimm status======
0>  chl[0] dimm0 0, dimm1 0
0>  chl[1] dimm0 0, dimm1 0
0>  chl[2] dimm0 2, dimm1 0
0>  chl[3] dimm0 0, dimm1 0
0>  chl[4] dimm0 0, dimm1 0
0>  chl[5] dimm0 0, dimm1 0
0>  chl[6] dimm0 0, dimm1 0
0>  chl[7] dimm0 0, dimm1 0
0>==========end==========
0>chl[2] registered, dimm mask = 0x1
0>=====dimm temp params=====
0>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
0>  is_thermal_thro_en  : 1
0>  is_aref_rate_auto   : 1
0>===========end============
1>uefi ddr init finish!
1>ipu interface task wait uefi end done from uefi...
1>ddr init done, start thermal dimm task
1>======dimm status======
1>  chl[0] dimm0 0, dimm1 0
1>  chl[1] dimm0 0, dimm1 0
1>  chl[2] dimm0 0, dimm1 0
1>  chl[3] dimm0 0, dimm1 0
1>  chl[4] dimm0 0, dimm1 0
1>  chl[5] dimm0 0, dimm1 0
1>  chl[6] dimm0 0, dimm1 0
1>  chl[7] dimm0 0, dimm1 0
1>==========end==========
1>=====dimm temp params=====
1>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
1>  is_thermal_thro_en  : 1
1>  is_aref_rate_auto   : 1
1>===========end============
2>uefi ddr init finish!
2>ipu interface task wait uefi end done from uefi...
2>ddr init done, start thermal dimm task
2>======dimm status======
2>  chl[0] dimm0 0, dimm1 0
2>  chl[1] dimm0 0, dimm1 0
2>  chl[2] dimm0 2, dimm1 0
2>  chl[3] dimm0 0, dimm1 0
2>  chl[4] dimm0 0, dimm1 0
2>  chl[5] dimm0 0, dimm1 0
2>  chl[6] dimm0 0, dimm1 0
2>  chl[7] dimm0 0, dimm1 0
2>==========end==========
2>chl[2] registered, dimm mask = 0x1
2>=====dimm temp params=====
2>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
2>  is_thermal_thro_en  : 1
2>  is_aref_rate_auto   : 1
2>===========end============
3>uefi ddr init finish!
3>ipu interface task wait uefi end done from uefi...
3>ddr init done, start thermal dimm task
3>======dimm status======
3>  chl[0] dimm0 0, dimm1 0
3>  chl[1] dimm0 0, dimm1 0
3>  chl[2] dimm0 0, dimm1 0
3>  chl[3] dimm0 0, dimm1 0
3>  chl[4] dimm0 0, dimm1 0
3>  chl[5] dimm0 0, dimm1 0
3>  chl[6] dimm0 0, dimm1 0
3>  chl[7] dimm0 0, dimm1 0
3>==========end==========
3>=====dimm temp params=====
3>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
3>  is_thermal_thro_en  : 1
3>  is_aref_rate_auto   : 1
3>===========end============
[0.01.09.720]DDR Rreserved for IMU: len = 3e00000
[LOG]head = 0x0, tail = 0x4f35, logSize = 0x4f35
copy registry.json file success
Set component all release version to sram end.
ipcMsgSend success
[0.01.09.762]starting ras Init
nodeId = 0, dieId = 0, isSasExist = 0.
nodeId = 0, dieId = 2, isSasExist = 0.
nodeId = 1, dieId = 0, isSasExist = 0.
nodeId = 1, dieId = 2, isSasExist = 0.
nodeId = 2, dieId = 0, isSasExist = 0.
nodeId = 2, dieId = 2, isSasExist = 0.
nodeId = 3, dieId = 0, isSasExist = 0.
nodeId = 3, dieId = 2, isSasExist = 0.
Mce Table head exist!
RasIntRegister init 452 
RasIntRegister init 453 
RasIntRegister init 64 
RasIntRegister init 65 
RasIntRegister init 465 
RasIntRegister init 466 
RasIntRegister init 86 
RasIntRegister init 87 
RasIntRegister init 478 
RasIntRegister init 479 
RasIntRegister init 108 
RasIntRegister init 109 
RasIntRegister init 491 
RasIntRegister init 492 
RasIntRegister init 130 
RasIntRegister init 131 
RasIntRegister init 504 
RasIntRegister init 505 
RasIntRegister init 152 
RasIntRegister init 153 
RasIntRegister init 517 
RasIntRegister init 518 
RasIntRegister init 174 
RasIntRegister init 175 
RasIntRegister init 530 
RasIntRegister init 531 
RasIntRegister init 196 
RasIntRegister init 197 
RasIntRegister init 543 
RasIntRegister init 544 
RasIntRegister init 218 
RasIntRegister init 219 
RasIntRegister init 76 
RasIntRegister init 98 
RasIntRegister init 120 
RasIntRegister init 142 
RasIntRegister init 164 
RasIntRegister init 186 
RasIntRegister init 208 
RasIntRegister init 230 
[0.01.09.883]starting ras end


HSM_LOG:
[00:00:00.000][info] succeed to do thirdparty dfx_pabuk init
[00:00:00.000][info] succeed to do thirdparty crypto_driver init




HSM_LOG:
[00:00:00.010][info] os_mem_system_init default pool done
[00:00:00.016][info] succeed to do thirdparty otpc_pabuk init
[00:00

0>chl[2] max_temp 33'C, aref_rate 0x5 --> 0x4
2>chl[2] max_temp 33'C, aref_rate 0x5 --> 0x4


HSM_LOG:
:00.017][info] succeed to do thirdparty boot_profile_driver init
[00:00:00.017][info] succeed to do thirdparty measure_value_ma



HSM_LOG:
nage_driver init
[00:00:00.018][info] succeed to do thirdparty period_driver init
[00:00:00.018][info]  start loading internal



HSM_LOG:
 task ...
[00:00:00.018][info]  task name is ccm_task
[00:00:00.019][info]  hm_dynamic_loadelf successfully!
[00:00:00.019][i



HSM_LOG:
nfo] internal task[1] task_name=ccm_task load successfully
[00:00:00.020][info]  task name is upgrade_task
[00:00:00.020][info



HSM_LOG:
]  hm_dynamic_loadelf successfully!
[00:00:00.021][info] internal task[2] task_name=upgrade_task load successfully
[00:00:00.0



HSM_LOG:
22][info]  task name is hes_task
[00:00:00.022][info]  hm_dynamic_loadelf successfully!
[00:00:00.023][info] internal task[3] 



HSM_LOG:
task_name=hes_task load successfully
[00:00:00.024][info] created task ccm_task success!
[00:00:00.025][info] created task upg



HSM_LOG:
rade_task success!
[00:00:00.026][info] created task hes_task success!
[00:00:00.026][info] Init start.
[1970-01-01 00:00:00.

[0.01.30.525][ERR]cmd not support! cmd = 0xd


HSM_LOG:
027][HSM][INFO][54] Platform init 0x20250523 0x4e.

[1970-01-01 00:00:00.027][HSM][INFO][197] ccm start.

[1970-01-01 00:00:00



HSM_LOG:
.028][HSM][INFO][86] upgrade task init success.

[1970-01-01 00:00:00.028][HSM][INFO][95] upgrade recv cmd, 0x181.

[1970-01-0



HSM_LOG:
1 00:00:00.029][HSM][INFO][103] upgrade res, 0x3a5aa5a3.

[1970-01-01 00:00:00.030][HSM][INFO][75] hes tee_task_entry.

[1970-



HSM_LOG:
01-01 00:00:00.554][HSM][INFO][44] hes init success.

[00:00:00.554][info] Init over.


[0.01.39.406]TF Heartbeat Start
[0.01.44.483]PCIE INIT DONE.
g_mctpQueueCount(48) > tabCnt(42)
Interrupt 454 register OK
Interrupt 467 register OK
Interrupt 480 register OK
Interrupt 493 register OK
Interrupt 506 register OK
Interrupt 519 register OK
Interrupt 532 register OK
Interrupt 545 register OK
data = 0x0
pmt Init done

Add ep: bdf=5500 eid=9 epCnt=1 eid_alloc=a
Add ep: bdf=300 eid=a epCnt=1 eid_alloc=b
mctp task ok.
[0.02.20.321]Receive ras int[491]
First coalesce handler start
Type2 status = 0x0
Type1 status = 0x4
Found error node[2]
False alarm reporting!
Type0 status = 0x0
ras int[491] end

[0.02.48.545]BIOS POST END.
Create SetReportPcieMmioToBmc ok.
Start SetReportPcieMmioToBmc ok.
slotNum = 0xb
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[0] port:24  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[1] port:26  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[2] port:32  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[3] port:24  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[4] port:26  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[5] port:32  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[6] port:34  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[7] port:12  pcieSlotCtrl.data (after)0x4801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[8] port:14  pcieSlotCtrl.data (after)0x4801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[9] port:16  pcieSlotCtrl.data (after)0x4801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[10] port:18  pcieSlotCtrl.data (after)0x4801c0.

Enter current value process
0>uefi end finish!
0>ipu interface task exit!
0>amu task parameters from uefi ready
1>uefi end finish!
1>ipu interface task exit!
1>amu task parameters from uefi ready
2>uefi end finish!
2>ipu interface task exit!
2>amu task parameters from uefi ready
3>uefi end finish!
3>ipu interface task exit!
3>amu task parameters from uefi ready
0>amu task activated
0>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
1>amu task activated
1>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
2>amu task activated
2>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
3>amu task activated
3>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
ORE_DVFS_TB       | NB PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
2>power domain[3] UNCORE_DVFS        | NB PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 943 mV | pmu:MP2882
2>power domain[15] NB_AVDD_SDS        | 150, avs:3 volt:810mv
2>core trim freq:2200, avs:4 volt:814mv
2>core trim freq:2200, avs:4 volt:813mv
2>core trim freq:2250, avs:5 volt:827mv
2>core trim freq:2250, avs:5 volt:825mv
2>core trim freq:2300, avs:6 volt:840mv
2>core trim fre -> Vol TA[ 810]mv TB[ 810]mv
3>[1400]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1450]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1500]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1550]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1600]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>TB[ 810]mv
3>[2050]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2100]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2150]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2200]MHZ -> Vol TA[ 810]mv TB[ 811]mv
3>[2250]MHZ -> Vol TA[ 820]mv TB[ 824]mv
3>[2300]MHZ -> Vol TA> Vol TA[ 845]mv TB[ 849]mv
3>[2400]MHZ -> Vol TA[ 858]mv TB[ 862]mv
3>[2450]MHZ -> Vol TA[ 870]mv TB[ 874]mv
3>[2500]MHZ -> Vol TA[ 883]mv TB[ 887]mv
3>[2550]MHZ -> Vol TA[ 895]mv TB[ 900]mv
3>[2600]MHZ -> Vol TA[ 908]mv TB[ 912]mv
3>[2]mv TB[ 938]mv
3>[2750]MHZ -> Vol TA[ 951]mv TB[ 956]mv
3>[2800]MHZ -> Vol TA[ 969]mv TB[ 974]mv
3>[2850]MHZ -> Vol TA[ 987]mv TB[ 992]mv
3>[2900]MHZ -> Vol TA[1005]mv TB[1011]mv
3>[2950]MHZ -> Vol TA[1022]mv TB[1028]mv
3>[3000]MHZ -> VoHZ -> Vol TA[1053]mv TB[1058]mv
3>[3100]MHZ -> Vol TA[1067]mv TB[1072]mv
3>Uncore VF curve:
3>Uncore [   0]MHZ -> Vol [ 810]mv
3>Uncore [ 100]MHZ -> Vol [ 810]mv
3>Uncore [ 200]MHZ -> Vol [ 810]mv
3>Uncore [ 300]MHZ -> Vol [ 810]mv
3>Uncncore [ 500]MHZ -> Vol [ 810]mv
3>Uncore [ 600]MHZ -> Vol [ 810]mv
3>Uncore [ 700]MHZ -> Vol [ 810]mv
3>Uncore [ 800]MHZ -> Vol [ 810]mv
3>Uncore [ 900]MHZ -> Vol [ 810]mv
3>Uncore [1000]MHZ -> Vol [ 810]mv
3>Uncore [1100]MHZ -> Vol [ 81ol [ 810]mv
3>Uncore [1400]MHZ -> Vol [ 810]mv
3>Uncore [1500]MHZ -> Vol [ 810]mv
3>Uncore [1600]MHZ -> Vol [ 810]mv
3>Uncore [1700]MHZ -> Vol [ 810]mv
3>Uncore [1800]MHZ -> Vol [ 810]mv
3>Uncore [1900]MHZ -> Vol [ 810]mv
3>Uncore [2000]0]MHZ -> Vol [ 810]mv
3>Uncore [2200]MHZ -> Vol [ 811]mv
3>Uncore [2300]MHZ -> Vol [ 828]mv
3>Uncore [2400]MHZ -> Vol [ 845]mv
3>Uncore [2500]MHZ -> Vol [ 862]mv
3>Uncore [2600]MHZ -> Vol [ 882]mv
3>Uncore [2700]MHZ -> Vol [ 902]mv
3>Uncncore [2900]MHZ -> Vol [ 943]mv
3>Uncore [3000]MHZ -> Vol [1100]mv
3>[TracePoint] type[  0] cmd[  1] data[  6]
3>[TracePoint] type[  0] cmd[  1] data[  7]
3>
********Hello Huawei LiteOS********

KpxxxxIPU Firmware Version : V32.70.0
Li[0]
3>build time : Feb 05 2026 20:30:00

3>**********************************
3>
main core booting up...
3>start set affinity
3>
mpidr = 0x810c0000
3>sram ecc state: 0x0, sram ecc cnt: 0x0
3>[TracePoint] type[  0] cmd[  2] data[  1]
3>te & local tsensor init failed
3>[ERR]3>die[0] cluster[2] remote & local tsensor init failed
3>soc tsensor init done
3>========vrd info from cpld========
3>vrd_id | u64                | pmbus_en | avsbus_en | loop | pmbus_id | pmbus_addr | avs_sw | pmbus_sw | addr_9545 | domain_type | die_mask | reserved
3>  00   | 0x0001000100002017 | 0x1      | 0x1       | 0x1  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0100   | 0x0
3>  01   | 0x000300030000201b | 0x1      | 0x1       | 0x2  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x3         | 0x0300   | 0x0
3>  02   | 0x0000010a00002715 | 0x1      | 0x0       | 0x1  | 0x1      | 0x27       | 0x0    | 0x0      | 0x0       | 0xa         | 0x0001   | 0x0
3>  03   | 0x0000010500002719 | 0x1      | 0x0       | 0x2  | 0x1      | 0x27       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0001   | 0x0
3>  04   | 0x0000020600002a15 | 0x1      | 0x0       | 0x1  | 0x1      | 0x2a       | 0x0    | 0x0      | 0x0       | 0x6         | 0x0002   | 0x0
3>  05   | 0x0000010600002a19 | 0x1      | 0x0       | 0x2  | 0x1      | 0x2a       | 0x0    | 0x0      | 0x0       | 0x6         | 0x0001   | 0x0
3>  06   | 0x0000020a00002f15 | 0x1      | 0x0       | 0x1  | 0x1      | 0x2f       | 0x0    | 0x0      | 0x0       | 0xa         | 0x0002   | 0x0
3>  07   | 0x0002000100002027 | 0x1      | 0x1       | 0x1  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0200   | 0x0
3>  08   | 0x000300020000202b | 0x1      | 0x1       | 0x2  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x2         | 0x0300   | 0x0
3>  09   | 0x0000030500002725 | 0x1      | 0x0       | 0x1  | 0x2      | 0x27       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0003   | 0x0
3>  10   | 0x0003000400002729 | 0x1      | 0x0       | 0x2  | 0x2      | 0x27       | 0x0    | 0x0      | 0x0       | 0x4         | 0x0300   | 0x0
3>================end===============
3>=============vrd info=============
3>power domain num: 11
3>power domain[00] id:0 | CORE_DVFS_TA       | PMBus NA | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
3>power domain[01] id:1 | DDR_VDD            | PMBus NA | cap:0x3 | rail:1 | addr:0x20 | def_volt: 800 mV | min_volt: 760 mV | max_volt: 840 mV
3>power domain[02] id:14 | NA_AVDD_SDS        | PMBus NA | cap:0x1 | rail:0 | addr:0x27 | def_volt:1200 mV | min_volt:1164 mV | max_volt:1236 mV
3>power domain[03] id:4 | IO_DVDD_NA         | PMBus NA | cap:0x1 | rail:1 | addr:0x27 | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
3>power domain[04] id:11 | IO_DVDD09_NB       | PMBus NA | cap:0x1 | rail:0 | addr:0x2a | def_volt: 900 mV | min_volt: 700 mV | max_volt: 900 mV
3>power domain[05] id:10 | IO_DVDD09_NA       | PMBus NA | cap:0x1 | rail:1 | addr:0x2a | def_volt: 900 mV | min_volt: 700 mV | max_volt: 900 mV
3>power domain[06] id:16 | NB_AVDD_SDS        | PMBus NA | cap:0x1 | rail:0 | addr:0x2f | def_volt:1200 mV | min_volt:1164 mV | max_volt:1236 mV
3>power domain[07] id:2 | CORE_DVFS_TB       | PMBus NB | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
3>power domain[08] id:3 | UNCORE_DVFS        | PMBus NB | cap:0x3 | rail:1 | addr:0x20 | def_volt: 943 mV | min_volt: 750 mV | max_volt:1100 mV
3>power domain[09] id:12 | IO_DVDD_NANB       | PMBus NB | cap:0x1 | rail:0 | addr:0x27 | def_volt: 800 mV | min_volt: 750 mV | max_volt: 900 mV
3>power domain[10] id:6 | DDR_VDDQ           | PMBus NB | cap:0x1 | rail:1 | addr:0x27 | def_volt:1100 mV | min_volt:1000 mV | max_volt:1200 mV
3>================end===============
3>pmbus[0] init done
3>pmbus[1] init done
3>power domain[0] CORE_DVFS_TA       | NA PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
3>power domain[1] DDR_VDD            | NA PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 800 mV | pmu:MP2882
3>power domain[14] NA_AVDD_SDS        | NA PMBus        | rail:0 | addr:0x27 | def_volt:1200 mV | pmu:MP2882
3>power domain[4] IO_DVDD_NA         | NA PMBus        | rail:1 | addr:0x27 | def_volt: 800 mV | pmu:MP2882
3>power domain[11] IO_DVDD09_NB       | NA PMBus        | rail:0 | addr:0x2a | def_volt: 900 mV | pmu:MP2882
3>power domain[10] IO_DVDD09_NA       | NA PMBus        | rail:1 | addr:0x2a | def_volt: 900 mV | pmu:MP2882
3>power domain[16] NB_AVDD_SDS        | NA PMBus        | rail:0 | addr:0x2f | def_volt:1200 mV | pmu:MP2882
3>power domain[2] CORE_DVFS_TB       | NB PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
3>power domain[3] UNCORE_DVFS        | NB PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 943 mV | pmu:MP2882
3>power domain[12] IO_DVDD_NANB       | NB PMBus        | rail:0 | addr:0x27 | def_volt: 800 mV | pmu:MP2882
3>power domain[6] DDR_VDDQ           | NB PMBus        | rail:1 | addr:0x27 | def_volt:1100 mV | pmu:MP2882
3>power domain[0] CORE_DVFS_TA       is transferred to AVSBus mode
3>power domain[1] DDR_VDD            is transferred to AVSBus mode
3>power domain[2] CORE_DVFS_TB       is transferred to AVSBus mode
3>power domain[3] UNCORE_DVFS        is transferred to AVSBus mode
3>avsbus resync success
3>avsbus[0] init done
3>avsbus resync success
3>avsbus[1] init done
3>============volt boot============
3>power domain[0] volt = 1103 mV
3>power domain[1] volt =  804 mV
3>power domain[14] volt = 1201 mV
3>power domain[4] volt =  802 mV
3>power domain[11] volt =  904 mV
3>power domain[10] volt =  904 mV
3>power domain[16] volt = 1203 mV
3>power domain[2] volt = 1103 mV
3>power domain[3] volt = 1007 mV
3>power domain[12] volt =  804 mV
3>power domain[6] volt = 1105 mV
3>===============end===============
3>--w&h rd rail:0, 1103, CORE_DVFS_TA
3>--w&h rd rail:1, 800, CORE_DVFS_TA
3>power domain[0] set volt --> 1103 mV success
3>--w&h rd rail:0, 1103, CORE_DVFS_TB
3>--w&h rd rail:1, 1007, CORE_DVFS_TB
3>power domain[2] set volt --> 1103 mV success
3>power domain[3] set volt -->  949 mV success
3>============volt post============
3>power domain[0] volt = 1103 mV
3>power domain[1] volt =  804 mV
3>power domain[14] volt = 1201 mV
3>power domain[4] volt =  802 mV
3>power domain[11] volt =  904 mV
3>power domain[10] volt =  904 mV
3>power domain[16] volt = 1205 mV
3>power domain[2] volt = 1103 mV
3>power domain[3] volt =  949 mV
3>power domain[12] volt =  804 mV
3>power domain[6] volt = 1105 mV
3>===============end===============
3>the power sensor : manu id = 2peak, die id = TPA626
3>power sensor[0] init success
3>die[0] its[0] init done
3>die[0] its[1] init done
3>die[0] its[2] init done
3>die[0] its[3] init done
3>die[0] its[4] init done
3>die[0] its[5] init done
3>die[0] its[6] init done
3>die[0] its[7] init done
3>die[0] its[8] init done
3>die[0] its[9] init done
3>die[1] its[0] init done
3>die[1] its[1] init done
3>die[1] its[2] init done
3>die[1] its[3] init done
3>die[1] its[4] init done
3>die[1] its[5] init done
3>die[1] its[6] init done
3>die[1] its[7] init done
3>die[1] its[8] init done
3>die[1] its[9] init done
3>Totem[0] Core Boot Vol [1103]mv
3>Totem[0] Core Current Vol [1100]mv
3>Totem[1] Core Boot Vol [1103]mv
3>Totem[1] Core Current Vol [1100]mv
3>NA 1620V1a0
3>NB 1620V1a0
3>GetCoreBaseFreq [2500000KHZ]
3>GetCoreTurboFreq [2500000KHZ]
3>GetCustomClusterNum [10]
3>Ipu ACG Training Done!
3>AP Last Time:[0.00.01.732]
3>wait UEFI pll init...
3>done
3>acg trim start
3>core trim freq:2000, avs:0 volt:810mv
3>core trim freq:2000, avs:0 volt:810mv
3>core trim freq:2050, avs:1 volt:810mv
3>core trim freq:2050, avs:1 volt:810mv
3>core trim freq:2100, avs:2 volt:810mv
3>core trim freq:2100, avs:2 volt:810mv
3>core trim freq:2150, avs:3 volt:810mv
3>core trim freq:2150, avs:3 volt:810mv
3>core trim freq:2200, avs:4 volt:810mv
3>core trim freq:2200, avs:4 volt:811mv
3>core trim freq:2250, avs:5 volt:820mv
3>core trim freq:2250, avs:5 volt:824mv
3>core trim freq:2300, avs:6 volt:833mv
3>core trim freq:2300, avs:6 volt:836mv
3>core trim freq:2350, avs:7 volt:845mv
3>core trim freq:2350, avs:7 volt:849mv
3>core trim freq:2400, avs:8 volt:858mv
3>core trim freq:2400, avs:8 volt:862mv
3>core trim freq:2450, avs:9 volt:870mv
3>core trim freq:2450, avs:9 volt:874mv
3>core trim freq:2500, avs:10 volt:883mv
3>core trim freq:2500, avs:10 volt:887mv
3>core trim freq:2550, avs:11 volt:895mv
3>core trim freq:2550, avs:11 volt:900mv
3>core trim freq:2600, avs:12 volt:908mv
3>core trim freq:2600, avs:12 volt:912mv
3>core trim freq:2650, avs:13 volt:920mv
3>core trim freq:2650, avs:13 volt:925mv
3>core trim freq:2700, avs:14 volt:933mv
3>core trim freq:2700, avs:14 volt:938mv
3>core trim freq:2750, avs:15 volt:951mv
3>core trim freq:2750, avs:15 volt:956mv
3>core trim freq:2800, avs:16 volt:969mv
3>core trim freq:2800, avs:16 volt:974mv
3>core trim freq:2850, avs:17 volt:987mv
3>core trim freq:2850, avs:17 volt:992mv
3>core trim freq:2900, avs:18 volt:1005mv
3>core trim freq:2900, avs:18 volt:1011mv
3>core trim freq:2950, avs:19 volt:1022mv
3>core trim freq:2950, avs:19 volt:1028mv
3>core trim freq:3000, avs:20 volt:1039mv
3>core trim freq:3000, avs:20 volt:1045mv
3>core trim freq:3050, avs:21 volt:1053mv
3>core trim freq:3050, avs:21 volt:1058mv
3>core trim freq:3100, avs:22 volt:1067mv
3>core trim freq:3100, avs:22 volt:1072mv
3>acg trim end
3>LDO disabled
3>[TracePoint] type[  0] cmd[  2] data[  3]
3>Interrupt 423 register OK
3>Interrupt 430 register OK
3>[TracePoint] type[  0] cmd[  2] data[  4]
3>
3>cpu 0 entering scheduler
3>[TracePoint] type[  0] cmd[  3] data[  1]
3>add your ipu app init here!
3>IpuInterfaceTaskStart Entry ...
3>ipu interface task wait parameters from uefi...
3>thermal soc task enabled
3>AP Last Time:[0.00.41.169]
3>ThermalDimmStart Entry ...
3>wait ddr init done...
3>power task start...
3>[TracePoint] type[  0] cmd[  3] data[  2]
3>ufs task wait parameters from uefi...
3>AmuTaskStart Entry ... 
3>amu task wait parameters from uefi...
3>ThermalSiwStart Entry ...
3>ThermalSiwTask idle...
3>DemtTaskStart Entry ...
3>[TracePoint] type[  0] cmd[  3] data[  3]
3>HiBoostTaskStart Entry ...
3>HiBoost task enabled
3>Waiting for UEFI parameters...
3>[TracePoint] type[  0] cmd[  3] data[  4]
3>demt task wait parameters from uefi...
3>AgeTaskStart Entry ...
3>age task wait parameters from uefi...
3>[TracePoint] type[  0] cmd[  3] data[  5]
[0.00.45.709]ext0 int trigger
[0.00.46.142]ext0 int trigger
pwr cap[0]: 0, 63
[0.00.46.548]ext0 int trigger
[0.00.46.941]ext0 int trigger
[0.00.47.314]ext0 int trigger
[0.00.47.691]ext0 int trigger
[0.00.48.175]ext0 int trigger
[0.00.48.555]ext0 int trigger
[0.00.48.942]ext0 int trigger
[0.00.49.284]ext0 int trigger
pwr cap[1]: f, 27
[0.00.49.628]ext0 int trigger
Get Setup Config.
[0.00.49.994]ext0 int trigger
[0.00.50.399]ext0 int trigger
2>uefi parameters ready!
2>UFSProfile[0]
2>PowerPolicy[2] BenchMarkSelection[0]
2>ufs task parameters from uefi ready
2>uncore domain[0] freq:2900
2>uncore domain[1] freq:2900
2>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
2>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
2>======sioe status======
2>thermal soc task restore underclocking_en=1
2>ppu alert temp div init done
2>TA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
2>TA_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
2>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
2>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
2>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
2>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
2>==========end==========
2>sioe init done
2>ufs task enabled
2>--> UFS profile[0]
2>ipu interface task wait ddr init done from uefi...
2>UEFI parameters ready
2>UncoreMaxFreq Set to [2900 MHZ]
2>get TDP from efuse success, value = 307500mw
2>target power set to [307500]mw, brd:[307500]
2>demt task parameters from uefi ready
2>age task parameters from uefi ready
2>age task enabled
3>uefi parameters ready!
3>UFSProfile[0]
3>ufs task parameters from uefi ready
3>uncore domain[0] freq:2900
3>uncore domain[1] freq:2900
3>thermal soc task restore underclocking_en=1
3>ppu alert temp div init done
3>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
3>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
3>======sioe status======
3>TA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
3>TA_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
3>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
3>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
3>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
3>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
3>==========end==========
3>sioe init done
3>ufs task enabled
3>--> UFS profile[0]
3>PowerPolicy[2] BenchMarkSelection[0]
3>ipu interface task wait ddr init done from uefi...
3>UEFI parameters ready
3>UncoreMaxFreq Set to [2900 MHZ]
3>get TDP from efuse success, value = 307500mw
3>target power set to [307500]mw, brd:[307500]
3>demt task parameters from uefi ready
3>age task parameters from uefi ready
3>age task enabled
[0.00.50.758]ext0 int trigger
[0.00.51.098]ext0 int trigger
[0.00.51.445]ext0 int trigger
[0.00.51.795]ext0 int trigger
[0.00.52.137]ext0 int trigger
pwr cap[2]: 1, 3
[0.00.52.551]ext0 int trigger
0>uefi parameters ready!
0>UFSProfile[0]
0>PowerPolicy[2] BenchMarkSelection[0]
0>ufs task parameters from uefi ready
0>uncore domain[0] freq:2900
0>uncore domain[1] freq:2900
0>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
0>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
0>thermal soc task restore underclocking_en=1
0>ppu alert temp div init done
0>======sioe status======
0>TA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TA_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TA_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TA_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
0>TA_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
0>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
0>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
0>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
0>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
0>==========end==========
0>sioe init done
0>ufs task enabled
0>--> UFS profile[0]
0>ipu interface task wait ddr init done from uefi...
0>UEFI parameters ready
0>UncoreMaxFreq Set to [2900 MHZ]
0>get TDP from efuse success, value = 307500mw
0>target power set to [307500]mw, brd:[307500]
0>demt task parameters from uefi ready
0>age task parameters from uefi ready
0>age task enabled
1>uefi parameters ready!
1>UFSProfile[0]
1>ufs task parameters from uefi ready
1>uncore domain[0] freq:2900
1>uncore domain[1] freq:2900
1>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
1>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
1>======sioe status======
1>TA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TA_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
1>thermal soc task restore underclocking_en=1
1>ppu alert temp div init done
1>TA_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TA_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
1>TA_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
1>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
1>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
1>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
1>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
1>==========end==========
1>sioe init done
1>ufs task enabled
1>--> UFS profile[0]
1>PowerPolicy[2] BenchMarkSelection[0]
1>ipu interface task wait ddr init done from uefi...
1>UEFI parameters ready
1>UncoreMaxFreq Set to [2900 MHZ]
1>get TDP from efuse success, value = 307500mw
1>target power set to [307500]mw, brd:[307500]
1>demt task parameters from uefi ready
1>age task parameters from uefi ready
1>age task enabled
[0.00.52.927]ext0 int trigger
[0.00.53.271]ext0 int trigger
Node 0, Die 0 ImpState is 0 skip exec.
Node 0, Die 2 ImpState is 0 skip exec.
Node 1, Die 0 ImpState is 0 skip exec.
Node 1, Die 2 ImpState is 0 skip exec.
Node 2, Die 0 ImpState is 0 skip exec.
Node 2, Die 2 ImpState is 0 skip exec.
Node 3, Die 0 ImpState is 0 skip exec.
Node 3, Die 2 ImpState is 0 skip exec.
[0.00.53.511]ext0 int trigger
[0.00.53.722]ext0 int trigger
[0.00.53.931]ext0 int trigger
[0.00.54.141]ext0 int trigger
[0.00.54.350]ext0 int trigger
[0.00.54.610]ext0 int trigger
[0.00.54.830]ext0 int trigger
[0.00.55.039]ext0 int trigger
[0.00.55.249]ext0 int trigger
[0.00.55.458]ext0 int trigger
[0.00.55.668]ext0 int trigger
[0.00.55.878]ext0 int trigger
[0.00.56.088]ext0 int trigger
[0.00.56.299]ext0 int trigger
[0.00.56.509]ext0 int trigger
[0.00.56.781]ext0 int trigger
[0.00.56.991]ext0 int trigger
[0.00.57.211]ext0 int trigger
[0.00.57.421]ext0 int trigger
[0.00.57.630]ext0 int trigger
[0.00.57.840]ext0 int trigger
[0.00.58.050]ext0 int trigger
[0.00.58.270]ext0 int trigger
[0.00.58.480]ext0 int trigger
[0.00.58.711]ext0 int trigger
[0.00.58.951]ext0 int trigger
[0.00.59.179]ext0 int trigger
[0.00.59.393]ext0 int trigger
[0.00.59.603]ext0 int trigger
[0.00.59.813]ext0 int trigger
[0.01.00.023]ext0 int trigger
[0.01.00.232]ext0 int trigger
[0.01.00.442]ext0 int trigger
[0.01.00.651]ext0 int trigger
[0.01.00.914]ext0 int trigger
[0.01.01.123]ext0 int trigger
[0.01.01.333]ext0 int trigger
[0.01.01.543]ext0 int trigger
[0.01.01.753]ext0 int trigger
[0.01.01.962]ext0 int trigger
[0.01.02.171]ext0 int trigger
[0.01.02.381]ext0 int trigger
[0.01.02.591]ext0 int trigger
[0.01.02.810]ext0 int trigger
[0.01.03.066]ext0 int trigger
[0.01.03.276]ext0 int trigger
[0.01.03.485]ext0 int trigger
[0.01.03.696]ext0 int trigger
[0.01.03.906]ext0 int trigger
[0.01.04.115]ext0 int trigger
[0.01.04.324]ext0 int trigger
[0.01.04.546]ext0 int trigger
[0.01.04.756]ext0 int trigger
[0.01.04.977]ext0 int trigger
[0.01.05.238]ext0 int trigger
[0.01.05.447]ext0 int trigger
[0.01.05.685]ext0 int trigger
[0.01.05.895]ext0 int trigger
[0.01.06.115]ext0 int trigger
[0.01.06.325]ext0 int trigger
[0.01.06.534]ext0 int trigger
[0.01.06.745]ext0 int trigger
[0.01.06.965]ext0 int trigger
[0.01.07.182]ext0 int trigger
[0.01.07.432]ext0 int trigger
[0.01.07.641]ext0 int trigger
[0.01.07.850]ext0 int trigger
[0.01.08.060]ext0 int trigger
[0.01.08.269]ext0 int trigger
[0.01.08.480]ext0 int trigger
[0.01.08.689]ext0 int trigger
[0.01.08.905]ext0 int trigger
[0.01.09.116]ext0 int trigger
[0.01.09.346]ext0 int trigger
[0.01.09.581]ext0 int trigger
[0.01.09.792]ext0 int trigger
[0.01.10.001]ext0 int trigger
[0.01.10.212]ext0 int trigger
[0.01.10.421]ext0 int trigger
[0.01.10.631]ext0 int trigger
[0.01.10.840]ext0 int trigger
[0.01.11.059]ext0 int trigger
[0.01.11.269]ext0 int trigger
[0.01.11.510]ext0 int trigger
[0.01.11.729]ext0 int trigger
[0.01.11.964]ext0 int trigger
[0.01.12.187]ext0 int trigger
[0.01.12.407]ext0 int trigger
[0.01.12.616]ext0 int trigger
[0.01.12.826]ext0 int trigger
0>uefi ddr init finish!
0>ipu interface task wait uefi end done from uefi...
1>uefi ddr init finish!
1>ipu interface task wait uefi end done from uefi...
2>uefi ddr init finish!
2>ipu interface task wait uefi end done from uefi...
3>uefi ddr init finish!
3>ipu interface task wait uefi end done from uefi...
[0.01.13.046]ext0 int trigger
[0.01.13.256]ext0 int trigger
[0.01.13.466]ext0 int trigger
[0.01.13.726]ext0 int trigger
[0.01.13.937]ext0 int trigger
[0.01.14.146]ext0 int trigger
[0.01.14.351]DDR Rreserved for IMU: len = 3e00000
[LOG]head = 0x0, tail = 0x4fe9, logSize = 0x4fe9
[0.01.14.357]ext0 int trigger
copy registry.json file success
Set component all release version to sram end.
ipcMsgSend success
[0.01.14.426]starting ras Init
nodeId = 0, dieId = 0, isSasExist = 0.
nodeId = 0, dieId = 2, isSasExist = 0.
nodeId = 1, dieId = 0, isSasExist = 0.
nodeId = 1, dieId = 2, isSasExist = 0.
nodeId = 2, dieId = 0, isSasExist = 0.
nodeId = 2, dieId = 2, isSasExist = 0.
nodeId = 3, dieId = 0, isSasExist = 0.
nodeId = 3, dieId = 2, isSasExist = 0.
Mce Table head exist!
RasIntRegister init 452 
RasIntRegister init 453 
RasIntRegister init 64 
RasIntRegister init 65 
RasIntRegister init 465 
RasIntRegister init 466 
RasIntRegister init 86 
RasIntRegister init 87 
RasIntRegister init 478 
RasIntRegister init 479 
RasIntRegister init 108 
RasIntRegister init 109 
RasIntRegister init 491 
RasIntRegister init 492 
RasIntRegister init 130 
RasIntRegister init 131 
RasIntRegister init 504 
RasIntRegister init 505 
RasIntRegister init 152 
RasIntRegister init 153 
RasIntRegister init 517 
RasIntRegister init 518 
RasIntRegister init 174 
RasIntRegister init 175 
RasIntRegister init 530 
RasIntRegister init 531 
RasIntRegister init 196 
RasIntRegister init 197 
RasIntRegister init 543 
RasIntRegister init 544 
RasIntRegister init 218 
RasIntRegister init 219 
RasIntRegister init 76 
RasIntRegister init 98 
RasIntRegister init 120 
RasIntRegister init 142 
[0.01.14.748]ext0 int trigger
RasIntRegister init 164 
RasIntRegister init 186 
RasIntRegister init 208 
RasIntRegister init 230 
[0.01.14.758]starting ras end
[0.01.14.966]ext0 int trigger


HSM_LOG:
[00:00:00.000][info] succeed to do thirdparty dfx_pabuk init
[00:00:00.000][info] succeed to do thirdparty crypto_driver init


0>ddr init done, start thermal dimm task
0>======dimm status======
0>  chl[0] dimm0 0, dimm1 0
0>  chl[1] dimm0 0, dimm1 0
0>  chl[2] dimm0 2, dimm1 0
0>  chl[3] dimm0 0, dimm1 0
0>  chl[4] dimm0 0, dimm1 0
0>  chl[5] dimm0 0, dimm1 0
0>  chl[6] dimm0 0, dimm1 0
0>  chl[7] dimm0 0, dimm1 0
0>==========end==========
0>chl[2] registered, dimm mask = 0x1
0>=====dimm temp params=====
0>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
0>  is_thermal_thro_en  : 1
0>  is_aref_rate_auto   : 1
0>===========end============
1>ddr init done, start thermal dimm task
1>======dimm status======
1>  chl[0] dimm0 0, dimm1 0
1>  chl[1] dimm0 0, dimm1 0
1>  chl[2] dimm0 0, dimm1 0
1>  chl[3] dimm0 0, dimm1 0
1>  chl[4] dimm0 0, dimm1 0
1>  chl[5] dimm0 0, dimm1 0
1>  chl[6] dimm0 0, dimm1 0
1>  chl[7] dimm0 0, dimm1 0
1>==========end==========
1>=====dimm temp params=====
1>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
1>  is_thermal_thro_en  : 1
1>  is_aref_rate_auto   : 1
1>===========end============
2>ddr init done, start thermal dimm task
2>======dimm status======
2>  chl[0] dimm0 0, dimm1 0
2>  chl[1] dimm0 0, dimm1 0
2>  chl[2] dimm0 2, dimm1 0
2>  chl[3] dimm0 0, dimm1 0
2>  chl[4] dimm0 0, dimm1 0
2>  chl[5] dimm0 0, dimm1 0
2>  chl[6] dimm0 0, dimm1 0
2>  chl[7] dimm0 0, dimm1 0
2>==========end==========
2>chl[2] registered, dimm mask = 0x1
2>=====dimm temp params=====
2>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
2>  is_thermal_thro_en  : 1
2>  is_aref_rate_auto   : 1
2>===========end============
3>ddr init done, start thermal dimm task
3>======dimm status======
3>  chl[0] dimm0 0, dimm1 0
3>  chl[1] dimm0 0, dimm1 0
3>  chl[2] dimm0 0, dimm1 0
3>  chl[3] dimm0 0, dimm1 0
3>  chl[4] dimm0 0, dimm1 0
3>  chl[5] dimm0 0, dimm1 0
3>  chl[6] dimm0 0, dimm1 0
3>  chl[7] dimm0 0, dimm1 0
3>==========end==========
3>=====dimm temp params=====
3>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
3>  is_thermal_thro_en  : 1
3>  is_aref_rate_auto   : 1
3>===========end============
[0.01.15.194]ext0 int trigger
[0.01.15.405]ext0 int trigger
[0.01.15.616]ext0 int trigger
[0.01.15.878]ext0 int trigger
[0.01.16.087]ext0 int trigger
[0.01.16.297]ext0 int trigger
[0.01.16.506]ext0 int trigger
[0.01.16.716]ext0 int trigger
[0.01.16.925]ext0 int trigger


HSM_LOG:
[00:00:00.010][info] os_mem_system_init default pool done
[00:00:00.016][info] succeed to do thirdparty otpc_pabuk init
[00:00

[0.01.17.153]ext0 int trigger
[0.01.17.364]ext0 int trigger
[0.01.17.574]ext0 int trigger
[0.01.17.783]ext0 int trigger
[0.01.18.045]ext0 int trigger
[0.01.18.271]ext0 int trigger
[0.01.18.489]ext0 int trigger
[0.01.18.699]ext0 int trigger
[0.01.18.910]ext0 int trigger


HSM_LOG:
:00.017][info] succeed to do thirdparty boot_profile_driver init
[00:00:00.017][info] succeed to do thirdparty measure_value_ma

0>chl[2] max_temp 35'C, aref_rate 0x5 --> 0x4
2>chl[2] max_temp 35'C, aref_rate 0x5 --> 0x4
[0.01.19.136]ext0 int trigger
[0.01.19.345]ext0 int trigger
[0.01.19.555]ext0 int trigger
[0.01.19.765]ext0 int trigger
[0.01.19.999]ext0 int trigger
[0.01.20.225]ext0 int trigger
[0.01.20.435]ext0 int trigger
[0.01.20.644]ext0 int trigger
[0.01.20.859]ext0 int trigger
[0.01.21.070]ext0 int trigger


HSM_LOG:
nage_driver init
[00:00:00.018][info] succeed to do thirdparty period_driver init
[00:00:00.018][info]  start loading internal

[0.01.21.307]ext0 int trigger
[0.01.21.516]ext0 int trigger
[0.01.21.726]ext0 int trigger
[0.01.21.935]ext0 int trigger
[0.01.22.188]ext0 int trigger
[0.01.22.398]ext0 int trigger
[0.01.22.608]ext0 int trigger
[0.01.22.820]ext0 int trigger
[0.01.23.030]ext0 int trigger


HSM_LOG:
 task ...
[00:00:00.018][info]  task name is ccm_task
[00:00:00.019][info]  hm_dynamic_loadelf successfully!
[00:00:00.019][i

[0.01.23.256]ext0 int trigger
[0.01.23.467]ext0 int trigger
[0.01.23.676]ext0 int trigger
[0.01.23.886]ext0 int trigger
[0.01.24.096]ext0 int trigger
[0.01.24.357]ext0 int trigger
[0.01.24.567]ext0 int trigger
[0.01.24.798]ext0 int trigger
[0.01.25.009]ext0 int trigger


HSM_LOG:
nfo] internal task[1] task_name=ccm_task load successfully
[00:00:00.020][info]  task name is upgrade_task
[00:00:00.020][info

[0.01.25.242]ext0 int trigger
[0.01.25.452]ext0 int trigger
[0.01.25.661]ext0 int trigger
[0.01.25.871]ext0 int trigger
[0.01.26.082]ext0 int trigger
[0.01.26.295]ext0 int trigger
[0.01.26.556]ext0 int trigger
[0.01.26.765]ext0 int trigger
[0.01.26.976]ext0 int trigger
[0.01.27.186]ext0 int trigger


HSM_LOG:
]  hm_dynamic_loadelf successfully!
[00:00:00.021][info] internal task[2] task_name=upgrade_task load successfully
[00:00:00.0

[0.01.27.413]ext0 int trigger
[0.01.27.623]ext0 int trigger
[0.01.27.832]ext0 int trigger
[0.01.28.046]ext0 int trigger
[0.01.28.255]ext0 int trigger
[0.01.28.488]ext0 int trigger
[0.01.28.727]ext0 int trigger
[0.01.28.937]ext0 int trigger
[0.01.29.162]ext0 int trigger


HSM_LOG:
22][info]  task name is hes_task
[00:00:00.022][info]  hm_dynamic_loadelf successfully!
[00:00:00.023][info] internal task[3] 

[0.01.29.388]ext0 int trigger
[0.01.29.602]ext0 int trigger
[0.01.29.813]ext0 int trigger
[0.01.30.023]ext0 int trigger
[0.01.30.233]ext0 int trigger
[0.01.30.443]ext0 int trigger
[0.01.30.697]ext0 int trigger
[0.01.30.906]ext0 int trigger
[0.01.31.115]ext0 int trigger


HSM_LOG:
task_name=hes_task load successfully
[00:00:00.024][info] created task ccm_task success!
[00:00:00.025][info] created task upg

[0.01.31.350]ext0 int trigger
[0.01.31.578]ext0 int trigger
[0.01.31.788]ext0 int trigger
[0.01.31.997]ext0 int trigger
[0.01.32.208]ext0 int trigger
[0.01.32.417]ext0 int trigger
[0.01.32.627]ext0 int trigger
[0.01.32.888]ext0 int trigger
[0.01.33.098]ext0 int trigger
[0.01.33.310]ext0 int trigger


HSM_LOG:
rade_task success!
[00:00:00.026][info] created task hes_task success!
[00:00:00.026][info] Init start.
[1970-01-01 00:00:00.

[0.01.33.539]ext0 int trigger
[0.01.33.751]ext0 int trigger
[0.01.33.960]ext0 int trigger
[0.01.34.170]ext0 int trigger
[0.01.34.379]ext0 int trigger
[0.01.34.591]ext0 int trigger
[0.01.34.802]ext0 int trigger
[0.01.35.061]ext0 int trigger
[0.01.35.271]ext0 int trigger


HSM_LOG:
027][HSM][INFO][54] Platform init 0x20250523 0x4e.

[1970-01-01 00:00:00.027][HSM][INFO][197] ccm start.

[1970-01-01 00:00:00

[0.01.35.497]ext0 int trigger
[0.01.35.707]ext0 int trigger
[0.01.35.890][ERR]cmd not support! cmd = 0xd
[0.01.35.922]ext0 int trigger
[0.01.36.162]ext0 int trigger
[0.01.36.377]ext0 int trigger
[0.01.36.586]ext0 int trigger
[0.01.36.798]ext0 int trigger
[0.01.37.052]ext0 int trigger
[0.01.37.262]ext0 int trigger


HSM_LOG:
.028][HSM][INFO][86] upgrade task init success.

[1970-01-01 00:00:00.028][HSM][INFO][95] upgrade recv cmd, 0x181.

[1970-01-0

[0.01.37.490]ext0 int trigger
[0.01.37.735]ext0 int trigger
[0.01.37.953]ext0 int trigger
[0.01.38.162]ext0 int trigger
[0.01.38.373]ext0 int trigger
[0.01.38.583]ext0 int trigger
[0.01.38.826]ext0 int trigger
[0.01.39.035]ext0 int trigger
[0.01.39.316]ext0 int trigger


HSM_LOG:
1 00:00:00.029][HSM][INFO][103] upgrade res, 0x3a5aa5a3.

[1970-01-01 00:00:00.030][HSM][INFO][75] hes tee_task_entry.

[1970-

[0.01.39.537]ext0 int trigger
[0.01.39.767]ext0 int trigger
[0.01.39.976]ext0 int trigger
[0.01.40.206]ext0 int trigger
[0.01.40.417]ext0 int trigger
[0.01.40.626]ext0 int trigger
[0.01.40.862]ext0 int trigger
[0.01.41.097]ext0 int trigger
[0.01.41.366]ext0 int trigger


HSM_LOG:
01-01 00:00:00.553][HSM][INFO][44] hes init success.

[00:00:00.553][info] Init over.


[0.01.41.606]ext0 int trigger
[0.01.41.816]ext0 int trigger
[0.01.42.036]ext0 int trigger
[0.01.42.257]ext0 int trigger
[0.01.42.466]ext0 int trigger
[0.01.42.676]ext0 int trigger
[0.01.42.886]ext0 int trigger
[0.01.43.095]ext0 int trigger
[0.01.43.336]ext0 int trigger
[0.01.43.594]ext0 int trigger
[0.01.43.835]ext0 int trigger
[0.01.44.050]ext0 int trigger
[0.01.44.279]ext0 int trigger
[0.01.44.489]ext0 int trigger
[0.01.44.698]ext0 int trigger
[0.01.44.919]ext0 int trigger
[0.01.45.129]ext0 int trigger
[0.01.45.359]ext0 int trigger
[0.01.45.626]ext0 int trigger
[0.01.45.872]ext0 int trigger
[0.01.46.082]ext0 int trigger
[0.01.46.292]ext0 int trigger
[0.01.46.507]ext0 int trigger
[0.01.46.717]ext0 int trigger
[0.01.46.937]ext0 int trigger
[0.01.47.147]ext0 int trigger
[0.01.47.357]ext0 int trigger
[0.01.47.577]ext0 int trigger
[0.01.47.840]ext0 int trigger
[0.01.48.049]ext0 int trigger
[0.01.48.264]ext0 int trigger
[0.01.48.457]TF Heartbeat Start
[0.01.48.475]ext0 int trigger
[0.01.48.686]ext0 int trigger
[0.01.48.901]ext0 int trigger
[0.01.49.111]ext0 int trigger
[0.01.49.323]ext0 int trigger
[0.01.49.544]ext0 int trigger
[0.01.49.797]ext0 int trigger
[0.01.50.017]ext0 int trigger
[0.01.50.226]ext0 int trigger
[0.01.50.441]ext0 int trigger
[0.01.50.666]ext0 int trigger
[0.01.50.885]ext0 int trigger
[0.01.51.106]ext0 int trigger
[0.01.51.316]ext0 int trigger
[0.01.51.526]ext0 int trigger
[0.01.51.739]ext0 int trigger
[0.01.52.000]ext0 int trigger
[0.01.52.210]ext0 int trigger
[0.01.52.419]ext0 int trigger
[0.01.52.629]ext0 int trigger
[0.01.52.845]ext0 int trigger
[0.01.53.054]ext0 int trigger
[0.01.53.263]ext0 int trigger
[0.01.53.474]ext0 int trigger
[0.01.53.688]ext0 int trigger
[0.01.53.908]ext0 int trigger
[0.01.54.023]PCIE INIT DONE.
g_mctpQueueCount(48) > tabCnt(42)
Interrupt 454 register OK
Interrupt 467 register OK
Interrupt 480 register OK
Interrupt 493 register OK
Interrupt 506 register OK
Interrupt 519 register OK
Interrupt 532 register OK
Interrupt 545 register OK
data = 0x0
pmt Init done

Add ep: bdf=5500 eid=9 epCnt=1 eid_alloc=a
Add ep: bdf=300 eid=a epCnt=1 eid_alloc=b
[0.01.54.186]ext0 int trigger
[0.01.54.402]ext0 int trigger
[0.01.54.621]ext0 int trigger
[0.01.54.838]ext0 int trigger
[0.01.55.056]ext0 int trigger
[0.01.55.284]ext0 int trigger
[0.01.55.499]ext0 int trigger
[0.01.55.716]ext0 int trigger
[0.01.55.942]ext0 int trigger
[0.01.56.199]ext0 int trigger
[0.01.56.423]ext0 int trigger
[0.01.56.640]ext0 int trigger
[0.01.56.868]ext0 int trigger
[0.01.57.108]ext0 int trigger
[0.01.57.326]ext0 int trigger
[0.01.57.544]ext0 int trigger
[0.01.57.762]ext0 int trigger
[0.01.57.988]ext0 int trigger
[0.01.58.208]ext0 int trigger
[0.01.58.490]ext0 int trigger
[0.01.58.708]ext0 int trigger
[0.01.58.926]ext0 int trigger
[0.01.59.144]ext0 int trigger
[0.01.59.362]ext0 int trigger
[0.01.59.580]ext0 int trigger
[0.01.59.799]ext0 int trigger
[0.02.00.023]ext0 int trigger
[0.02.00.241]ext0 int trigger
[0.02.00.501]ext0 int trigger
[0.02.00.718]ext0 int trigger
[0.02.00.937]ext0 int trigger
[0.02.01.155]ext0 int trigger
[0.02.01.373]ext0 int trigger
[0.02.01.591]ext0 int trigger
[0.02.01.809]ext0 int trigger
[0.02.02.039]ext0 int trigger
[0.02.02.257]ext0 int trigger
[0.02.02.476]ext0 int trigger
[0.02.02.757]ext0 int trigger
[0.02.02.975]ext0 int trigger
[0.02.03.198]ext0 int trigger
[0.02.03.441]ext0 int trigger
[0.02.03.661]ext0 int trigger
[0.02.03.883]ext0 int trigger
[0.02.04.110]ext0 int trigger
[0.02.04.330]ext0 int trigger
[0.02.04.547]ext0 int trigger
[0.02.04.802]ext0 int trigger
[0.02.05.020]ext0 int trigger
[0.02.05.239]ext0 int trigger
[0.02.05.458]ext0 int trigger
[0.02.05.676]ext0 int trigger
[0.02.05.895]ext0 int trigger
[0.02.06.125]ext0 int trigger
[0.02.06.343]ext0 int trigger
[0.02.06.560]ext0 int trigger
[0.02.06.784]ext0 int trigger
[0.02.07.039]ext0 int trigger
[0.02.07.257]ext0 int trigger
[0.02.07.475]ext0 int trigger
[0.02.07.693]ext0 int trigger
[0.02.07.911]ext0 int trigger
[0.02.08.135]ext0 int trigger
[0.02.08.353]ext0 int trigger
[0.02.08.572]ext0 int trigger
[0.02.08.792]ext0 int trigger
[0.02.09.069]ext0 int trigger
[0.02.09.287]ext0 int trigger
[0.02.09.505]ext0 int trigger
[0.02.09.744]ext0 int trigger
[0.02.09.974]ext0 int trigger
[0.02.10.204]ext0 int trigger
[0.02.10.422]ext0 int trigger
[0.02.10.642]ext0 int trigger
[0.02.10.860]ext0 int trigger
[0.02.11.102]ext0 int trigger
[0.02.11.353]ext0 int trigger
[0.02.11.570]ext0 int trigger
[0.02.11.790]ext0 int trigger
[0.02.12.018]ext0 int trigger
[0.02.12.242]ext0 int trigger
[0.02.12.462]ext0 int trigger
[0.02.12.679]ext0 int trigger
[0.02.12.898]ext0 int trigger
[0.02.13.116]ext0 int trigger
[0.02.13.399]ext0 int trigger
[0.02.13.617]ext0 int trigger
[0.02.13.834]ext0 int trigger
[0.02.14.060]ext0 int trigger
[0.02.14.286]ext0 int trigger
[0.02.14.504]ext0 int trigger
[0.02.14.722]ext0 int trigger
[0.02.14.940]ext0 int trigger
[0.02.15.168]ext0 int trigger
[0.02.15.437]ext0 int trigger
[0.02.15.654]ext0 int trigger
[0.02.15.872]ext0 int trigger
[0.02.16.123]ext0 int trigger
[0.02.16.347]ext0 int trigger
[0.02.16.565]ext0 int trigger
[0.02.16.783]ext0 int trigger
[0.02.17.003]ext0 int trigger
[0.02.17.221]ext0 int trigger
[0.02.17.446]ext0 int trigger
[0.02.17.698]ext0 int trigger
[0.02.17.916]ext0 int trigger
[0.02.18.140]ext0 int trigger
[0.02.18.359]ext0 int trigger
[0.02.18.579]ext0 int trigger
[0.02.18.808]ext0 int trigger
[0.02.19.025]ext0 int trigger
[0.02.19.243]ext0 int trigger
mctp task ok.
[0.02.19.465]ext0 int trigger
[0.02.19.714]ext0 int trigger
[0.02.19.933]ext0 int trigger
[0.02.20.160]ext0 int trigger
[0.02.20.377]ext0 int trigger
[0.02.20.595]ext0 int trigger
[0.02.20.813]ext0 int trigger
[0.02.21.031]ext0 int trigger
[0.02.21.253]ext0 int trigger
[0.02.21.471]ext0 int trigger
[0.02.21.689]ext0 int trigger
[0.02.21.972]ext0 int trigger
[0.02.22.196]ext0 int trigger
[0.02.22.441]ext0 int trigger
[0.02.22.664]ext0 int trigger
[0.02.22.882]ext0 int trigger
[0.02.23.102]ext0 int trigger
[0.02.23.320]ext0 int trigger
[0.02.23.540]ext0 int trigger
[0.02.23.757]ext0 int trigger
[0.02.24.015]ext0 int trigger
[0.02.24.241]ext0 int trigger
[0.02.24.461]ext0 int trigger
[0.02.24.679]ext0 int trigger
[0.02.24.898]ext0 int trigger
[0.02.25.120]ext0 int trigger
[0.02.25.338]ext0 int trigger
[0.02.25.556]ext0 int trigger
[0.02.25.774]ext0 int trigger
[0.02.25.999]ext0 int trigger
[0.02.26.255]ext0 int trigger
[0.02.26.477]ext0 int trigger
[0.02.26.696]ext0 int trigger
[0.02.26.916]ext0 int trigger
[0.02.27.134]ext0 int trigger
[0.02.27.352]ext0 int trigger
[0.02.27.570]ext0 int trigger
[0.02.27.788]ext0 int trigger
[0.02.28.006]ext0 int trigger
[0.02.28.275]ext0 int trigger
[0.02.28.499]ext0 int trigger
[0.02.28.718]ext0 int trigger
[0.02.28.957]ext0 int trigger
[0.02.29.179]ext0 int trigger
[0.02.29.397]ext0 int trigger
[0.02.29.615]ext0 int trigger
[0.02.29.833]ext0 int trigger
[0.02.30.054]ext0 int trigger
[0.02.30.279]ext0 int trigger
[0.02.30.560]ext0 int trigger
[0.02.30.777]ext0 int trigger
[0.02.30.994]ext0 int trigger
[0.02.31.210]ext0 int trigger
[0.02.31.427]ext0 int trigger
[0.02.31.458]Receive ras int[491]
First coalesce handler start
Type2 status = 0x0
Type1 status = 0x4
Found error node[2]
False alarm reporting!
Type0 status = 0x0
ras int[491] end

[0.02.31.655]ext0 int trigger
[0.02.31.873]ext0 int trigger
[0.02.32.093]ext0 int trigger
[0.02.32.309]ext0 int trigger
[0.02.32.589]ext0 int trigger
[0.02.32.805]ext0 int trigger
[0.02.33.022]ext0 int trigger
[0.02.33.239]ext0 int trigger
[0.02.33.457]ext0 int trigger
[0.02.33.675]ext0 int trigger
[0.02.33.892]ext0 int trigger
[0.02.34.109]ext0 int trigger
[0.02.34.326]ext0 int trigger
[0.02.34.641]ext0 int trigger
[0.02.34.985]ext0 int trigger
[0.02.35.238]ext0 int trigger
[0.02.35.467]ext0 int trigger
[0.02.35.687]ext0 int trigger
[0.02.35.904]ext0 int trigger
[0.02.36.124]ext0 int trigger
[0.02.36.341]ext0 int trigger
[0.02.36.566]ext0 int trigger
[0.02.36.828]ext0 int trigger
[0.02.37.045]ext0 int trigger
[0.02.37.262]ext0 int trigger
[0.02.37.477]ext0 int trigger
[0.02.37.695]ext0 int trigger
[0.02.37.912]ext0 int trigger
[0.02.38.128]ext0 int trigger
[0.02.38.344]ext0 int trigger
[0.02.38.570]ext0 int trigger
[0.02.38.787]ext0 int trigger
[0.02.39.068]ext0 int trigger
[0.02.39.285]ext0 int trigger
[0.02.39.500]ext0 int trigger
[0.02.39.716]ext0 int trigger
[0.02.39.931]ext0 int trigger
[0.02.40.148]ext0 int trigger
[0.02.40.362]ext0 int trigger
[0.02.40.585]ext0 int trigger
[0.02.40.802]ext0 int trigger
[0.02.41.298]ext0 int trigger
[0.02.41.521]ext0 int trigger
[0.02.41.754]ext0 int trigger
[0.02.41.979]ext0 int trigger
[0.02.42.196]ext0 int trigger
[0.02.42.413]ext0 int trigger
[0.02.42.638]ext0 int trigger
[0.02.42.870]ext0 int trigger
[0.02.43.097]ext0 int trigger
[0.02.43.347]ext0 int trigger
[0.02.43.567]ext0 int trigger
[0.02.43.784]ext0 int trigger
[0.02.44.003]ext0 int trigger
[0.02.44.221]ext0 int trigger
[0.02.44.439]ext0 int trigger
[0.02.44.665]ext0 int trigger
[0.02.44.883]ext0 int trigger
[0.02.45.102]ext0 int trigger
[0.02.45.357]ext0 int trigger
[0.02.45.576]ext0 int trigger
[0.02.45.794]ext0 int trigger
[0.02.46.023]ext0 int trigger
[0.02.46.242]ext0 int trigger
[0.02.46.461]ext0 int trigger
[0.02.46.688]ext0 int trigger
[0.02.46.916]ext0 int trigger
[0.02.47.134]ext0 int trigger
[0.02.47.352]ext0 int trigger
[0.02.47.635]ext0 int trigger
[0.02.47.853]ext0 int trigger
[0.02.48.085]ext0 int trigger
[0.02.48.312]ext0 int trigger
[0.02.48.531]ext0 int trigger
[0.02.48.762]ext0 int trigger
[0.02.48.981]ext0 int trigger
[0.02.49.200]ext0 int trigger
[0.02.49.419]ext0 int trigger
[0.02.49.702]ext0 int trigger
[0.02.49.920]ext0 int trigger
[0.02.50.139]ext0 int trigger
[0.02.50.357]ext0 int trigger
[0.02.50.576]ext0 int trigger
[0.02.50.806]ext0 int trigger
[0.02.51.024]ext0 int trigger
[0.02.51.242]ext0 int trigger
[0.02.51.460]ext0 int trigger
[0.02.51.702]ext0 int trigger
[0.02.51.938]ext0 int trigger
[0.02.52.156]ext0 int trigger
[0.02.52.373]ext0 int trigger
[0.02.52.588]ext0 int trigger
[0.02.52.825]ext0 int trigger
[0.02.53.041]ext0 int trigger
[0.02.53.258]ext0 int trigger
[0.02.53.485]ext0 int trigger
[0.02.53.699]ext0 int trigger
[0.02.53.964]ext0 int trigger
[0.02.54.181]ext0 int trigger
[0.02.54.415]ext0 int trigger
[0.02.54.655]ext0 int trigger
[0.02.54.881]ext0 int trigger
[0.02.55.100]ext0 int trigger
[0.02.55.318]ext0 int trigger
[0.02.55.533]ext0 int trigger
[0.02.55.750]ext0 int trigger
[0.02.55.994]ext0 int trigger
[0.02.56.230]ext0 int trigger
[0.02.56.448]ext0 int trigger
[0.02.56.665]ext0 int trigger
[0.02.56.883]ext0 int trigger
[0.02.57.105]ext0 int trigger
[0.02.57.322]ext0 int trigger
[0.02.57.363]BIOS POST END.
Create SetReportPcieMmioToBmc ok.
Start SetReportPcieMmioToBmc ok.
slotNum = 0xb
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[0] port:24  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[1] port:26  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[2] port:32  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[3] port:24  pcieSlotCtrl.data (after)0x14801c0.

[0.02.57.722]ext0 int trigger
pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[4] port:26  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[5] port:32  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[6] port:34  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
[0.02.58.176]ext0 int trigger
Pcie slot[7] port:12  pcieSlotCtrl.data (after)0x4801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[8] port:14  pcieSlotCtrl.data (after)0x4801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[9] port:16  pcieSlotCtrl.data (after)0x4801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[10] port:18  pcieSlotCtrl.data (after)0x4801c0.

[0.02.58.624]ext0 int trigger
0>uefi end finish!
0>ipu interface task exit!
0>amu task parameters from uefi ready
1>uefi end finish!
1>ipu interface task exit!
1>amu task parameters from uefi ready
2>uefi end finish!
2>ipu interface task exit!
2>amu task parameters from uefi ready
3>uefi end finish!
3>ipu interface task exit!
[0.02.59.065]ext0 int trigger
[0.02.59.085]slot: 1, slotCtrl = 0x14801c0
Enter current value process
3>amu task parameters from uefi ready
[0.03.01.198]ext0 int trigger
[0.03.01.210]slot: 1, slotCtrl = 0x10801c0
[0.03.01.308]ext0 int trigger
[0.03.01.331]slot: 1, slotCtrl = 0x14805c0
[0.03.03.898]ext0 int trigger
[0.03.03.910]slot: 1, slotCtrl = 0x815f8
[0.03.03.980]slot[1] port:26 begin to power ON.
[0.03.04.015]ext0 int trigger
[0.03.04.039]slot: 1, slotCtrl = 0x4816f8
[0.03.04.148]ext0 int trigger
[0.03.04.265]ext0 int trigger
[0.03.10.098]ext0 int trigger
[0.03.10.110]slot: 1, slotCtrl = 0x815f8
[0.03.10.208]ext0 int trigger
[0.03.10.231]slot: 1, slotCtrl = 0x4816f8
[0.03.20.897]ext0 int trigger
[0.03.20.911]slot: 1, slotCtrl = 0x815f8
[0.03.21.025]ext0 int trigger
[0.03.21.028]slot[1] port:26 begin to power ON.
[0.03.21.055]slot: 1, slotCtrl = 0x4815f8
[0.03.21.232]slot[1] port:26 begin to power ON.
[0.03.35.497]ext0 int trigger
[0.03.35.510]slot: 1, slotCtrl = 0x811f8
[0.03.35.650]ext0 int trigger
[0.03.35.667]slot: 1, slotCtrl = 0x4815f8
[0.03.37.757]slot[1] port:26 begin to power ON.
[0.03.55.197]ext0 int trigger
[0.03.55.210]slot: 1, slotCtrl = 0x811f8
[0.03.55.318]ext0 int trigger
[0.03.55.342]slot: 1, slotCtrl = 0x4815f8
[0.03.55.441]ext0 int trigger
[0.03.55.560]ext0 int trigger
[0.04.01.397]ext0 int trigger
[0.04.01.411]slot: 1, slotCtrl = 0x815f8
[0.04.01.543]ext0 int trigger
[0.04.01.560]slot: 1, slotCtrl = 0x4815f8
[0.04.02.997]ext0 int trigger
[0.04.03.010]slot: 1, slotCtrl = 0x815f8
[0.04.03.108]ext0 int trigger
[0.04.03.131]slot: 1, slotCtrl = 0x4815f8
[0.04.03.239]ext0 int trigger
[0.04.06.903]slot[1] port:26 begin to power ON.
[0.04.09.797]ext0 int trigger
[0.04.09.810]slot: 1, slotCtrl = 0x811f8
[0.04.09.919]ext0 int trigger
[0.04.09.943]slot: 1, slotCtrl = 0x4815f8
[0.04.10.049]ext0 int trigger
[0.04.10.167]ext0 int trigger
[0.04.10.274]ext0 int trigger
[0.04.12.597]ext0 int trigger
[0.04.12.610]slot: 1, slotCtrl = 0x815f8
[0.04.12.718]ext0 int trigger
[0.04.12.731]slot: 1, slotCtrl = 0x4815f8
[0.04.14.026]slot[1] port:26 begin to power ON.
[0.04.14.897]ext0 int trigger
[0.04.14.910]slot: 1, slotCtrl = 0x811f8
[0.04.15.010]ext0 int trigger
[0.04.15.041]slot: 1, slotCtrl = 0x4815f8
[0.04.15.168]ext0 int trigger
[0.04.15.287]ext0 int trigger
[0.04.15.405]ext0 int trigger
[0.04.15.523]ext0 int trigger
[0.04.15.641]ext0 int trigger
[0.04.15.997]ext0 int trigger
[0.04.16.010]slot: 1, slotCtrl = 0x815f8
[0.04.16.115]ext0 int trigger
[0.04.16.139]slot: 1, slotCtrl = 0x4815f8
[0.04.18.541]slot[1] port:26 begin to power ON.
[0.04.29.497]ext0 int trigger
[0.04.29.510]slot: 1, slotCtrl = 0x811f8
[0.04.29.633]ext0 int trigger
[0.04.29.664]slot: 1, slotCtrl = 0x4815f8
[0.04.29.767]ext0 int trigger
[0.04.29.886]ext0 int trigger
[0.04.30.987]slot[1] port:26 begin to power ON.
[0.04.35.697]ext0 int trigger
[0.04.35.710]slot: 1, slotCtrl = 0x811f8
[0.04.35.817]ext0 int trigger
[0.04.35.843]slot: 1, slotCtrl = 0x4815f8
[0.04.37.121]slot[1] port:26 begin to power ON.
[0.04.41.897]ext0 int trigger
[0.04.41.909]slot: 1, slotCtrl = 0x811f8
[0.04.42.006]ext0 int trigger
[0.04.42.030]slot: 1, slotCtrl = 0x4815f8
[0.04.42.161]ext0 int trigger
[0.04.43.311]slot[1] port:26 begin to power ON.
[0.04.50.297]ext0 int trigger
[0.04.50.309]slot: 1, slotCtrl = 0x811f8
[0.04.50.418]ext0 int trigger
[0.04.50.447]slot: 1, slotCtrl = 0x4815f8
[0.04.50.579]ext0 int trigger
[0.04.51.760]slot[1] port:26 begin to power ON.
[0.04.56.497]ext0 int trigger
[0.04.56.509]slot: 1, slotCtrl = 0x811f8
[0.04.56.617]ext0 int trigger
[0.04.56.652]slot: 1, slotCtrl = 0x4815f8
[0.04.56.783]ext0 int trigger
[0.04.56.915]ext0 int trigger
[0.04.57.914]slot[1] port:26 begin to power ON.
0>amu task activated
0>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
1>amu task activated
1>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
2>amu task activated
2>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
3>amu task activated
3>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
[0.05.01.096]ext0 int trigger
[0.05.01.109]slot: 1, slotCtrl = 0x811f8
[0.05.01.219]ext0 int trigger
[0.05.01.232]slot: 1, slotCtrl = 0x4815f8
[0.05.01.329]ext0 int trigger
[0.05.02.539]slot[1] port:26 begin to power ON.
[0.05.07.296]ext0 int trigger
[0.05.07.309]slot: 1, slotCtrl = 0x811f8
[0.05.07.417]ext0 int trigger
[0.05.07.451]slot: 1, slotCtrl = 0x4815f8
[0.05.07.549]ext0 int trigger
[0.05.08.820]slot[1] port:26 begin to power ON.
[0.05.09.996]ext0 int trigger
[0.05.10.009]slot: 1, slotCtrl = 0x811f8
[0.05.10.117]ext0 int trigger
[0.05.10.141]slot: 1, slotCtrl = 0x4815f8
[0.05.11.358]slot[1] port:26 begin to power ON.
[0.05.16.196]ext0 int trigger
[0.05.16.209]slot: 1, slotCtrl = 0x811f8
[0.05.16.306]ext0 int trigger
[0.05.16.330]slot: 1, slotCtrl = 0x4815f8
[0.05.17.585]slot[1] port:26 begin to power ON.
[0.05.26.996]ext0 int trigger
[0.05.27.009]slot: 1, slotCtrl = 0x811f8
[0.05.27.106]ext0 int trigger
[0.05.27.119]slot: 1, slotCtrl = 0x4815f8
[0.05.28.442]slot[1] port:26 begin to power ON.
[0.05.35.396]ext0 int trigger
[0.05.35.409]slot: 1, slotCtrl = 0x811f8
[0.05.35.510]ext0 int trigger
[0.05.35.533]slot: 1, slotCtrl = 0x4815f8
[0.05.35.631]ext0 int trigger
[0.05.36.861]slot[1] port:26 begin to power ON.
[0.05.41.596]ext0 int trigger
[0.05.41.609]slot: 1, slotCtrl = 0x811f8
[0.05.41.707]ext0 int trigger
[0.05.41.732]slot: 1, slotCtrl = 0x4815f8
[0.05.41.840]ext0 int trigger
[0.05.42.096]ext0 int trigger
[0.05.42.109]slot: 1, slotCtrl = 0x815f8
[0.05.42.206]ext0 int trigger
[0.05.42.230]slot: 1, slotCtrl = 0x4815f8
[0.05.42.347]ext0 int trigger
[0.05.43.027]slot[1] port:26 begin to power ON.
[0.05.54.496]ext0 int trigger
[0.05.54.509]slot: 1, slotCtrl = 0x811f8
[0.05.54.606]ext0 int trigger
[0.05.54.630]slot: 1, slotCtrl = 0x4815f8
[0.05.54.737]ext0 int trigger
[0.05.54.893]ext0 int trigger
[0.05.55.986]slot[1] port:26 begin to power ON.
[0.05.58.396]ext0 int trigger
[0.05.58.409]slot: 1, slotCtrl = 0x811f8
[0.05.58.517]ext0 int trigger
[0.05.58.541]slot: 1, slotCtrl = 0x4815f8
[0.05.58.649]ext0 int trigger
[0.05.58.767]ext0 int trigger
[0.05.58.886]ext0 int trigger
[0.05.59.026]ext0 int trigger
[0.05.59.159]ext0 int trigger
[0.05.59.865]slot[1] port:26 begin to power ON.
[0.06.01.296]ext0 int trigger
[0.06.01.309]slot: 1, slotCtrl = 0x811f8
[0.06.01.407]ext0 int trigger
[0.06.01.431]slot: 1, slotCtrl = 0x4815f8
[0.06.02.742]slot[1] port:26 begin to power ON.
[0.06.04.096]ext0 int trigger
[0.06.04.109]slot: 1, slotCtrl = 0x811f8
[0.06.04.206]ext0 int trigger
[0.06.04.230]slot: 1, slotCtrl = 0x4815f8
[0.06.05.559]slot[1] port:26 begin to power ON.
[0.06.06.396]ext0 int trigger
[0.06.06.409]slot: 1, slotCtrl = 0x811f8
[0.06.06.517]ext0 int trigger
[0.06.06.541]slot: 1, slotCtrl = 0x4815f8
[0.06.06.639]ext0 int trigger
[0.06.07.496]ext0 int trigger
[0.06.07.509]slot: 1, slotCtrl = 0x815f8
[0.06.07.606]ext0 int trigger
[0.06.07.619]slot: 1, slotCtrl = 0x4815f8
[0.06.07.847]slot[1] port:26 begin to power ON.
[0.06.20.996]ext0 int trigger
[0.06.21.009]slot: 1, slotCtrl = 0x811f8
[0.06.21.106]ext0 int trigger
[0.06.21.130]slot: 1, slotCtrl = 0x4815f8
[0.06.21.227]ext0 int trigger
[0.06.22.476]slot[1] port:26 begin to power ON.
[0.06.27.196]ext0 int trigger
[0.06.27.209]slot: 1, slotCtrl = 0x811f8
[0.06.27.306]ext0 int trigger
[0.06.27.329]slot: 1, slotCtrl = 0x4815f8
[0.06.28.793]slot[1] port:26 begin to power ON.
[0.06.33.396]ext0 int trigger
[0.06.33.409]slot: 1, slotCtrl = 0x811f8
[0.06.33.506]ext0 int trigger
[0.06.33.530]slot: 1, slotCtrl = 0x4815f8
[0.06.34.812]slot[1] port:26 begin to power ON.
[0.06.41.796]ext0 int trigger
[0.06.41.808]slot: 1, slotCtrl = 0x811f8
[0.06.41.918]ext0 int trigger
[0.06.41.942]slot: 1, slotCtrl = 0x4815f8
[0.06.43.293]slot[1] port:26 begin to power ON.
[0.06.47.996]ext0 int trigger
[0.06.48.009]slot: 1, slotCtrl = 0x811f8
[0.06.48.106]ext0 int trigger
[0.06.48.130]slot: 1, slotCtrl = 0x4815f8
[0.06.49.410]slot[1] port:26 begin to power ON.
[0.06.54.696]ext0 int trigger
[0.06.54.708]slot: 1, slotCtrl = 0x811f8
[0.06.54.813]ext0 int trigger
[0.06.54.837]slot: 1, slotCtrl = 0x4815f8
[0.06.56.143]slot[1] port:26 begin to power ON.
[0.07.01.495]ext0 int trigger
[0.07.01.508]slot: 1, slotCtrl = 0x811f8
[0.07.01.616]ext0 int trigger
[0.07.01.640]slot: 1, slotCtrl = 0x4815f8
[0.07.01.737]ext0 int trigger
[0.07.02.934]slot[1] port:26 begin to power ON.
[0.07.07.695]ext0 int trigger
[0.07.07.708]slot: 1, slotCtrl = 0x811f8
[0.07.07.816]ext0 int trigger
[0.07.07.840]slot: 1, slotCtrl = 0x4815f8
[0.07.07.937]ext0 int trigger
[0.07.09.124]slot[1] port:26 begin to power ON.
[0.07.21.195]ext0 int trigger
[0.07.21.209]slot: 1, slotCtrl = 0x811f8
[0.07.21.318]ext0 int trigger
[0.07.21.342]slot: 1, slotCtrl = 0x4815f8
[0.07.22.697]slot[1] port:26 begin to power ON.
[0.07.27.395]ext0 int trigger
[0.07.27.408]slot: 1, slotCtrl = 0x811f8
[0.07.27.506]ext0 int trigger
[0.07.27.518]slot: 1, slotCtrl = 0x4815f8
[0.07.28.900]slot[1] port:26 begin to power ON.
[0.07.33.595]ext0 int trigger
[0.07.33.608]slot: 1, slotCtrl = 0x811f8
[0.07.33.716]ext0 int trigger
[0.07.33.739]slot: 1, slotCtrl = 0x4815f8
[0.07.33.837]ext0 int trigger
[0.07.35.070]slot[1] port:26 begin to power ON.
[0.07.36.995]ext0 int trigger
[0.07.37.008]slot: 1, slotCtrl = 0x811f8
[0.07.37.127]ext0 int trigger
[0.07.37.151]slot: 1, slotCtrl = 0x4815f8
[0.07.37.249]ext0 int trigger
[0.07.38.605]slot[1] port:26 begin to power ON.
[0.07.45.995]ext0 int trigger
[0.07.46.008]slot: 1, slotCtrl = 0x811f8
[0.07.46.105]ext0 int trigger
[0.07.46.128]slot: 1, slotCtrl = 0x4815f8
[0.07.46.226]ext0 int trigger
[0.07.47.095]ext0 int trigger
[0.07.47.108]slot: 1, slotCtrl = 0x815f8
[0.07.47.205]ext0 int trigger
[0.07.47.229]slot: 1, slotCtrl = 0x4815f8
[0.07.47.349]ext0 int trigger
[0.07.47.354]slot[1] port:26 begin to power ON.
[0.07.49.895]ext0 int trigger
[0.07.49.908]slot: 1, slotCtrl = 0x811f8
[0.07.50.016]ext0 int trigger
[0.07.50.039]slot: 1, slotCtrl = 0x4815f8
[0.07.50.136]ext0 int trigger
[0.07.50.244]ext0 int trigger
[0.07.51.402]slot[1] port:26 begin to power ON.
[0.07.53.295]ext0 int trigger
[0.07.53.319]slot: 1, slotCtrl = 0x811f8
[0.07.53.428]ext0 int trigger
[0.07.53.441]slot: 1, slotCtrl = 0x4815f8
[0.07.54.797]slot[1] port:26 begin to power ON.
[0.07.55.595]ext0 int trigger
[0.07.55.608]slot: 1, slotCtrl = 0x811f8
[0.07.55.725]ext0 int trigger
[0.07.55.738]slot: 1, slotCtrl = 0x4815f8
[0.07.55.835]ext0 int trigger
[0.07.57.100]slot[1] port:26 begin to power ON.
[0.07.57.363]IpmiCmdReportPcieMMIO start
[0.08.01.695]ext0 int trigger
[0.08.01.713]slot: 1, slotCtrl = 0x811f8
[0.08.01.880]ext0 int trigger
[0.08.01.913]slot: 1, slotCtrl = 0x4815f8
[0.08.02.060]ext0 int trigger
[0.08.07.895]ext0 int trigger
[0.08.07.917]slot: 1, slotCtrl = 0x811f8
[0.08.08.081]ext0 int trigger
[0.08.08.100]slot: 1, slotCtrl = 0x4815f8
[0.08.12.495]ext0 int trigger
[0.08.12.514]slot: 1, slotCtrl = 0x811f8
[0.08.12.667]ext0 int trigger
[0.08.12.686]slot: 1, slotCtrl = 0x4815f8
[0.08.18.695]ext0 int trigger
[0.08.18.714]slot: 1, slotCtrl = 0x811f8
[0.08.18.870]ext0 int trigger
[0.08.18.901]slot: 1, slotCtrl = 0x4815f8
[0.08.19.048]ext0 int trigger
[0.08.19.224]ext0 int trigger
[0.08.19.255]slot: 1, slotCtrl = 0x815f8
[0.08.19.409]ext0 int trigger
[0.08.19.428]slot: 1, slotCtrl = 0x4815f8
[0.08.22.870]IpmiCmdReportPcieMMIO end
pool addr          pool size    used size     free size    max free node size   used node num     free node num      UsageWaterLine
---------------    --------     -------       --------     --------------       -------------      ------------      ------------
0x840908e708       0x204c0      0x19fc8       0x6288       0x41d8               0xd9               0x3                0x1c2a8        
[0.08.22.949]slot[1] port:26 begin to power ON.
[0.08.24.895]ext0 int trigger
[0.08.24.907]slot: 1, slotCtrl = 0x811f8
[0.08.25.015]ext0 int trigger
[0.08.25.028]slot: 1, slotCtrl = 0x4815f8
[0.08.26.343]slot[1] port:26 begin to power ON.
[0.08.27.595]ext0 int trigger
[0.08.27.608]slot: 1, slotCtrl = 0x811f8
[0.08.27.715]ext0 int trigger
[0.08.27.739]slot: 1, slotCtrl = 0x4815f8
[0.08.27.836]ext0 int trigger
[0.08.29.049]slot[1] port:26 begin to power ON.
[0.08.33.795]ext0 int trigger
[0.08.33.807]slot: 1, slotCtrl = 0x811f8
[0.08.33.905]ext0 int trigger
[0.08.33.928]slot: 1, slotCtrl = 0x4815f8
[0.08.34.026]ext0 int trigger
[0.08.35.220]slot[1] port:26 begin to power ON.
[0.08.38.395]ext0 int trigger
[0.08.38.407]slot: 1, slotCtrl = 0x811f8
[0.08.38.505]ext0 int trigger
[0.08.38.528]slot: 1, slotCtrl = 0x4815f8
[0.08.39.864]slot[1] port:26 begin to power ON.
[0.08.44.595]ext0 int trigger
[0.08.44.607]slot: 1, slotCtrl = 0x811f8
[0.08.44.705]ext0 int trigger
[0.08.44.717]slot: 1, slotCtrl = 0x4815f8
[0.08.46.061]slot[1] port:26 begin to power ON.
[0.08.47.295]ext0 int trigger
[0.08.47.307]slot: 1, slotCtrl = 0x811f8
[0.08.47.409]ext0 int trigger
[0.08.47.440]slot: 1, slotCtrl = 0x4815f8
[0.08.47.568]ext0 int trigger
[0.08.47.688]ext0 int trigger
[0.08.47.817]ext0 int trigger
[0.08.48.891]slot[1] port:26 begin to power ON.
[0.08.53.495]ext0 int trigger
[0.08.53.507]slot: 1, slotCtrl = 0x811f8
[0.08.53.604]ext0 int trigger
[0.08.53.617]slot: 1, slotCtrl = 0x4815f8
[0.08.54.924]slot[1] port:26 begin to power ON.
[0.09.04.294]ext0 int trigger
[0.09.04.307]slot: 1, slotCtrl = 0x811f8
[0.09.04.415]ext0 int trigger
[0.09.04.439]slot: 1, slotCtrl = 0x4815f8
[0.09.04.547]ext0 int trigger
[0.09.05.743]slot[1] port:26 begin to power ON.
[0.09.06.994]ext0 int trigger
[0.09.07.007]slot: 1, slotCtrl = 0x811f8
[0.09.07.105]ext0 int trigger
[0.09.07.117]slot: 1, slotCtrl = 0x4815f8
[0.09.08.450]slot[1] port:26 begin to power ON.
[0.09.13.194]ext0 int trigger
[0.09.13.207]slot: 1, slotCtrl = 0x811f8
[0.09.13.305]ext0 int trigger
[0.09.13.328]slot: 1, slotCtrl = 0x4815f8
[0.09.13.436]ext0 int trigger
[0.09.14.531]slot[1] port:26 begin to power ON.
[0.09.19.394]ext0 int trigger
[0.09.19.409]slot: 1, slotCtrl = 0x811f8
[0.09.19.507]ext0 int trigger
[0.09.19.531]slot: 1, slotCtrl = 0x4815f8
[0.09.19.638]ext0 int trigger
[0.09.19.757]ext0 int trigger
[0.09.20.761]slot[1] port:26 begin to power ON.
[0.09.22.794]ext0 int trigger
[0.09.22.807]slot: 1, slotCtrl = 0x811f8
[0.09.22.904]ext0 int trigger
[0.09.22.928]slot: 1, slotCtrl = 0x4815f8
[0.09.23.994]ext0 int trigger
[0.09.24.007]slot: 1, slotCtrl = 0x815f8
[0.09.24.104]ext0 int trigger
[0.09.24.128]slot: 1, slotCtrl = 0x4815f8
[0.09.24.274]slot[1] port:26 begin to power ON.
[0.09.30.194]ext0 int trigger
[0.09.30.207]slot: 1, slotCtrl = 0x811f8
[0.09.30.305]ext0 int trigger
[0.09.30.329]slot: 1, slotCtrl = 0x4815f8
[0.09.31.665]slot[1] port:26 begin to power ON.
[0.09.31.794]ext0 int trigger
[0.09.31.808]slot: 1, slotCtrl = 0x812f8
[0.09.31.917]ext0 int trigger
[0.09.31.930]slot: 1, slotCtrl = 0x4816f8
[0.09.32.089]slot[1] port:26 begin to power ON.
[0.09.32.894]ext0 int trigger
[0.09.32.907]slot: 1, slotCtrl = 0x811f8
[0.09.33.012]ext0 int trigger
[0.09.33.041]slot: 1, slotCtrl = 0x4815f8
[0.09.33.178]ext0 int trigger
[0.09.33.296]ext0 int trigger
[0.09.34.388]slot[1] port:26 begin to power ON.
[0.09.35.694]ext0 int trigger
[0.09.35.707]slot: 1, slotCtrl = 0x811f8
[0.09.35.815]ext0 int trigger
[0.09.35.839]slot: 1, slotCtrl = 0x4815f8
[0.09.37.232]slot[1] port:26 begin to power ON.
[0.09.39.094]ext0 int trigger
[0.09.39.107]slot: 1, slotCtrl = 0x811f8
[0.09.39.204]ext0 int trigger
[0.09.39.233]slot: 1, slotCtrl = 0x4815f8
[0.09.40.550]slot[1] port:26 begin to power ON.
[0.09.41.394]ext0 int trigger
[0.09.41.411]slot: 1, slotCtrl = 0x811f8
[0.09.41.539]ext0 int trigger
[0.09.41.563]slot: 1, slotCtrl = 0x4815f8
[0.09.41.660]ext0 int trigger
[0.09.42.803]slot[1] port:26 begin to power ON.
[0.09.48.694]ext0 int trigger
[0.09.48.707]slot: 1, slotCtrl = 0x811f8
[0.09.48.804]ext0 int trigger
[0.09.48.827]slot: 1, slotCtrl = 0x4815f8
[0.09.48.935]ext0 int trigger
[0.09.49.894]ext0 int trigger
[0.09.49.907]slot: 1, slotCtrl = 0x815f8
[0.09.50.019]ext0 int trigger
[0.09.50.043]slot: 1, slotCtrl = 0x4815f8
[0.09.50.153]ext0 int trigger
[0.09.50.231]slot[1] port:26 begin to power ON.
[0.09.50.278]ext0 int trigger
[0.09.50.396]ext0 int trigger
[0.09.58.294]ext0 int trigger
[0.09.58.307]slot: 1, slotCtrl = 0x811f8
[0.09.58.415]ext0 int trigger
[0.09.58.439]slot: 1, slotCtrl = 0x4815f8
[0.09.58.547]ext0 int trigger
[0.09.58.794]ext0 int trigger
[0.09.58.807]slot: 1, slotCtrl = 0x815f8
[0.09.58.915]ext0 int trigger
[0.09.58.939]slot: 1, slotCtrl = 0x4815f8
[0.09.59.047]ext0 int trigger
[0.09.59.165]ext0 int trigger
[0.09.59.724]slot[1] port:26 begin to power ON.
[0.10.04.994]ext0 int trigger
[0.10.05.007]slot: 1, slotCtrl = 0x811f8
[0.10.05.115]ext0 int trigger
[0.10.05.139]slot: 1, slotCtrl = 0x4815f8
[0.10.05.246]ext0 int trigger
[0.10.05.365]ext0 int trigger
[0.10.05.484]ext0 int trigger
[0.10.05.603]ext0 int trigger
[0.10.06.387]slot[1] port:26 begin to power ON.
[0.10.07.894]ext0 int trigger
[0.10.07.907]slot: 1, slotCtrl = 0x811f8
[0.10.08.015]ext0 int trigger
[0.10.08.039]slot: 1, slotCtrl = 0x4815f8
[0.10.08.147]ext0 int trigger
[0.10.09.357]slot[1] port:26 begin to power ON.
[0.10.09.594]ext0 int trigger
[0.10.09.607]slot: 1, slotCtrl = 0x812f8
[0.10.09.715]ext0 int trigger
[0.10.09.738]slot: 1, slotCtrl = 0x4815f8
[0.10.09.835]ext0 int trigger
[0.10.09.954]ext0 int trigger
[0.10.11.132]slot[1] port:26 begin to power ON.
[0.10.15.794]ext0 int trigger
[0.10.15.807]slot: 1, slotCtrl = 0x811f8
[0.10.15.915]ext0 int trigger
[0.10.15.928]slot: 1, slotCtrl = 0x4815f8
[0.10.17.206]slot[1] port:26 begin to power ON.
[0.10.24.194]ext0 int trigger
[0.10.24.207]slot: 1, slotCtrl = 0x811f8
[0.10.24.304]ext0 int trigger
[0.10.24.318]slot: 1, slotCtrl = 0x4815f8
[0.10.24.694]ext0 int trigger
[0.10.24.706]slot: 1, slotCtrl = 0x815f8
[0.10.24.804]ext0 int trigger
[0.10.24.827]slot: 1, slotCtrl = 0x4815f8
[0.10.24.944]ext0 int trigger
[0.10.25.085]ext0 int trigger
[0.10.25.584]slot[1] port:26 begin to power ON.
[0.10.35.494]ext0 int trigger
[0.10.35.507]slot: 1, slotCtrl = 0x811f8
[0.10.35.606]ext0 int trigger
[0.10.35.619]slot: 1, slotCtrl = 0x4815f8
[0.10.36.983]slot[1] port:26 begin to power ON.
[0.10.50.094]ext0 int trigger
[0.10.50.106]slot: 1, slotCtrl = 0x811f8
[0.10.50.203]ext0 int trigger
[0.10.50.227]slot: 1, slotCtrl = 0x4815f8
[0.10.50.335]ext0 int trigger
[0.10.50.454]ext0 int trigger
[0.10.51.386]slot[1] port:26 begin to power ON.
[0.11.01.393]ext0 int trigger
[0.11.01.407]slot: 1, slotCtrl = 0x811f8
[0.11.01.506]ext0 int trigger
[0.11.01.520]slot: 1, slotCtrl = 0x4815f8
[0.11.02.824]slot[1] port:26 begin to power ON.
[0.11.09.793]ext0 int trigger
[0.11.09.808]slot: 1, slotCtrl = 0x811f8
[0.11.09.915]ext0 int trigger
[0.11.09.950]slot: 1, slotCtrl = 0x4815f8
[0.11.10.047]ext0 int trigger
[0.11.10.165]ext0 int trigger
[0.11.10.284]ext0 int trigger
[0.11.10.402]ext0 int trigger
[0.11.11.205]slot[1] port:26 begin to power ON.
[0.11.15.993]ext0 int trigger
[0.11.16.007]slot: 1, slotCtrl = 0x811f8
[0.11.16.117]ext0 int trigger
[0.11.16.140]slot: 1, slotCtrl = 0x4815f8
[0.11.17.337]slot[1] port:26 begin to power ON.
[0.11.17.693]ext0 int trigger
[0.11.17.706]slot: 1, slotCtrl = 0x812f8
[0.11.17.804]ext0 int trigger
[0.11.17.828]slot: 1, slotCtrl = 0x4815f8
[0.11.19.134]slot[1] port:26 begin to power ON.
[0.11.23.793]ext0 int trigger
[0.11.23.806]slot: 1, slotCtrl = 0x811f8
[0.11.23.917]ext0 int trigger
[0.11.23.930]slot: 1, slotCtrl = 0x4815f8
[0.11.25.331]slot[1] port:26 begin to power ON.
[0.11.35.693]ext0 int trigger
[0.11.35.706]slot: 1, slotCtrl = 0x811f8
[0.11.35.806]ext0 int trigger
[0.11.35.819]slot: 1, slotCtrl = 0x4815f8
[0.11.35.918]ext0 int trigger
[0.11.37.257]slot[1] port:26 begin to power ON.
[0.11.47.993]ext0 int trigger
[0.11.48.006]slot: 1, slotCtrl = 0x811f8
[0.11.48.104]ext0 int trigger
[0.11.48.128]slot: 1, slotCtrl = 0x4815f8
[0.11.48.235]ext0 int trigger
[0.11.48.354]ext0 int trigger
[0.11.48.473]ext0 int trigger
[0.11.49.522]slot[1] port:26 begin to power ON.
[0.11.55.393]ext0 int trigger
[0.11.55.406]slot: 1, slotCtrl = 0x811f8
[0.11.55.503]ext0 int trigger
[0.11.55.526]slot: 1, slotCtrl = 0x4815f8
[0.11.55.635]ext0 int trigger
[0.11.55.753]ext0 int trigger
[0.11.56.761]slot[1] port:26 begin to power ON.
[0.12.01.593]ext0 int trigger
[0.12.01.606]slot: 1, slotCtrl = 0x811f8
[0.12.01.703]ext0 int trigger
[0.12.01.727]slot: 1, slotCtrl = 0x4815f8
[0.12.02.942]slot[1] port:26 begin to power ON.
[0.12.13.893]ext0 int trigger
[0.12.13.906]slot: 1, slotCtrl = 0x811f8
[0.12.14.005]ext0 int trigger
[0.12.14.029]slot: 1, slotCtrl = 0x4815f8
[0.12.14.128]ext0 int trigger
[0.12.15.093]ext0 int trigger
[0.12.15.106]slot: 1, slotCtrl = 0x815f8
[0.12.15.214]ext0 int trigger
[0.12.15.238]slot: 1, slotCtrl = 0x4815f8
[0.12.15.335]ext0 int trigger
[0.12.15.408]slot[1] port:26 begin to power ON.
[0.12.21.293]ext0 int trigger
[0.12.21.316]slot: 1, slotCtrl = 0x811f8
[0.12.21.414]ext0 int trigger
[0.12.21.438]slot: 1, slotCtrl = 0x4815f8
[0.12.22.663]slot[1] port:26 begin to power ON.
[0.12.40.993]ext0 int trigger
[0.12.41.006]slot: 1, slotCtrl = 0x811f8
[0.12.41.103]ext0 int trigger
[0.12.41.127]slot: 1, slotCtrl = 0x4815f8
[0.12.42.419]slot[1] port:26 begin to power ON.
[0.12.47.193]ext0 int trigger
[0.12.47.206]slot: 1, slotCtrl = 0x811f8
[0.12.47.305]ext0 int trigger
[0.12.47.329]slot: 1, slotCtrl = 0x4815f8
[0.12.47.438]ext0 int trigger
[0.12.47.557]ext0 int trigger
[0.12.47.675]ext0 int trigger
[0.12.47.793]ext0 int trigger
[0.12.47.956]ext0 int trigger
[0.12.48.078]ext0 int trigger
[0.12.48.674]slot[1] port:26 begin to power ON.
[0.12.50.593]ext0 int trigger
[0.12.50.605]slot: 1, slotCtrl = 0x811f8
[0.12.50.713]ext0 int trigger
[0.12.50.737]slot: 1, slotCtrl = 0x4815f8
[0.12.50.834]ext0 int trigger
[0.12.51.905]slot[1] port:26 begin to power ON.
[0.12.55.593]ext0 int trigger
[0.12.55.606]slot: 1, slotCtrl = 0x811f8
[0.12.55.715]ext0 int trigger
[0.12.55.739]slot: 1, slotCtrl = 0x4815f8
[0.12.57.092]slot[1] port:26 begin to power ON.
[0.12.59.593]ext0 int trigger
[0.12.59.605]slot: 1, slotCtrl = 0x811f8
[0.12.59.713]ext0 int trigger
[0.12.59.737]slot: 1, slotCtrl = 0x4815f8
[0.13.01.051]slot[1] port:26 begin to power ON.
[0.13.03.492]ext0 int trigger
[0.13.03.505]slot: 1, slotCtrl = 0x811f8
[0.13.03.602]ext0 int trigger
[0.13.03.626]slot: 1, slotCtrl = 0x4815f8
[0.13.03.734]ext0 int trigger
[0.13.04.840]slot[1] port:26 begin to power ON.
[0.13.06.892]ext0 int trigger
[0.13.06.905]slot: 1, slotCtrl = 0x811f8
[0.13.07.003]ext0 int trigger
[0.13.07.037]slot: 1, slotCtrl = 0x4815f8
[0.13.07.155]ext0 int trigger
[0.13.07.282]ext0 int trigger
[0.13.08.178]slot[1] port:26 begin to power ON.
[0.13.21.492]ext0 int trigger
[0.13.21.506]slot: 1, slotCtrl = 0x811f8
[0.13.21.615]ext0 int trigger
[0.13.21.639]slot: 1, slotCtrl = 0x4815f8
[0.13.21.739]ext0 int trigger
[0.13.21.859]ext0 int trigger
[0.13.22.878]slot[1] port:26 begin to power ON.
[0.13.32.792]ext0 int trigger
[0.13.32.805]slot: 1, slotCtrl = 0x811f8
[0.13.32.902]ext0 int trigger
[0.13.32.926]slot: 1, slotCtrl = 0x4815f8
[0.13.33.023]ext0 int trigger
[0.13.34.193]slot[1] port:26 begin to power ON.
[0.13.41.192]ext0 int trigger
[0.13.41.205]slot: 1, slotCtrl = 0x811f8
[0.13.41.305]ext0 int trigger
[0.13.41.329]slot: 1, slotCtrl = 0x4815f8
[0.13.42.727]slot[1] port:26 begin to power ON.
[0.13.47.392]ext0 int trigger
[0.13.47.405]slot: 1, slotCtrl = 0x811f8
[0.13.47.513]ext0 int trigger
[0.13.47.537]slot: 1, slotCtrl = 0x4815f8
[0.13.47.645]ext0 int trigger
[0.13.48.773]slot[1] port:26 begin to power ON.
[0.13.54.092]ext0 int trigger
[0.13.54.111]slot: 1, slotCtrl = 0x811f8
[0.13.54.239]ext0 int trigger
[0.13.54.273]slot: 1, slotCtrl = 0x4815f8
[0.13.54.371]ext0 int trigger
[0.13.54.489]ext0 int trigger
[0.13.55.501]slot[1] port:26 begin to power ON.
[0.14.00.892]ext0 int trigger
[0.14.00.905]slot: 1, slotCtrl = 0x811f8
[0.14.01.016]ext0 int trigger
[0.14.01.039]slot: 1, slotCtrl = 0x4815f8
[0.14.02.397]slot[1] port:26 begin to power ON.
[0.14.07.092]ext0 int trigger
[0.14.07.105]slot: 1, slotCtrl = 0x811f8
[0.14.07.202]ext0 int trigger
[0.14.07.226]slot: 1, slotCtrl = 0x4815f8
[0.14.08.475]slot[1] port:26 begin to power ON.
[0.14.20.592]ext0 int trigger
[0.14.20.605]slot: 1, slotCtrl = 0x811f8
[0.14.20.702]ext0 int trigger
[0.14.20.725]slot: 1, slotCtrl = 0x4815f8
[0.14.20.823]ext0 int trigger
[0.14.22.017]slot[1] port:26 begin to power ON.
[0.14.26.792]ext0 int trigger
[0.14.26.805]slot: 1, slotCtrl = 0x811f8
[0.14.26.902]ext0 int trigger
[0.14.26.925]slot: 1, slotCtrl = 0x4815f8
[0.14.27.034]ext0 int trigger
[0.14.28.057]slot[1] port:26 begin to power ON.
[0.14.32.992]ext0 int trigger
[0.14.33.005]slot: 1, slotCtrl = 0x811f8
[0.14.33.115]ext0 int trigger
[0.14.33.139]slot: 1, slotCtrl = 0x4815f8
[0.14.34.453]slot[1] port:26 begin to power ON.
[0.14.36.392]ext0 int trigger
[0.14.36.409]slot: 1, slotCtrl = 0x811f8
[0.14.36.512]ext0 int trigger
[0.14.36.538]slot: 1, slotCtrl = 0x4815f8
[0.14.36.646]ext0 int trigger
[0.14.37.753]slot[1] port:26 begin to power ON.
[0.14.45.392]ext0 int trigger
[0.14.45.405]slot: 1, slotCtrl = 0x811f8
[0.14.45.515]ext0 int trigger
[0.14.45.539]slot: 1, slotCtrl = 0x4815f8
[0.14.45.659]ext0 int trigger
[0.14.45.768]ext0 int trigger
[0.14.46.492]ext0 int trigger
[0.14.46.504]slot: 1, slotCtrl = 0x815f8
[0.14.46.602]ext0 int trigger
[0.14.46.626]slot: 1, slotCtrl = 0x4815f8
[0.14.46.858]slot[1] port:26 begin to power ON.
[0.14.49.292]ext0 int trigger
[0.14.49.304]slot: 1, slotCtrl = 0x811f8
[0.14.49.407]ext0 int trigger
[0.14.49.430]slot: 1, slotCtrl = 0x4815f8
[0.14.49.539]ext0 int trigger
[0.14.50.675]slot[1] port:26 begin to power ON.
[0.14.52.692]ext0 int trigger
[0.14.52.704]slot: 1, slotCtrl = 0x811f8
[0.14.52.821]ext0 int trigger
[0.14.52.845]slot: 1, slotCtrl = 0x4815f8
[0.14.52.943]ext0 int trigger
[0.14.54.028]slot[1] port:26 begin to power ON.
[0.14.54.992]ext0 int trigger
[0.14.55.004]slot: 1, slotCtrl = 0x811f8
[0.14.55.112]ext0 int trigger
[0.14.55.136]slot: 1, slotCtrl = 0x4815f8
[0.14.55.244]ext0 int trigger
[0.14.56.342]slot[1] port:26 begin to power ON.
[0.15.01.092]ext0 int trigger
[0.15.01.104]slot: 1, slotCtrl = 0x811f8
[0.15.01.202]ext0 int trigger
[0.15.01.214]slot: 1, slotCtrl = 0x4815f8
[0.15.02.292]ext0 int trigger
[0.15.02.304]slot: 1, slotCtrl = 0x815f8
[0.15.02.401]ext0 int trigger
[0.15.02.430]slot: 1, slotCtrl = 0x4815f8
[0.15.02.563]ext0 int trigger
[0.15.02.635]slot[1] port:26 begin to power ON.
[0.15.02.688]ext0 int trigger
[0.15.07.291]ext0 int trigger
[0.15.07.304]slot: 1, slotCtrl = 0x811f8
[0.15.07.402]ext0 int trigger
[0.15.07.425]slot: 1, slotCtrl = 0x4815f8
[0.15.08.610]slot[1] port:26 begin to power ON.
[0.15.11.891]ext0 int trigger
[0.15.11.905]slot: 1, slotCtrl = 0x811f8
[0.15.12.004]ext0 int trigger
[0.15.12.028]slot: 1, slotCtrl = 0x4815f8
[0.15.12.138]ext0 int trigger
[0.15.12.246]ext0 int trigger
[0.15.13.301]slot[1] port:26 begin to power ON.
[0.15.18.591]ext0 int trigger
[0.15.18.604]slot: 1, slotCtrl = 0x811f8
[0.15.18.712]ext0 int trigger
[0.15.18.736]slot: 1, slotCtrl = 0x4815f8
[0.15.19.921]slot[1] port:26 begin to power ON.
[0.15.26.991]ext0 int trigger
[0.15.27.004]slot: 1, slotCtrl = 0x811f8
[0.15.27.116]ext0 int trigger
[0.15.27.140]slot: 1, slotCtrl = 0x4815f8
[0.15.28.296]slot[1] port:26 begin to power ON.
[0.15.33.191]ext0 int trigger
[0.15.33.204]slot: 1, slotCtrl = 0x811f8
[0.15.33.302]ext0 int trigger
[0.15.33.315]slot: 1, slotCtrl = 0x4815f8
[0.15.34.585]slot[1] port:26 begin to power ON.
[0.15.37.791]ext0 int trigger
[0.15.37.805]slot: 1, slotCtrl = 0x811f8
[0.15.37.903]ext0 int trigger
[0.15.37.926]slot: 1, slotCtrl = 0x4815f8
[0.15.38.024]ext0 int trigger
[0.15.39.251]slot[1] port:26 begin to power ON.
[0.15.43.991]ext0 int trigger
[0.15.44.004]slot: 1, slotCtrl = 0x811f8
[0.15.44.112]ext0 int trigger
[0.15.44.146]slot: 1, slotCtrl = 0x4815f8
[0.15.44.254]ext0 int trigger
[0.15.44.372]ext0 int trigger
[0.15.44.490]ext0 int trigger
[0.15.44.608]ext0 int trigger
[0.15.45.484]slot[1] port:26 begin to power ON.
[0.15.46.691]ext0 int trigger
[0.15.46.706]slot: 1, slotCtrl = 0x811f8
[0.15.46.803]ext0 int trigger
[0.15.46.827]slot: 1, slotCtrl = 0x4815f8
[0.15.46.939]ext0 int trigger
[0.15.47.057]ext0 int trigger
[0.15.48.132]slot[1] port:26 begin to power ON.
[0.15.52.891]ext0 int trigger
[0.15.52.904]slot: 1, slotCtrl = 0x811f8
[0.15.53.008]ext0 int trigger
[0.15.53.022]slot: 1, slotCtrl = 0x4815f8
[0.15.54.310]slot[1] port:26 begin to power ON.
[0.16.03.691]ext0 int trigger
[0.16.03.704]slot: 1, slotCtrl = 0x811f8
[0.16.03.801]ext0 int trigger
[0.16.03.825]slot: 1, slotCtrl = 0x4815f8
[0.16.03.922]ext0 int trigger
[0.16.05.031]slot[1] port:26 begin to power ON.
[0.16.06.391]ext0 int trigger
[0.16.06.404]slot: 1, slotCtrl = 0x811f8
[0.16.06.512]ext0 int trigger
[0.16.06.525]slot: 1, slotCtrl = 0x4815f8
[0.16.07.747]slot[1] port:26 begin to power ON.
[0.16.12.591]ext0 int trigger
[0.16.12.604]slot: 1, slotCtrl = 0x811f8
[0.16.12.701]ext0 int trigger
[0.16.12.725]slot: 1, slotCtrl = 0x4815f8
[0.16.14.022]slot[1] port:26 begin to power ON.
[0.16.18.791]ext0 int trigger
[0.16.18.804]slot: 1, slotCtrl = 0x811f8
[0.16.18.901]ext0 int trigger
[0.16.18.924]slot: 1, slotCtrl = 0x4815f8
[0.16.20.115]slot[1] port:26 begin to power ON.
[0.16.23.391]ext0 int trigger
[0.16.23.404]slot: 1, slotCtrl = 0x811f8
[0.16.23.502]ext0 int trigger
[0.16.23.525]slot: 1, slotCtrl = 0x4815f8
[0.16.24.851]slot[1] port:26 begin to power ON.
[0.16.29.591]ext0 int trigger
[0.16.29.604]slot: 1, slotCtrl = 0x811f8
[0.16.29.712]ext0 int trigger
[0.16.29.735]slot: 1, slotCtrl = 0x4815f8
[0.16.29.843]ext0 int trigger
[0.16.30.873]slot[1] port:26 begin to power ON.
[0.16.32.291]ext0 int trigger
[0.16.32.304]slot: 1, slotCtrl = 0x811f8
[0.16.32.412]ext0 int trigger
[0.16.32.435]slot: 1, slotCtrl = 0x4815f8
[0.16.32.533]ext0 int trigger
[0.16.32.651]ext0 int trigger
[0.16.32.770]ext0 int trigger
[0.16.32.889]ext0 int trigger
[0.16.33.007]ext0 int trigger
[0.16.33.600]slot[1] port:26 begin to power ON.
[0.16.35.091]ext0 int trigger
[0.16.35.104]slot: 1, slotCtrl = 0x811f8
[0.16.35.212]ext0 int trigger
[0.16.35.235]slot: 1, slotCtrl = 0x4815f8
[0.16.35.344]ext0 int trigger
[0.16.36.435]slot[1] port:26 begin to power ON.
[0.16.37.391]ext0 int trigger
[0.16.37.407]slot: 1, slotCtrl = 0x811f8
[0.16.37.519]ext0 int trigger
[0.16.37.543]slot: 1, slotCtrl = 0x4815f8
[0.16.38.491]ext0 int trigger
[0.16.38.504]slot: 1, slotCtrl = 0x815f8
[0.16.38.601]ext0 int trigger
[0.16.38.625]slot: 1, slotCtrl = 0x4815f8
[0.16.38.723]ext0 int trigger
[0.16.38.778]slot[1] port:26 begin to power ON.
[0.16.40.791]ext0 int trigger
[0.16.40.804]slot: 1, slotCtrl = 0x811f8
[0.16.40.901]ext0 int trigger
[0.16.40.924]slot: 1, slotCtrl = 0x4815f8
[0.16.41.032]ext0 int trigger
[0.16.41.151]ext0 int trigger
[0.16.41.269]ext0 int trigger
[0.16.41.397]ext0 int trigger
[0.16.42.184]slot[1] port:26 begin to power ON.
[0.16.49.291]ext0 int trigger
[0.16.49.303]slot: 1, slotCtrl = 0x811f8
[0.16.49.411]ext0 int trigger
[0.16.49.435]slot: 1, slotCtrl = 0x4815f8
[0.16.49.539]ext0 int trigger
[0.16.50.651]slot[1] port:26 begin to power ON.
[0.16.51.991]ext0 int trigger
[0.16.52.003]slot: 1, slotCtrl = 0x811f8
[0.16.52.114]ext0 int trigger
[0.16.52.138]slot: 1, slotCtrl = 0x4815f8
[0.16.52.274]ext0 int trigger
[0.16.52.392]ext0 int trigger
[0.16.52.510]ext0 int trigger
[0.16.52.629]ext0 int trigger
[0.16.53.389]slot[1] port:26 begin to power ON.
[0.16.58.191]ext0 int trigger
[0.16.58.203]slot: 1, slotCtrl = 0x811f8
[0.16.58.301]ext0 int trigger
[0.16.58.325]slot: 1, slotCtrl = 0x4815f8
[0.16.59.615]slot[1] port:26 begin to power ON.
[0.17.04.391]ext0 int trigger
[0.17.04.403]slot: 1, slotCtrl = 0x811f8
[0.17.04.501]ext0 int trigger
[0.17.04.524]slot: 1, slotCtrl = 0x4815f8
[0.17.04.639]ext0 int trigger
[0.17.04.787]ext0 int trigger
[0.17.05.777]slot[1] port:26 begin to power ON.
[0.17.08.991]ext0 int trigger
[0.17.09.003]slot: 1, slotCtrl = 0x811f8
[0.17.09.100]ext0 int trigger
[0.17.09.124]slot: 1, slotCtrl = 0x4815f8
[0.17.10.346]slot[1] port:26 begin to power ON.
[0.17.15.190]ext0 int trigger
[0.17.15.203]slot: 1, slotCtrl = 0x811f8
[0.17.15.302]ext0 int trigger
[0.17.15.325]slot: 1, slotCtrl = 0x4815f8
[0.17.15.423]ext0 int trigger
[0.17.16.518]slot[1] port:26 begin to power ON.
[0.17.17.890]ext0 int trigger
[0.17.17.903]slot: 1, slotCtrl = 0x811f8
[0.17.18.007]ext0 int trigger
[0.17.18.031]slot: 1, slotCtrl = 0x4815f8
[0.17.18.128]ext0 int trigger
[0.17.19.289]slot[1] port:26 begin to power ON.
[0.17.24.090]ext0 int trigger
[0.17.24.103]slot: 1, slotCtrl = 0x811f8
[0.17.24.211]ext0 int trigger
[0.17.24.235]slot: 1, slotCtrl = 0x4815f8
[0.17.24.332]ext0 int trigger
[0.17.25.465]slot[1] port:26 begin to power ON.
[0.17.28.690]ext0 int trigger
[0.17.28.703]slot: 1, slotCtrl = 0x811f8
[0.17.28.802]ext0 int trigger
[0.17.28.825]slot: 1, slotCtrl = 0x4815f8
[0.17.28.933]ext0 int trigger
[0.17.29.986]slot[1] port:26 begin to power ON.
[0.17.34.890]ext0 int trigger
[0.17.34.903]slot: 1, slotCtrl = 0x811f8
[0.17.35.017]ext0 int trigger
[0.17.35.040]slot: 1, slotCtrl = 0x4815f8
[0.17.35.137]ext0 int trigger
[0.17.36.231]slot[1] port:26 begin to power ON.
[0.17.43.790]ext0 int trigger
[0.17.43.803]slot: 1, slotCtrl = 0x811f8
[0.17.43.900]ext0 int trigger
[0.17.43.913]slot: 1, slotCtrl = 0x4815f8
[0.17.45.169]slot[1] port:26 begin to power ON.
[0.17.54.590]ext0 int trigger
[0.17.54.603]slot: 1, slotCtrl = 0x811f8
[0.17.54.701]ext0 int trigger
[0.17.54.714]slot: 1, slotCtrl = 0x4815f8
[0.17.55.961]slot[1] port:26 begin to power ON.
[0.18.00.790]ext0 int trigger
[0.18.00.803]slot: 1, slotCtrl = 0x811f8
[0.18.00.900]ext0 int trigger
[0.18.00.926]slot: 1, slotCtrl = 0x4815f8
[0.18.01.025]ext0 int trigger
[0.18.02.202]slot[1] port:26 begin to power ON.
[0.18.09.190]ext0 int trigger
[0.18.09.203]slot: 1, slotCtrl = 0x811f8
[0.18.09.311]ext0 int trigger
[0.18.09.335]slot: 1, slotCtrl = 0x4815f8
[0.18.09.442]ext0 int trigger
[0.18.09.690]ext0 int trigger
[0.18.09.703]slot: 1, slotCtrl = 0x815f8
[0.18.09.811]ext0 int trigger
[0.18.09.835]slot: 1, slotCtrl = 0x4815f8
[0.18.10.614]slot[1] port:26 begin to power ON.
[0.18.14.290]ext0 int trigger
[0.18.14.303]slot: 1, slotCtrl = 0x811f8
[0.18.14.402]ext0 int trigger
[0.18.14.426]slot: 1, slotCtrl = 0x4815f8
[0.18.15.794]slot[1] port:26 begin to power ON.
[0.18.17.090]ext0 int trigger
[0.18.17.105]slot: 1, slotCtrl = 0x811f8
[0.18.17.238]ext0 int trigger
[0.18.17.262]slot: 1, slotCtrl = 0x4815f8
[0.18.18.376]slot[1] port:26 begin to power ON.
[0.18.20.490]ext0 int trigger
[0.18.20.503]slot: 1, slotCtrl = 0x811f8
[0.18.20.611]ext0 int trigger
[0.18.20.634]slot: 1, slotCtrl = 0x4815f8
[0.18.20.742]ext0 int trigger
[0.18.21.989]slot[1] port:26 begin to power ON.
[0.18.23.190]ext0 int trigger
[0.18.23.203]slot: 1, slotCtrl = 0x811f8
[0.18.23.311]ext0 int trigger
[0.18.23.345]slot: 1, slotCtrl = 0x4815f8
[0.18.23.489]ext0 int trigger
[0.18.24.546]slot[1] port:26 begin to power ON.
[0.18.28.890]ext0 int trigger
[0.18.28.903]slot: 1, slotCtrl = 0x811f8
[0.18.29.000]ext0 int trigger
[0.18.29.023]slot: 1, slotCtrl = 0x4815f8
[0.18.29.122]ext0 int trigger
[0.18.29.240]ext0 int trigger
[0.18.30.240]slot[1] port:26 begin to power ON.
[0.18.40.190]ext0 int trigger
[0.18.40.203]slot: 1, slotCtrl = 0x811f8
[0.18.40.313]ext0 int trigger
[0.18.40.337]slot: 1, slotCtrl = 0x4815f8
[0.18.40.436]ext0 int trigger
[0.18.41.714]slot[1] port:26 begin to power ON.
[0.18.46.390]ext0 int trigger
[0.18.46.403]slot: 1, slotCtrl = 0x811f8
[0.18.46.500]ext0 int trigger
[0.18.46.523]slot: 1, slotCtrl = 0x4815f8
[0.18.46.621]ext0 int trigger
[0.18.47.390]ext0 int trigger
[0.18.47.403]slot: 1, slotCtrl = 0x815f8
[0.18.47.510]ext0 int trigger
[0.18.47.534]slot: 1, slotCtrl = 0x4815f8
[0.18.47.642]ext0 int trigger
[0.18.47.837]slot[1] port:26 begin to power ON.
[0.18.54.790]ext0 int trigger
[0.18.54.802]slot: 1, slotCtrl = 0x811f8
[0.18.54.910]ext0 int trigger
[0.18.54.934]slot: 1, slotCtrl = 0x4815f8
[0.18.55.042]ext0 int trigger
[0.18.55.160]ext0 int trigger
[0.18.56.231]slot[1] port:26 begin to power ON.
[0.19.06.090]ext0 int trigger
[0.19.06.103]slot: 1, slotCtrl = 0x811f8
[0.19.06.203]ext0 int trigger
[0.19.06.216]slot: 1, slotCtrl = 0x4815f8
[0.19.07.540]slot[1] port:26 begin to power ON.
[0.19.07.690]ext0 int trigger
[0.19.07.702]slot: 1, slotCtrl = 0x812f8
[0.19.07.810]ext0 int trigger
[0.19.07.834]slot: 1, slotCtrl = 0x4816f8
[0.19.07.966]slot[1] port:26 begin to power ON.
[0.19.14.490]ext0 int trigger
[0.19.14.503]slot: 1, slotCtrl = 0x811f8
[0.19.14.613]ext0 int trigger
[0.19.14.637]slot: 1, slotCtrl = 0x4815f8
[0.19.14.752]ext0 int trigger
[0.19.14.870]ext0 int trigger
[0.19.15.947]slot[1] port:26 begin to power ON.
[0.19.20.689]ext0 int trigger
[0.19.20.702]slot: 1, slotCtrl = 0x811f8
[0.19.20.804]ext0 int trigger
[0.19.20.828]slot: 1, slotCtrl = 0x4815f8
[0.19.20.935]ext0 int trigger
[0.19.21.054]ext0 int trigger
[0.19.21.172]ext0 int trigger
[0.19.21.290]ext0 int trigger
[0.19.21.995]slot[1] port:26 begin to power ON.
[0.19.34.189]ext0 int trigger
[0.19.34.204]slot: 1, slotCtrl = 0x811f8
[0.19.34.312]ext0 int trigger
[0.19.34.336]slot: 1, slotCtrl = 0x4815f8
[0.19.34.444]ext0 int trigger
[0.19.34.563]ext0 int trigger
[0.19.35.593]slot[1] port:26 begin to power ON.
[0.19.40.389]ext0 int trigger
[0.19.40.402]slot: 1, slotCtrl = 0x811f8
[0.19.40.510]ext0 int trigger
[0.19.40.534]slot: 1, slotCtrl = 0x4815f8
[0.19.40.642]ext0 int trigger
[0.19.41.725]slot[1] port:26 begin to power ON.
[0.19.46.589]ext0 int trigger
[0.19.46.602]slot: 1, slotCtrl = 0x811f8
[0.19.46.701]ext0 int trigger
[0.19.46.725]slot: 1, slotCtrl = 0x4815f8
[0.19.46.824]ext0 int trigger
[0.19.46.942]ext0 int trigger
[0.19.47.073]ext0 int trigger
[0.19.47.191]ext0 int trigger
[0.19.47.310]ext0 int trigger
[0.19.47.428]ext0 int trigger
[0.19.47.546]ext0 int trigger
[0.19.47.665]ext0 int trigger
[0.19.47.783]ext0 int trigger
[0.19.48.042]slot[1] port:26 begin to power ON.
[0.19.53.289]ext0 int trigger
[0.19.53.302]slot: 1, slotCtrl = 0x811f8
[0.19.53.400]ext0 int trigger
[0.19.53.423]slot: 1, slotCtrl = 0x4815f8
[0.19.53.521]ext0 int trigger
[0.19.54.619]slot[1] port:26 begin to power ON.
[0.19.57.189]ext0 int trigger
[0.19.57.202]slot: 1, slotCtrl = 0x811f8
[0.19.57.300]ext0 int trigger
[0.19.57.313]slot: 1, slotCtrl = 0x4815f8
[0.19.58.758]slot[1] port:26 begin to power ON.
[0.20.00.089]ext0 int trigger
[0.20.00.102]slot: 1, slotCtrl = 0x811f8
[0.20.00.210]ext0 int trigger
[0.20.00.234]slot: 1, slotCtrl = 0x4815f8
[0.20.01.470]slot[1] port:26 begin to power ON.
[0.20.02.889]ext0 int trigger
[0.20.02.903]slot: 1, slotCtrl = 0x811f8
[0.20.03.011]ext0 int trigger
[0.20.03.034]slot: 1, slotCtrl = 0x4815f8
[0.20.04.237]slot[1] port:26 begin to power ON.
[0.20.05.189]ext0 int trigger
[0.20.05.202]slot: 1, slotCtrl = 0x811f8
[0.20.05.310]ext0 int trigger
[0.20.05.334]slot: 1, slotCtrl = 0x4815f8
[0.20.05.444]ext0 int trigger
[0.20.06.289]ext0 int trigger
[0.20.06.302]slot: 1, slotCtrl = 0x815f8
[0.20.06.399]ext0 int trigger
[0.20.06.423]slot: 1, slotCtrl = 0x4815f8
[0.20.06.452]slot[1] port:26 begin to power ON.
[0.20.19.789]ext0 int trigger
[0.20.19.802]slot: 1, slotCtrl = 0x811f8
[0.20.19.911]ext0 int trigger
[0.20.19.935]slot: 1, slotCtrl = 0x4815f8
[0.20.21.132]slot[1] port:26 begin to power ON.
[0.20.25.989]ext0 int trigger
[0.20.26.002]slot: 1, slotCtrl = 0x811f8
[0.20.26.099]ext0 int trigger
[0.20.26.123]slot: 1, slotCtrl = 0x4815f8
[0.20.27.321]slot[1] port:26 begin to power ON.
[0.20.29.389]ext0 int trigger
[0.20.29.402]slot: 1, slotCtrl = 0x811f8
[0.20.29.511]ext0 int trigger
[0.20.29.535]slot: 1, slotCtrl = 0x4815f8
[0.20.29.642]ext0 int trigger
[0.20.30.717]slot[1] port:26 begin to power ON.
[0.20.32.189]ext0 int trigger
[0.20.32.202]slot: 1, slotCtrl = 0x811f8
[0.20.32.310]ext0 int trigger
[0.20.32.333]slot: 1, slotCtrl = 0x4815f8
[0.20.33.622]slot[1] port:26 begin to power ON.
[0.20.45.689]ext0 int trigger
[0.20.45.702]slot: 1, slotCtrl = 0x811f8
[0.20.45.800]ext0 int trigger
[0.20.45.812]slot: 1, slotCtrl = 0x4815f8
[0.20.47.028]slot[1] port:26 begin to power ON.
[0.20.51.889]ext0 int trigger
[0.20.51.902]slot: 1, slotCtrl = 0x811f8
[0.20.52.009]ext0 int trigger
[0.20.52.033]slot: 1, slotCtrl = 0x4815f8
[0.20.53.345]slot[1] port:26 begin to power ON.
[0.21.11.589]ext0 int trigger
[0.21.11.601]slot: 1, slotCtrl = 0x811f8
[0.21.11.710]ext0 int trigger
[0.21.11.734]slot: 1, slotCtrl = 0x4815f8
[0.21.11.831]ext0 int trigger
[0.21.12.924]slot[1] port:26 begin to power ON.
[0.21.31.288]ext0 int trigger
[0.21.31.302]slot: 1, slotCtrl = 0x811f8
[0.21.31.412]ext0 int trigger
[0.21.31.425]slot: 1, slotCtrl = 0x4815f8
[0.21.32.767]slot[1] port:26 begin to power ON.
[0.21.37.488]ext0 int trigger
[0.21.37.501]slot: 1, slotCtrl = 0x811f8
[0.21.37.613]ext0 int trigger
[0.21.37.637]slot: 1, slotCtrl = 0x4815f8
[0.21.37.747]ext0 int trigger
[0.21.37.865]ext0 int trigger
[0.21.37.983]ext0 int trigger
[0.21.38.958]slot[1] port:26 begin to power ON.
[0.21.39.188]ext0 int trigger
[0.21.39.201]slot: 1, slotCtrl = 0x812f8
[0.21.39.309]ext0 int trigger
[0.21.39.333]slot: 1, slotCtrl = 0x4815f8
[0.21.39.445]ext0 int trigger
[0.21.40.688]slot[1] port:26 begin to power ON.
[0.21.45.288]ext0 int trigger
[0.21.45.301]slot: 1, slotCtrl = 0x811f8
[0.21.45.409]ext0 int trigger
[0.21.45.433]slot: 1, slotCtrl = 0x4815f8
[0.21.45.540]ext0 int trigger
[0.21.46.636]slot[1] port:26 begin to power ON.
[0.21.57.188]ext0 int trigger
[0.21.57.201]slot: 1, slotCtrl = 0x811f8
[0.21.57.310]ext0 int trigger
[0.21.57.333]slot: 1, slotCtrl = 0x4815f8
[0.21.57.432]ext0 int trigger
[0.21.57.565]ext0 int trigger
[0.21.57.683]ext0 int trigger
[0.21.58.625]slot[1] port:26 begin to power ON.
[0.22.09.488]ext0 int trigger
[0.22.09.501]slot: 1, slotCtrl = 0x811f8
[0.22.09.598]ext0 int trigger
[0.22.09.611]slot: 1, slotCtrl = 0x4815f8
[0.22.10.770]slot[1] port:26 begin to power ON.
[0.22.16.888]ext0 int trigger
[0.22.16.901]slot: 1, slotCtrl = 0x811f8
[0.22.17.009]ext0 int trigger
[0.22.17.033]slot: 1, slotCtrl = 0x4815f8
[0.22.17.142]ext0 int trigger
[0.22.17.260]ext0 int trigger
[0.22.18.218]slot[1] port:26 begin to power ON.
[0.22.23.088]ext0 int trigger
[0.22.23.101]slot: 1, slotCtrl = 0x811f8
[0.22.23.198]ext0 int trigger
[0.22.23.222]slot: 1, slotCtrl = 0x4815f8
[0.22.24.404]slot[1] port:26 begin to power ON.
[0.22.29.788]ext0 int trigger
[0.22.29.803]slot: 1, slotCtrl = 0x811f8
[0.22.29.948]ext0 int trigger
[0.22.29.961]slot: 1, slotCtrl = 0x4815f8
[0.22.31.232]slot[1] port:26 begin to power ON.
[0.22.36.588]ext0 int trigger
[0.22.36.601]slot: 1, slotCtrl = 0x811f8
[0.22.36.702]ext0 int trigger
[0.22.36.726]slot: 1, slotCtrl = 0x4815f8
[0.22.36.836]ext0 int trigger
[0.22.36.954]ext0 int trigger
[0.22.37.989]slot[1] port:26 begin to power ON.
[0.22.42.788]ext0 int trigger
[0.22.42.801]slot: 1, slotCtrl = 0x811f8
[0.22.42.898]ext0 int trigger
[0.22.42.922]slot: 1, slotCtrl = 0x4815f8
[0.22.44.307]slot[1] port:26 begin to power ON.
[0.22.56.288]ext0 int trigger
[0.22.56.301]slot: 1, slotCtrl = 0x811f8
[0.22.56.411]ext0 int trigger
[0.22.56.424]slot: 1, slotCtrl = 0x4815f8
[0.22.57.715]slot[1] port:26 begin to power ON.
[0.23.02.488]ext0 int trigger
[0.23.02.501]slot: 1, slotCtrl = 0x811f8
[0.23.02.598]ext0 int trigger
[0.23.02.622]slot: 1, slotCtrl = 0x4815f8
[0.23.03.909]slot[1] port:26 begin to power ON.
[0.23.08.688]ext0 int trigger
[0.23.08.700]slot: 1, slotCtrl = 0x811f8
[0.23.08.808]ext0 int trigger
[0.23.08.843]slot: 1, slotCtrl = 0x4815f8
[0.23.08.951]ext0 int trigger
[0.23.09.069]ext0 int trigger
[0.23.09.203]ext0 int trigger
[0.23.10.091]slot[1] port:26 begin to power ON.
[0.23.13.788]ext0 int trigger
[0.23.13.800]slot: 1, slotCtrl = 0x811f8
[0.23.13.908]ext0 int trigger
[0.23.13.932]slot: 1, slotCtrl = 0x4815f8
[0.23.14.030]ext0 int trigger
[0.23.15.189]slot[1] port:26 begin to power ON.
[0.23.15.388]ext0 int trigger
[0.23.15.400]slot: 1, slotCtrl = 0x812f8
[0.23.15.527]ext0 int trigger
[0.23.15.547]slot: 1, slotCtrl = 0x4816f8
[0.23.15.659]slot[1] port:26 begin to power ON.
[0.23.19.288]ext0 int trigger
[0.23.19.300]slot: 1, slotCtrl = 0x811f8
[0.23.19.397]ext0 int trigger
[0.23.19.421]slot: 1, slotCtrl = 0x4815f8
[0.23.19.529]ext0 int trigger
[0.23.20.671]slot[1] port:26 begin to power ON.
[0.23.22.188]ext0 int trigger
[0.23.22.200]slot: 1, slotCtrl = 0x811f8
[0.23.22.297]ext0 int trigger
[0.23.22.321]slot: 1, slotCtrl = 0x4815f8
[0.23.23.533]slot[1] port:26 begin to power ON.
[0.23.24.988]ext0 int trigger
[0.23.25.000]slot: 1, slotCtrl = 0x811f8
[0.23.25.098]ext0 int trigger
[0.23.25.121]slot: 1, slotCtrl = 0x4815f8
[0.23.25.235]ext0 int trigger
[0.23.25.355]ext0 int trigger
[0.23.26.280]slot[1] port:26 begin to power ON.
[0.23.27.287]ext0 int trigger
[0.23.27.300]slot: 1, slotCtrl = 0x811f8
[0.23.27.408]ext0 int trigger
[0.23.27.432]slot: 1, slotCtrl = 0x4815f8
[0.23.28.388]ext0 int trigger
[0.23.28.401]slot: 1, slotCtrl = 0x815f8
[0.23.28.510]ext0 int trigger
[0.23.28.534]slot: 1, slotCtrl = 0x4815f8
[0.23.28.641]ext0 int trigger
[0.23.28.715]slot[1] port:26 begin to power ON.
[0.23.28.775]ext0 int trigger
[0.23.41.887]ext0 int trigger
[0.23.41.901]slot: 1, slotCtrl = 0x811f8
[0.23.42.010]ext0 int trigger
[0.23.42.035]slot: 1, slotCtrl = 0x4815f8
[0.23.43.191]slot[1] port:26 begin to power ON.
[0.23.48.087]ext0 int trigger
[0.23.48.100]slot: 1, slotCtrl = 0x811f8
[0.23.48.208]ext0 int trigger
[0.23.48.232]slot: 1, slotCtrl = 0x4815f8
[0.23.49.484]slot[1] port:26 begin to power ON.
[0.23.51.487]ext0 int trigger
[0.23.51.500]slot: 1, slotCtrl = 0x811f8
[0.23.51.597]ext0 int trigger
[0.23.51.621]slot: 1, slotCtrl = 0x4815f8
[0.23.51.729]ext0 int trigger
[0.23.52.888]slot[1] port:26 begin to power ON.
[0.23.54.287]ext0 int trigger
[0.23.54.300]slot: 1, slotCtrl = 0x811f8
[0.23.54.410]ext0 int trigger
[0.23.54.423]slot: 1, slotCtrl = 0x4815f8
[0.23.55.656]slot[1] port:26 begin to power ON.
[0.23.59.387]ext0 int trigger
[0.23.59.400]slot: 1, slotCtrl = 0x811f8
[0.23.59.508]ext0 int trigger
[0.23.59.531]slot: 1, slotCtrl = 0x4815f8
[0.24.00.812]slot[1] port:26 begin to power ON.
[0.24.07.787]ext0 int trigger
[0.24.07.800]slot: 1, slotCtrl = 0x811f8
[0.24.07.908]ext0 int trigger
[0.24.07.932]slot: 1, slotCtrl = 0x4815f8
[0.24.08.045]ext0 int trigger
[0.24.09.112]slot[1] port:26 begin to power ON.
[0.24.19.087]ext0 int trigger
[0.24.19.100]slot: 1, slotCtrl = 0x811f8
[0.24.19.198]ext0 int trigger
[0.24.19.222]slot: 1, slotCtrl = 0x4815f8
[0.24.19.319]ext0 int trigger
[0.24.20.492]slot[1] port:26 begin to power ON.
[0.24.33.687]ext0 int trigger
[0.24.33.700]slot: 1, slotCtrl = 0x811f8
[0.24.33.804]ext0 int trigger
[0.24.33.827]slot: 1, slotCtrl = 0x4815f8
[0.24.35.165]slot[1] port:26 begin to power ON.
[0.24.38.787]ext0 int trigger
[0.24.38.800]slot: 1, slotCtrl = 0x811f8
[0.24.38.898]ext0 int trigger
[0.24.38.922]slot: 1, slotCtrl = 0x4815f8
[0.24.39.040]ext0 int trigger
[0.24.40.098]slot[1] port:26 begin to power ON.

********Hello Huawei LiteOS********

KpxxxxIMU Firmware Version : V32.70.0
LiteOS Kernel Version : 5.7.0
Run on ChipVersion[0] Node[0] Die[2]
build time : Feb 05 2026 20:30:00

**********************************

main core booting up...
start set affinity

mpidr = 0x81020000
sram ecc state: 0x0, sram ecc cnt: 0x0
[0.00.00.033]node 0 begins init all serdes.
BoardInfo->NodeNum 4.
BoardInfo->NodeId 0.
BoardInfo->InfoVersion 5.
BoardInfo->NASerdesSceneMode 3.
BoardInfo->NBSerdesSceneMode 3.
BoardInfo->HccsTopologyType 7.
BoardInfo->BoardId 0.
ChipVersionIsPro: 1.
BoardInfo Node 0, SerdesUseMode: 1 2 12 4 4 4 4  1 1 1 4 4 1 1 
BoardInfo Node 1, SerdesUseMode: 1 1 1 4 4 1 1  12 13 1 4 4 4 4 
BoardInfo Node 2, SerdesUseMode: 12 13 12 4 4 4 4  1 1 1 4 4 1 1 
BoardInfo Node 3, SerdesUseMode: 1 1 1 4 4 1 1  12 13 1 4 4 4 4 
BoardInfo Node 0, SerdesRxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 255 255 
BoardInfo Node 1, SerdesRxPolarityReverse: 255 255 255 0 0 255 255  0 0 0 0 0 0 0 
BoardInfo Node 2, SerdesRxPolarityReverse: 0 0 0 0 0 0 0  0 0 255 0 0 0 255 
BoardInfo Node 3, SerdesRxPolarityReverse: 255 255 255 0 0 0 0  0 0 255 0 0 0 0 
BoardInfo Node 0, SerdesTxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 255 255 
BoardInfo Node 1, SerdesTxPolarityReverse: 255 255 255 0 0 255 255  0 0 0 0 0 0 0 
BoardInfo Node 2, SerdesTxPolarityReverse: 0 0 0 0 0 0 0  0 0 255 0 0 0 0 
BoardInfo Node 3, SerdesTxPolarityReverse: 255 255 255 0 0 0 0  0 0 255 0 0 0 0 
serdessdk version: 2.0_5.0_20241203_imu
node_id 0, die 0, ind 0, usemode 1 begin serdes-init.
node_id 0, die 0, ind 1, usemode 2 begin serdes-init.
node_id 0, die 0, ind 2, usemode 12 begin serdes-init.
chip_id 0, die 0, ind 2, usemode 12 don't support, power down macro!
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
node_id 0, die 2, ind 0, usemode 1 begin serdes-init.
node_id 0, die 2, ind 1, usemode 1 begin serdes-init.
chip serdes init status:0x0.
[0.00.00.483]node 0 ends init all serdes.
link[0] freq_type:1 | peer_chip_type:1 | peer_node_id:1 | peer_link_id:6
link[1] freq_type:1 | peer_chip_type:1 | peer_node_id:1 | peer_link_id:7
link[2] freq_type:1 | peer_chip_type:1 | peer_node_id:1 | peer_link_id:4
link[3] freq_type:1 | peer_chip_type:1 | peer_node_id:1 | peer_link_id:5
link[4] freq_type:1 | peer_chip_type:1 | peer_node_id:3 | peer_link_id:0
link[5] freq_type:1 | peer_chip_type:1 | peer_node_id:2 | peer_link_id:4
register hccs done
nodeId 0, dieId 0, linkId 0, FFE info: fir_pre1 0, fir_main 63, fir_post1 0
node_id 0, die 0, ind 4, usemode 4 begin serdes-init.
nodeId 0, dieId 0, linkId 1, FFE info: fir_pre1 0, fir_main 63, fir_post1 0
node_id 0, die 0, ind 3, usemode 4 begin serdes-init.
nodeId 0, dieId 0, linkId 2, FFE info: fir_pre1 0, fir_main 63, fir_post1 0
node_id 0, die 0, ind 5, usemode 4 begin serdes-init.
nodeId 0, dieId 0, linkId 3, FFE info: fir_pre1 0, fir_main 63, fir_post1 0
node_id 0, die 0, ind 6, usemode 4 begin serdes-init.
node_id 0, die 2, ind 4, usemode 4 begin serdes-init.
node_id 0, die 2, ind 3, usemode 4 begin serdes-init.
hccs init start...
pa ring link down success
reset pa success
link[0] pcs init success
link[1] pcs init success
link[2] pcs init success
link[3] pcs init success
link[4] pcs init success
link[5] pcs init success
release reset pa success
link[0] macro adapt done (lane_mask=0xff) (0ms)
link[1] macro adapt done (lane_mask=0xff) (0ms)
link[2] macro adapt done (lane_mask=0xff) (0ms)
link[3] macro adapt done (lane_mask=0xff) (0ms)
link[4] macro adapt done (lane_mask=0xff) (0ms)
link[5] macro adapt done (lane_mask=0xff) (0ms)
link[0] pcs training success (10ms)
link[1] pcs training success (10ms)
link[2] pcs training success (10ms)
link[4] pcs training success (10ms)
link[5] pcs training success (10ms)
link[0] training success (20ms)
link[1] training success (20ms)
link[2] training success (20ms)
link[4] training success (20ms)
link[5] training success (20ms)
link[3] pcs training success (940ms)
link[3] training success (950ms)
link[0]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link[1]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link[2]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link[3]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link[4]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link[5]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
HLLC_ST_FSM_1_REG = 0x3
link training success
pa[0] linkEn = 0xf
pa[0] allNodeLink0 = 0xf0
pa[0] allNodeLink1 = 0x0
pa[1] linkEn = 0x3
pa[1] allNodeLink0 = 0x1200
pa[1] allNodeLink1 = 0x0
pa init success
COM_PAID_INTLV_REG = 0xc
paid decode init success
pa[0] PA_PM_BASE_INFO = 0xff8421
pa[0] PA_PM_MAP_LINK_NUM = 0x2184
pa[1] PA_PM_BASE_INFO = 0x330021
pa[1] PA_PM_MAP_LINK_NUM = 0x11
hccs performace config success
pa ring link up success
hccs init done
hccs access test start
node[0] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[1] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[2] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[3] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[1] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
node[2] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
node[3] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
hccs access test success
======hccs status======
  node[0] mask: expected = 0x3f, link up = 0x3f, width reduction = 0x0, link down = 0x0
  node[1] mask: expected = 0xf3, link up = 0xf3, width reduction = 0x0, link down = 0x0
  node[2] mask: expected = 0x3f, link up = 0x3f, width reduction = 0x0, link down = 0x0
  node[3] mask: expected = 0xf3, link up = 0xf3, width reduction = 0x0, link down = 0x0
==========end==========
report hccs status success
node[0] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
LRDXSD_LOCK_OFFSET = 0x0
LRDXSD_ERRIMSK_OFFSET = 0x0
LRDXSD_DBG_OTIMSK_OFFSET = 0x0
LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
LRDXSD_DBG_EN_OFFSET = 0x1
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
ID[0x3a25c2]!
ID[0x0]!
[ERR]Don't support the flash, CS[1] ID[0x0]!!
sfdp detect, try to get dummy data from hboot1 first.
ID[0x3a25c2]!
flash 0 support sfdp.
Interrupt 423 register OK
Interrupt 425 register OK
Interrupt 427 register OK
Interrupt 429 register OK
Interrupt 430 register OK
Interrupt 431 register OK
Interrupt 436 register OK

cpu 0 entering scheduler
[0.00.43.086]ext0 int trigger
[IMU] Watchdog Initialization done!
ScmiTaskEntry start.
Interrupt 456 register OK
Interrupt 469 register OK
Interrupt 482 register OK
Interrupt 495 register OK
Interrupt 508 register OK
Interrupt 521 register OK
Interrupt 534 register OK
Interrupt 547 register OK
starting Fpc Isolation Task end
starting fdm Err Info Task end
starting Roce recovery Task end
starting Ce_Storm Contrl Task end
starting Ras_Data_Update Task end
power register ubios call id
Interrupt 459 register OK
Interrupt 472 register OK
Interrupt 485 register OK
Interrupt 498 register OK
Interrupt 511 register OK
Interrupt 524 register OK
Interrupt 537 register OK
Interrupt 550 register OK
[0.00.43.153]Real time now 2026.7.25 01:35:12
NIC CARD[0][0]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[0][1]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[1][0]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[1][1]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[2][0]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[2][1]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[3][0]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[3][1]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
[0.00.43.293]ext0 int trigger
Init heart-beat-task end
Init SeamlessUpdateTask end
pool addr          pool size    used size     free size    max free node size   used node num     free node num      UsageWaterLine
---------------    --------     -------       --------     --------------       -------------      ------------      ------------
0x840908e708       0x204c0      0x1a780       0x5ad0       0x5ad0               0x79               0x1                0x1a9f0        
[0.00.43.734]ext0 int trigger
[0.00.44.127]ext0 int trigger
[0.00.44.512]ext0 int trigger
[0.00.44.895]ext0 int trigger
[0.00.45.265]ext0 int trigger
[0.00.45.694]ext0 int trigger
[0.00.46.132]ext0 int trigger
[0.00.46.542]ext0 int trigger
[0.00.46.918]ext0 int trigger
[0.00.47.292]ext0 int trigger
[0.00.47.670]ext0 int trigger
[0.00.48.111]ext0 int trigger
[0.00.48.481]ext0 int trigger
[0.00.48.856]ext0 int trigger
[0.00.49.227]ext0 int trigger
pwr cap[0]: 0, 5f
[0.00.49.575]ext0 int trigger
[0.00.49.914]ext0 int trigger
Get Setup Config.
[0.00.50.325]ext0 int trigger
[0.00.50.668]ext0 int trigger
[0.00.51.007]ext0 int trigger
[0.00.51.347]ext0 int trigger
[0.00.51.686]ext0 int trigger
[0.00.52.025]ext0 int trigger
[0.00.52.430]ext0 int trigger
[0.00.52.769]ext0 int trigger
[0.00.53.108]ext0 int trigger
[0.00.53.452]ext0 int trigger
[0.00.53.791]ext0 int trigger
[0.00.54.142]ext0 int trigger
[0.00.54.541]ext0 int trigger
[0.00.54.880]ext0 int trigger
[0.00.55.219]ext0 int trigger
[0.00.55.560]ext0 int trigger
[0.00.55.899]ext0 int trigger
pwr cap[1]: f, 27
[0.00.56.259]ext0 int trigger
[0.00.56.660]ext0 int trigger
Node 0, Die 0 ImpState is 0 skip exec.
Node 0, Die 2 ImpState is 0 skip exec.
Node 1, Die 0 ImpState is 0 skip exec.
Node 1, Die 2 ImpState is 0 skip exec.
Node 2, Die 0 ImpState is 0 skip exec.
Node 2, Die 2 ImpState is 0 skip exec.
Node 3, Die 0 ImpState is 0 skip exec.
Node 3, Die 2 ImpState is 0 skip exec.
[0.00.56.931]ext0 int trigger
[0.00.57.141]ext0 int trigger
[0.00.57.350]ext0 int trigger
[0.00.57.560]ext0 int trigger
[0.00.57.770]ext0 int trigger
[0.00.57.980]ext0 int trigger
[0.00.58.189]ext0 int trigger
pwr cap[2]: 1, 3
[0.00.58.400]ext0 int trigger
[0.00.58.609]ext0 int trigger
[0.00.58.849]ext0 int trigger
[0.00.59.072]ext0 int trigger
[0.00.59.283]ext0 int trigger
[0.00.59.493]ext0 int trigger
[0.00.59.703]ext0 int trigger
[0.00.59.912]ext0 int trigger
[0.01.00.122]ext0 int trigger
[0.01.00.331]ext0 int trigger
[0.01.00.541]ext0 int trigger
[0.01.00.750]ext0 int trigger
[0.01.01.003]ext0 int trigger
[0.01.01.215]ext0 int trigger
[0.01.01.424]ext0 int trigger
[0.01.01.634]ext0 int trigger
[0.01.01.843]ext0 int trigger
[0.01.02.054]ext0 int trigger
[0.01.02.263]ext0 int trigger
[0.01.02.472]ext0 int trigger
[0.01.02.682]ext0 int trigger
[0.01.02.892]ext0 int trigger
[0.01.03.178]ext0 int trigger
[0.01.03.387]ext0 int trigger
[0.01.03.596]ext0 int trigger
[0.01.03.806]ext0 int trigger
[0.01.04.015]ext0 int trigger
[0.01.04.225]ext0 int trigger
[0.01.04.434]ext0 int trigger
[0.01.04.644]ext0 int trigger
[0.01.04.854]ext0 int trigger
[0.01.05.065]ext0 int trigger
[0.01.05.326]ext0 int trigger
[0.01.05.536]ext0 int trigger
[0.01.05.745]ext0 int trigger
[0.01.05.955]ext0 int trigger
[0.01.06.164]ext0 int trigger
[0.01.06.376]ext0 int trigger
[0.01.06.585]ext0 int trigger
[0.01.06.795]ext0 int trigger
[0.01.07.005]ext0 int trigger
[0.01.07.214]ext0 int trigger
[0.01.07.474]ext0 int trigger
[0.01.07.684]ext0 int trigger
[0.01.07.895]ext0 int trigger
[0.01.08.106]ext0 int trigger
[0.01.08.316]ext0 int trigger
[0.01.08.526]ext0 int trigger
[0.01.08.735]ext0 int trigger
[0.01.08.945]ext0 int trigger
[0.01.09.165]ext0 int trigger
[0.01.09.392]ext0 int trigger
[0.01.09.662]ext0 int trigger
[0.01.09.872]ext0 int trigger
[0.01.10.082]ext0 int trigger
[0.01.10.291]ext0 int trigger
[0.01.10.501]ext0 int trigger
[0.01.10.711]ext0 int trigger
[0.01.10.920]ext0 int trigger
[0.01.11.130]ext0 int trigger
[0.01.11.340]ext0 int trigger
[0.01.11.563]ext0 int trigger
[0.01.11.807]ext0 int trigger
[0.01.12.017]ext0 int trigger
[0.01.12.226]ext0 int trigger
[0.01.12.436]ext0 int trigger
[0.01.12.645]ext0 int trigger
[0.01.12.855]ext0 int trigger
[0.01.13.065]ext0 int trigger
[0.01.13.274]ext0 int trigger
[0.01.13.484]ext0 int trigger
[0.01.13.715]ext0 int trigger
[0.01.13.948]ext0 int trigger
[0.01.14.158]ext0 int trigger
[0.01.14.368]ext0 int trigger
[0.01.14.577]ext0 int trigger
[0.01.14.787]ext0 int trigger
[0.01.14.996]ext0 int trigger
[0.01.15.206]ext0 int trigger
[0.01.15.416]ext0 int trigger
[0.01.15.625]ext0 int trigger
[0.01.15.906]ext0 int trigger
[0.01.16.125]ext0 int trigger
[0.01.16.336]ext0 int trigger
[0.01.16.545]ext0 int trigger
[0.01.16.755]ext0 int trigger
[0.01.16.965]ext0 int trigger
[0.01.17.175]ext0 int trigger
[0.01.17.385]ext0 int trigger
[0.01.17.599]ext0 int trigger
[0.01.17.809]ext0 int trigger
[0.01.18.063]ext0 int trigger
[0.01.18.272]ext0 int trigger
[0.01.18.482]ext0 int trigger
[0.01.18.703]ext0 int trigger
[0.01.18.912]ext0 int trigger
[0.01.19.122]ext0 int trigger
[0.01.19.332]ext0 int trigger
[0.01.19.542]ext0 int trigger
[0.01.19.672]DDR Rreserved for IMU: len = 3e00000
[LOG]head = 0x0, tail = 0x3c29, logSize = 0x3c29
copy registry.json file success
Set component all release version to sram end.
ipcMsgSend success
[0.01.19.746]starting ras Init
nodeId = 0, dieId = 0, isSasExist = 0.
nodeId = 0, dieId = 2, isSasExist = 0.
nodeId = 1, dieId = 0, isSasExist = 0.
nodeId = 1, dieId = 2, isSasExist = 0.
nodeId = 2, dieId = 0, isSasExist = 0.
nodeId = 2, dieId = 2, isSasExist = 0.
nodeId = 3, dieId = 0, isSasExist = 0.
nodeId = 3, dieId = 2, isSasExist = 0.
Mce Table head exist!
RasIntRegister init 452 
RasIntRegister init 453 
RasIntRegister init 64 
RasIntRegister init 65 
RasIntRegister init 465 
RasIntRegister init 466 
RasIntRegister init 86 
RasIntRegister init 87 
RasIntRegister init 478 
RasIntRegister init 479 
RasIntRegister init 108 
RasIntRegister init 109 
RasIntRegister init 491 
RasIntRegister init 492 
RasIntRegister init 130 
RasIntRegister init 131 
[0.01.19.823]ext0 int trigger
RasIntRegister init 504 
RasIntRegister init 505 
RasIntRegister init 152 
RasIntRegister init 153 
RasIntRegister init 517 
RasIntRegister init 518 
RasIntRegister init 174 
RasIntRegister init 175 
RasIntRegister init 530 
RasIntRegister init 531 
RasIntRegister init 196 
RasIntRegister init 197 
RasIntRegister init 543 
RasIntRegister init 544 
RasIntRegister init 218 
RasIntRegister init 219 
RasIntRegister init 76 
RasIntRegister init 98 
RasIntRegister init 120 
RasIntRegister init 142 
RasIntRegister init 164 
RasIntRegister init 186 
RasIntRegister init 208 
RasIntRegister init 230 
[0.01.19.877]starting ras end
[0.01.20.080]ext0 int trigger
[0.01.20.348]ext0 int trigger
[0.01.20.558]ext0 int trigger
[0.01.20.768]ext0 int trigger
[0.01.20.977]ext0 int trigger
[0.01.21.188]ext0 int trigger
[0.01.21.398]ext0 int trigger
[0.01.21.607]ext0 int trigger
[0.01.21.817]ext0 int trigger
[0.01.22.027]ext0 int trigger
[0.01.22.279]ext0 int trigger
[0.01.22.525]ext0 int trigger
[0.01.22.735]ext0 int trigger
[0.01.22.946]ext0 int trigger
[0.01.23.155]ext0 int trigger
[0.01.23.365]ext0 int trigger
[0.01.23.575]ext0 int trigger
[0.01.23.786]ext0 int trigger
[0.01.23.998]ext0 int trigger
[0.01.24.208]ext0 int trigger
[0.01.24.442]ext0 int trigger
[0.01.24.670]ext0 int trigger
[0.01.24.879]ext0 int trigger
[0.01.25.089]ext0 int trigger
[0.01.25.298]ext0 int trigger
[0.01.25.508]ext0 int trigger
[0.01.25.722]ext0 int trigger
[0.01.25.931]ext0 int trigger
[0.01.26.141]ext0 int trigger
[0.01.26.352]ext0 int trigger
[0.01.26.598]ext0 int trigger
[0.01.26.813]ext0 int trigger
[0.01.27.023]ext0 int trigger
[0.01.27.234]ext0 int trigger
[0.01.27.443]ext0 int trigger
[0.01.27.654]ext0 int trigger
[0.01.27.864]ext0 int trigger
[0.01.28.075]ext0 int trigger
[0.01.28.285]ext0 int trigger
[0.01.28.508]ext0 int trigger
[0.01.28.782]ext0 int trigger
[0.01.28.993]ext0 int trigger
[0.01.29.209]ext0 int trigger
[0.01.29.420]ext0 int trigger
[0.01.29.629]ext0 int trigger
[0.01.29.839]ext0 int trigger
[0.01.30.049]ext0 int trigger
[0.01.30.259]ext0 int trigger
[0.01.30.469]ext0 int trigger
[0.01.30.679]ext0 int trigger
[0.01.30.944]ext0 int trigger
[0.01.31.155]ext0 int trigger
[0.01.31.364]ext0 int trigger
[0.01.31.574]ext0 int trigger
[0.01.31.784]ext0 int trigger
[0.01.31.994]ext0 int trigger
[0.01.32.204]ext0 int trigger
[0.01.32.414]ext0 int trigger
[0.01.32.623]ext0 int trigger
[0.01.32.839]ext0 int trigger
[0.01.33.126]ext0 int trigger
[0.01.33.347]ext0 int trigger
[0.01.33.557]ext0 int trigger
[0.01.33.772]ext0 int trigger
[0.01.33.992]ext0 int trigger
[0.01.34.203]ext0 int trigger
[0.01.34.416]ext0 int trigger
[0.01.34.627]ext0 int trigger
[0.01.34.849]ext0 int trigger
[0.01.35.084]ext0 int trigger
[0.01.35.334]ext0 int trigger
[0.01.35.543]ext0 int trigger
[0.01.35.752]ext0 int trigger
[0.01.35.962]ext0 int trigger
[0.01.36.175]ext0 int trigger
[0.01.36.389]ext0 int trigger
[0.01.36.599]ext0 int trigger
[0.01.36.809]ext0 int trigger
[0.01.37.019]ext0 int trigger
[0.01.37.248]ext0 int trigger
[0.01.37.483]ext0 int trigger
[0.01.37.693]ext0 int trigger
[0.01.37.903]ext0 int trigger
[0.01.38.113]ext0 int trigger
[0.01.38.318]ext0 int trigger
[0.01.38.520]ext0 int trigger
[0.01.38.722]ext0 int trigger
[0.01.38.924]ext0 int trigger
[0.01.39.125]ext0 int trigger
[0.01.39.336]ext0 int trigger
[0.01.39.507][ERR]cmd not support! cmd = 0xd
[0.01.39.588]ext0 int trigger
[0.01.39.818]ext0 int trigger
[0.01.40.025]ext0 int trigger
[0.01.40.228]ext0 int trigger
[0.01.40.429]ext0 int trigger
[0.01.40.631]ext0 int trigger
[0.01.40.833]ext0 int trigger
[0.01.41.035]ext0 int trigger
[0.01.41.282]ext0 int trigger
[0.01.41.526]ext0 int trigger
[0.01.41.745]ext0 int trigger
[0.01.41.948]ext0 int trigger
[0.01.42.149]ext0 int trigger
[0.01.42.351]ext0 int trigger
[0.01.42.593]ext0 int trigger
[0.01.42.795]ext0 int trigger
[0.01.43.012]ext0 int trigger
[0.01.43.215]ext0 int trigger
[0.01.43.427]ext0 int trigger
[0.01.43.656]ext0 int trigger
[0.01.43.876]ext0 int trigger
[0.01.44.097]ext0 int trigger
[0.01.44.300]ext0 int trigger
[0.01.44.502]ext0 int trigger
[0.01.44.743]ext0 int trigger
[0.01.44.991]ext0 int trigger
[0.01.45.197]ext0 int trigger
[0.01.45.424]ext0 int trigger
[0.01.45.625]ext0 int trigger
[0.01.45.867]ext0 int trigger
[0.01.46.069]ext0 int trigger
[0.01.46.271]ext0 int trigger
[0.01.46.489]ext0 int trigger
[0.01.46.690]ext0 int trigger
[0.01.46.921]ext0 int trigger
[0.01.47.123]ext0 int trigger
[0.01.47.325]ext0 int trigger
[0.01.47.527]ext0 int trigger
[0.01.47.740]ext0 int trigger
[0.01.47.997]ext0 int trigger
[0.01.48.199]ext0 int trigger
[0.01.48.421]ext0 int trigger
[0.01.48.622]ext0 int trigger
[0.01.48.824]ext0 int trigger
[0.01.49.051]ext0 int trigger
[0.01.49.258]ext0 int trigger
[0.01.49.459]ext0 int trigger
[0.01.49.661]ext0 int trigger
[0.01.49.863]ext0 int trigger
[0.01.50.109]ext0 int trigger
[0.01.50.313]ext0 int trigger
[0.01.50.516]ext0 int trigger
[0.01.50.718]ext0 int trigger
[0.01.50.919]ext0 int trigger
[0.01.51.121]ext0 int trigger
[0.01.51.324]ext0 int trigger
[0.01.51.528]ext0 int trigger
[0.01.51.749]ext0 int trigger
[0.01.51.774]TF Heartbeat Start
[0.01.51.958]ext0 int trigger
[0.01.52.206]ext0 int trigger
[0.01.52.422]ext0 int trigger
[0.01.52.632]ext0 int trigger
[0.01.52.842]ext0 int trigger
[0.01.53.053]ext0 int trigger
[0.01.53.264]ext0 int trigger
[0.01.53.474]ext0 int trigger
[0.01.53.684]ext0 int trigger
[0.01.53.894]ext0 int trigger
[0.01.54.113]ext0 int trigger
[0.01.54.384]ext0 int trigger
[0.01.54.594]ext0 int trigger
[0.01.54.804]ext0 int trigger
[0.01.55.014]ext0 int trigger
[0.01.55.224]ext0 int trigger
[0.01.55.434]ext0 int trigger
[0.01.55.646]ext0 int trigger
[0.01.55.856]ext0 int trigger
[0.01.56.066]ext0 int trigger
[0.01.56.277]ext0 int trigger
[0.01.56.540]ext0 int trigger
[0.01.56.750]ext0 int trigger
[0.01.56.965]ext0 int trigger
[0.01.57.175]ext0 int trigger
[0.01.57.296]PCIE INIT DONE.
g_mctpQueueCount(48) > tabCnt(42)
Interrupt 454 register OK
Interrupt 467 register OK
Interrupt 480 register OK
Interrupt 493 register OK
Interrupt 506 register OK
Interrupt 519 register OK
Interrupt 532 register OK
Interrupt 545 register OK
data = 0x0
pmt Init done

Add ep: bdf=5500 eid=9 epCnt=1 eid_alloc=a
[0.01.57.412]ext0 int trigger
Add ep: bdf=300 eid=a epCnt=1 eid_alloc=b
[0.01.57.627]ext0 int trigger
[0.01.57.842]ext0 int trigger
[0.01.58.059]ext0 int trigger
[0.01.58.275]ext0 int trigger
[0.01.58.493]ext0 int trigger
[0.01.58.761]ext0 int trigger
[0.01.58.988]ext0 int trigger
[0.01.59.205]ext0 int trigger
[0.01.59.424]ext0 int trigger
[0.01.59.641]ext0 int trigger
[0.01.59.857]ext0 int trigger
[0.02.00.074]ext0 int trigger
[0.02.00.291]ext0 int trigger
[0.02.00.524]ext0 int trigger
[0.02.00.789]ext0 int trigger
[0.02.01.009]ext0 int trigger
[0.02.01.229]ext0 int trigger
[0.02.01.447]ext0 int trigger
[0.02.01.665]ext0 int trigger
[0.02.01.883]ext0 int trigger
[0.02.02.100]ext0 int trigger
[0.02.02.318]ext0 int trigger
[0.02.02.535]ext0 int trigger
[0.02.02.753]ext0 int trigger
[0.02.03.038]ext0 int trigger
[0.02.03.255]ext0 int trigger
[0.02.03.472]ext0 int trigger
[0.02.03.700]ext0 int trigger
[0.02.03.918]ext0 int trigger
[0.02.04.135]ext0 int trigger
[0.02.04.354]ext0 int trigger
[0.02.04.571]ext0 int trigger
[0.02.04.789]ext0 int trigger
[0.02.05.042]ext0 int trigger
[0.02.05.265]ext0 int trigger
[0.02.05.483]ext0 int trigger
[0.02.05.700]ext0 int trigger
[0.02.05.920]ext0 int trigger
[0.02.06.138]ext0 int trigger
[0.02.06.359]ext0 int trigger
[0.02.06.578]ext0 int trigger
[0.02.06.801]ext0 int trigger
[0.02.07.043]ext0 int trigger
[0.02.07.297]ext0 int trigger
[0.02.07.515]ext0 int trigger
[0.02.07.733]ext0 int trigger
[0.02.07.952]ext0 int trigger
[0.02.08.173]ext0 int trigger
[0.02.08.391]ext0 int trigger
[0.02.08.608]ext0 int trigger
[0.02.08.826]ext0 int trigger
[0.02.09.044]ext0 int trigger
[0.02.09.289]ext0 int trigger
[0.02.09.528]ext0 int trigger
[0.02.09.747]ext0 int trigger
[0.02.09.975]ext0 int trigger
[0.02.10.192]ext0 int trigger
[0.02.10.409]ext0 int trigger
[0.02.10.626]ext0 int trigger
[0.02.10.843]ext0 int trigger
[0.02.11.060]ext0 int trigger
[0.02.11.277]ext0 int trigger
[0.02.11.544]ext0 int trigger
[0.02.11.764]ext0 int trigger
[0.02.11.983]ext0 int trigger
[0.02.12.202]ext0 int trigger
[0.02.12.419]ext0 int trigger
[0.02.12.637]ext0 int trigger
[0.02.12.855]ext0 int trigger
[0.02.13.073]ext0 int trigger
[0.02.13.311]ext0 int trigger
[0.02.13.559]ext0 int trigger
[0.02.13.795]ext0 int trigger
[0.02.14.012]ext0 int trigger
[0.02.14.230]ext0 int trigger
[0.02.14.448]ext0 int trigger
[0.02.14.667]ext0 int trigger
[0.02.14.885]ext0 int trigger
[0.02.15.102]ext0 int trigger
[0.02.15.322]ext0 int trigger
[0.02.15.539]ext0 int trigger
[0.02.15.822]ext0 int trigger
[0.02.16.040]ext0 int trigger
[0.02.16.258]ext0 int trigger
[0.02.16.475]ext0 int trigger
[0.02.16.694]ext0 int trigger
[0.02.16.912]ext0 int trigger
[0.02.17.131]ext0 int trigger
[0.02.17.349]ext0 int trigger
[0.02.17.566]ext0 int trigger
[0.02.17.796]ext0 int trigger
[0.02.18.057]ext0 int trigger
[0.02.18.274]ext0 int trigger
[0.02.18.491]ext0 int trigger
[0.02.18.710]ext0 int trigger
[0.02.18.929]ext0 int trigger
[0.02.19.152]ext0 int trigger
[0.02.19.371]ext0 int trigger
[0.02.19.604]ext0 int trigger
[0.02.19.832]ext0 int trigger
[0.02.20.113]ext0 int trigger
[0.02.20.331]ext0 int trigger
[0.02.20.549]ext0 int trigger
[0.02.20.767]ext0 int trigger
[0.02.20.985]ext0 int trigger
[0.02.21.204]ext0 int trigger
[0.02.21.421]ext0 int trigger
[0.02.21.640]ext0 int trigger
[0.02.21.857]ext0 int trigger
[0.02.22.103]ext0 int trigger
[0.02.22.344]ext0 int trigger
mctp task ok.
[0.02.22.562]ext0 int trigger
[0.02.22.780]ext0 int trigger
[0.02.22.999]ext0 int trigger
[0.02.23.217]ext0 int trigger
[0.02.23.435]ext0 int trigger
[0.02.23.653]ext0 int trigger
[0.02.23.870]ext0 int trigger
[0.02.24.101]ext0 int trigger
[0.02.24.356]ext0 int trigger
[0.02.24.574]ext0 int trigger
[0.02.24.791]ext0 int trigger
[0.02.25.009]ext0 int trigger
[0.02.25.228]ext0 int trigger
[0.02.25.445]ext0 int trigger
[0.02.25.663]ext0 int trigger
[0.02.25.888]ext0 int trigger
[0.02.26.124]ext0 int trigger
[0.02.26.360]ext0 int trigger
[0.02.26.601]ext0 int trigger
[0.02.26.820]ext0 int trigger
[0.02.27.038]ext0 int trigger
[0.02.27.255]ext0 int trigger
[0.02.27.473]ext0 int trigger
[0.02.27.693]ext0 int trigger
[0.02.27.910]ext0 int trigger
[0.02.28.128]ext0 int trigger
[0.02.28.347]ext0 int trigger
[0.02.28.605]ext0 int trigger
[0.02.28.835]ext0 int trigger
[0.02.29.053]ext0 int trigger
[0.02.29.273]ext0 int trigger
[0.02.29.495]ext0 int trigger
[0.02.29.713]ext0 int trigger
[0.02.29.931]ext0 int trigger
[0.02.30.147]ext0 int trigger
[0.02.30.375]ext0 int trigger
[0.02.30.596]ext0 int trigger
[0.02.30.688]Receive ras int[491]
First coalesce handler start
Type2 status = 0x0
Type1 status = 0x4
Found error node[2]
False alarm reporting!
Type0 status = 0x0
ras int[491] end

[0.02.30.870]ext0 int trigger
[0.02.31.087]ext0 int trigger
[0.02.31.306]ext0 int trigger
[0.02.31.522]ext0 int trigger
[0.02.31.741]ext0 int trigger
[0.02.31.969]ext0 int trigger
[0.02.32.185]ext0 int trigger
[0.02.32.431]ext0 int trigger
[0.02.32.648]ext0 int trigger
[0.02.32.931]ext0 int trigger
[0.02.33.148]ext0 int trigger
[0.02.33.365]ext0 int trigger
[0.02.33.584]ext0 int trigger
[0.02.33.800]ext0 int trigger
[0.02.34.076]ext0 int trigger
[0.02.34.344]ext0 int trigger


HSM_LOG:
[00:00:00.000][info] succeed to do thirdparty dfx_pabuk init
[00:00:00.000][info] succeed to do thirdparty crypto_driver init



0>[2450]MHZ -> Vol TA[ 872]mv TB[ 870]mv
0>[2500]MHZ -> Vol TA[ 884]mv TB[ 883]mv
0>[2550]MHZ -> Vol TA[ 897]mv TB[ 895]mv
0>[2600]MHZ -> Vol TA[ 909]mv TB[ 908]mv
0>[2650]MHZ -> Vol TA[ 922]mv TB[ 920]mv
0>[2700]MHZ -> Vol TA[ 935]mv TB[ 933]mv
0>[2750]MHZ -> Vol TA[ 953]mv TB[ 950]mv
0>[2800]MHZ -> Vol TA[ 971]mv TB[ 968]mv
0>[2850]MHZ -> Vol TA[ 989]mv TB[ 986]mv
0>[2900]MHZ -> Vol TA[1007]mv TB[1004]mv
0>[2950]MHZ -> Vol TA[1024]mv TB[1021]mv
0>[3000]MHZ -> Vol TA[1041]mv TB[1038]mv
0>[3050]MHZ -> Vol TA[1054]mv TB[1052]mv
0>[3100]MHZ -> Vol TA[1068]mv TB[1066]mv
0>Uncore VF curve:
0>Uncore [   0]MHZ -> Vol [ 810]mv
0>Uncore [ 100]MHZ -> Vol [ 810]mv
0>Uncore [ 200]MHZ -> Vol [ 810]mv
0>Uncore [ 300]MHZ -> Vol [ 810]mv
0>Uncore [ 400]MHZ -> Vol [ 810]mv
0>Uncore [ 500]MHZ -> Vol [ 810]mv
0>Uncore [ 600]MHZ -> Vol [ 810]mv
0>Uncore [ 700]MHZ -> Vol [ 810]mv
0>Uncore [ 800]MHZ -> Vol [ 810]mv
0>Uncore [ 900]MHZ -> Vol [ 810]mv
0>Uncore [1000]MHZ -> Vol [ 810]mv
0>Uncore [1100]MHZ -> Vol [ 810]mv
0>Uncore [1200]MHZ -> Vol [ 810]mv
0>Uncore [1300]MHZ -> Vol [ 810]mv
0>Uncore [1400]MHZ -> Vol [ 810]mv
0>Uncore [1500]MHZ -> Vol [ 810]mv
0>Uncore [1600]MHZ -> Vol [ 810]mv
0>Uncore [1700]MHZ -> Vol [ 810]mv
0>Uncore [1800]MHZ -> Vol [ 810]mv
0>Uncore [1900]MHZ -> Vol [ 810]mv
0>Uncore [2000]MHZ -> Vol [ 810]mv
0>Uncore [2100]MHZ -> Vol [ 810]mv
0>Uncore [2200]MHZ -> Vol [ 812]mv
0>Uncore [2300]MHZ -> Vol [ 829]mv
0>Uncore [2400]MHZ -> Vol [ 846]mv
0>Uncore [2500]MHZ -> Vol [ 863]mv
0>Uncore [2600]MHZ -> Vol [ 883]mv
0>Uncore [2700]MHZ -> Vol [ 903]mv
0>Uncore [2800]MHZ -> Vol [ 923]mv
0>Uncore [2900]MHZ -> Vol [ 944]mv
0>Uncore [3000]MHZ -> Vol [1100]mv
0>[TracePoint] type[  0] cmd[  1] data[  6]
0>[TracePoint] type[  0] cmd[  1] data[  7]
0>
********Hello Huawei LiteOS********

KpxxxxIPU Firmware Version : V32.70.0
LiteOS Kernel Version : 5.7.0
0>Run on ChipVersion[0] Node[0] Die[0]
0>build time : Feb 05 2026 20:30:00

0>**********************************
0>
main core booting up...
0>start set affinity
0>
mpidr = 0x81000000
0>sram ecc state: 0x0, sram ecc cnt: 0x0
0>[TracePoint] type[  0] cmd[  2] data[  1]
0>[TracePoint] type[  0] cmd[  2] data[  2]
0>LRDXSD_LOCK_OFFSET = 0x0
0>LRDXSD_ERRIMSK_OFFSET = 0x0
0>LRDXSD_DBG_OTIMSK_OFFSET = 0x0
0>LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
0>LRDXSD_DBG_EN_OFFSET = 0x1
0>======tsensor params======
0>  is_trimmed       : 1
0>  underclocking_en : 1
0>===========end============
0>soc tsensor init done
0>========vrd info from cpld========
0>vrd_id | u64                | pmbus_en | avsbus_en | loop | pmbus_id | pmbus_addr | avs_sw | pmbus_sw | addr_9545 | domain_type | die_mask | reserved
0>  00   | 0x0001000100002017 | 0x1      | 0x1       | 0x1  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0100   | 0x0
0>  01   | 0x000001060000201b | 0x1      | 0x1       | 0x2  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x6         | 0x0001   | 0x0
0>  02   | 0x0003000300002715 | 0x1      | 0x0       | 0x1  | 0x1      | 0x27       | 0x0    | 0x0      | 0x0       | 0x3         | 0x0300   | 0x0
0>  03   | 0x0003000400002719 | 0x1      | 0x0       | 0x2  | 0x1      | 0x27       | 0x0    | 0x0      | 0x0       | 0x4         | 0x0300   | 0x0
0>  04   | 0x0002000100002027 | 0x1      | 0x1       | 0x1  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0200   | 0x0
0>  05   | 0x000300020000202b | 0x1      | 0x1       | 0x2  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x2         | 0x0300   | 0x0
0>  06   | 0x0000020a00002725 | 0x1      | 0x0       | 0x1  | 0x2      | 0x27       | 0x0    | 0x0      | 0x0       | 0xa         | 0x0002   | 0x0
0>  07   | 0x0000020500002729 | 0x1      | 0x0       | 0x2  | 0x2      | 0x27       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0002   | 0x0
0>  08   | 0x0000020600002a25 | 0x1      | 0x0       | 0x1  | 0x2      | 0x2a       | 0x0    | 0x0      | 0x0       | 0x6         | 0x0002   | 0x0
0>  09   | 0x0000010a00002a29 | 0x1      | 0x0       | 0x2  | 0x2      | 0x2a       | 0x0    | 0x0      | 0x0       | 0xa         | 0x0001   | 0x0
0>================end===============
0>=============vrd info=============
0>power domain num: 10
0>power domain[00] id:0 | CORE_DVFS_TA       | PMBus NA | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
0>power domain[01] id:10 | IO_DVDD09_NA       | PMBus NA | cap:0x3 | rail:1 | addr:0x20 | def_volt: 900 mV | min_volt: 700 mV | max_volt: 900 mV
0>power domain[02] id:1 | DDR_VDD            | PMBus NA | cap:0x1 | rail:0 | addr:0x27 | def_volt: 800 mV | min_volt: 760 mV | max_volt: 840 mV
0>power domain[03] id:6 | DDR_VDDQ           | PMBus NA | cap:0x1 | rail:1 | addr:0x27 | def_volt:1100 mV | min_volt:1000 mV | max_volt:1200 mV
0>power domain[04] id:2 | CORE_DVFS_TB       | PMBus NB | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
0>power domain[05] id:3 | UNCORE_DVFS        | PMBus NB | cap:0x3 | rail:1 | addr:0x20 | def_volt: 944 mV | min_volt: 750 mV | max_volt:1100 mV
0>power domain[06] id:15 | NB_AVDD_SDS        | PMBus NB | cap:0x1 | rail:0 | addr:0x27 | def_volt:1200 mV | min_volt:1164 mV | max_volt:1236 mV
0>power domain[07] id:5 | IO_DVDD_NB         | PMBus NB | cap:0x1 | rail:1 | addr:0x27 | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
0>power domain[08] id:11 | IO_DVDD09_NB       | PMBus NB | cap:0x1 | rail:0 | addr:0x2a | def_volt: 900 mV | min_volt: 700 mV | max_volt: 900 mV
0>power domain[09] id:13 | NA_AVDD_SDS        | PMBus NB | cap:0x1 | rail:1 | addr:0x2a | def_volt:1200 mV | min_volt:1164 mV | max_volt:1236 mV
0>================end===============
0>pmbus[0] init done
0>pmbus[1] init done
0>power domain[0] CORE_DVFS_TA       | NA PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
0>power domain[10] IO_DVDD09_NA       | NA PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 900 mV | pmu:MP2882
0>power domain[1] DDR_VDD            | NA PMBus        | rail:0 | addr:0x27 | def_volt: 800 mV | pmu:MP2882
0>power domain[6] DDR_VDDQ           | NA PMBus        | rail:1 | addr:0x27 | def_volt:1100 mV | pmu:MP2882
0>power domain[2] CORE_DVFS_TB       | NB PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
0>power domain[3] UNCORE_DVFS        | NB PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 944 mV | pmu:MP2882
0>power domain[15] NB_AVDD_SDS        | NB PMBus        | rail:0 | addr:0x27 | def_volt:1200 mV | pmu:MP2882
0>power domain[5] IO_DVDD_NB         | NB PMBus        | rail:1 | addr:0x27 | def_volt: 800 mV | pmu:MP2882
0>power domain[11] IO_DVDD09_NB       | NB PMBus        | rail:0 | addr:0x2a | def_volt: 900 mV | pmu:MP2882
0>power domain[13] NA_AVDD_SDS        | NB PMBus        | rail:1 | addr:0x2a | def_volt:1200 mV | pmu:MP2882
0>power domain[0] CORE_DVFS_TA       is transferred to AVSBus mode
0>power domain[10] IO_DVDD09_NA       is transferred to AVSBus mode
0>power domain[2] CORE_DVFS_TB       is transferred to AVSBus mode
0>power domain[3] UNCORE_DVFS        is transferred to AVSBus mode
0>avsbus resync success
0>avsbus[0] init done
0>avsbus resync success
0>avsbus[1] init done
0>============volt boot============
0>power domain[0] volt = 1097 mV
0>power domain[10] volt =  908 mV
0>power domain[1] volt =  806 mV
0>power domain[6] volt = 1105 mV
0>power domain[2] volt = 1105 mV
0>power domain[3] volt = 1009 mV
0>power domain[15] volt = 1205 mV
0>power domain[5] volt =  806 mV
0>power domain[11] volt =  908 mV
0>power domain[13] volt = 1206 mV
0>===============end===============
0>--w&h rd rail:0, 1097, CORE_DVFS_TA
0>--w&h rd rail:1, 900, CORE_DVFS_TA
0>power domain[0] set volt --> 1097 mV success
0>--w&h rd rail:0, 1105, CORE_DVFS_TB
0>--w&h rd rail:1, 1009, CORE_DVFS_TB
0>power domain[2] set volt --> 1105 mV success
0>power domain[3] set volt -->  951 mV success
0>============volt post============
0>power domain[0] volt = 1097 mV
0>power domain[10] volt =  904 mV
0>power domain[1] volt =  806 mV
0>power domain[6] volt = 1103 mV
0>power domain[2] volt = 1105 mV
0>power domain[3] volt =  951 mV
0>power domain[15] volt = 1205 mV
0>power domain[5] volt =  804 mV
0>power domain[11] volt =  906 mV
0>power domain[13] volt = 1205 mV
0>===============end===============
0>die[0] its[0] init done
0>die[0] its[1] init done
0>die[0] its[2] init done
0>die[0] its[3] init done
0>die[0] its[4] init done
0>die[0] its[5] init done
0>die[0] its[6] init done
0>die[0] its[7] init done
0>die[0] its[8] init done
0>die[0] its[9] init done
0>die[1] its[0] init done
0>die[1] its[1] init done
0>die[1] its[2] init done
0>die[1] its[3] init done
0>die[1] its[4] init done
0>die[1] its[5] init done
0>die[1] its[6] init done
0>die[1] its[7] init done
0>die[1] its[8] init done
0>die[1] its[9] init done
0>Totem[0] Core Boot Vol [1097]mv
0>Totem[0] Core Current Vol [1100]mv
0>Totem[1] Core Boot Vol [1105]mv
0>Totem[1] Core Current Vol [1100]mv
0>NA 1620V1a0
0>NB 1620V1a0
0>GetCoreBaseFreq [2500000KHZ]
0>GetCoreTurboFreq [2500000KHZ]
0>GetCustomClusterNum [10]
0>Ipu ACG Training Done!
0>AP Last Time:[0.00.02.067]
0>wait UEFI pll init...
0>done
0>acg trim start
0>core trim freq:2000, avs:0 volt:810mv
0>core trim freq:2000, avs:0 volt:810mv
0>core trim freq:2050, avs:1 volt:810mv
0>core trim freq:2050, avs:1 volt:810mv
0>core trim freq:2100, avs:2 volt:810mv
0>core trim freq:2100, avs:2 volt:810mv
0>core trim freq:2150, avs:3 volt:810mv
0>core trim freq:2150, avs:3 volt:810mv
0>core trim freq:2200, avs:4 volt:810mv
0>core trim freq:2200, avs:4 volt:810mv
0>core trim freq:2250, avs:5 volt:821mv
0>core trim freq:2250, avs:5 volt:820mv
0>core trim freq:2300, avs:6 volt:834mv
0>core trim freq:2300, avs:6 volt:833mv
0>core trim freq:2350, avs:7 volt:847mv
0>core trim freq:2350, avs:7 volt:845mv
0>core trim freq:2400, avs:8 volt:859mv
0>core trim freq:2400, avs:8 volt:858mv
0>core trim freq:2450, avs:9 volt:872mv
0>core trim freq:2450, avs:9 volt:870mv
0>core trim freq:2500, avs:10 volt:884mv
0>core trim freq:2500, avs:10 volt:883mv
0>core trim freq:2550, avs:11 volt:897mv
0>core trim freq:2550, avs:11 volt:895mv
0>core trim freq:2600, avs:12 volt:909mv
0>core trim freq:2600, avs:12 volt:908mv
0>core trim freq:2650, avs:13 volt:922mv
0>core trim freq:2650, avs:13 volt:920mv
0>core trim freq:2700, avs:14 volt:935mv
0>core trim freq:2700, avs:14 volt:933mv
0>core trim freq:2750, avs:15 volt:953mv
0>core trim freq:2750, avs:15 volt:950mv
0>core trim freq:2800, avs:16 volt:971mv
0>core trim freq:2800, avs:16 volt:968mv
0>core trim freq:2850, avs:17 volt:989mv
0>core trim freq:2850, avs:17 volt:986mv
0>core trim freq:2900, avs:18 volt:1007mv
0>core trim freq:2900, avs:18 volt:1004mv
0>core trim freq:2950, avs:19 volt:1024mv
0>core trim freq:2950, avs:19 volt:1021mv
0>core trim freq:3000, avs:20 volt:1041mv
0>core trim freq:3000, avs:20 volt:1038mv
0>core trim freq:3050, avs:21 volt:1054mv
0>core trim freq:3050, avs:21 volt:1052mv
0>core trim freq:3100, avs:22 volt:1068mv
0>core trim freq:3100, avs:22 volt:1066mv
0>acg trim end
0>LDO disabled
0>[TracePoint] type[  0] cmd[  2] data[  3]
0>Interrupt 423 register OK
0>Interrupt 430 register OK
0>[TracePoint] type[  0] cmd[  2] data[  4]
0>
0>cpu 0 entering scheduler
0>[TracePoint] type[  0] cmd[  3] data[  1]
0>add your ipu app init here!
0>IpuInterfaceTaskStart Entry ...
0>ipu interface task wait parameters from uefi...
0>thermal soc task enabled
0>AP Last Time:[0.00.40.950]
0>ThermalDimmStart Entry ...
0>wait ddr init done...
0>power task start...
0>[TracePoint] type[  0] cmd[  3] data[  2]
0>ufs task wait parameters from uefi...
0>AmuTaskStart Entry ... 
0>amu task wait parameters from uefi...
0>ThermalSiwStart Entry ...
0>ThermalSiwTask idle...
0>DemtTaskStart Entry ...
0>[TracePoint] type[  0] cmd[  3] data[  3]
0>demt task wait parameters from uefi...
0>HiBoostTaskStart Entry ...
0>HiBoost task enabled
0>Waiting for UEFI parameters...
0>[TracePoint] type[  0] cmd[  3] data[  4]
0>AgeTaskStart Entry ...
0>age task wait parameters from uefi...
0>[TracePoint] type[  0] cmd[  3] data[  5]
0>uefi parameters ready!
0>UFSProfile[0]
0>PowerPolicy[2] BenchMarkSelection[0]
0>ipu interface task wait ddr init done from uefi...
0>ufs task parameters from uefi ready
0>uncore domain[0] freq:2900
0>uncore domain[1] freq:2900
0>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
0>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
0>======sioe status======
0>thermal soc task restore underclocking_en=1
0>ppu alert temp div init done
0>TA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TA_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TA_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TA_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
0>TA_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
0>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
0>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
0>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
0>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
0>==========end==========
0>sioe init done
0>ufs task enabled
0>--> UFS profile[0]
0>UEFI parameters ready
0>UncoreMaxFreq Set to [2900 MHZ]
0>get TDP from efuse success, value = 307500mw
0>target power set to [307500]mw, brd:[307500]
0>demt task parameters from uefi ready
0>age task parameters from uefi ready
0>age task enabled
0>uefi ddr init finish!
0>ipu interface task wait uefi end done from uefi...
0>ddr init done, start thermal dimm task
0>======dimm status======
0>  chl[0] dimm0 0, dimm1 0
0>  chl[1] dimm0 0, dimm1 0
0>  chl[2] dimm0 2, dimm1 0
0>  chl[3] dimm0 0, dimm1 0
0>  chl[4] dimm0 0, dimm1 0
0>  chl[5] dimm0 0, dimm1 0
0>  chl[6] dimm0 0, dimm1 0
0>  chl[7] dimm0 0, dimm1 0
0>==========end==========
0>chl[2] registered, dimm mask = 0x1
0>=====dimm temp params=====
0>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
0>  is_thermal_thro_en  : 1
0>  is_aref_rate_auto   : 1
0>===========end============
0>chl[2] max_temp 44'C, aref_rate 0x5 --> 0x4
 TA[1050]mv TB[1047]mv
1>[3050]MHZ -> Vol TA[1063]mv TB[1060]mv
1>[3100]MHZ -> Vol TA[1076]mv TB[1074]mv
1>Uncore VF curve:
1>Uncore [   0]MHZ -> Vol [ 810]mv
1>Uncore [ 100]MHZ -> Vol [ 810]mv
1>Uncore [ 200]MHZ -> Vol [ 810]mv
1>Uncore [ 300]MHZ -> Vol [ 810]mv
1>Uncore [ 400]MHZ -> Vol [ 810]mv
1>Uncore [ 500]MHZ -> Vol [ 810]mv
1>Uncore [ 600]MHZ -> Vol [ 810]mv
1>Uncore [ 700]MHZ -> Vol [ 810]mv
1>Uncore [ 800]MHZ -> Vol [ 810]mv
1>Uncore [ 900]MHZ -> Vol [ 810]mv
1>Uncore [1000]MHZ -> Vol [ 810]mv
1>Uncore [1100]MHZ -> Vol [ 810]mv
1>Uncore [1200]MHZ -> Vol [ 810]mv
1>Uncore [1300]MHZ -> Vol [ 810]mv
1>Uncore [1400]MHZ -> Vol [ 810]mv
1>Uncore [1500]MHZ -> Vol [ 810]mv
1>Uncore [1600]MHZ -> Vol [ 810]mv
1>Uncore [1700]MHZ -> Vol [ 810]mv
1>Uncore [1800]MHZ -> Vol [ 810]mv
1>Uncore [1900]MHZ -> Vol [ 810]mv
1>Uncore [2000]MHZ -> Vol [ 810]mv
1>Uncore [2100]MHZ -> Vol [ 810]mv
1>Uncore [2200]MHZ -> Vol [ 814]mv
1>Uncore [2300]MHZ -> Vol [ 831]mv
1>Uncore [2400]MHZ -> Vol [ 848]mv
1>Uncore [2500]MHZ -> Vol [ 866]mv
1>Uncore [2600]MHZ -> Vol [ 886]mv
1>Uncore [2700]MHZ -> Vol [ 907]mv
1>Uncore [2800]MHZ -> Vol [ 927]mv
1>Uncore [2900]MHZ -> Vol [ 948]mv
1>Uncore [3000]MHZ -> Vol [1100]mv
1>[TracePoint] type[  0] cmd[  1] data[  6]
1>[TracePoint] type[  0] cmd[  1] data[  7]
1>
********Hello Huawei LiteOS********

KpxxxxIPU Firmware Version : V32.70.0
LiteOS Kernel Version : 5.7.0
1>Run on ChipVersion[0] Node[1] Die[0]
1>build time : Feb 05 2026 20:30:00

1>**********************************
1>
main core booting up...
1>start set affinity
1>
mpidr = 0x81040000
1>sram ecc state: 0x0, sram ecc cnt: 0x0
1>[TracePoint] type[  0] cmd[  2] data[  1]
1>[TracePoint] type[  0] cmd[  2] data[  2]
1>LRDXSD_LOCK_OFFSET = 0x0
1>LRDXSD_ERRIMSK_OFFSET = 0x0
1>LRDXSD_DBG_OTIMSK_OFFSET = 0x0
1>LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
1>LRDXSD_DBG_EN_OFFSET = 0x1
1>======tsensor params======
1>  is_trimmed       : 1
1>  underclocking_en : 1
1>===========end============
1>soc tsensor init done
1>========vrd info from cpld========
1>vrd_id | u64                | pmbus_en | avsbus_en | loop | pmbus_id | pmbus_addr | avs_sw | pmbus_sw | addr_9545 | domain_type | die_mask | reserved
1>  00   | 0x0001000100002017 | 0x1      | 0x1       | 0x1  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0100   | 0x0
1>  01   | 0x000300030000201b | 0x1      | 0x1       | 0x2  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x3         | 0x0300   | 0x0
1>  02   | 0x0000010a00002715 | 0x1      | 0x0       | 0x1  | 0x1      | 0x27       | 0x0    | 0x0      | 0x0       | 0xa         | 0x0001   | 0x0
1>  03   | 0x0000010500002719 | 0x1      | 0x0       | 0x2  | 0x1      | 0x27       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0001   | 0x0
1>  04   | 0x0000020600002a15 | 0x1      | 0x0       | 0x1  | 0x1      | 0x2a       | 0x0    | 0x0      | 0x0       | 0x6         | 0x0002   | 0x0
1>  05   | 0x0000010600002a19 | 0x1      | 0x0       | 0x2  | 0x1      | 0x2a       | 0x0    | 0x0      | 0x0       | 0x6         | 0x0001   | 0x0
1>  06   | 0x0000020a00002f15 | 0x1      | 0x0       | 0x1  | 0x1      | 0x2f       | 0x0    | 0x0      | 0x0       | 0xa         | 0x0002   | 0x0
1>  07   | 0x0002000100002027 | 0x1      | 0x1       | 0x1  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0200   | 0x0
1>  08   | 0x000300020000202b | 0x1      | 0x1       | 0x2  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x2         | 0x0300   | 0x0
1>  09   | 0x0000030500002725 | 0x1      | 0x0       | 0x1  | 0x2      | 0x27       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0003   | 0x0
1>  10   | 0x0003000400002729 | 0x1      | 0x0       | 0x2  | 0x2      | 0x27       | 0x0    | 0x0      | 0x0       | 0x4         | 0x0300   | 0x0
1>================end===============
1>=============vrd info=============
1>power domain num: 11
1>power domain[00] id:0 | CORE_DVFS_TA       | PMBus NA | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
1>power domain[01] id:1 | DDR_VDD            | PMBus NA | cap:0x3 | rail:1 | addr:0x20 | def_volt: 800 mV | min_volt: 760 mV | max_volt: 840 mV
1>power domain[02] id:14 | NA_AVDD_SDS        | PMBus NA | cap:0x1 | rail:0 | addr:0x27 | def_volt:1200 mV | min_volt:1164 mV | max_volt:1236 mV
1>power domain[03] id:4 | IO_DVDD_NA         | PMBus NA | cap:0x1 | rail:1 | addr:0x27 | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
1>power domain[04] id:11 | IO_DVDD09_NB       | PMBus NA | cap:0x1 | rail:0 | addr:0x2a | def_volt: 900 mV | min_volt: 700 mV | max_volt: 900 mV
1>power domain[05] id:10 | IO_DVDD09_NA       | PMBus NA | cap:0x1 | rail:1 | addr:0x2a | def_volt: 900 mV | min_volt: 700 mV | max_volt: 900 mV
1>power domain[06] id:16 | NB_AVDD_SDS        | PMBus NA | cap:0x1 | rail:0 | addr:0x2f | def_volt:1200 mV | min_volt:1164 mV | max_volt:1236 mV
1>power domain[07] id:2 | CORE_DVFS_TB       | PMBus NB | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
1>power domain[08] id:3 | UNCORE_DVFS        | PMBus NB | cap:0x3 | rail:1 | addr:0x20 | def_volt: 948 mV | min_volt: 750 mV | max_volt:1100 mV
1>power domain[09] id:12 | IO_DVDD_NANB       | PMBus NB | cap:0x1 | rail:0 | addr:0x27 | def_volt: 800 mV | min_volt: 750 mV | max_volt: 900 mV
1>power domain[10] id:6 | DDR_VDDQ           | PMBus NB | cap:0x1 | rail:1 | addr:0x27 | def_volt:1100 mV | min_volt:1000 mV | max_volt:1200 mV
1>================end===============
1>pmbus[0] init done
1>pmbus[1] init done
1>power domain[0] CORE_DVFS_TA       | NA PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
1>power domain[1] DDR_VDD            | NA PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 800 mV | pmu:MP2882
1>power domain[14] NA_AVDD_SDS        | NA PMBus        | rail:0 | addr:0x27 | def_volt:1200 mV | pmu:MP2882
1>power domain[4] IO_DVDD_NA         | NA PMBus        | rail:1 | addr:0x27 | def_volt: 800 mV | pmu:MP2882
1>power domain[11] IO_DVDD09_NB       | NA PMBus        | rail:0 | addr:0x2a | def_volt: 900 mV | pmu:MP2882
1>power domain[10] IO_DVDD09_NA       | NA PMBus        | rail:1 | addr:0x2a | def_volt: 900 mV | pmu:MP2882
1>power domain[16] NB_AVDD_SDS        | NA PMBus        | rail:0 | addr:0x2f | def_volt:1200 mV | pmu:MP2882
1>power domain[2] CORE_DVFS_TB       | NB PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
1>power domain[3] UNCORE_DVFS        | NB PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 948 mV | pmu:MP2882
1>power domain[12] IO_DVDD_NANB       | NB PMBus        | rail:0 | addr:0x27 | def_volt: 800 mV | pmu:MP2882
1>power domain[6] DDR_VDDQ           | NB PMBus        | rail:1 | addr:0x27 | def_volt:1100 mV | pmu:MP2882
1>power domain[0] CORE_DVFS_TA       is transferred to AVSBus mode
1>power domain[1] DDR_VDD            is transferred to AVSBus mode
1>power domain[2] CORE_DVFS_TB       is transferred to AVSBus mode
1>power domain[3] UNCORE_DVFS        is transferred to AVSBus mode
1>avsbus resync success
1>avsbus[0] init done
1>avsbus resync success
1>avsbus[1] init done
1>============volt boot============
1>power domain[0] volt = 1103 mV
1>power domain[1] volt =  808 mV
1>power domain[14] volt = 1205 mV
1>power domain[4] volt =  806 mV
1>power domain[11] volt =  906 mV
1>power domain[10] volt =  904 mV
1>power domain[16] volt = 1203 mV
1>power domain[2] volt = 1097 mV
1>power domain[3] volt = 1007 mV
1>power domain[12] volt =  808 mV
1>power domain[6] volt = 1105 mV
1>===============end===============
1>--w&h rd rail:0, 1103, CORE_DVFS_TA
1>--w&h rd rail:1, 800, CORE_DVFS_TA
1>power domain[0] set volt --> 1103 mV success
1>--w&h rd rail:0, 1097, CORE_DVFS_TB
1>--w&h rd rail:1, 1007, CORE_DVFS_TB
1>power domain[2] set volt --> 1097 mV success
1>power domain[3] set volt -->  953 mV success
1>============volt post============
1>power domain[0] volt = 1103 mV
1>power domain[1] volt =  804 mV
1>power domain[14] volt = 1205 mV
1>power domain[4] volt =  806 mV
1>power domain[11] volt =  906 mV
1>power domain[10] volt =  906 mV
1>power domain[16] volt = 1203 mV
1>power domain[2] volt = 1097 mV
1>power domain[3] volt =  951 mV
1>power domain[12] volt =  808 mV
1>power domain[6] volt = 1105 mV
1>===============end===============
1>the power sensor : manu id = 2peak, die id = TPA626
1>power sensor[0] init success
1>die[0] its[0] init done
1>die[0] its[1] init done
1>die[0] its[2] init done
1>die[0] its[3] init done
1>die[0] its[4] init done
1>die[0] its[5] init done
1>die[0] its[6] init done
1>die[0] its[7] init done
1>die[0] its[8] init done
1>die[0] its[9] init done
1>die[1] its[0] init done
1>die[1] its[1] init done
1>die[1] its[2] init done
1>die[1] its[3] init done
1>die[1] its[4] init done
1>die[1] its[5] init done
1>die[1] its[6] init done
1>die[1] its[7] init done
1>die[1] its[8] init done
1>die[1] its[9] init done
1>Totem[0] Core Boot Vol [1103]mv
1>Totem[0] Core Current Vol [1100]mv
1>Totem[1] Core Boot Vol [1099]mv
1>Totem[1] Core Current Vol [1100]mv
1>NA 1620V1a0
1>NB 1620V1a0
1>GetCoreBaseFreq [2500000KHZ]
1>GetCoreTurboFreq [2500000KHZ]
1>GetCustomClusterNum [10]
1>Ipu ACG Training Done!
1>AP Last Time:[0.00.01.719]
1>wait UEFI pll init...
1>done
1>acg trim start
1>core trim freq:2000, avs:0 volt:810mv
1>core trim freq:2000, avs:0 volt:810mv
1>core trim freq:2050, avs:1 volt:810mv
1>core trim freq:2050, avs:1 volt:810mv
1>core trim freq:2100, avs:2 volt:810mv
1>core trim freq:2100, avs:2 volt:810mv
1>core trim freq:2150, avs:3 volt:810mv
1>core trim freq:2150, avs:3 volt:810mv
1>core trim freq:2200, avs:4 volt:814mv
1>core trim freq:2200, avs:4 volt:812mv
1>core trim freq:2250, avs:5 volt:826mv
1>core trim freq:2250, avs:5 volt:825mv
1>core trim freq:2300, avs:6 volt:839mv
1>core trim freq:2300, avs:6 volt:838mv
1>core trim freq:2350, avs:7 volt:852mv
1>core trim freq:2350, avs:7 volt:851mv
1>core trim freq:2400, avs:8 volt:865mv
1>core trim freq:2400, avs:8 volt:863mv
1>core trim freq:2450, avs:9 volt:878mv
1>core trim freq:2450, avs:9 volt:876mv
1>core trim freq:2500, avs:10 volt:890mv
1>core trim freq:2500, avs:10 volt:889mv
1>core trim freq:2550, avs:11 volt:903mv
1>core trim freq:2550, avs:11 volt:901mv
1>core trim freq:2600, avs:12 volt:916mv
1>core trim freq:2600, avs:12 volt:914mv
1>core trim freq:2650, avs:13 volt:929mv
1>core trim freq:2650, avs:13 volt:927mv
1>core trim freq:2700, avs:14 volt:942mv
1>core trim freq:2700, avs:14 volt:940mv
1>core trim freq:2750, avs:15 volt:960mv
1>core trim freq:2750, avs:15 volt:958mv
1>core trim freq:2800, avs:16 volt:978mv
1>core trim freq:2800, avs:16 volt:976mv
1>core trim freq:2850, avs:17 volt:996mv
1>core trim freq:2850, avs:17 volt:994mv
1>core trim freq:2900, avs:18 volt:1015mv
1>core trim freq:2900, avs:18 volt:1012mv
1>core trim freq:2950, avs:19 volt:1032mv
1>core trim freq:2950, avs:19 volt:1029mv
1>core trim freq:3000, avs:20 volt:1050mv
1>core trim freq:3000, avs:20 volt:1047mv
1>core trim freq:3050, avs:21 volt:1063mv
1>core trim freq:3050, avs:21 volt:1060mv
1>core trim freq:3100, avs:22 volt:1076mv
1>core trim freq:3100, avs:22 volt:1074mv
1>acg trim end
1>LDO disabled
1>[TracePoint] type[  0] cmd[  2] data[  3]
1>Interrupt 423 register OK
1>Interrupt 430 register OK
1>[TracePoint] type[  0] cmd[  2] data[  4]
1>
1>cpu 0 entering scheduler
1>[TracePoint] type[  0] cmd[  3] data[  1]
1>add your ipu app init here!
1>IpuInterfaceTaskStart Entry ...
1>ipu interface task wait parameters from uefi...
1>thermal soc task enabled
1>AP Last Time:[0.00.40.979]
1>ThermalDimmStart Entry ...
1>wait ddr init done...
1>power task start...
1>[TracePoint] type[  0] cmd[  3] data[  2]
1>ufs task wait parameters from uefi...
1>AmuTaskStart Entry ... 
1>amu task wait parameters from uefi...
1>ThermalSiwStart Entry ...
1>ThermalSiwTask idle...
1>DemtTaskStart Entry ...
1>[TracePoint] type[  0] cmd[  3] data[  3]
1>HiBoostTaskStart Entry ...
1>HiBoost task enabled
1>Waiting for UEFI parameters...
1>[TracePoint] type[  0] cmd[  3] data[  4]
1>demt task wait parameters from uefi...
1>AgeTaskStart Entry ...
1>age task wait parameters from uefi...
1>[TracePoint] type[  0] cmd[  3] data[  5]
1>uefi parameters ready!
1>UFSProfile[0]
1>ufs task parameters from uefi ready
1>uncore domain[0] freq:2900
1>uncore domain[1] freq:2900
1>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
1>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
1>======sioe status======
1>TA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TA_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
1>thermal soc task restore underclocking_en=1
1>ppu alert temp div init done
1>TA_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TA_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
1>TA_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
1>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
1>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
1>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
1>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
1>==========end==========
1>sioe init done
1>ufs task enabled
1>--> UFS profile[0]
1>PowerPolicy[2] BenchMarkSelection[0]
1>ipu interface task wait ddr init done from uefi...
1>UEFI parameters ready
1>UncoreMaxFreq Set to [2900 MHZ]
1>get TDP from efuse success, value = 307500mw
1>target power set to [307500]mw, brd:[307500]
1>demt task parameters from uefi ready
1>age task parameters from uefi ready
1>age task enabled
1>uefi ddr init finish!
1>ipu interface task wait uefi end done from uefi...
1>ddr init done, start thermal dimm task
1>======dimm status======
1>  chl[0] dimm0 0, dimm1 0
1>  chl[1] dimm0 0, dimm1 0
1>  chl[2] dimm0 0, dimm1 0
1>  chl[3] dimm0 0, dimm1 0
1>  chl[4] dimm0 0, dimm1 0
1>  chl[5] dimm0 0, dimm1 0
1>  chl[6] dimm0 0, dimm1 0
1>  chl[7] dimm0 0, dimm1 0
1>==========end==========
1>=====dimm temp params=====
1>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
1>  is_thermal_thro_en  : 1
1>  is_aref_rate_auto   : 1
1>===========end============

2>[2450]MHZ -> Vol TA[ 878]mv TB[ 877]mv
2>[2500]MHZ -> Vol TA[ 891]mv TB[ 889]mv
2>[2550]MHZ -> Vol TA[ 904]mv TB[ 902]mv
2>[2600]MHZ -> Vol TA[ 917]mv TB[ 915]mv
2>[2650]MHZ -> Vol TA[ 930]mv TB[ 928]mv
2>[2700]MHZ -> Vol TA[ 943]mv TB[ 941]mv
2>[2750]MHZ -> Vol TA[ 961]mv TB[ 959]mv
2>[2800]MHZ -> Vol TA[ 979]mv TB[ 977]mv
2>[2850]MHZ -> Vol TA[ 997]mv TB[ 995]mv
2>[2900]MHZ -> Vol TA[1016]mv TB[1014]mv
2>[2950]MHZ -> Vol TA[1033]mv TB[1031]mv
2>[3000]MHZ -> Vol TA[1051]mv TB[1049]mv
2>[3050]MHZ -> Vol TA[1064]mv TB[1062]mv
2>[3100]MHZ -> Vol TA[1077]mv TB[1075]mv
2>Uncore VF curve:
2>Uncore [   0]MHZ -> Vol [ 810]mv
2>Uncore [ 100]MHZ -> Vol [ 810]mv
2>Uncore [ 200]MHZ -> Vol [ 810]mv
2>Uncore [ 300]MHZ -> Vol [ 810]mv
2>Uncore [ 400]MHZ -> Vol [ 810]mv
2>Uncore [ 500]MHZ -> Vol [ 810]mv
2>Uncore [ 600]MHZ -> Vol [ 810]mv
2>Uncore [ 700]MHZ -> Vol [ 810]mv
2>Uncore [ 800]MHZ -> Vol [ 810]mv
2>Uncore [ 900]MHZ -> Vol [ 810]mv
2>Uncore [1000]MHZ -> Vol [ 810]mv
2>Uncore [1100]MHZ -> Vol [ 810]mv
2>Uncore [1200]MHZ -> Vol [ 810]mv
2>Uncore [1300]MHZ -> Vol [ 810]mv
2>Uncore [1400]MHZ -> Vol [ 810]mv
2>Uncore [1500]MHZ -> Vol [ 810]mv
2>Uncore [1600]MHZ -> Vol [ 810]mv
2>Uncore [1700]MHZ -> Vol [ 810]mv
2>Uncore [1800]MHZ -> Vol [ 810]mv
2>Uncore [1900]MHZ -> Vol [ 810]mv
2>Uncore [2000]MHZ -> Vol [ 810]mv
2>Uncore [2100]MHZ -> Vol [ 810]mv
2>Uncore [2200]MHZ -> Vol [ 811]mv
2>Uncore [2300]MHZ -> Vol [ 828]mv
2>Uncore [2400]MHZ -> Vol [ 845]mv
2>Uncore [2500]MHZ -> Vol [ 862]mv
2>Uncore [2600]MHZ -> Vol [ 882]mv
2>Uncore [2700]MHZ -> Vol [ 902]mv
2>Uncore [2800]MHZ -> Vol [ 922]mv
2>Uncore [2900]MHZ -> Vol [ 943]mv
2>Uncore [3000]MHZ -> Vol [1100]mv
2>[TracePoint] type[  0] cmd[  1] data[  6]
2>[TracePoint] type[  0] cmd[  1] data[  7]
2>
********Hello Huawei LiteOS********

KpxxxxIPU Firmware Version : V32.70.0
LiteOS Kernel Version : 5.7.0
2>Run on ChipVersion[0] Node[2] Die[0]
2>build time : Feb 05 2026 20:30:00

2>**********************************
2>
main core booting up...
2>start set affinity
2>
mpidr = 0x81080000
2>sram ecc state: 0x0, sram ecc cnt: 0x0
2>[TracePoint] type[  0] cmd[  2] data[  1]
2>[TracePoint] type[  0] cmd[  2] data[  2]
2>LRDXSD_LOCK_OFFSET = 0x0
2>LRDXSD_ERRIMSK_OFFSET = 0x0
2>LRDXSD_DBG_OTIMSK_OFFSET = 0x0
2>LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
2>LRDXSD_DBG_EN_OFFSET = 0x1
2>======tsensor params======
2>  is_trimmed       : 1
2>  underclocking_en : 1
2>===========end============
2>soc tsensor init done
2>========vrd info from cpld========
2>vrd_id | u64                | pmbus_en | avsbus_en | loop | pmbus_id | pmbus_addr | avs_sw | pmbus_sw | addr_9545 | domain_type | die_mask | reserved
2>  00   | 0x0001000100002017 | 0x1      | 0x1       | 0x1  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0100   | 0x0
2>  01   | 0x000001060000201b | 0x1      | 0x1       | 0x2  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x6         | 0x0001   | 0x0
2>  02   | 0x0003000300002715 | 0x1      | 0x0       | 0x1  | 0x1      | 0x27       | 0x0    | 0x0      | 0x0       | 0x3         | 0x0300   | 0x0
2>  03   | 0x0003000400002719 | 0x1      | 0x0       | 0x2  | 0x1      | 0x27       | 0x0    | 0x0      | 0x0       | 0x4         | 0x0300   | 0x0
2>  04   | 0x0002000100002027 | 0x1      | 0x1       | 0x1  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0200   | 0x0
2>  05   | 0x000300020000202b | 0x1      | 0x1       | 0x2  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x2         | 0x0300   | 0x0
2>  06   | 0x0000020a00002725 | 0x1      | 0x0       | 0x1  | 0x2      | 0x27       | 0x0    | 0x0      | 0x0       | 0xa         | 0x0002   | 0x0
2>  07   | 0x0000020500002729 | 0x1      | 0x0       | 0x2  | 0x2      | 0x27       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0002   | 0x0
2>  08   | 0x0000020600002a25 | 0x1      | 0x0       | 0x1  | 0x2      | 0x2a       | 0x0    | 0x0      | 0x0       | 0x6         | 0x0002   | 0x0
2>  09   | 0x0000010a00002a29 | 0x1      | 0x0       | 0x2  | 0x2      | 0x2a       | 0x0    | 0x0      | 0x0       | 0xa         | 0x0001   | 0x0
2>================end===============
2>=============vrd info=============
2>power domain num: 10
2>power domain[00] id:0 | CORE_DVFS_TA       | PMBus NA | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
2>power domain[01] id:10 | IO_DVDD09_NA       | PMBus NA | cap:0x3 | rail:1 | addr:0x20 | def_volt: 900 mV | min_volt: 700 mV | max_volt: 900 mV
2>power domain[02] id:1 | DDR_VDD            | PMBus NA | cap:0x1 | rail:0 | addr:0x27 | def_volt: 800 mV | min_volt: 760 mV | max_volt: 840 mV
2>power domain[03] id:6 | DDR_VDDQ           | PMBus NA | cap:0x1 | rail:1 | addr:0x27 | def_volt:1100 mV | min_volt:1000 mV | max_volt:1200 mV
2>power domain[04] id:2 | CORE_DVFS_TB       | PMBus NB | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
2>power domain[05] id:3 | UNCORE_DVFS        | PMBus NB | cap:0x3 | rail:1 | addr:0x20 | def_volt: 943 mV | min_volt: 750 mV | max_volt:1100 mV
2>power domain[06] id:15 | NB_AVDD_SDS        | PMBus NB | cap:0x1 | rail:0 | addr:0x27 | def_volt:1200 mV | min_volt:1164 mV | max_volt:1236 mV
2>power domain[07] id:5 | IO_DVDD_NB         | PMBus NB | cap:0x1 | rail:1 | addr:0x27 | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
2>power domain[08] id:11 | IO_DVDD09_NB       | PMBus NB | cap:0x1 | rail:0 | addr:0x2a | def_volt: 900 mV | min_volt: 700 mV | max_volt: 900 mV
2>power domain[09] id:13 | NA_AVDD_SDS        | PMBus NB | cap:0x1 | rail:1 | addr:0x2a | def_volt:1200 mV | min_volt:1164 mV | max_volt:1236 mV
2>================end===============
2>pmbus[0] init done
2>pmbus[1] init done
2>power domain[0] CORE_DVFS_TA       | NA PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
2>power domain[10] IO_DVDD09_NA       | NA PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 900 mV | pmu:MP2882
2>power domain[1] DDR_VDD            | NA PMBus        | rail:0 | addr:0x27 | def_volt: 800 mV | pmu:MP2882
2>power domain[6] DDR_VDDQ           | NA PMBus        | rail:1 | addr:0x27 | def_volt:1100 mV | pmu:MP2882
2>power domain[2] CORE_DVFS_TB       | NB PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
2>power domain[3] UNCORE_DVFS        | NB PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 943 mV | pmu:MP2882
2>power domain[15] NB_AVDD_SDS        | NB PMBus        | rail:0 | addr:0x27 | def_volt:1200 mV | pmu:MP2882
2>power domain[5] IO_DVDD_NB         | NB PMBus        | rail:1 | addr:0x27 | def_volt: 800 mV | pmu:MP2882
2>power domain[11] IO_DVDD09_NB       | NB PMBus        | rail:0 | addr:0x2a | def_volt: 900 mV | pmu:MP2882
2>power domain[13] NA_AVDD_SDS        | NB PMBus        | rail:1 | addr:0x2a | def_volt:1200 mV | pmu:MP2882
2>power domain[0] CORE_DVFS_TA       is transferred to AVSBus mode
2>power domain[10] IO_DVDD09_NA       is transferred to AVSBus mode
2>power domain[2] CORE_DVFS_TB       is transferred to AVSBus mode
2>power domain[3] UNCORE_DVFS        is transferred to AVSBus mode
2>avsbus resync success
2>avsbus[0] init done
2>avsbus resync success
2>avsbus[1] init done
2>============volt boot============
2>power domain[0] volt = 1105 mV
2>power domain[10] volt =  904 mV
2>power domain[1] volt =  806 mV
2>power domain[6] volt = 1103 mV
2>power domain[2] volt = 1109 mV
2>power domain[3] volt = 1005 mV
2>power domain[15] volt = 1206 mV
2>power domain[5] volt =  806 mV
2>power domain[11] volt =  906 mV
2>power domain[13] volt = 1205 mV
2>===============end===============
2>--w&h rd rail:0, 1103, CORE_DVFS_TA
2>--w&h rd rail:1, 900, CORE_DVFS_TA
2>power domain[0] set volt --> 1105 mV success
2>--w&h rd rail:0, 1109, CORE_DVFS_TB
2>--w&h rd rail:1, 1007, CORE_DVFS_TB
2>power domain[2] set volt --> 1109 mV success
2>power domain[3] set volt -->  947 mV success
2>============volt post============
2>power domain[0] volt = 1105 mV
2>power domain[10] volt =  904 mV
2>power domain[1] volt =  806 mV
2>power domain[6] volt = 1105 mV
2>power domain[2] volt = 1109 mV
2>power domain[3] volt =  947 mV
2>power domain[15] volt = 1206 mV
2>power domain[5] volt =  806 mV
2>power domain[11] volt =  906 mV
2>power domain[13] volt = 1205 mV
2>===============end===============
2>die[0] its[0] init done
2>die[0] its[1] init done
2>die[0] its[2] init done
2>die[0] its[3] init done
2>die[0] its[4] init done
2>die[0] its[5] init done
2>die[0] its[6] init done
2>die[0] its[7] init done
2>die[0] its[8] init done
2>die[0] its[9] init done
2>die[1] its[0] init done
2>die[1] its[1] init done
2>die[1] its[2] init done
2>die[1] its[3] init done
2>die[1] its[4] init done
2>die[1] its[5] init done
2>die[1] its[6] init done
2>die[1] its[7] init done
2>die[1] its[8] init done
2>die[1] its[9] init done
2>Totem[0] Core Boot Vol [1105]mv
2>Totem[0] Core Current Vol [1100]mv
2>Totem[1] Core Boot Vol [1109]mv
2>Totem[1] Core Current Vol [1100]mv
2>NA 1620V1a0
2>NB 1620V1a0
2>GetCoreBaseFreq [2500000KHZ]
2>GetCoreTurboFreq [2500000KHZ]
2>GetCustomClusterNum [10]
2>Ipu ACG Training Done!
2>AP Last Time:[0.00.01.664]
2>wait UEFI pll init...
2>done
2>acg trim start
2>core trim freq:2000, avs:0 volt:810mv
2>core trim freq:2000, avs:0 volt:810mv
2>core trim freq:2050, avs:1 volt:810mv
2>core trim freq:2050, avs:1 volt:810mv
2>core trim freq:2100, avs:2 volt:810mv
2>core trim freq:2100, avs:2 volt:810mv
2>core trim freq:2150, avs:3 volt:810mv
2>core trim freq:2150, avs:3 volt:810mv
2>core trim freq:2200, avs:4 volt:814mv
2>core trim freq:2200, avs:4 volt:813mv
2>core trim freq:2250, avs:5 volt:827mv
2>core trim freq:2250, avs:5 volt:825mv
2>core trim freq:2300, avs:6 volt:840mv
2>core trim freq:2300, avs:6 volt:838mv
2>core trim freq:2350, avs:7 volt:853mv
2>core trim freq:2350, avs:7 volt:851mv
2>core trim freq:2400, avs:8 volt:865mv
2>core trim freq:2400, avs:8 volt:864mv
2>core trim freq:2450, avs:9 volt:878mv
2>core trim freq:2450, avs:9 volt:877mv
2>core trim freq:2500, avs:10 volt:891mv
2>core trim freq:2500, avs:10 volt:889mv
2>core trim freq:2550, avs:11 volt:904mv
2>core trim freq:2550, avs:11 volt:902mv
2>core trim freq:2600, avs:12 volt:917mv
2>core trim freq:2600, avs:12 volt:915mv
2>core trim freq:2650, avs:13 volt:930mv
2>core trim freq:2650, avs:13 volt:928mv
2>core trim freq:2700, avs:14 volt:943mv
2>core trim freq:2700, avs:14 volt:941mv
2>core trim freq:2750, avs:15 volt:961mv
2>core trim freq:2750, avs:15 volt:959mv
2>core trim freq:2800, avs:16 volt:979mv
2>core trim freq:2800, avs:16 volt:977mv
2>core trim freq:2850, avs:17 volt:997mv
2>core trim freq:2850, avs:17 volt:995mv
2>core trim freq:2900, avs:18 volt:1016mv
2>core trim freq:2900, avs:18 volt:1014mv
2>core trim freq:2950, avs:19 volt:1033mv
2>core trim freq:2950, avs:19 volt:1031mv
2>core trim freq:3000, avs:20 volt:1051mv
2>core trim freq:3000, avs:20 volt:1049mv
2>core trim freq:3050, avs:21 volt:1064mv
2>core trim freq:3050, avs:21 volt:1062mv
2>core trim freq:3100, avs:22 volt:1077mv
2>core trim freq:3100, avs:22 volt:1075mv
2>acg trim end
2>LDO disabled
2>[TracePoint] type[  0] cmd[  2] data[  3]
2>Interrupt 423 register OK
2>Interrupt 430 register OK
2>[TracePoint] type[  0] cmd[  2] data[  4]
2>
2>cpu 0 entering scheduler
2>[TracePoint] type[  0] cmd[  3] data[  1]
2>add your ipu app init here!
2>IpuInterfaceTaskStart Entry ...
2>ipu interface task wait parameters from uefi...
2>thermal soc task enabled
2>AP Last Time:[0.00.40.941]
2>ThermalDimmStart Entry ...
2>wait ddr init done...
2>power task start...
2>[TracePoint] type[  0] cmd[  3] data[  2]
2>ufs task wait parameters from uefi...
2>AmuTaskStart Entry ... 
2>amu task wait parameters from uefi...
2>ThermalSiwStart Entry ...
2>ThermalSiwTask idle...
2>DemtTaskStart Entry ...
2>[TracePoint] type[  0] cmd[  3] data[  3]
2>demt task wait parameters from uefi...
2>HiBoostTaskStart Entry ...
2>HiBoost task enabled
2>Waiting for UEFI parameters...
2>[TracePoint] type[  0] cmd[  3] data[  4]
2>AgeTaskStart Entry ...
2>age task wait parameters from uefi...
2>[TracePoint] type[  0] cmd[  3] data[  5]
2>uefi parameters ready!
2>UFSProfile[0]
2>PowerPolicy[2] BenchMarkSelection[0]
2>ipu interface task wait ddr init done from uefi...
2>ufs task parameters from uefi ready
2>uncore domain[0] freq:2900
2>uncore domain[1] freq:2900
2>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
2>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
2>======sioe status======
2>TA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
2>thermal soc task restore underclocking_en=1
2>ppu alert temp div init done
2>TA_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
2>TA_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
2>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
2>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
2>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
2>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
2>==========end==========
2>sioe init done
2>ufs task enabled
2>--> UFS profile[0]
2>UEFI parameters ready
2>UncoreMaxFreq Set to [2900 MHZ]
2>get TDP from efuse success, value = 307500mw
2>target power set to [307500]mw, brd:[307500]
2>demt task parameters from uefi ready
2>age task parameters from uefi ready
2>age task enabled
2>uefi ddr init finish!
2>ipu interface task wait uefi end done from uefi...
2>ddr init done, start thermal dimm task
2>======dimm status======
2>  chl[0] dimm0 0, dimm1 0
2>  chl[1] dimm0 0, dimm1 0
2>  chl[2] dimm0 2, dimm1 0
2>  chl[3] dimm0 0, dimm1 0
2>  chl[4] dimm0 0, dimm1 0
2>  chl[5] dimm0 0, dimm1 0
2>  chl[6] dimm0 0, dimm1 0
2>  chl[7] dimm0 0, dimm1 0
2>==========end==========
2>chl[2] registered, dimm mask = 0x1
2>=====dimm temp params=====
2>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
2>  is_thermal_thro_en  : 1
2>  is_aref_rate_auto   : 1
2>===========end============
2>chl[2] max_temp 47'C, aref_rate 0x5 --> 0x4
3>Uncore [   0]MHZ -> Vol [ 810]mv
3>Uncore [ 100]MHZ -> Vol [ 810]mv
3>Uncore [ 200]MHZ -> Vol [ 810]mv
3>Uncore [ 300]MHZ -> Vol [ 810]mv
3>Uncore [ 400]MHZ -> Vol [ 810]mv
3>Uncore [ 500]MHZ -> Vol [ 810]mv
3>Uncore [ 600]MHZ -> Vol [ 810]mv
3>Uncore [ 700]MHZ -> Vol [ 810]mv
3>Uncore [ 800]MHZ -> Vol [ 810]mv
3>Uncore [ 900]MHZ -> Vol [ 810]mv
3>Uncore [1000]MHZ -> Vol [ 810]mv
3>Uncore [1100]MHZ -> Vol [ 810]mv
3>Uncore [1200]MHZ -> Vol [ 810]mv
3>Uncore [1300]MHZ -> Vol [ 810]mv
3>Uncore [1400]MHZ -> Vol [ 810]mv
3>Uncore [1500]MHZ -> Vol [ 810]mv
3>Uncore [1600]MHZ -> Vol [ 810]mv
3>Uncore [1700]MHZ -> Vol [ 810]mv
3>Uncore [1800]MHZ -> Vol [ 810]mv
3>Uncore [1900]MHZ -> Vol [ 810]mv
3>Uncore [2000]MHZ -> Vol [ 810]mv
3>Uncore [2100]MHZ -> Vol [ 810]mv
3>Uncore [2200]MHZ -> Vol [ 811]mv
3>Uncore [2300]MHZ -> Vol [ 828]mv
3>Uncore [2400]MHZ -> Vol [ 845]mv
3>Uncore [2500]MHZ -> Vol [ 862]mv
3>Uncore [2600]MHZ -> Vol [ 882]mv
3>Uncore [2700]MHZ -> Vol [ 902]mv
3>Uncore [2800]MHZ -> Vol [ 922]mv
3>Uncore [2900]MHZ -> Vol [ 943]mv
3>Uncore [3000]MHZ -> Vol [1100]mv
3>[TracePoint] type[  0] cmd[  1] data[  6]
3>[TracePoint] type[  0] cmd[  1] data[  7]
3>
