ID      |Generation Time     |Severity    |Event Code  |Status      |Event Description
429     |2026-03-14 06:55:58 |Major       |0x000000DE  |Deasserted  |CPU 2(CpuBoard1 CPU2) Uncore voltage (1.01 V) exceeds the overvoltage threshold ( V).
428     |2026-03-14 06:54:53 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
427     |2026-03-14 06:54:47 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
426     |2026-03-14 06:52:30 |Major       |0x000000DD  |Asserted    |CPU 2(CpuBoard1 CPU2) Uncore voltage (1.01 V) exceeds the overvoltage threshold ( V).
425     |2026-03-14 06:51:25 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
424     |2026-03-14 06:51:18 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
423     |2026-03-14 06:48:20 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
422     |2026-03-14 06:48:17 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
421     |2026-03-14 06:40:48 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
420     |2026-03-14 06:40:44 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
419     |2026-03-14 06:37:15 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
418     |2026-03-14 06:37:08 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
417     |2026-03-14 06:34:53 |Major       |0x000000DE  |Deasserted  |CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
416     |2026-03-14 06:34:52 |Major       |0x000000DE  |Deasserted  |CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
415     |2026-03-14 06:33:48 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
414     |2026-03-14 06:33:45 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
413     |2026-03-14 06:30:54 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
412     |2026-03-14 06:30:14 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
411     |2026-03-14 06:26:47 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
410     |2026-03-14 06:26:43 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
409     |2026-03-14 06:24:24 |Major       |0x000000DD  |Asserted    |CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
408     |2026-03-14 06:23:57 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
407     |2026-03-14 06:23:18 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
406     |2026-03-14 06:20:52 |Major       |0x000000DE  |Deasserted  |CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
405     |2026-03-14 06:20:26 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
404     |2026-03-14 06:19:47 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
403     |2026-03-14 06:17:02 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
402     |2026-03-14 06:16:23 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
401     |2026-03-14 06:13:43 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
400     |2026-03-14 06:12:57 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
399     |2026-03-14 06:09:50 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
398     |2026-03-14 06:09:43 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
397     |2026-03-14 06:06:14 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
396     |2026-03-14 06:06:06 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
395     |2026-03-14 06:02:44 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
394     |2026-03-14 06:02:40 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
393     |2026-03-14 06:00:21 |Major       |0x000000DD  |Asserted    |CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
392     |2026-03-14 06:00:21 |Major       |0x000000DD  |Asserted    |CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
391     |2026-03-14 05:59:54 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
390     |2026-03-14 05:59:14 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
389     |2026-03-14 05:56:33 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
388     |2026-03-14 05:55:46 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
387     |2026-03-14 05:52:48 |Critical    |0x0300000D  |Asserted    |The AC/DC input of PSU 4 is lost or out-of-range (SN:G1302262NA241102023, BN:302004098).
386     |2026-03-14 05:52:22 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
385     |2026-03-14 05:51:48 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
384     |2026-03-14 05:49:18 |Critical    |0x0300000D  |Asserted    |The AC/DC input of PSU 3 is lost or out-of-range (SN:G1302262NA241202431, BN:302004098).
383     |2026-03-14 05:48:39 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
382     |2026-03-14 05:48:32 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
381     |2026-03-14 05:43:49 |Critical    |0x0300000E  |Deasserted  |The AC/DC input of PSU 4 is lost or out-of-range (SN:G1302262NA241102023, BN:302004098).
380     |2026-03-14 05:43:49 |Critical    |0x0300000E  |Deasserted  |The AC/DC input of PSU 3 is lost or out-of-range (SN:G1302262NA241202431, BN:302004098).
379     |2026-03-14 05:42:54 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
378     |2026-03-14 05:42:51 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
377     |2026-03-14 05:40:06 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
376     |2026-03-14 05:40:04 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
375     |2026-03-14 05:37:38 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
374     |2026-03-14 05:36:59 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
373     |2026-03-14 05:34:35 |Major       |0x000000DE  |Deasserted  |CPU 2(CpuBoard1 CPU2) Uncore voltage (1.01 V) exceeds the overvoltage threshold ( V).
372     |2026-03-14 05:33:30 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
371     |2026-03-14 05:33:26 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
370     |2026-03-14 05:30:28 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
369     |2026-03-14 05:30:23 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
368     |2026-03-14 05:27:25 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
367     |2026-03-14 05:27:17 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
366     |2026-03-14 05:25:03 |Major       |0x000000DD  |Asserted    |CPU 2(CpuBoard1 CPU2) Uncore voltage (1.01 V) exceeds the overvoltage threshold ( V).
365     |2026-03-14 05:20:43 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
364     |2026-03-14 05:20:35 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
363     |2026-03-14 05:17:14 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
362     |2026-03-14 05:17:09 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
361     |2026-03-14 05:13:23 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
360     |2026-03-14 05:13:20 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
359     |2026-03-14 05:10:12 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
358     |2026-03-14 05:10:07 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
357     |2026-03-14 05:07:07 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
356     |2026-03-14 05:07:00 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
355     |2026-03-14 05:02:21 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
354     |2026-03-14 05:02:17 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
353     |2026-03-14 04:59:03 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
352     |2026-03-14 04:58:55 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
351     |2026-03-14 04:53:13 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
350     |2026-03-14 04:49:58 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
349     |2026-03-14 04:49:50 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
348     |2026-03-14 04:47:39 |Major       |0x000000DE  |Deasserted  |CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
347     |2026-03-14 04:46:33 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
346     |2026-03-14 04:46:28 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
345     |2026-03-14 04:44:06 |Major       |0x000000DE  |Deasserted  |CPU 1(CpuBoard1 CPU1) Uncore voltage (1.01 V) exceeds the overvoltage threshold ( V).
344     |2026-03-14 04:40:17 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
343     |2026-03-14 04:39:36 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
342     |2026-03-14 04:36:13 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
341     |2026-03-14 04:36:07 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
340     |2026-03-14 04:33:39 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
339     |2026-03-14 04:32:50 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
338     |2026-03-14 04:27:46 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
337     |2026-03-14 04:27:00 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
336     |2026-03-14 04:23:47 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
335     |2026-03-14 04:23:41 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
334     |2026-03-14 04:20:52 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
333     |2026-03-14 04:20:45 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
332     |2026-03-14 04:18:27 |Major       |0x000000DD  |Asserted    |CPU 1(CpuBoard1 CPU1) Uncore voltage (1.01 V) exceeds the overvoltage threshold ( V).
331     |2026-03-14 04:18:27 |Major       |0x000000DD  |Asserted    |CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
330     |2026-03-14 04:17:21 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
329     |2026-03-14 04:17:16 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
328     |2026-03-14 04:11:17 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
327     |2026-03-14 04:09:01 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
326     |2026-03-14 04:08:17 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
325     |2026-03-14 04:05:58 |Major       |0x000000DE  |Deasserted  |CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
324     |2026-03-14 04:05:58 |Major       |0x000000DE  |Deasserted  |CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
323     |2026-03-14 04:01:23 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
322     |2026-03-14 03:59:13 |Major       |0x000000DD  |Asserted    |CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
321     |2026-03-14 03:59:13 |Major       |0x000000DD  |Asserted    |CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
320     |2026-03-14 03:54:55 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
319     |2026-03-14 03:52:21 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
318     |2026-03-14 03:51:34 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
317     |2026-03-14 03:49:23 |Major       |0x000000DE  |Deasserted  |CPU 1(CpuBoard1 CPU1) Uncore voltage (1.01 V) exceeds the overvoltage threshold ( V).
316     |2026-03-14 03:49:22 |Major       |0x000000DE  |Deasserted  |CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
315     |2026-03-14 03:48:54 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
314     |2026-03-14 03:48:12 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
313     |2026-03-14 03:45:55 |Major       |0x000000DD  |Asserted    |CPU 1(CpuBoard1 CPU1) Uncore voltage (1.01 V) exceeds the overvoltage threshold ( V).
312     |2026-03-14 03:45:54 |Major       |0x000000DD  |Asserted    |CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
311     |2026-03-14 03:41:58 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
310     |2026-03-14 03:41:50 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
309     |2026-03-14 03:39:00 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
308     |2026-03-14 03:38:53 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
307     |2026-03-14 03:35:56 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
306     |2026-03-14 03:35:53 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
305     |2026-03-14 03:33:02 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
304     |2026-03-14 03:32:58 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
303     |2026-03-14 03:30:36 |Major       |0x000000DE  |Deasserted  |CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
302     |2026-03-14 03:29:33 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
301     |2026-03-14 03:29:28 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
300     |2026-03-14 03:27:03 |Major       |0x000000DD  |Asserted    |CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
299     |2026-03-14 03:26:01 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
298     |2026-03-14 03:25:58 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
297     |2026-03-14 03:23:05 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
296     |2026-03-14 03:22:57 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
295     |2026-03-14 03:19:33 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
294     |2026-03-14 03:19:29 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
293     |2026-03-14 03:16:48 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
292     |2026-03-14 03:16:00 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
291     |2026-03-14 03:13:17 |Critical    |0x0300000D  |Asserted    |The AC/DC input of PSU 3 is lost or out-of-range (SN:G1302262NA241202431, BN:302004098).
290     |2026-03-14 03:13:17 |Critical    |0x0300000D  |Asserted    |The AC/DC input of PSU 4 is lost or out-of-range (SN:G1302262NA241102023, BN:302004098).
289     |2026-03-14 03:12:17 |Critical    |0x0300000E  |Deasserted  |The AC/DC input of PSU 4 is lost or out-of-range (SN:G1302262NA241102023, BN:302004098).
288     |2026-03-14 03:11:53 |Critical    |0x0300000E  |Deasserted  |The AC/DC input of PSU 3 is lost or out-of-range (SN:G1302262NA241202431, BN:302004098).
287     |2026-03-14 03:11:52 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
286     |2026-03-14 03:11:20 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
285     |2026-03-14 03:08:07 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
284     |2026-03-14 03:08:02 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
283     |2026-03-14 03:05:01 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
282     |2026-03-14 03:04:56 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
281     |2026-03-14 03:02:05 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
280     |2026-03-14 03:01:21 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
279     |2026-03-14 02:58:35 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
278     |2026-03-14 02:57:55 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
277     |2026-03-14 02:55:35 |Major       |0x000000DE  |Deasserted  |CPU 1(CpuBoard1 CPU1) Uncore voltage (1.01 V) exceeds the overvoltage threshold ( V).
276     |2026-03-14 02:55:34 |Major       |0x000000DE  |Deasserted  |CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
275     |2026-03-14 02:55:07 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
274     |2026-03-14 02:54:28 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
273     |2026-03-14 02:52:04 |Major       |0x000000DD  |Asserted    |CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
272     |2026-03-14 02:50:59 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
271     |2026-03-14 02:50:53 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
270     |2026-03-14 02:48:34 |Major       |0x000000DD  |Asserted    |CPU 1(CpuBoard1 CPU1) Uncore voltage (1.01 V) exceeds the overvoltage threshold ( V).
269     |2026-03-14 02:47:30 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
268     |2026-03-14 02:47:23 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
267     |2026-03-14 02:43:55 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
266     |2026-03-14 02:43:47 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
265     |2026-03-14 02:41:33 |Major       |0x000000DE  |Deasserted  |CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
264     |2026-03-14 02:40:27 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
263     |2026-03-14 02:40:19 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
262     |2026-03-14 02:38:00 |Major       |0x000000DE  |Deasserted  |CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
261     |2026-03-14 02:36:55 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
260     |2026-03-14 02:36:51 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
259     |2026-03-14 02:33:38 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
258     |2026-03-14 02:33:32 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
257     |2026-03-14 02:30:44 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
256     |2026-03-14 02:29:57 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
255     |2026-03-14 02:23:38 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
254     |2026-03-14 02:21:30 |Major       |0x000000DD  |Asserted    |CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
253     |2026-03-14 02:21:29 |Major       |0x000000DD  |Asserted    |CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
252     |2026-03-14 02:21:27 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
251     |2026-03-14 02:20:20 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
250     |2026-03-14 02:13:14 |Major       |0x000000DE  |Deasserted  |CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold (1.1 V).
249     |2026-03-14 02:13:13 |Major       |0x000000DE  |Deasserted  |CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
248     |2026-03-14 02:13:12 |Critical    |0x0300000D  |Asserted    |The AC/DC input of PSU 3 is lost or out-of-range (SN:G1302262NA241202431, BN:302004098).
247     |2026-03-14 02:13:12 |Critical    |0x0300000D  |Asserted    |The AC/DC input of PSU 4 is lost or out-of-range (SN:G1302262NA241102023, BN:302004098).
246     |2026-03-14 02:11:27 |Critical    |0x0300000E  |Deasserted  |The AC/DC input of PSU 3 is lost or out-of-range (SN:G1302262NA241202431, BN:302004098).
245     |2026-03-14 02:11:27 |Critical    |0x0300000E  |Deasserted  |The AC/DC input of PSU 4 is lost or out-of-range (SN:G1302262NA241102023, BN:302004098).
244     |2026-03-14 02:10:55 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
243     |2026-03-14 02:10:52 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
242     |2026-03-14 02:07:51 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
241     |2026-03-14 02:07:46 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
240     |2026-03-14 02:05:28 |Major       |0x000000DD  |Asserted    |CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
239     |2026-03-14 02:05:00 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
238     |2026-03-14 02:04:08 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
237     |2026-03-14 02:01:04 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
236     |2026-03-14 02:01:01 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
235     |2026-03-14 01:58:36 |Major       |0x000000DD  |Asserted    |CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold (1.1 V).
234     |2026-03-14 01:57:31 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
233     |2026-03-14 01:57:25 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
232     |2026-03-14 01:55:05 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
231     |2026-03-14 01:54:21 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
230     |2026-03-14 01:47:37 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
229     |2026-03-14 01:47:30 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
228     |2026-03-14 01:44:45 |Major       |0x000000DE  |Deasserted  |CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
227     |2026-03-14 01:44:43 |Major       |0x000000DE  |Deasserted  |CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
226     |2026-03-14 01:44:16 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
225     |2026-03-14 01:43:41 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
224     |2026-03-14 01:40:49 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
223     |2026-03-14 01:40:03 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
222     |2026-03-14 01:37:49 |Major       |0x000000DD  |Asserted    |CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
221     |2026-03-14 01:37:49 |Major       |0x000000DD  |Asserted    |CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
220     |2026-03-14 01:36:43 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
219     |2026-03-14 01:36:40 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
218     |2026-03-14 01:33:13 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
217     |2026-03-14 01:33:05 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
216     |2026-03-14 01:30:31 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
215     |2026-03-14 01:29:47 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
214     |2026-03-14 01:27:02 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
213     |2026-03-14 01:26:19 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
212     |2026-03-14 01:22:58 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
211     |2026-03-14 01:22:54 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
210     |2026-03-14 01:09:29 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
209     |2026-03-14 01:09:20 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
208     |2026-03-14 01:05:33 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
207     |2026-03-14 01:05:31 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
206     |2026-03-14 00:57:15 |Critical    |0x0300000D  |Asserted    |The AC/DC input of PSU 4 is lost or out-of-range (SN:G1302262NA241102023, BN:302004098).
205     |2026-03-14 00:57:15 |Critical    |0x0300000D  |Asserted    |The AC/DC input of PSU 3 is lost or out-of-range (SN:G1302262NA241202431, BN:302004098).
204     |2026-03-14 00:56:28 |Major       |0x000000DE  |Deasserted  |CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
203     |2026-03-14 00:56:27 |Major       |0x000000DE  |Deasserted  |CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
202     |2026-03-14 00:56:18 |Critical    |0x0300000E  |Deasserted  |The AC/DC input of PSU 3 is lost or out-of-range (SN:G1302262NA241202431, BN:302004098).
201     |2026-03-14 00:56:17 |Critical    |0x0300000E  |Deasserted  |The AC/DC input of PSU 4 is lost or out-of-range (SN:G1302262NA241102023, BN:302004098).
200     |2026-03-14 00:55:21 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
199     |2026-03-14 00:55:18 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
198     |2026-03-14 00:52:20 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
197     |2026-03-14 00:52:15 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
196     |2026-03-14 00:46:24 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
195     |2026-03-14 00:44:10 |Major       |0x000000DD  |Asserted    |CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
194     |2026-03-14 00:44:09 |Major       |0x000000DD  |Asserted    |CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
193     |2026-03-14 00:43:06 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
192     |2026-03-14 00:43:04 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
191     |2026-03-14 00:38:46 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
190     |2026-03-14 00:38:14 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
189     |2026-03-14 00:35:46 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
188     |2026-03-14 00:35:09 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
187     |2026-03-14 00:31:49 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
186     |2026-03-14 00:31:44 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
185     |2026-03-14 00:22:41 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
184     |2026-03-14 00:22:27 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
183     |2026-03-14 00:19:36 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
182     |2026-03-14 00:19:34 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
181     |2026-03-14 00:17:06 |Major       |0x000000DE  |Deasserted  |CPU 1(CpuBoard1 CPU1) Uncore voltage (1.01 V) exceeds the overvoltage threshold ( V).
180     |2026-03-14 00:17:06 |Major       |0x000000DE  |Deasserted  |CPU 2(CpuBoard1 CPU2) Uncore voltage (1.01 V) exceeds the overvoltage threshold ( V).
179     |2026-03-14 00:16:39 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
178     |2026-03-14 00:15:55 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
177     |2026-03-14 00:13:37 |Major       |0x000000DD  |Asserted    |CPU 1(CpuBoard1 CPU1) Uncore voltage (1.01 V) exceeds the overvoltage threshold ( V).
176     |2026-03-14 00:13:36 |Major       |0x000000DD  |Asserted    |CPU 2(CpuBoard1 CPU2) Uncore voltage (1.01 V) exceeds the overvoltage threshold ( V).
175     |2026-03-14 00:13:35 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
174     |2026-03-14 00:13:33 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
173     |2026-03-14 00:03:50 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
172     |2026-03-14 00:03:48 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
171     |2026-03-14 00:00:22 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
170     |2026-03-13 23:59:47 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
169     |2026-03-13 23:53:47 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
168     |2026-03-13 23:50:22 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
167     |2026-03-13 23:49:58 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
166     |2026-03-13 23:46:53 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
165     |2026-03-13 23:46:29 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
164     |2026-03-13 23:42:27 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
163     |2026-03-13 23:42:23 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
162     |2026-03-13 23:39:35 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
161     |2026-03-13 23:38:58 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
160     |2026-03-13 23:35:34 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
159     |2026-03-13 23:35:30 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
158     |2026-03-13 23:33:10 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
157     |2026-03-13 23:32:46 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
156     |2026-03-13 23:29:42 |Major       |0x000000DE  |Deasserted  |CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
155     |2026-03-13 23:29:42 |Major       |0x000000DE  |Deasserted  |CPU 1(CpuBoard1 CPU1) Uncore voltage (1.01 V) exceeds the overvoltage threshold ( V).
154     |2026-03-13 23:29:40 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
153     |2026-03-13 23:29:38 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
152     |2026-03-13 23:24:22 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
151     |2026-03-13 23:23:48 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
150     |2026-03-13 23:21:46 |Major       |0x000000DD  |Asserted    |CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
149     |2026-03-13 23:21:44 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
148     |2026-03-13 23:21:42 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
147     |2026-03-13 23:18:12 |Major       |0x000000DE  |Deasserted  |CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold (1.1 V).
146     |2026-03-13 23:14:46 |Major       |0x000000DD  |Asserted    |CPU 1(CpuBoard1 CPU1) Uncore voltage (1.01 V) exceeds the overvoltage threshold ( V).
145     |2026-03-13 23:14:46 |Major       |0x000000DD  |Asserted    |CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold (1.1 V).
144     |2026-03-13 23:14:46 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
143     |2026-03-13 23:14:45 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
142     |2026-03-13 23:08:10 |Major       |0x000000DE  |Deasserted  |CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
141     |2026-03-13 23:08:09 |Major       |0x000000DE  |Deasserted  |CPU 1(CpuBoard1 CPU1) Uncore voltage (1.01 V) exceeds the overvoltage threshold ( V).
140     |2026-03-13 23:08:09 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
139     |2026-03-13 23:07:45 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
138     |2026-03-13 23:04:39 |Major       |0x000000DD  |Asserted    |CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
137     |2026-03-13 22:54:49 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
136     |2026-03-13 22:51:25 |Major       |0x000000DD  |Asserted    |CPU 1(CpuBoard1 CPU1) Uncore voltage (1.01 V) exceeds the overvoltage threshold ( V).
135     |2026-03-13 22:48:00 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
134     |2026-03-13 22:44:34 |Major       |0x000000DE  |Deasserted  |CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
133     |2026-03-13 22:44:33 |Major       |0x000000DE  |Deasserted  |CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
132     |2026-03-13 22:44:33 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
131     |2026-03-13 22:44:08 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
130     |2026-03-13 22:40:04 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
129     |2026-03-13 22:40:02 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
128     |2026-03-13 22:37:41 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
127     |2026-03-13 22:37:39 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
126     |2026-03-13 22:33:01 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
125     |2026-03-13 22:32:57 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
124     |2026-03-13 22:21:18 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
123     |2026-03-13 22:18:19 |Major       |0x000000DD  |Asserted    |CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
122     |2026-03-13 22:18:18 |Major       |0x000000DD  |Asserted    |CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
121     |2026-03-13 22:18:14 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
120     |2026-03-13 22:18:12 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
119     |2026-03-13 22:13:33 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
118     |2026-03-13 22:13:31 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
117     |2026-03-13 22:05:26 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
116     |2026-03-13 22:04:49 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
115     |2026-03-13 22:00:26 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
114     |2026-03-13 22:00:26 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
113     |2026-03-13 21:58:15 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
112     |2026-03-13 21:57:12 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
111     |2026-03-13 21:53:43 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
110     |2026-03-13 21:53:39 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
109     |2026-03-13 21:50:41 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
108     |2026-03-13 21:50:39 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
107     |2026-03-13 21:46:18 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
106     |2026-03-13 21:46:14 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
105     |2026-03-13 21:42:51 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
104     |2026-03-13 21:42:43 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
103     |2026-03-13 21:40:29 |Major       |0x000000DE  |Deasserted  |CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
102     |2026-03-13 21:40:28 |Major       |0x000000DE  |Deasserted  |CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
101     |2026-03-13 21:37:02 |Major       |0x000000DD  |Asserted    |CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
100     |2026-03-13 21:37:01 |Major       |0x000000DD  |Asserted    |CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
99      |2026-03-13 21:37:01 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
98      |2026-03-13 21:37:00 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
97      |2026-03-13 21:33:37 |Major       |0x000000DD  |Asserted    |CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
96      |2026-03-13 21:33:36 |Major       |0x000000DD  |Asserted    |CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
95      |2026-03-13 21:32:24 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
94      |2026-03-13 21:32:17 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
93      |2026-03-13 21:24:19 |Major       |0x000000DE  |Deasserted  |CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
92      |2026-03-13 21:23:07 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
91      |2026-03-13 21:23:04 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
90      |2026-03-13 21:20:51 |Major       |0x000000DE  |Deasserted  |CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
89      |2026-03-13 21:20:50 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
88      |2026-03-13 21:20:26 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
87      |2026-03-13 21:16:59 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
86      |2026-03-13 21:16:26 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
85      |2026-03-13 21:12:46 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
84      |2026-03-13 21:12:44 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
83      |2026-03-13 21:09:13 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
82      |2026-03-13 21:09:10 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
81      |2026-03-13 21:05:41 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
80      |2026-03-13 21:05:33 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
79      |2026-03-13 21:03:19 |Major       |0x000000DD  |Asserted    |CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
78      |2026-03-13 21:03:19 |Major       |0x000000DD  |Asserted    |CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
77      |2026-03-13 21:02:11 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
76      |2026-03-13 21:02:04 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
75      |2026-03-13 20:59:53 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
74      |2026-03-13 20:59:27 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
73      |2026-03-13 20:59:27 |Major       |0x03000008  |Deasserted  |Lost power supply redundancy.
72      |2026-03-13 20:59:27 |Major       |0x03000007  |Asserted    |Lost power supply redundancy.
71      |2026-03-13 20:53:05 |Major       |0x000000DE  |Deasserted  |CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
70      |2026-03-13 20:53:04 |Major       |0x000000DE  |Deasserted  |CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
69      |2026-03-13 20:53:01 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
68      |2026-03-13 20:53:00 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
67      |2026-03-13 20:49:38 |Major       |0x000000DD  |Asserted    |CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
66      |2026-03-13 20:49:38 |Major       |0x000000DD  |Asserted    |CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
65      |2026-03-13 20:48:27 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
64      |2026-03-13 20:48:19 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
63      |2026-03-13 20:45:37 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
62      |2026-03-13 20:45:30 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
61      |2026-03-13 20:43:14 |Major       |0x000000DE  |Deasserted  |CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
60      |2026-03-13 20:43:13 |Major       |0x000000DE  |Deasserted  |CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
59      |2026-03-13 20:43:12 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
58      |2026-03-13 20:42:48 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
57      |2026-03-13 20:39:43 |Major       |0x000000DD  |Asserted    |CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
56      |2026-03-13 20:39:42 |Major       |0x000000DD  |Asserted    |CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
55      |2026-03-13 20:39:40 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
54      |2026-03-13 20:39:17 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
53      |2026-03-13 20:35:41 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
52      |2026-03-13 20:35:39 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
51      |2026-03-13 20:32:46 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
50      |2026-03-13 20:32:03 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
49      |2026-03-13 20:28:50 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
48      |2026-03-13 20:28:47 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
47      |2026-03-13 20:26:28 |Major       |0x000000DD  |Asserted    |CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
46      |2026-03-13 20:26:27 |Major       |0x000000DD  |Asserted    |CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
45      |2026-03-13 20:26:20 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
44      |2026-03-13 20:26:18 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
43      |2026-03-13 20:21:06 |Major       |0x000000DE  |Deasserted  |CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
42      |2026-03-13 20:20:38 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
41      |2026-03-13 20:19:57 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
40      |2026-03-13 20:17:35 |Major       |0x000000DE  |Deasserted  |CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
39      |2026-03-13 20:17:34 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
38      |2026-03-13 20:17:32 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
37      |2026-03-13 20:13:46 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
36      |2026-03-13 20:13:06 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
35      |2026-03-13 20:07:47 |Major       |0x000000DD  |Asserted    |CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
34      |2026-03-13 20:07:46 |Major       |0x000000DD  |Asserted    |CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
33      |2026-03-13 19:54:55 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
32      |2026-03-13 19:49:28 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
31      |2026-03-13 19:49:25 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
30      |2026-03-13 19:46:45 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
29      |2026-03-13 19:46:38 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
28      |2026-03-13 19:43:45 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
27      |2026-03-13 19:43:42 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
26      |2026-03-13 19:38:32 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
25      |2026-03-13 19:37:43 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
24      |2026-03-13 19:34:27 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
23      |2026-03-13 19:34:20 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
22      |2026-03-13 19:32:01 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
21      |2026-03-13 19:31:36 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
20      |2026-03-13 19:27:52 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
19      |2026-03-13 19:27:50 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
18      |2026-03-13 19:25:28 |Major       |0x000000DE  |Deasserted  |CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
17      |2026-03-13 19:25:27 |Major       |0x000000DE  |Deasserted  |CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
16      |2026-03-13 19:19:01 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
15      |2026-03-13 19:15:55 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
14      |2026-03-13 19:15:53 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
13      |2026-03-13 19:12:23 |Major       |0x000000DD  |Asserted    |CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
12      |2026-03-13 19:11:56 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
11      |2026-03-13 19:11:18 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
10      |2026-03-13 19:08:54 |Major       |0x000000DD  |Asserted    |CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
9       |2026-03-13 19:08:51 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
8       |2026-03-13 19:08:50 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
7       |2026-03-13 19:05:20 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
6       |2026-03-13 19:05:18 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
5       |2026-03-13 18:58:31 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
4       |2026-03-13 18:58:31 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
3       |2026-03-13 18:54:56 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x0.
2       |2026-03-13 18:54:54 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
1       |2026-03-13 18:51:05 |Normal      |0x1A00000F  |Asserted    |openUBMC event records are cleared.
