2026-03-09T15:27:27.544684+08:03 R624-K2-2512-BMC om:     1,2026-03-09 15:27:07,Normal,0x1A00000D,Asserted,openUBMC is restarted after AC power supply is restored.
2026-03-09T15:27:27.653995+08:03 R624-K2-2512-BMC om:     2,2026-03-09 15:27:12,Normal,0x2C000017,Asserted,The host is restarted after being powered on (Power strategy is 'Turn On').
2026-03-09T15:27:46.328507+08:03 R624-K2-2512-BMC om:     3,2026-03-09 15:27:46,Normal,0x2C000009,Asserted,ACPI is in the working state.
2026-03-09T15:27:46.615308+08:03 R624-K2-2512-BMC om:     4,2026-03-09 15:27:46,Minor,0x1A000049,Asserted,Insecure protocol SNMP v1 is enabled in the system.
2026-03-09T15:28:09.620433+08:03 R624-K2-2512-BMC om:     5,2026-03-09 15:28:09,Critical,0x0300000D,Asserted,The AC/DC input of PSU 4 is lost or out-of-range (SN:G1302262NA241102023, BN:302004098).
2026-03-09T15:28:09.850468+08:03 R624-K2-2512-BMC om:     6,2026-03-09 15:28:09,Minor,0x1A000049,Asserted,Insecure protocol SNMP v2 is enabled in the system.
2026-03-09T15:28:10.236836+08:03 R624-K2-2512-BMC om:     7,2026-03-09 15:28:09,Critical,0x0300000D,Asserted,The AC/DC input of PSU 2 is lost or out-of-range (SN:G1302262NA241202437, BN:302004098).
2026-03-09T15:28:11.445790+08:03 R624-K2-2512-BMC om:     8,2026-03-09 15:28:10,Critical,0x0300000D,Asserted,The AC/DC input of PSU 3 is lost or out-of-range (SN:G1302262NA241202431, BN:302004098).
2026-03-09T15:29:55.518883+08:03 R624-K2-2512-BMC om:     9,2026-03-09 15:29:55,Major,0x0300001F,Asserted,Server power failure occurred at 2026-03-09 15:26:55 UTC, The power has been already restored.
2026-03-09T15:59:21.394004+08:03 R624-K2-2512-BMC om:    10,2026-03-09 15:59:21,Normal,0x1A000057,Asserted,The user 3 has been locked.
2026-03-09T16:00:21.556189+08:03 R624-K2-2512-BMC om:    11,2026-03-09 16:00:21,Normal,0x1A000058,Deasserted,The user 3 has been locked.
2026-03-09T17:29:06.957814+08:03 R624-K2-2512-BMC om:    12,2026-03-09 17:29:06,Critical,0x0300000E,Deasserted,The AC/DC input of PSU 2 is lost or out-of-range (SN:G1302262NA241202437, BN:302004098).
2026-03-09T17:56:13.346474+08:03 R624-K2-2512-BMC om:    13,2026-03-09 17:56:13,Normal,0x1A00000F,Asserted,openUBMC event records are cleared.
2026-03-09T17:56:30.359370+08:03 R624-K2-2512-BMC om:    14,2026-03-09 17:56:30,Minor,0x1A00004A,Deasserted,Insecure protocol SNMP v1 is enabled in the system.
2026-03-09T17:56:30.562159+08:03 R624-K2-2512-BMC om:    15,2026-03-09 17:56:30,Minor,0x1A00004A,Deasserted,Insecure protocol SNMP v2 is enabled in the system.
2026-03-09T17:56:45.264211+08:03 R624-K2-2512-BMC om:    16,2026-03-09 17:56:45,Normal,0x1A00000F,Asserted,openUBMC event records are cleared.
2026-03-10T09:42:17.325831+08:03 R624-K2-2512-BMC om:    17,2026-03-10 09:42:16,Normal,0x2C00000B,Asserted,ACPI is in the soft-off state.
2026-03-10T09:42:56.446172+08:03 R624-K2-2512-BMC om:    18,2026-03-10 09:42:56,Normal,0x2C000011,Asserted,The host was restarted by command.
2026-03-10T09:42:56.826961+08:03 R624-K2-2512-BMC om:    19,2026-03-10 09:42:56,Normal,0x2C000009,Asserted,ACPI is in the working state.
2026-03-10T09:51:14.782679+08:03 R624-K2-2512-BMC om:    20,2026-03-10 09:51:14,Normal,0x2C00000B,Asserted,ACPI is in the soft-off state.
2026-03-10T09:52:01.367943+08:03 R624-K2-2512-BMC om:    21,2026-03-10 09:52:01,Normal,0x2C000011,Asserted,The host was restarted by command.
2026-03-10T09:52:01.909583+08:03 R624-K2-2512-BMC om:    22,2026-03-10 09:52:01,Normal,0x2C000009,Asserted,ACPI is in the working state.
2026-03-10T10:03:52.282810+08:03 R624-K2-2512-BMC om:    23,2026-03-10 10:03:52,Normal,0x2C000011,Asserted,The host was restarted by command.
2026-03-10T10:07:17.146528+08:03 R624-K2-2512-BMC om:    24,2026-03-10 10:07:16,Normal,0x2C00000B,Asserted,ACPI is in the soft-off state.
2026-03-10T10:07:39.354001+08:03 R624-K2-2512-BMC om:    25,2026-03-10 10:07:38,Normal,0x2C000011,Asserted,The host was restarted by command.
2026-03-10T10:07:39.823151+08:03 R624-K2-2512-BMC om:    26,2026-03-10 10:07:39,Normal,0x2C000009,Asserted,ACPI is in the working state.
2026-03-10T10:12:09.462477+08:03 R624-K2-2512-BMC om:    27,2026-03-10 10:12:09,Normal,0x2C00000B,Asserted,ACPI is in the soft-off state.
2026-03-10T10:12:27.791924+08:03 R624-K2-2512-BMC om:    28,2026-03-10 10:12:27,Normal,0x2C000011,Asserted,The host was restarted by command.
2026-03-10T10:12:28.180602+08:03 R624-K2-2512-BMC om:    29,2026-03-10 10:12:27,Normal,0x2C000009,Asserted,ACPI is in the working state.
2026-03-10T12:38:02.227917+08:03 R624-K2-2512-BMC om:    30,2026-03-10 12:38:02,Minor,0x1A000049,Asserted,Insecure protocol VNC is enabled in the system.
2026-03-10T14:33:25.044058+08:03 R624-K2-2512-BMC om:    31,2026-03-10 14:33:24,Normal,0x2C00000F,Asserted,The host was restarted due to unrecognized reason.
2026-03-10T14:38:15.525279+08:03 R624-K2-2512-BMC om:    32,2026-03-10 14:38:15,Normal,0x2C000053,Asserted,The hard disk partition(/dev/sr0) usage (100%) exceeds the threshold (100%).
2026-03-10T15:54:09.697091+08:03 R624-K2-2512-BMC om:     1,2026-03-10 15:51:30,Normal,0x2C000054,Deasserted,The hard disk partition(/dev/sr0) usage (100%) exceeds the threshold (100%).
2026-03-10T15:54:09.798997+08:03 R624-K2-2512-BMC om:     2,2026-03-10 15:52:06,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-10T15:54:09.839859+08:03 R624-K2-2512-BMC om:     3,2026-03-10 15:52:06,Normal,0x2C000053,Asserted,The hard disk partition(/dev/sr0) usage (100%) exceeds the threshold (100%).
2026-03-10T15:54:09.895324+08:03 R624-K2-2512-BMC om:     4,2026-03-10 15:52:06,Normal,0x5D00000D,Asserted,Expansion board 1 is replaced from serial number(elable_test) to serial number(//) (SN://).
2026-03-10T15:54:09.941447+08:03 R624-K2-2512-BMC om:     5,2026-03-10 15:52:33,Normal,0x05000015,Asserted,The disk backplane 1 is replaced from SN(D92490183748) to SN(//) (SN://).
2026-03-10T16:29:12.263561+08:03 R624-K2-2512-BMC om:     1,2026-03-10 16:26:20,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-10T16:29:12.308066+08:03 R624-K2-2512-BMC om:     2,2026-03-10 16:26:45,Normal,0x2C000054,Deasserted,The hard disk partition(/dev/sr0) usage (100%) exceeds the threshold (100%).
2026-03-10T16:29:12.358134+08:03 R624-K2-2512-BMC om:     3,2026-03-10 16:27:05,Normal,0x2C000053,Asserted,The hard disk partition(/dev/sr0) usage (100%) exceeds the threshold (100%).
2026-03-10T16:38:09.224293+08:03 R624-K2-2512-BMC om:     4,2026-03-10 16:38:08,Normal,0x2C000054,Deasserted,The hard disk partition(/dev/sr0) usage (100%) exceeds the threshold (100%).
2026-03-10T17:30:53.224061+08:03 R624-K2-2512-BMC om:     5,2026-03-10 17:30:52,Normal,0x2C00000F,Asserted,The host was restarted due to unrecognized reason.
2026-03-10T17:32:41.482760+08:03 R624-K2-2512-BMC om:     6,2026-03-10 17:32:41,Normal,0x2C000011,Asserted,The host was restarted by command.
2026-03-10T18:18:48.511727+08:03 R624-K2-2512-BMC om:     7,2026-03-10 18:18:47,Normal,0x2C00000B,Asserted,ACPI is in the soft-off state.
2026-03-10T18:19:10.313665+08:03 R624-K2-2512-BMC om:     8,2026-03-10 18:19:10,Normal,0x2C000011,Asserted,The host was restarted by command.
2026-03-10T18:19:10.832329+08:03 R624-K2-2512-BMC om:     9,2026-03-10 18:19:10,Normal,0x2C000009,Asserted,ACPI is in the working state.
2026-03-10T18:21:22.181277+08:03 R624-K2-2512-BMC om:    10,2026-03-10 18:21:21,Normal,0x2C000011,Asserted,The host was restarted by command.
2026-03-10T19:30:44.856282+08:03 R624-K2-2512-BMC om:    11,2026-03-10 19:30:44,Normal,0x2C00000B,Asserted,ACPI is in the soft-off state.
2026-03-10T19:31:06.691366+08:03 R624-K2-2512-BMC om:    12,2026-03-10 19:31:06,Normal,0x2C000011,Asserted,The host was restarted by command.
2026-03-10T19:31:07.194626+08:03 R624-K2-2512-BMC om:    13,2026-03-10 19:31:06,Normal,0x2C000009,Asserted,ACPI is in the working state.
2026-03-10T19:33:21.472124+08:03 R624-K2-2512-BMC om:    14,2026-03-10 19:33:21,Normal,0x2C000011,Asserted,The host was restarted by command.
2026-03-10T19:35:30.463079+08:03 R624-K2-2512-BMC om:    15,2026-03-10 19:35:30,Normal,0x2C000011,Asserted,The host was restarted by command.
2026-03-11T10:57:23.335233+08:03 R624-K2-2512-BMC om:    16,2026-03-11 10:57:23,Normal,0x1A00000F,Asserted,openUBMC event records are cleared.
2026-03-11T11:18:15.657724+08:03 R624-K2-2512-BMC om:    17,2026-03-11 11:18:14,Normal,0x2C00000B,Asserted,ACPI is in the soft-off state.
2026-03-11T15:59:17.279488+08:03 R624-K2-2512-BMC om:    18,2026-03-11 15:59:17,Normal,0x1A000057,Asserted,The user 2 has been locked.
2026-03-11T16:00:22.540150+08:03 R624-K2-2512-BMC om:    19,2026-03-11 16:00:22,Normal,0x1A000058,Deasserted,The user 2 has been locked.
2026-03-11T16:01:05.940377+08:03 R624-K2-2512-BMC om:    20,2026-03-11 16:01:05,Normal,0x1A000057,Asserted,The user 2 has been locked.
2026-03-11T16:02:11.223811+08:03 R624-K2-2512-BMC om:    21,2026-03-11 16:02:11,Normal,0x1A000058,Deasserted,The user 2 has been locked.
2026-03-11T16:52:25.419315+08:03 R624-K2-2512-BMC om:    22,2026-03-11 16:52:24,Normal,0x2C000011,Asserted,The host was restarted by command.
2026-03-11T16:52:25.882879+08:03 R624-K2-2512-BMC om:    23,2026-03-11 16:52:25,Normal,0x2C000009,Asserted,ACPI is in the working state.
2026-03-12T12:44:13.785291+06:00 R624-K2-2512-BMC-test om:    24,2026-03-12 12:44:12,Normal,0x2C00000B,Asserted,ACPI is in the soft-off state.
2026-03-12T12:44:45.446213+06:00 R624-K2-2512-BMC-test om:    25,2026-03-12 12:44:45,Normal,0x2C000011,Asserted,The host was restarted by command.
2026-03-12T12:44:45.968079+06:00 R624-K2-2512-BMC-test om:    26,2026-03-12 12:44:45,Normal,0x2C000009,Asserted,ACPI is in the working state.
2026-03-12T12:46:31.391564+06:00 R624-K2-2512-BMC-test om:    27,2026-03-12 12:46:30,Normal,0x2C00000B,Asserted,ACPI is in the soft-off state.
2026-03-12T12:46:49.556065+06:00 R624-K2-2512-BMC-test om:    28,2026-03-12 12:46:49,Normal,0x2C000011,Asserted,The host was restarted by command.
2026-03-12T12:46:50.236371+06:00 R624-K2-2512-BMC-test om:    29,2026-03-12 12:46:49,Normal,0x2C000009,Asserted,ACPI is in the working state.
2026-03-12T12:48:05.762180+06:00 R624-K2-2512-BMC-test om:    30,2026-03-12 12:48:05,Normal,0x2C00000B,Asserted,ACPI is in the soft-off state.
2026-03-12T12:48:24.820512+06:00 R624-K2-2512-BMC-test om:    31,2026-03-12 12:48:24,Normal,0x2C000011,Asserted,The host was restarted by command.
2026-03-12T12:48:25.160163+06:00 R624-K2-2512-BMC-test om:    32,2026-03-12 12:48:24,Normal,0x2C000009,Asserted,ACPI is in the working state.
2026-03-12T12:53:27.024288+06:00 R624-K2-2512-BMC-test om:    33,2026-03-12 12:53:26,Normal,0x2C00000B,Asserted,ACPI is in the soft-off state.
2026-03-12T12:53:48.737502+06:00 R624-K2-2512-BMC-test om:    34,2026-03-12 12:53:48,Normal,0x2C000009,Asserted,ACPI is in the working state.
2026-03-12T12:53:48.987904+06:00 R624-K2-2512-BMC-test om:    35,2026-03-12 12:53:48,Normal,0x2C000011,Asserted,The host was restarted by command.
2026-03-12T12:59:30.849715+06:00 R624-K2-2512-BMC-test om:    36,2026-03-12 12:59:30,Normal,0x2C00000B,Asserted,ACPI is in the soft-off state.
2026-03-12T12:59:52.686625+06:00 R624-K2-2512-BMC-test om:    37,2026-03-12 12:59:52,Normal,0x2C000011,Asserted,The host was restarted by command.
2026-03-12T12:59:53.158928+06:00 R624-K2-2512-BMC-test om:    38,2026-03-12 12:59:52,Normal,0x2C000009,Asserted,ACPI is in the working state.
2026-03-12T13:03:11.511241+06:00 R624-K2-2512-BMC-test om:    39,2026-03-12 13:03:10,Normal,0x2C00000B,Asserted,ACPI is in the soft-off state.
2026-03-12T13:03:30.219285+06:00 R624-K2-2512-BMC-test om:    40,2026-03-12 13:03:29,Normal,0x2C000011,Asserted,The host was restarted by command.
2026-03-12T13:03:30.526143+06:00 R624-K2-2512-BMC-test om:    41,2026-03-12 13:03:30,Normal,0x2C000009,Asserted,ACPI is in the working state.
2026-03-12T13:08:29.363583+06:00 R624-K2-2512-BMC-test om:    42,2026-03-12 13:08:28,Normal,0x2C00000B,Asserted,ACPI is in the soft-off state.
2026-03-12T13:08:48.045224+06:00 R624-K2-2512-BMC-test om:    43,2026-03-12 13:08:47,Normal,0x2C000011,Asserted,The host was restarted by command.
2026-03-12T13:08:48.494132+06:00 R624-K2-2512-BMC-test om:    44,2026-03-12 13:08:48,Normal,0x2C000009,Asserted,ACPI is in the working state.
2026-03-12T16:13:25.578146+06:00 R624-K2-2512-BMC-test om:    45,2026-03-12 16:13:25,Normal,0x1A000029,Asserted,openUBMC time is stepped by more than 179 minutes.
2026-03-12T16:13:46.580280+06:00 R624-K2-2512-BMC-test om:    46,2026-03-12 16:13:45,Normal,0x2C00000B,Asserted,ACPI is in the soft-off state.
2026-03-12T16:14:18.002079+06:00 R624-K2-2512-BMC-test om:    47,2026-03-12 16:14:17,Normal,0x2C000011,Asserted,The host was restarted by command.
2026-03-12T16:14:18.331492+06:00 R624-K2-2512-BMC-test om:    48,2026-03-12 16:14:18,Normal,0x2C000009,Asserted,ACPI is in the working state.
2026-03-12T16:30:18.617801+06:00 R624-K2-2512-BMC-test om:     1,2026-03-12 16:23:47,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-12T16:30:18.674686+06:00 R624-K2-2512-BMC-test om:     2,2026-03-12 16:27:41,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x1.
2026-03-12T16:30:18.724561+06:00 R624-K2-2512-BMC-test om:     3,2026-03-12 16:27:47,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-12T17:17:59.289564+06:00 R624-K2-2512-BMC-test om:     4,2026-03-12 17:17:59,Normal,0x31000003,Asserted,The UID button on the panel is pressed.
2026-03-12T17:20:13.168508+06:00 R624-K2-2512-BMC-test om:     5,2026-03-12 17:20:12,Normal,0x31000003,Asserted,The UID button on the panel is pressed.
2026-03-12T17:20:26.082386+06:00 R624-K2-2512-BMC-test om:     6,2026-03-12 17:20:25,Normal,0x31000003,Asserted,The UID button on the panel is pressed.
2026-03-12T17:24:35.315881+06:00 R624-K2-2512-BMC-test om:     7,2026-03-12 17:24:34,Normal,0x2C00000B,Asserted,ACPI is in the soft-off state.
2026-03-12T17:25:11.806714+06:00 R624-K2-2512-BMC-test om:     8,2026-03-12 17:25:11,Normal,0x2C000011,Asserted,The host was restarted by command.
2026-03-12T17:25:12.462199+06:00 R624-K2-2512-BMC-test om:     9,2026-03-12 17:25:12,Normal,0x2C000009,Asserted,ACPI is in the working state.
2026-03-12T17:28:11.321602+06:00 R624-K2-2512-BMC-test om:    10,2026-03-12 17:28:09,Normal,0x2C00000B,Asserted,ACPI is in the soft-off state.
2026-03-12T17:29:36.823061+06:00 R624-K2-2512-BMC-test om:    11,2026-03-12 17:29:36,Normal,0x2C000011,Asserted,The host was restarted by command.
2026-03-12T17:29:37.128423+06:00 R624-K2-2512-BMC-test om:    12,2026-03-12 17:29:36,Normal,0x2C000009,Asserted,ACPI is in the working state.
2026-03-12T17:32:57.602189+06:00 R624-K2-2512-BMC-test om:    13,2026-03-12 17:32:57,Normal,0x2C000011,Asserted,The host was restarted by command.
2026-03-12T17:40:48.309509+06:00 R624-K2-2512-BMC-test om:    14,2026-03-12 17:40:47,Normal,0x2C00000B,Asserted,ACPI is in the soft-off state.
2026-03-12T17:41:11.396887+06:00 R624-K2-2512-BMC-test om:    15,2026-03-12 17:41:10,Normal,0x2C000009,Asserted,ACPI is in the working state.
2026-03-12T17:41:11.617749+06:00 R624-K2-2512-BMC-test om:    16,2026-03-12 17:41:11,Normal,0x2C000011,Asserted,The host was restarted by command.
2026-03-12T17:44:32.159421+06:00 R624-K2-2512-BMC-test om:    17,2026-03-12 17:44:31,Normal,0x2C00000B,Asserted,ACPI is in the soft-off state.
2026-03-12T17:44:51.055555+06:00 R624-K2-2512-BMC-test om:    18,2026-03-12 17:44:50,Normal,0x2C000011,Asserted,The host was restarted by command.
2026-03-12T17:44:51.224643+06:00 R624-K2-2512-BMC-test om:    19,2026-03-12 17:44:50,Normal,0x2C000009,Asserted,ACPI is in the working state.
2026-03-12T17:49:27.011077+06:00 R624-K2-2512-BMC-test om:    20,2026-03-12 17:49:26,Normal,0x2C00000B,Asserted,ACPI is in the soft-off state.
2026-03-12T17:49:53.115616+06:00 R624-K2-2512-BMC-test om:    21,2026-03-12 17:49:52,Normal,0x2C000011,Asserted,The host was restarted by command.
2026-03-12T17:49:54.091968+06:00 R624-K2-2512-BMC-test om:    22,2026-03-12 17:49:53,Normal,0x2C000009,Asserted,ACPI is in the working state.
2026-03-12T17:55:41.398325+06:00 R624-K2-2512-BMC-test om:    23,2026-03-12 17:55:40,Normal,0x2C00000B,Asserted,ACPI is in the soft-off state.
2026-03-12T17:56:00.609370+06:00 R624-K2-2512-BMC-test om:    24,2026-03-12 17:56:00,Normal,0x2C000011,Asserted,The host was restarted by command.
2026-03-12T17:56:01.082777+06:00 R624-K2-2512-BMC-test om:    25,2026-03-12 17:56:00,Normal,0x2C000009,Asserted,ACPI is in the working state.
2026-03-12T18:00:30.187448+06:00 R624-K2-2512-BMC-test om:    26,2026-03-12 18:00:29,Normal,0x2C00000B,Asserted,ACPI is in the soft-off state.
2026-03-12T18:00:52.699412+06:00 R624-K2-2512-BMC-test om:    27,2026-03-12 18:00:52,Normal,0x2C000011,Asserted,The host was restarted by command.
2026-03-12T18:00:53.457576+06:00 R624-K2-2512-BMC-test om:    28,2026-03-12 18:00:53,Normal,0x2C000009,Asserted,ACPI is in the working state.
2026-03-12T18:04:19.179457+06:00 R624-K2-2512-BMC-test om:    29,2026-03-12 18:04:18,Normal,0x2C000011,Asserted,The host was restarted by command.
2026-03-12T18:10:09.057141+06:00 R624-K2-2512-BMC-test om:    30,2026-03-12 18:10:08,Normal,0x31000001,Asserted,The power button on the panel is pressed.
2026-03-12T18:11:49.218689+06:00 R624-K2-2512-BMC-test om:    31,2026-03-12 18:11:48,Normal,0x31000001,Asserted,The power button on the panel is pressed.
2026-03-12T18:11:50.729422+06:00 R624-K2-2512-BMC-test om:    32,2026-03-12 18:11:50,Normal,0x31000001,Asserted,The power button on the panel is pressed.
2026-03-12T18:11:58.086012+06:00 R624-K2-2512-BMC-test om:    33,2026-03-12 18:11:57,Normal,0x2C00000B,Asserted,ACPI is in the soft-off state.
2026-03-12T18:12:06.662444+06:00 R624-K2-2512-BMC-test om:    34,2026-03-12 18:12:06,Normal,0x31000001,Asserted,The power button on the panel is pressed.
2026-03-12T18:12:08.760417+06:00 R624-K2-2512-BMC-test om:    35,2026-03-12 18:12:08,Normal,0x2C000013,Asserted,The host was restarted by power button.
2026-03-12T18:12:09.081387+06:00 R624-K2-2512-BMC-test om:    36,2026-03-12 18:12:08,Normal,0x2C000009,Asserted,ACPI is in the working state.
2026-03-12T18:30:12.626905+06:00 R624-K2-2512-BMC-test om:    37,2026-03-12 18:30:12,Normal,0x1A00000F,Asserted,openUBMC event records are cleared.
2026-03-12T20:35:06.677208+06:00 R624-K2-2512-BMC-test om:    38,2026-03-12 20:35:06,Normal,0x1A00001B,Asserted,openUBMC operation log has reached 90% space capacity.
2026-03-12T21:03:36.835618+06:00 R624-K2-2512-BMC-test om:    39,2026-03-12 21:03:36,Normal,0x1A00001C,Deasserted,openUBMC operation log has reached 90% space capacity.
2026-03-13T01:19:07.180004+06:00 R624-K2-2512-BMC-test om:    40,2026-03-13 01:19:06,Normal,0x1A00001B,Asserted,openUBMC operation log has reached 90% space capacity.
2026-03-13T01:52:37.375552+06:00 R624-K2-2512-BMC-test om:    41,2026-03-13 01:52:37,Normal,0x1A00001C,Deasserted,openUBMC operation log has reached 90% space capacity.
2026-03-13T06:09:07.756501+06:00 R624-K2-2512-BMC-test om:    42,2026-03-13 06:09:07,Normal,0x1A00001B,Asserted,openUBMC operation log has reached 90% space capacity.
2026-03-13T18:01:52.046596+06:00 R624-K2-2512-BMC-test om:    43,2026-03-13 18:01:51,Critical,0x0300000D,Asserted,The AC/DC input of PSU 1 is lost or out-of-range (SN:G1302262NA241202438, BN:302004098).
2026-03-13T18:02:10.507010+06:00 R624-K2-2512-BMC-test om:    44,2026-03-13 18:02:10,Critical,0x0300000E,Deasserted,The AC/DC input of PSU 1 is lost or out-of-range (SN:G1302262NA241202438, BN:302004098).
2026-03-13T18:51:05.961789+06:00 R624-K2-2512-BMC-test om:    45,2026-03-13 18:51:05,Normal,0x1A00000F,Asserted,openUBMC event records are cleared.
2026-03-13T20:22:34.783471+06:00 R624-K2-2512-BMC-test om:     1,2026-03-13 19:08:54,Major,0x000000DD,Asserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-13T20:22:34.842442+06:00 R624-K2-2512-BMC-test om:     2,2026-03-13 19:11:18,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-13T20:22:34.884951+06:00 R624-K2-2512-BMC-test om:     3,2026-03-13 19:11:56,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-13T20:22:34.929201+06:00 R624-K2-2512-BMC-test om:     4,2026-03-13 19:12:23,Major,0x000000DD,Asserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-13T20:22:34.985891+06:00 R624-K2-2512-BMC-test om:     5,2026-03-13 19:15:53,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-13T20:22:35.041155+06:00 R624-K2-2512-BMC-test om:     6,2026-03-13 19:15:55,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-13T20:22:35.100023+06:00 R624-K2-2512-BMC-test om:     7,2026-03-13 19:19:01,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-13T20:22:35.140902+06:00 R624-K2-2512-BMC-test om:     8,2026-03-13 19:25:27,Major,0x000000DE,Deasserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-13T20:22:35.193806+06:00 R624-K2-2512-BMC-test om:     9,2026-03-13 19:25:28,Major,0x000000DE,Deasserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-13T20:22:35.243132+06:00 R624-K2-2512-BMC-test om:    10,2026-03-13 19:27:50,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-13T20:22:35.300996+06:00 R624-K2-2512-BMC-test om:    11,2026-03-13 18:54:54,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-13T20:22:35.339758+06:00 R624-K2-2512-BMC-test om:    12,2026-03-13 19:27:52,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-13T20:22:35.385896+06:00 R624-K2-2512-BMC-test om:    13,2026-03-13 19:31:36,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-13T20:22:35.433977+06:00 R624-K2-2512-BMC-test om:    14,2026-03-13 19:32:01,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-13T20:22:35.484562+06:00 R624-K2-2512-BMC-test om:    15,2026-03-13 19:34:20,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-13T20:22:35.523763+06:00 R624-K2-2512-BMC-test om:    16,2026-03-13 19:34:27,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-13T20:22:35.580852+06:00 R624-K2-2512-BMC-test om:    17,2026-03-13 19:37:43,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-13T20:22:35.626471+06:00 R624-K2-2512-BMC-test om:    18,2026-03-13 19:38:32,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-13T20:22:35.686762+06:00 R624-K2-2512-BMC-test om:    19,2026-03-13 19:43:42,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-13T20:22:35.749199+06:00 R624-K2-2512-BMC-test om:    20,2026-03-13 19:43:45,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-13T20:22:35.814774+06:00 R624-K2-2512-BMC-test om:    21,2026-03-13 19:46:38,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-13T20:22:35.867616+06:00 R624-K2-2512-BMC-test om:    22,2026-03-13 18:54:56,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-13T20:22:35.904843+06:00 R624-K2-2512-BMC-test om:    23,2026-03-13 19:46:45,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-13T20:22:35.945814+06:00 R624-K2-2512-BMC-test om:    24,2026-03-13 19:49:25,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-13T20:22:36.004334+06:00 R624-K2-2512-BMC-test om:    25,2026-03-13 19:49:28,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-13T20:22:36.044965+06:00 R624-K2-2512-BMC-test om:    26,2026-03-13 19:54:55,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-13T20:22:36.101869+06:00 R624-K2-2512-BMC-test om:    27,2026-03-13 20:07:46,Major,0x000000DD,Asserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-13T20:22:36.143734+06:00 R624-K2-2512-BMC-test om:    28,2026-03-13 20:07:47,Major,0x000000DD,Asserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-13T20:22:36.194970+06:00 R624-K2-2512-BMC-test om:    29,2026-03-13 20:13:06,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-13T20:22:36.239406+06:00 R624-K2-2512-BMC-test om:    30,2026-03-13 20:13:46,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-13T20:22:36.300181+06:00 R624-K2-2512-BMC-test om:    31,2026-03-13 20:17:32,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-13T20:22:36.357296+06:00 R624-K2-2512-BMC-test om:    32,2026-03-13 20:17:34,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-13T20:22:36.411946+06:00 R624-K2-2512-BMC-test om:    33,2026-03-13 18:58:31,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-13T20:22:36.451702+06:00 R624-K2-2512-BMC-test om:    34,2026-03-13 20:17:35,Major,0x000000DE,Deasserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-13T20:22:36.501043+06:00 R624-K2-2512-BMC-test om:    35,2026-03-13 20:19:57,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-13T20:22:36.585405+06:00 R624-K2-2512-BMC-test om:    36,2026-03-13 20:20:38,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-13T20:22:36.626595+06:00 R624-K2-2512-BMC-test om:    37,2026-03-13 20:21:06,Major,0x000000DE,Deasserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-13T20:22:36.683538+06:00 R624-K2-2512-BMC-test om:    38,2026-03-13 18:58:31,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-13T20:22:36.736903+06:00 R624-K2-2512-BMC-test om:    39,2026-03-13 19:05:18,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-13T20:22:36.791940+06:00 R624-K2-2512-BMC-test om:    40,2026-03-13 19:05:20,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-13T20:22:36.834733+06:00 R624-K2-2512-BMC-test om:    41,2026-03-13 19:08:50,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-13T20:22:36.878886+06:00 R624-K2-2512-BMC-test om:    42,2026-03-13 19:08:51,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:43.546054+06:00 localhost om:     1,2026-03-13 19:08:54,Major,0x000000DD,Asserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:05:43.599983+06:00 localhost om:     2,2026-03-13 21:37:01,Major,0x000000DD,Asserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:05:43.637383+06:00 localhost om:     3,2026-03-13 21:37:02,Major,0x000000DD,Asserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:05:43.672629+06:00 localhost om:     4,2026-03-13 21:40:28,Major,0x000000DE,Deasserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:05:43.714203+06:00 localhost om:     5,2026-03-13 21:40:29,Major,0x000000DE,Deasserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:05:43.757321+06:00 localhost om:     6,2026-03-13 21:42:43,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:43.792438+06:00 localhost om:     7,2026-03-13 21:42:51,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:43.836990+06:00 localhost om:     8,2026-03-13 21:46:14,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:43.875388+06:00 localhost om:     9,2026-03-13 21:46:18,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:43.917702+06:00 localhost om:    10,2026-03-13 21:50:39,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:43.975494+06:00 localhost om:    11,2026-03-13 21:50:41,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:44.016402+06:00 localhost om:    12,2026-03-13 19:11:18,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:44.056871+06:00 localhost om:    13,2026-03-13 21:53:39,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:44.100501+06:00 localhost om:    14,2026-03-13 21:53:43,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:44.152600+06:00 localhost om:    15,2026-03-13 21:57:12,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:44.194869+06:00 localhost om:    16,2026-03-13 21:58:15,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:44.237983+06:00 localhost om:    17,2026-03-13 22:00:26,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:44.288436+06:00 localhost om:    18,2026-03-13 22:00:26,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:44.365286+06:00 localhost om:    19,2026-03-13 22:04:49,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:44.406035+06:00 localhost om:    20,2026-03-13 22:05:26,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:44.443903+06:00 localhost om:    21,2026-03-13 22:13:31,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:44.477372+06:00 localhost om:    22,2026-03-13 22:13:33,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:44.518738+06:00 localhost om:    23,2026-03-13 19:11:56,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:44.563203+06:00 localhost om:    24,2026-03-13 22:18:12,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:44.610743+06:00 localhost om:    25,2026-03-13 22:18:14,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:44.657547+06:00 localhost om:    26,2026-03-13 22:18:18,Major,0x000000DD,Asserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:05:44.712326+06:00 localhost om:    27,2026-03-13 22:18:19,Major,0x000000DD,Asserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:05:44.749669+06:00 localhost om:    28,2026-03-13 22:21:18,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:44.786565+06:00 localhost om:    29,2026-03-13 22:32:57,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:44.830004+06:00 localhost om:    30,2026-03-13 22:33:01,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:44.870715+06:00 localhost om:    31,2026-03-13 22:37:39,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:44.931229+06:00 localhost om:    32,2026-03-13 22:37:41,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:44.978324+06:00 localhost om:    33,2026-03-13 22:40:02,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:45.034022+06:00 localhost om:    34,2026-03-13 19:12:23,Major,0x000000DD,Asserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:05:45.089979+06:00 localhost om:    35,2026-03-13 22:40:04,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:45.125861+06:00 localhost om:    36,2026-03-13 22:44:08,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:45.167061+06:00 localhost om:    37,2026-03-13 22:44:33,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:45.207067+06:00 localhost om:    38,2026-03-13 22:44:33,Major,0x000000DE,Deasserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:05:45.256151+06:00 localhost om:    39,2026-03-13 22:44:34,Major,0x000000DE,Deasserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:05:45.299123+06:00 localhost om:    40,2026-03-13 22:48:00,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:45.357518+06:00 localhost om:    41,2026-03-13 22:51:25,Major,0x000000DD,Asserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (1.01 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:05:45.397070+06:00 localhost om:    42,2026-03-13 22:54:49,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:45.455630+06:00 localhost om:    43,2026-03-13 23:04:39,Major,0x000000DD,Asserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:05:45.491053+06:00 localhost om:    44,2026-03-13 23:07:45,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:45.526322+06:00 localhost om:    45,2026-03-13 19:15:53,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:45.583639+06:00 localhost om:    46,2026-03-13 23:08:09,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:45.659208+06:00 localhost om:    47,2026-03-13 23:08:09,Major,0x000000DE,Deasserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (1.01 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:05:45.694999+06:00 localhost om:    48,2026-03-13 23:08:10,Major,0x000000DE,Deasserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:05:45.740580+06:00 localhost om:    49,2026-03-13 23:14:45,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:45.787903+06:00 localhost om:    50,2026-03-13 23:14:46,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:45.820364+06:00 localhost om:    51,2026-03-13 23:14:46,Major,0x000000DD,Asserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold (1.1 V).
2026-03-14T00:05:45.875793+06:00 localhost om:    52,2026-03-13 23:14:46,Major,0x000000DD,Asserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (1.01 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:05:45.919523+06:00 localhost om:    53,2026-03-13 23:18:12,Major,0x000000DE,Deasserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold (1.1 V).
2026-03-14T00:05:45.962910+06:00 localhost om:    54,2026-03-13 23:21:42,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:46.009262+06:00 localhost om:    55,2026-03-13 23:21:44,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:46.047550+06:00 localhost om:    56,2026-03-13 19:15:55,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:46.089924+06:00 localhost om:    57,2026-03-13 23:21:46,Major,0x000000DD,Asserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:05:46.129739+06:00 localhost om:    58,2026-03-13 23:23:48,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:46.188719+06:00 localhost om:    59,2026-03-13 23:24:22,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:46.250267+06:00 localhost om:    60,2026-03-13 23:29:38,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:46.332772+06:00 localhost om:    61,2026-03-13 23:29:40,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:46.381918+06:00 localhost om:    62,2026-03-13 23:29:42,Major,0x000000DE,Deasserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (1.01 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:05:46.418565+06:00 localhost om:    63,2026-03-13 23:29:42,Major,0x000000DE,Deasserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:05:46.451792+06:00 localhost om:    64,2026-03-13 23:32:46,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:46.488283+06:00 localhost om:    65,2026-03-13 23:33:10,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:46.529415+06:00 localhost om:    66,2026-03-13 23:35:30,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:46.581853+06:00 localhost om:    67,2026-03-13 19:19:01,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:46.636956+06:00 localhost om:    68,2026-03-13 23:35:34,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:46.695836+06:00 localhost om:    69,2026-03-13 23:38:58,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:46.735611+06:00 localhost om:    70,2026-03-13 23:39:35,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:46.772659+06:00 localhost om:    71,2026-03-13 23:42:23,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:46.822584+06:00 localhost om:    72,2026-03-13 23:42:27,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:46.861251+06:00 localhost om:    73,2026-03-13 23:46:29,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:46.902969+06:00 localhost om:    74,2026-03-13 23:46:53,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:46.956870+06:00 localhost om:    75,2026-03-13 23:49:58,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:47.023847+06:00 localhost om:    76,2026-03-13 23:50:22,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:47.072806+06:00 localhost om:    77,2026-03-13 23:53:47,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:47.105711+06:00 localhost om:    78,2026-03-13 19:25:27,Major,0x000000DE,Deasserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:05:47.135759+06:00 localhost om:    79,2026-03-13 23:59:47,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:47.173496+06:00 localhost om:    80,2026-03-14 00:00:22,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:47.231024+06:00 localhost om:    81,2026-03-14 00:03:48,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:47.274329+06:00 localhost om:    82,2026-03-14 00:03:50,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:47.315809+06:00 localhost om:    83,2026-03-13 19:25:28,Major,0x000000DE,Deasserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:05:47.357202+06:00 localhost om:    84,2026-03-13 19:27:50,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:47.420608+06:00 localhost om:    85,2026-03-13 19:27:52,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:47.466868+06:00 localhost om:    86,2026-03-13 19:31:36,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:47.511037+06:00 localhost om:    87,2026-03-13 19:32:01,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:47.553721+06:00 localhost om:    88,2026-03-13 19:34:20,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:47.605865+06:00 localhost om:    89,2026-03-13 19:34:27,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:47.659940+06:00 localhost om:    90,2026-03-13 19:37:43,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:47.703308+06:00 localhost om:    91,2026-03-13 19:38:32,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:47.764152+06:00 localhost om:    92,2026-03-13 19:43:42,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:47.817362+06:00 localhost om:    93,2026-03-13 19:43:45,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:47.863312+06:00 localhost om:    94,2026-03-13 19:46:38,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:47.901597+06:00 localhost om:    95,2026-03-13 19:46:45,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:47.942564+06:00 localhost om:    96,2026-03-13 19:49:25,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:47.985508+06:00 localhost om:    97,2026-03-13 19:49:28,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:48.038601+06:00 localhost om:    98,2026-03-13 19:54:55,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:48.081891+06:00 localhost om:    99,2026-03-13 20:07:46,Major,0x000000DD,Asserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:05:48.157059+06:00 localhost om:   100,2026-03-13 20:07:47,Major,0x000000DD,Asserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:05:48.203236+06:00 localhost om:   101,2026-03-13 20:13:06,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:48.253334+06:00 localhost om:   102,2026-03-13 20:13:46,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:48.308062+06:00 localhost om:   103,2026-03-13 20:17:32,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:48.373673+06:00 localhost om:   104,2026-03-13 20:17:34,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:48.455978+06:00 localhost om:   105,2026-03-13 20:17:35,Major,0x000000DE,Deasserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:05:48.505037+06:00 localhost om:   106,2026-03-13 20:19:57,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:48.568696+06:00 localhost om:   107,2026-03-13 20:20:38,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:48.657946+06:00 localhost om:   108,2026-03-13 20:21:06,Major,0x000000DE,Deasserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:05:48.710841+06:00 localhost om:   109,2026-03-13 20:26:18,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:48.750350+06:00 localhost om:   110,2026-03-13 20:26:20,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:48.795481+06:00 localhost om:   111,2026-03-13 20:26:27,Major,0x000000DD,Asserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:05:48.850372+06:00 localhost om:   112,2026-03-13 20:26:28,Major,0x000000DD,Asserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:05:48.893753+06:00 localhost om:   113,2026-03-13 20:28:47,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:48.945408+06:00 localhost om:   114,2026-03-13 20:28:50,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:48.982536+06:00 localhost om:   115,2026-03-13 20:32:03,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:49.055594+06:00 localhost om:   116,2026-03-13 20:32:46,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:49.111058+06:00 localhost om:   117,2026-03-13 20:35:39,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:49.166849+06:00 localhost om:   118,2026-03-13 20:35:41,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:49.202739+06:00 localhost om:   119,2026-03-13 20:39:17,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:49.242057+06:00 localhost om:   120,2026-03-13 20:39:40,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:49.277329+06:00 localhost om:   121,2026-03-13 20:39:42,Major,0x000000DD,Asserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:05:49.320562+06:00 localhost om:   122,2026-03-13 20:39:43,Major,0x000000DD,Asserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:05:49.383258+06:00 localhost om:   123,2026-03-13 20:42:48,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:49.430864+06:00 localhost om:   124,2026-03-13 20:43:12,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:49.470206+06:00 localhost om:   125,2026-03-13 20:43:13,Major,0x000000DE,Deasserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:05:49.506185+06:00 localhost om:   126,2026-03-13 20:43:14,Major,0x000000DE,Deasserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:05:49.545085+06:00 localhost om:   127,2026-03-13 20:45:30,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:49.583031+06:00 localhost om:   128,2026-03-13 20:45:37,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:49.636727+06:00 localhost om:   129,2026-03-13 20:48:19,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:49.693690+06:00 localhost om:   130,2026-03-13 20:48:27,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:49.778001+06:00 localhost om:   131,2026-03-13 20:49:38,Major,0x000000DD,Asserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:05:49.810605+06:00 localhost om:   132,2026-03-13 20:49:38,Major,0x000000DD,Asserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:05:49.842423+06:00 localhost om:   133,2026-03-13 20:53:00,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:49.880935+06:00 localhost om:   134,2026-03-13 20:53:01,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:49.933098+06:00 localhost om:   135,2026-03-13 20:53:04,Major,0x000000DE,Deasserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:05:49.972139+06:00 localhost om:   136,2026-03-13 20:53:05,Major,0x000000DE,Deasserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:05:50.008840+06:00 localhost om:   137,2026-03-13 20:59:27,Major,0x03000007,Asserted,Lost power supply redundancy.
2026-03-14T00:05:50.043789+06:00 localhost om:   138,2026-03-13 20:59:27,Major,0x03000008,Deasserted,Lost power supply redundancy.
2026-03-14T00:05:50.104220+06:00 localhost om:   139,2026-03-13 20:59:27,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:50.141182+06:00 localhost om:   140,2026-03-13 20:59:53,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:50.177318+06:00 localhost om:   141,2026-03-13 21:02:04,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:50.232286+06:00 localhost om:   142,2026-03-13 21:02:11,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:50.276668+06:00 localhost om:   143,2026-03-13 21:03:19,Major,0x000000DD,Asserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:05:50.326935+06:00 localhost om:   144,2026-03-13 21:03:19,Major,0x000000DD,Asserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:05:50.382208+06:00 localhost om:   145,2026-03-13 21:05:33,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:50.421718+06:00 localhost om:   146,2026-03-13 21:05:41,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:50.471825+06:00 localhost om:   147,2026-03-13 21:09:10,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:50.507021+06:00 localhost om:   148,2026-03-13 21:09:13,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:50.545872+06:00 localhost om:   149,2026-03-13 21:12:44,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:50.583743+06:00 localhost om:   150,2026-03-13 21:12:46,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:50.625924+06:00 localhost om:   151,2026-03-13 21:16:26,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:50.681340+06:00 localhost om:   152,2026-03-13 21:16:59,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:50.733664+06:00 localhost om:   153,2026-03-13 21:20:26,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:50.775008+06:00 localhost om:   154,2026-03-13 21:20:50,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:50.834688+06:00 localhost om:   155,2026-03-13 21:20:51,Major,0x000000DE,Deasserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:05:50.881000+06:00 localhost om:   156,2026-03-13 21:23:04,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:50.941253+06:00 localhost om:   157,2026-03-13 21:23:07,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:50.993169+06:00 localhost om:   158,2026-03-13 21:24:19,Major,0x000000DE,Deasserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:05:51.057680+06:00 localhost om:   159,2026-03-13 21:32:17,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:51.100551+06:00 localhost om:   160,2026-03-13 21:32:24,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:05:51.135215+06:00 localhost om:   161,2026-03-13 21:33:36,Major,0x000000DD,Asserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:05:51.169805+06:00 localhost om:   162,2026-03-13 21:33:37,Major,0x000000DD,Asserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:05:51.224597+06:00 localhost om:   163,2026-03-13 21:37:00,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:05:51.263631+06:00 localhost om:   164,2026-03-13 21:37:01,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:25:22.831969+06:00 localhost om:     1,2026-03-13 21:37:01,Major,0x000000DD,Asserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:25:22.906904+06:00 localhost om:     2,2026-03-13 21:37:02,Major,0x000000DD,Asserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:25:22.956458+06:00 localhost om:     3,2026-03-13 21:40:28,Major,0x000000DE,Deasserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:25:23.001407+06:00 localhost om:     4,2026-03-13 21:40:29,Major,0x000000DE,Deasserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:25:23.058211+06:00 localhost om:     5,2026-03-13 21:42:43,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:25:23.098930+06:00 localhost om:     6,2026-03-13 21:42:51,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:25:23.140829+06:00 localhost om:     7,2026-03-13 21:46:14,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:25:23.179959+06:00 localhost om:     8,2026-03-13 21:46:18,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:25:23.230676+06:00 localhost om:     9,2026-03-13 21:50:39,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:25:23.279272+06:00 localhost om:    10,2026-03-13 21:50:41,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:25:23.321437+06:00 localhost om:    11,2026-03-13 21:53:39,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:25:23.391573+06:00 localhost om:    12,2026-03-13 21:53:43,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:25:23.454528+06:00 localhost om:    13,2026-03-13 21:57:12,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:25:23.503293+06:00 localhost om:    14,2026-03-13 21:58:15,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:25:23.550288+06:00 localhost om:    15,2026-03-13 22:00:26,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:25:23.593657+06:00 localhost om:    16,2026-03-13 22:00:26,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:25:23.656408+06:00 localhost om:    17,2026-03-13 22:04:49,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:25:23.717819+06:00 localhost om:    18,2026-03-13 22:05:26,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:25:23.770206+06:00 localhost om:    19,2026-03-13 22:13:31,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:25:23.825158+06:00 localhost om:    20,2026-03-13 22:13:33,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:25:23.901770+06:00 localhost om:    21,2026-03-13 22:18:12,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:25:23.950712+06:00 localhost om:    22,2026-03-13 22:18:14,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:25:24.019430+06:00 localhost om:    23,2026-03-13 22:18:18,Major,0x000000DD,Asserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:25:24.071319+06:00 localhost om:    24,2026-03-13 22:18:19,Major,0x000000DD,Asserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:25:24.120669+06:00 localhost om:    25,2026-03-13 22:21:18,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:25:24.173834+06:00 localhost om:    26,2026-03-13 22:32:57,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:25:24.232863+06:00 localhost om:    27,2026-03-13 22:33:01,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:25:24.289569+06:00 localhost om:    28,2026-03-13 22:37:39,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:25:24.347886+06:00 localhost om:    29,2026-03-13 22:37:41,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:25:24.384904+06:00 localhost om:    30,2026-03-13 22:40:02,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:25:24.433274+06:00 localhost om:    31,2026-03-13 22:40:04,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:25:24.491564+06:00 localhost om:    32,2026-03-13 22:44:08,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:25:24.535025+06:00 localhost om:    33,2026-03-13 22:44:33,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:25:24.578968+06:00 localhost om:    34,2026-03-13 22:44:33,Major,0x000000DE,Deasserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:25:24.629091+06:00 localhost om:    35,2026-03-13 22:44:34,Major,0x000000DE,Deasserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:25:24.678670+06:00 localhost om:    36,2026-03-13 22:48:00,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:25:24.768165+06:00 localhost om:    37,2026-03-13 22:51:25,Major,0x000000DD,Asserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (1.01 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:25:24.838438+06:00 localhost om:    38,2026-03-13 22:54:49,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:25:24.892995+06:00 localhost om:    39,2026-03-13 23:04:39,Major,0x000000DD,Asserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:25:24.951076+06:00 localhost om:    40,2026-03-13 23:07:45,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:25:25.006158+06:00 localhost om:    41,2026-03-13 23:08:09,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:25:25.048528+06:00 localhost om:    42,2026-03-13 23:08:09,Major,0x000000DE,Deasserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (1.01 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:25:25.096584+06:00 localhost om:    43,2026-03-13 23:08:10,Major,0x000000DE,Deasserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:25:25.150542+06:00 localhost om:    44,2026-03-13 23:14:45,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:25:25.226183+06:00 localhost om:    45,2026-03-13 23:14:46,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:25:25.266400+06:00 localhost om:    46,2026-03-13 23:14:46,Major,0x000000DD,Asserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold (1.1 V).
2026-03-14T00:25:25.312968+06:00 localhost om:    47,2026-03-13 23:14:46,Major,0x000000DD,Asserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (1.01 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:25:25.352473+06:00 localhost om:    48,2026-03-13 23:18:12,Major,0x000000DE,Deasserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold (1.1 V).
2026-03-14T00:25:25.405648+06:00 localhost om:    49,2026-03-13 23:21:42,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:25:25.446148+06:00 localhost om:    50,2026-03-13 23:21:44,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:25:25.507958+06:00 localhost om:    51,2026-03-13 23:21:46,Major,0x000000DD,Asserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:25:25.582497+06:00 localhost om:    52,2026-03-13 23:23:48,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:25:25.637652+06:00 localhost om:    53,2026-03-13 23:24:22,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:25:25.675404+06:00 localhost om:    54,2026-03-13 23:29:38,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:25:25.719380+06:00 localhost om:    55,2026-03-13 23:29:40,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:25:25.762866+06:00 localhost om:    56,2026-03-13 23:29:42,Major,0x000000DE,Deasserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (1.01 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:25:25.803717+06:00 localhost om:    57,2026-03-13 23:29:42,Major,0x000000DE,Deasserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:25:25.869010+06:00 localhost om:    58,2026-03-13 23:32:46,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:25:25.918782+06:00 localhost om:    59,2026-03-13 23:33:10,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:25:25.962892+06:00 localhost om:    60,2026-03-13 23:35:30,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:25:26.036162+06:00 localhost om:    61,2026-03-13 23:35:34,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:25:26.082731+06:00 localhost om:    62,2026-03-13 23:38:58,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:25:26.133425+06:00 localhost om:    63,2026-03-13 23:39:35,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:25:26.194348+06:00 localhost om:    64,2026-03-13 23:42:23,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:25:26.239876+06:00 localhost om:    65,2026-03-13 23:42:27,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:25:26.273575+06:00 localhost om:    66,2026-03-13 23:46:29,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:25:26.324298+06:00 localhost om:    67,2026-03-13 23:46:53,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:25:26.369739+06:00 localhost om:    68,2026-03-13 23:49:58,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:25:26.450174+06:00 localhost om:    69,2026-03-13 23:50:22,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:25:26.499778+06:00 localhost om:    70,2026-03-13 23:53:47,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:25:26.546274+06:00 localhost om:    71,2026-03-13 23:59:47,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:25:26.605271+06:00 localhost om:    72,2026-03-14 00:00:22,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:25:26.658223+06:00 localhost om:    73,2026-03-14 00:03:48,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:25:26.709476+06:00 localhost om:    74,2026-03-14 00:03:50,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:25:26.766582+06:00 localhost om:    75,2026-03-14 00:13:33,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:25:26.830422+06:00 localhost om:    76,2026-03-14 00:13:35,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:25:26.904409+06:00 localhost om:    77,2026-03-14 00:13:36,Major,0x000000DD,Asserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (1.01 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:25:26.961771+06:00 localhost om:    78,2026-03-14 00:13:37,Major,0x000000DD,Asserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (1.01 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:25:27.036877+06:00 localhost om:    79,2026-03-14 00:15:55,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:25:27.085377+06:00 localhost om:    80,2026-03-14 00:16:39,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:25:27.142340+06:00 localhost om:    81,2026-03-14 00:17:06,Major,0x000000DE,Deasserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (1.01 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:25:27.193956+06:00 localhost om:    82,2026-03-14 00:17:06,Major,0x000000DE,Deasserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (1.01 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:25:27.248827+06:00 localhost om:    83,2026-03-14 00:19:34,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:25:27.286753+06:00 localhost om:    84,2026-03-14 00:19:36,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:25:27.330889+06:00 localhost om:    85,2026-03-14 00:22:27,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:25:27.418684+06:00 localhost om:    86,2026-03-14 00:22:41,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:58:06.477262+06:00 localhost om:     1,2026-03-14 00:31:44,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:58:06.536112+06:00 localhost om:     2,2026-03-14 00:31:49,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:58:06.577039+06:00 localhost om:     3,2026-03-14 00:35:09,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:58:06.616227+06:00 localhost om:     4,2026-03-14 00:35:46,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:58:06.662066+06:00 localhost om:     5,2026-03-14 00:38:14,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:58:06.710970+06:00 localhost om:     6,2026-03-14 00:38:46,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:58:06.748733+06:00 localhost om:     7,2026-03-14 00:43:04,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:58:06.785691+06:00 localhost om:     8,2026-03-14 00:43:06,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:58:06.843098+06:00 localhost om:     9,2026-03-14 00:44:09,Major,0x000000DD,Asserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:58:06.895977+06:00 localhost om:    10,2026-03-14 00:44:10,Major,0x000000DD,Asserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:58:06.952712+06:00 localhost om:    11,2026-03-14 00:46:24,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:58:06.997434+06:00 localhost om:    12,2026-03-14 00:52:15,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:58:07.038187+06:00 localhost om:    13,2026-03-14 00:52:20,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:58:07.081844+06:00 localhost om:    14,2026-03-14 00:55:18,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T00:58:07.131097+06:00 localhost om:    15,2026-03-14 00:55:21,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T00:58:07.170723+06:00 localhost om:    16,2026-03-14 00:56:17,Critical,0x0300000E,Deasserted,The AC/DC input of PSU 4 is lost or out-of-range (SN:G1302262NA241102023, BN:302004098).
2026-03-14T00:58:07.237775+06:00 localhost om:    17,2026-03-14 00:56:18,Critical,0x0300000E,Deasserted,The AC/DC input of PSU 3 is lost or out-of-range (SN:G1302262NA241202431, BN:302004098).
2026-03-14T00:58:07.308617+06:00 localhost om:    18,2026-03-14 00:56:27,Major,0x000000DE,Deasserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:58:07.367047+06:00 localhost om:    19,2026-03-14 00:56:28,Major,0x000000DE,Deasserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T00:58:07.414301+06:00 localhost om:    20,2026-03-14 00:57:15,Critical,0x0300000D,Asserted,The AC/DC input of PSU 3 is lost or out-of-range (SN:G1302262NA241202431, BN:302004098).
2026-03-14T00:58:07.461007+06:00 localhost om:    21,2026-03-14 00:57:15,Critical,0x0300000D,Asserted,The AC/DC input of PSU 4 is lost or out-of-range (SN:G1302262NA241102023, BN:302004098).
2026-03-14T02:13:41.733739+06:00 localhost om:     1,2026-03-14 01:05:31,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T02:13:41.828882+06:00 localhost om:     2,2026-03-14 01:05:33,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T02:13:41.877207+06:00 localhost om:     3,2026-03-14 01:09:20,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T02:13:41.927918+06:00 localhost om:     4,2026-03-14 01:09:29,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T02:13:41.969823+06:00 localhost om:     5,2026-03-14 01:22:54,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T02:13:42.022520+06:00 localhost om:     6,2026-03-14 01:22:58,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T02:13:42.065710+06:00 localhost om:     7,2026-03-14 01:26:19,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T02:13:42.120304+06:00 localhost om:     8,2026-03-14 01:27:02,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T02:13:42.182700+06:00 localhost om:     9,2026-03-14 01:29:47,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T02:13:42.226280+06:00 localhost om:    10,2026-03-14 01:30:31,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T02:13:42.287472+06:00 localhost om:    11,2026-03-14 01:33:05,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T02:13:42.329208+06:00 localhost om:    12,2026-03-14 01:33:13,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T02:13:42.367091+06:00 localhost om:    13,2026-03-14 01:36:40,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T02:13:42.417238+06:00 localhost om:    14,2026-03-14 01:36:43,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T02:13:42.460033+06:00 localhost om:    15,2026-03-14 01:37:49,Major,0x000000DD,Asserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T02:13:42.508375+06:00 localhost om:    16,2026-03-14 01:37:49,Major,0x000000DD,Asserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T02:13:42.554875+06:00 localhost om:    17,2026-03-14 01:40:03,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T02:13:42.600407+06:00 localhost om:    18,2026-03-14 01:40:49,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T02:13:42.655260+06:00 localhost om:    19,2026-03-14 01:43:41,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T02:13:42.698731+06:00 localhost om:    20,2026-03-14 01:44:16,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T02:13:42.750836+06:00 localhost om:    21,2026-03-14 01:44:43,Major,0x000000DE,Deasserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T02:13:42.817596+06:00 localhost om:    22,2026-03-14 01:44:45,Major,0x000000DE,Deasserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T02:13:42.873246+06:00 localhost om:    23,2026-03-14 01:47:30,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T02:13:42.911750+06:00 localhost om:    24,2026-03-14 01:47:37,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T02:13:42.960547+06:00 localhost om:    25,2026-03-14 01:54:21,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T02:13:42.998983+06:00 localhost om:    26,2026-03-14 01:55:05,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T02:13:43.051401+06:00 localhost om:    27,2026-03-14 01:57:25,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T02:13:43.110096+06:00 localhost om:    28,2026-03-14 01:57:31,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T02:13:43.150100+06:00 localhost om:    29,2026-03-14 01:58:36,Major,0x000000DD,Asserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold (1.1 V).
2026-03-14T02:13:43.210628+06:00 localhost om:    30,2026-03-14 02:01:01,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T02:13:43.250375+06:00 localhost om:    31,2026-03-14 02:01:04,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T02:13:43.298826+06:00 localhost om:    32,2026-03-14 02:04:08,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T02:13:43.360279+06:00 localhost om:    33,2026-03-14 02:05:00,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T02:13:43.425644+06:00 localhost om:    34,2026-03-14 02:05:28,Major,0x000000DD,Asserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T02:13:43.467306+06:00 localhost om:    35,2026-03-14 02:07:46,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T02:13:43.513227+06:00 localhost om:    36,2026-03-14 02:07:51,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T02:13:43.560805+06:00 localhost om:    37,2026-03-14 02:10:52,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T02:13:43.603803+06:00 localhost om:    38,2026-03-14 02:10:55,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T02:13:43.645610+06:00 localhost om:    39,2026-03-14 02:11:27,Critical,0x0300000E,Deasserted,The AC/DC input of PSU 4 is lost or out-of-range (SN:G1302262NA241102023, BN:302004098).
2026-03-14T02:13:43.697761+06:00 localhost om:    40,2026-03-14 02:11:27,Critical,0x0300000E,Deasserted,The AC/DC input of PSU 3 is lost or out-of-range (SN:G1302262NA241202431, BN:302004098).
2026-03-14T02:13:43.755733+06:00 localhost om:    41,2026-03-14 02:13:12,Critical,0x0300000D,Asserted,The AC/DC input of PSU 4 is lost or out-of-range (SN:G1302262NA241102023, BN:302004098).
2026-03-14T02:13:43.822579+06:00 localhost om:    42,2026-03-14 02:13:12,Critical,0x0300000D,Asserted,The AC/DC input of PSU 3 is lost or out-of-range (SN:G1302262NA241202431, BN:302004098).
2026-03-14T02:13:43.870488+06:00 localhost om:    43,2026-03-14 02:13:13,Major,0x000000DE,Deasserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T02:13:43.914974+06:00 localhost om:    44,2026-03-14 02:13:14,Major,0x000000DE,Deasserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold (1.1 V).
2026-03-14T05:45:32.459943+06:00 R624-K2-2512-BMC-test om:     1,2026-03-14 02:20:20,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:32.505473+06:00 R624-K2-2512-BMC-test om:     2,2026-03-14 02:21:27,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T05:45:32.550040+06:00 R624-K2-2512-BMC-test om:     3,2026-03-14 02:21:29,Major,0x000000DD,Asserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T05:45:32.590464+06:00 R624-K2-2512-BMC-test om:     4,2026-03-14 02:21:30,Major,0x000000DD,Asserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T05:45:32.643137+06:00 R624-K2-2512-BMC-test om:     5,2026-03-14 02:23:38,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:32.702641+06:00 R624-K2-2512-BMC-test om:     6,2026-03-14 02:29:57,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:32.770990+06:00 R624-K2-2512-BMC-test om:     7,2026-03-14 02:30:44,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T05:45:32.812090+06:00 R624-K2-2512-BMC-test om:     8,2026-03-14 02:33:32,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:32.851384+06:00 R624-K2-2512-BMC-test om:     9,2026-03-14 02:33:38,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T05:45:32.888448+06:00 R624-K2-2512-BMC-test om:    10,2026-03-14 02:36:51,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T05:45:32.947725+06:00 R624-K2-2512-BMC-test om:    11,2026-03-14 02:36:55,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:32.982636+06:00 R624-K2-2512-BMC-test om:    12,2026-03-14 02:38:00,Major,0x000000DE,Deasserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T05:45:33.019394+06:00 R624-K2-2512-BMC-test om:    13,2026-03-14 02:40:19,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:33.058952+06:00 R624-K2-2512-BMC-test om:    14,2026-03-14 02:40:27,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T05:45:33.105900+06:00 R624-K2-2512-BMC-test om:    15,2026-03-14 02:41:33,Major,0x000000DE,Deasserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T05:45:33.144821+06:00 R624-K2-2512-BMC-test om:    16,2026-03-14 02:43:47,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:33.184815+06:00 R624-K2-2512-BMC-test om:    17,2026-03-14 02:43:55,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T05:45:33.244400+06:00 R624-K2-2512-BMC-test om:    18,2026-03-14 02:47:23,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:33.298440+06:00 R624-K2-2512-BMC-test om:    19,2026-03-14 02:47:30,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T05:45:33.342287+06:00 R624-K2-2512-BMC-test om:    20,2026-03-14 02:48:34,Major,0x000000DD,Asserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (1.01 V) exceeds the overvoltage threshold ( V).
2026-03-14T05:45:33.391648+06:00 R624-K2-2512-BMC-test om:    21,2026-03-14 02:50:53,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:33.448259+06:00 R624-K2-2512-BMC-test om:    22,2026-03-14 02:50:59,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T05:45:33.487691+06:00 R624-K2-2512-BMC-test om:    23,2026-03-14 02:52:04,Major,0x000000DD,Asserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T05:45:33.543210+06:00 R624-K2-2512-BMC-test om:    24,2026-03-14 02:54:28,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T05:45:33.599086+06:00 R624-K2-2512-BMC-test om:    25,2026-03-14 02:55:07,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:33.645694+06:00 R624-K2-2512-BMC-test om:    26,2026-03-14 02:55:34,Major,0x000000DE,Deasserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T05:45:33.683923+06:00 R624-K2-2512-BMC-test om:    27,2026-03-14 02:55:35,Major,0x000000DE,Deasserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (1.01 V) exceeds the overvoltage threshold ( V).
2026-03-14T05:45:33.731678+06:00 R624-K2-2512-BMC-test om:    28,2026-03-14 02:57:55,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:33.771014+06:00 R624-K2-2512-BMC-test om:    29,2026-03-14 02:58:35,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T05:45:33.810223+06:00 R624-K2-2512-BMC-test om:    30,2026-03-14 03:01:21,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T05:45:33.853614+06:00 R624-K2-2512-BMC-test om:    31,2026-03-14 03:02:05,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:33.918519+06:00 R624-K2-2512-BMC-test om:    32,2026-03-14 03:04:56,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:33.969658+06:00 R624-K2-2512-BMC-test om:    33,2026-03-14 03:05:01,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T05:45:34.008416+06:00 R624-K2-2512-BMC-test om:    34,2026-03-14 03:08:02,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T05:45:34.050950+06:00 R624-K2-2512-BMC-test om:    35,2026-03-14 03:08:07,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:34.111397+06:00 R624-K2-2512-BMC-test om:    36,2026-03-14 03:11:20,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:34.161679+06:00 R624-K2-2512-BMC-test om:    37,2026-03-14 03:11:52,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T05:45:34.204124+06:00 R624-K2-2512-BMC-test om:    38,2026-03-14 03:11:53,Critical,0x0300000E,Deasserted,The AC/DC input of PSU 3 is lost or out-of-range (SN:G1302262NA241202431, BN:302004098).
2026-03-14T05:45:34.248126+06:00 R624-K2-2512-BMC-test om:    39,2026-03-14 03:12:17,Critical,0x0300000E,Deasserted,The AC/DC input of PSU 4 is lost or out-of-range (SN:G1302262NA241102023, BN:302004098).
2026-03-14T05:45:34.292190+06:00 R624-K2-2512-BMC-test om:    40,2026-03-14 03:13:17,Critical,0x0300000D,Asserted,The AC/DC input of PSU 4 is lost or out-of-range (SN:G1302262NA241102023, BN:302004098).
2026-03-14T05:45:34.334545+06:00 R624-K2-2512-BMC-test om:    41,2026-03-14 03:13:17,Critical,0x0300000D,Asserted,The AC/DC input of PSU 3 is lost or out-of-range (SN:G1302262NA241202431, BN:302004098).
2026-03-14T05:45:34.377605+06:00 R624-K2-2512-BMC-test om:    42,2026-03-14 03:16:00,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:34.430627+06:00 R624-K2-2512-BMC-test om:    43,2026-03-14 03:16:48,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T05:45:34.496406+06:00 R624-K2-2512-BMC-test om:    44,2026-03-14 03:19:29,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:34.562746+06:00 R624-K2-2512-BMC-test om:    45,2026-03-14 03:19:33,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T05:45:34.598180+06:00 R624-K2-2512-BMC-test om:    46,2026-03-14 03:22:57,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:34.639895+06:00 R624-K2-2512-BMC-test om:    47,2026-03-14 03:23:05,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T05:45:34.680280+06:00 R624-K2-2512-BMC-test om:    48,2026-03-14 03:25:58,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:34.731196+06:00 R624-K2-2512-BMC-test om:    49,2026-03-14 03:26:01,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T05:45:34.770679+06:00 R624-K2-2512-BMC-test om:    50,2026-03-14 03:27:03,Major,0x000000DD,Asserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T05:45:34.811851+06:00 R624-K2-2512-BMC-test om:    51,2026-03-14 03:29:28,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T05:45:34.883056+06:00 R624-K2-2512-BMC-test om:    52,2026-03-14 03:29:33,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:34.930978+06:00 R624-K2-2512-BMC-test om:    53,2026-03-14 03:30:36,Major,0x000000DE,Deasserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T05:45:34.970889+06:00 R624-K2-2512-BMC-test om:    54,2026-03-14 03:32:58,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T05:45:35.015623+06:00 R624-K2-2512-BMC-test om:    55,2026-03-14 03:33:02,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:35.070994+06:00 R624-K2-2512-BMC-test om:    56,2026-03-14 03:35:53,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:35.125268+06:00 R624-K2-2512-BMC-test om:    57,2026-03-14 03:35:56,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T05:45:35.165219+06:00 R624-K2-2512-BMC-test om:    58,2026-03-14 03:38:53,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:35.207170+06:00 R624-K2-2512-BMC-test om:    59,2026-03-14 03:39:00,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T05:45:35.259932+06:00 R624-K2-2512-BMC-test om:    60,2026-03-14 03:41:50,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:35.304709+06:00 R624-K2-2512-BMC-test om:    61,2026-03-14 03:41:58,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T05:45:35.354885+06:00 R624-K2-2512-BMC-test om:    62,2026-03-14 03:45:54,Major,0x000000DD,Asserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T05:45:35.399886+06:00 R624-K2-2512-BMC-test om:    63,2026-03-14 03:45:55,Major,0x000000DD,Asserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (1.01 V) exceeds the overvoltage threshold ( V).
2026-03-14T05:45:35.442639+06:00 R624-K2-2512-BMC-test om:    64,2026-03-14 03:48:12,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:35.484105+06:00 R624-K2-2512-BMC-test om:    65,2026-03-14 03:48:54,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T05:45:35.530807+06:00 R624-K2-2512-BMC-test om:    66,2026-03-14 03:49:22,Major,0x000000DE,Deasserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T05:45:35.580714+06:00 R624-K2-2512-BMC-test om:    67,2026-03-14 03:49:23,Major,0x000000DE,Deasserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (1.01 V) exceeds the overvoltage threshold ( V).
2026-03-14T05:45:35.644784+06:00 R624-K2-2512-BMC-test om:    68,2026-03-14 03:51:34,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T05:45:35.713660+06:00 R624-K2-2512-BMC-test om:    69,2026-03-14 03:52:21,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:35.752886+06:00 R624-K2-2512-BMC-test om:    70,2026-03-14 03:54:55,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:35.791377+06:00 R624-K2-2512-BMC-test om:    71,2026-03-14 03:59:13,Major,0x000000DD,Asserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T05:45:35.835067+06:00 R624-K2-2512-BMC-test om:    72,2026-03-14 03:59:13,Major,0x000000DD,Asserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T05:45:35.881575+06:00 R624-K2-2512-BMC-test om:    73,2026-03-14 04:01:23,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:35.926148+06:00 R624-K2-2512-BMC-test om:    74,2026-03-14 04:05:58,Major,0x000000DE,Deasserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T05:45:35.978953+06:00 R624-K2-2512-BMC-test om:    75,2026-03-14 04:05:58,Major,0x000000DE,Deasserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T05:45:36.027165+06:00 R624-K2-2512-BMC-test om:    76,2026-03-14 04:08:17,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:36.066837+06:00 R624-K2-2512-BMC-test om:    77,2026-03-14 04:09:01,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T05:45:36.114776+06:00 R624-K2-2512-BMC-test om:    78,2026-03-14 04:11:17,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:36.160890+06:00 R624-K2-2512-BMC-test om:    79,2026-03-14 04:17:16,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:36.229025+06:00 R624-K2-2512-BMC-test om:    80,2026-03-14 04:17:21,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T05:45:36.283663+06:00 R624-K2-2512-BMC-test om:    81,2026-03-14 04:18:27,Major,0x000000DD,Asserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T05:45:36.324180+06:00 R624-K2-2512-BMC-test om:    82,2026-03-14 04:18:27,Major,0x000000DD,Asserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (1.01 V) exceeds the overvoltage threshold ( V).
2026-03-14T05:45:36.370790+06:00 R624-K2-2512-BMC-test om:    83,2026-03-14 04:20:45,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T05:45:36.415056+06:00 R624-K2-2512-BMC-test om:    84,2026-03-14 04:20:52,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:36.455275+06:00 R624-K2-2512-BMC-test om:    85,2026-03-14 04:23:41,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:36.502057+06:00 R624-K2-2512-BMC-test om:    86,2026-03-14 04:23:47,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T05:45:36.548382+06:00 R624-K2-2512-BMC-test om:    87,2026-03-14 04:27:00,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:36.592121+06:00 R624-K2-2512-BMC-test om:    88,2026-03-14 04:27:46,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T05:45:36.633563+06:00 R624-K2-2512-BMC-test om:    89,2026-03-14 04:32:50,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:36.671241+06:00 R624-K2-2512-BMC-test om:    90,2026-03-14 04:33:39,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T05:45:36.741762+06:00 R624-K2-2512-BMC-test om:    91,2026-03-14 04:36:07,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T05:45:36.806168+06:00 R624-K2-2512-BMC-test om:    92,2026-03-14 04:36:13,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:36.845298+06:00 R624-K2-2512-BMC-test om:    93,2026-03-14 04:39:36,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:36.888207+06:00 R624-K2-2512-BMC-test om:    94,2026-03-14 04:40:17,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T05:45:36.930768+06:00 R624-K2-2512-BMC-test om:    95,2026-03-14 04:44:06,Major,0x000000DE,Deasserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (1.01 V) exceeds the overvoltage threshold ( V).
2026-03-14T05:45:36.973538+06:00 R624-K2-2512-BMC-test om:    96,2026-03-14 04:46:28,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:37.020807+06:00 R624-K2-2512-BMC-test om:    97,2026-03-14 04:46:33,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T05:45:37.069239+06:00 R624-K2-2512-BMC-test om:    98,2026-03-14 04:47:39,Major,0x000000DE,Deasserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T05:45:37.120560+06:00 R624-K2-2512-BMC-test om:    99,2026-03-14 04:49:50,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:37.167378+06:00 R624-K2-2512-BMC-test om:   100,2026-03-14 04:49:58,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T05:45:37.228149+06:00 R624-K2-2512-BMC-test om:   101,2026-03-14 04:53:13,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:37.272377+06:00 R624-K2-2512-BMC-test om:   102,2026-03-14 04:58:55,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T05:45:37.322891+06:00 R624-K2-2512-BMC-test om:   103,2026-03-14 04:59:03,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:37.380509+06:00 R624-K2-2512-BMC-test om:   104,2026-03-14 05:02:17,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:37.427791+06:00 R624-K2-2512-BMC-test om:   105,2026-03-14 05:02:21,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T05:45:37.475887+06:00 R624-K2-2512-BMC-test om:   106,2026-03-14 05:07:00,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:37.518419+06:00 R624-K2-2512-BMC-test om:   107,2026-03-14 05:07:07,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T05:45:37.559798+06:00 R624-K2-2512-BMC-test om:   108,2026-03-14 05:10:07,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:37.606329+06:00 R624-K2-2512-BMC-test om:   109,2026-03-14 05:10:12,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T05:45:37.646912+06:00 R624-K2-2512-BMC-test om:   110,2026-03-14 05:13:20,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:37.688943+06:00 R624-K2-2512-BMC-test om:   111,2026-03-14 05:13:23,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T05:45:37.752179+06:00 R624-K2-2512-BMC-test om:   112,2026-03-14 05:17:09,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:37.805609+06:00 R624-K2-2512-BMC-test om:   113,2026-03-14 05:17:14,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T05:45:37.844912+06:00 R624-K2-2512-BMC-test om:   114,2026-03-14 05:20:35,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T05:45:37.910241+06:00 R624-K2-2512-BMC-test om:   115,2026-03-14 05:20:43,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:37.967635+06:00 R624-K2-2512-BMC-test om:   116,2026-03-14 05:25:03,Major,0x000000DD,Asserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (1.01 V) exceeds the overvoltage threshold ( V).
2026-03-14T05:45:38.004246+06:00 R624-K2-2512-BMC-test om:   117,2026-03-14 05:27:17,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:38.041634+06:00 R624-K2-2512-BMC-test om:   118,2026-03-14 05:27:25,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T05:45:38.079342+06:00 R624-K2-2512-BMC-test om:   119,2026-03-14 05:30:23,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:38.131322+06:00 R624-K2-2512-BMC-test om:   120,2026-03-14 05:30:28,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T05:45:38.169933+06:00 R624-K2-2512-BMC-test om:   121,2026-03-14 05:33:26,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:38.221339+06:00 R624-K2-2512-BMC-test om:   122,2026-03-14 05:33:30,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T05:45:38.265228+06:00 R624-K2-2512-BMC-test om:   123,2026-03-14 05:34:35,Major,0x000000DE,Deasserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (1.01 V) exceeds the overvoltage threshold ( V).
2026-03-14T05:45:38.321260+06:00 R624-K2-2512-BMC-test om:   124,2026-03-14 05:36:59,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:38.359494+06:00 R624-K2-2512-BMC-test om:   125,2026-03-14 05:37:38,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T05:45:38.403754+06:00 R624-K2-2512-BMC-test om:   126,2026-03-14 05:40:04,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:38.458469+06:00 R624-K2-2512-BMC-test om:   127,2026-03-14 05:40:06,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T05:45:38.525214+06:00 R624-K2-2512-BMC-test om:   128,2026-03-14 05:42:51,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T05:45:38.564417+06:00 R624-K2-2512-BMC-test om:   129,2026-03-14 05:42:54,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T05:45:38.602134+06:00 R624-K2-2512-BMC-test om:   130,2026-03-14 05:43:49,Critical,0x0300000E,Deasserted,The AC/DC input of PSU 3 is lost or out-of-range (SN:G1302262NA241202431, BN:302004098).
2026-03-14T05:45:38.641694+06:00 R624-K2-2512-BMC-test om:   131,2026-03-14 05:43:49,Critical,0x0300000E,Deasserted,The AC/DC input of PSU 4 is lost or out-of-range (SN:G1302262NA241102023, BN:302004098).
2026-03-14T06:57:29.614495+06:00 R624-K2-2512-BMC-test om:     1,2026-03-14 02:20:20,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:29.664156+06:00 R624-K2-2512-BMC-test om:     2,2026-03-14 02:21:27,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:29.705603+06:00 R624-K2-2512-BMC-test om:     3,2026-03-14 02:21:29,Major,0x000000DD,Asserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T06:57:29.751194+06:00 R624-K2-2512-BMC-test om:     4,2026-03-14 02:21:30,Major,0x000000DD,Asserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T06:57:29.792477+06:00 R624-K2-2512-BMC-test om:     5,2026-03-14 02:23:38,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:29.841546+06:00 R624-K2-2512-BMC-test om:     6,2026-03-14 02:29:57,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:29.887635+06:00 R624-K2-2512-BMC-test om:     7,2026-03-14 02:30:44,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:29.945434+06:00 R624-K2-2512-BMC-test om:     8,2026-03-14 02:33:32,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:29.993906+06:00 R624-K2-2512-BMC-test om:     9,2026-03-14 02:33:38,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:30.038378+06:00 R624-K2-2512-BMC-test om:    10,2026-03-14 02:36:51,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:30.090325+06:00 R624-K2-2512-BMC-test om:    11,2026-03-14 02:36:55,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:30.162316+06:00 R624-K2-2512-BMC-test om:    12,2026-03-14 02:38:00,Major,0x000000DE,Deasserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T06:57:30.213986+06:00 R624-K2-2512-BMC-test om:    13,2026-03-14 02:40:19,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:30.255500+06:00 R624-K2-2512-BMC-test om:    14,2026-03-14 02:40:27,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:30.310720+06:00 R624-K2-2512-BMC-test om:    15,2026-03-14 02:41:33,Major,0x000000DE,Deasserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T06:57:30.354443+06:00 R624-K2-2512-BMC-test om:    16,2026-03-14 02:43:47,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:30.400627+06:00 R624-K2-2512-BMC-test om:    17,2026-03-14 02:43:55,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:30.448686+06:00 R624-K2-2512-BMC-test om:    18,2026-03-14 02:47:23,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:30.519196+06:00 R624-K2-2512-BMC-test om:    19,2026-03-14 02:47:30,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:30.602465+06:00 R624-K2-2512-BMC-test om:    20,2026-03-14 02:48:34,Major,0x000000DD,Asserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (1.01 V) exceeds the overvoltage threshold ( V).
2026-03-14T06:57:30.685078+06:00 R624-K2-2512-BMC-test om:    21,2026-03-14 02:50:53,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:30.729802+06:00 R624-K2-2512-BMC-test om:    22,2026-03-14 02:50:59,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:30.775919+06:00 R624-K2-2512-BMC-test om:    23,2026-03-14 02:52:04,Major,0x000000DD,Asserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T06:57:30.825639+06:00 R624-K2-2512-BMC-test om:    24,2026-03-14 02:54:28,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:30.876626+06:00 R624-K2-2512-BMC-test om:    25,2026-03-14 02:55:07,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:30.927029+06:00 R624-K2-2512-BMC-test om:    26,2026-03-14 02:55:34,Major,0x000000DE,Deasserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T06:57:30.977582+06:00 R624-K2-2512-BMC-test om:    27,2026-03-14 02:55:35,Major,0x000000DE,Deasserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (1.01 V) exceeds the overvoltage threshold ( V).
2026-03-14T06:57:31.020345+06:00 R624-K2-2512-BMC-test om:    28,2026-03-14 02:57:55,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:31.097173+06:00 R624-K2-2512-BMC-test om:    29,2026-03-14 02:58:35,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:31.155557+06:00 R624-K2-2512-BMC-test om:    30,2026-03-14 03:01:21,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:31.190530+06:00 R624-K2-2512-BMC-test om:    31,2026-03-14 03:02:05,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:31.229513+06:00 R624-K2-2512-BMC-test om:    32,2026-03-14 03:04:56,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:31.270301+06:00 R624-K2-2512-BMC-test om:    33,2026-03-14 03:05:01,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:31.313539+06:00 R624-K2-2512-BMC-test om:    34,2026-03-14 03:08:02,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:31.364866+06:00 R624-K2-2512-BMC-test om:    35,2026-03-14 03:08:07,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:31.417525+06:00 R624-K2-2512-BMC-test om:    36,2026-03-14 03:11:20,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:31.472980+06:00 R624-K2-2512-BMC-test om:    37,2026-03-14 03:11:52,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:31.516544+06:00 R624-K2-2512-BMC-test om:    38,2026-03-14 03:11:53,Critical,0x0300000E,Deasserted,The AC/DC input of PSU 3 is lost or out-of-range (SN:G1302262NA241202431, BN:302004098).
2026-03-14T06:57:31.562248+06:00 R624-K2-2512-BMC-test om:    39,2026-03-14 03:12:17,Critical,0x0300000E,Deasserted,The AC/DC input of PSU 4 is lost or out-of-range (SN:G1302262NA241102023, BN:302004098).
2026-03-14T06:57:31.611235+06:00 R624-K2-2512-BMC-test om:    40,2026-03-14 03:13:17,Critical,0x0300000D,Asserted,The AC/DC input of PSU 4 is lost or out-of-range (SN:G1302262NA241102023, BN:302004098).
2026-03-14T06:57:31.660009+06:00 R624-K2-2512-BMC-test om:    41,2026-03-14 03:13:17,Critical,0x0300000D,Asserted,The AC/DC input of PSU 3 is lost or out-of-range (SN:G1302262NA241202431, BN:302004098).
2026-03-14T06:57:31.720289+06:00 R624-K2-2512-BMC-test om:    42,2026-03-14 03:16:00,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:31.782809+06:00 R624-K2-2512-BMC-test om:    43,2026-03-14 03:16:48,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:31.838489+06:00 R624-K2-2512-BMC-test om:    44,2026-03-14 03:19:29,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:31.897335+06:00 R624-K2-2512-BMC-test om:    45,2026-03-14 03:19:33,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:31.952252+06:00 R624-K2-2512-BMC-test om:    46,2026-03-14 03:22:57,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:32.006739+06:00 R624-K2-2512-BMC-test om:    47,2026-03-14 03:23:05,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:32.061537+06:00 R624-K2-2512-BMC-test om:    48,2026-03-14 03:25:58,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:32.111249+06:00 R624-K2-2512-BMC-test om:    49,2026-03-14 03:26:01,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:32.156190+06:00 R624-K2-2512-BMC-test om:    50,2026-03-14 03:27:03,Major,0x000000DD,Asserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T06:57:32.203419+06:00 R624-K2-2512-BMC-test om:    51,2026-03-14 03:29:28,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:32.256164+06:00 R624-K2-2512-BMC-test om:    52,2026-03-14 03:29:33,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:32.341826+06:00 R624-K2-2512-BMC-test om:    53,2026-03-14 03:30:36,Major,0x000000DE,Deasserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T06:57:32.404725+06:00 R624-K2-2512-BMC-test om:    54,2026-03-14 03:32:58,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:32.455832+06:00 R624-K2-2512-BMC-test om:    55,2026-03-14 03:33:02,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:32.496896+06:00 R624-K2-2512-BMC-test om:    56,2026-03-14 03:35:53,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:32.539607+06:00 R624-K2-2512-BMC-test om:    57,2026-03-14 03:35:56,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:32.580623+06:00 R624-K2-2512-BMC-test om:    58,2026-03-14 03:38:53,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:32.628243+06:00 R624-K2-2512-BMC-test om:    59,2026-03-14 03:39:00,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:32.673015+06:00 R624-K2-2512-BMC-test om:    60,2026-03-14 03:41:50,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:32.744901+06:00 R624-K2-2512-BMC-test om:    61,2026-03-14 03:41:58,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:32.796451+06:00 R624-K2-2512-BMC-test om:    62,2026-03-14 03:45:54,Major,0x000000DD,Asserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T06:57:32.843501+06:00 R624-K2-2512-BMC-test om:    63,2026-03-14 03:45:55,Major,0x000000DD,Asserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (1.01 V) exceeds the overvoltage threshold ( V).
2026-03-14T06:57:32.887792+06:00 R624-K2-2512-BMC-test om:    64,2026-03-14 03:48:12,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:32.927524+06:00 R624-K2-2512-BMC-test om:    65,2026-03-14 03:48:54,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:33.004671+06:00 R624-K2-2512-BMC-test om:    66,2026-03-14 03:49:22,Major,0x000000DE,Deasserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T06:57:33.066639+06:00 R624-K2-2512-BMC-test om:    67,2026-03-14 03:49:23,Major,0x000000DE,Deasserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (1.01 V) exceeds the overvoltage threshold ( V).
2026-03-14T06:57:33.104848+06:00 R624-K2-2512-BMC-test om:    68,2026-03-14 03:51:34,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:33.152549+06:00 R624-K2-2512-BMC-test om:    69,2026-03-14 03:52:21,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:33.207725+06:00 R624-K2-2512-BMC-test om:    70,2026-03-14 03:54:55,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:33.248382+06:00 R624-K2-2512-BMC-test om:    71,2026-03-14 03:59:13,Major,0x000000DD,Asserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T06:57:33.305178+06:00 R624-K2-2512-BMC-test om:    72,2026-03-14 03:59:13,Major,0x000000DD,Asserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T06:57:33.350970+06:00 R624-K2-2512-BMC-test om:    73,2026-03-14 04:01:23,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:33.401387+06:00 R624-K2-2512-BMC-test om:    74,2026-03-14 04:05:58,Major,0x000000DE,Deasserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T06:57:33.459902+06:00 R624-K2-2512-BMC-test om:    75,2026-03-14 04:05:58,Major,0x000000DE,Deasserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T06:57:33.505911+06:00 R624-K2-2512-BMC-test om:    76,2026-03-14 04:08:17,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:33.553524+06:00 R624-K2-2512-BMC-test om:    77,2026-03-14 04:09:01,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:33.649936+06:00 R624-K2-2512-BMC-test om:    78,2026-03-14 04:11:17,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:33.697916+06:00 R624-K2-2512-BMC-test om:    79,2026-03-14 04:17:16,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:33.740743+06:00 R624-K2-2512-BMC-test om:    80,2026-03-14 04:17:21,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:33.788794+06:00 R624-K2-2512-BMC-test om:    81,2026-03-14 04:18:27,Major,0x000000DD,Asserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T06:57:33.841276+06:00 R624-K2-2512-BMC-test om:    82,2026-03-14 04:18:27,Major,0x000000DD,Asserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (1.01 V) exceeds the overvoltage threshold ( V).
2026-03-14T06:57:33.897837+06:00 R624-K2-2512-BMC-test om:    83,2026-03-14 04:20:45,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:33.938886+06:00 R624-K2-2512-BMC-test om:    84,2026-03-14 04:20:52,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:34.000705+06:00 R624-K2-2512-BMC-test om:    85,2026-03-14 04:23:41,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:34.046708+06:00 R624-K2-2512-BMC-test om:    86,2026-03-14 04:23:47,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:34.113388+06:00 R624-K2-2512-BMC-test om:    87,2026-03-14 04:27:00,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:34.222037+06:00 R624-K2-2512-BMC-test om:    88,2026-03-14 04:27:46,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:34.303744+06:00 R624-K2-2512-BMC-test om:    89,2026-03-14 04:32:50,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:34.365743+06:00 R624-K2-2512-BMC-test om:    90,2026-03-14 04:33:39,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:34.438412+06:00 R624-K2-2512-BMC-test om:    91,2026-03-14 04:36:07,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:34.488462+06:00 R624-K2-2512-BMC-test om:    92,2026-03-14 04:36:13,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:34.526994+06:00 R624-K2-2512-BMC-test om:    93,2026-03-14 04:39:36,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:34.574294+06:00 R624-K2-2512-BMC-test om:    94,2026-03-14 04:40:17,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:34.634594+06:00 R624-K2-2512-BMC-test om:    95,2026-03-14 04:44:06,Major,0x000000DE,Deasserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (1.01 V) exceeds the overvoltage threshold ( V).
2026-03-14T06:57:34.685719+06:00 R624-K2-2512-BMC-test om:    96,2026-03-14 04:46:28,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:34.734307+06:00 R624-K2-2512-BMC-test om:    97,2026-03-14 04:46:33,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:34.778404+06:00 R624-K2-2512-BMC-test om:    98,2026-03-14 04:47:39,Major,0x000000DE,Deasserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T06:57:34.826477+06:00 R624-K2-2512-BMC-test om:    99,2026-03-14 04:49:50,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:34.868529+06:00 R624-K2-2512-BMC-test om:   100,2026-03-14 04:49:58,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:34.918413+06:00 R624-K2-2512-BMC-test om:   101,2026-03-14 04:53:13,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:34.997878+06:00 R624-K2-2512-BMC-test om:   102,2026-03-14 04:58:55,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:35.046618+06:00 R624-K2-2512-BMC-test om:   103,2026-03-14 04:59:03,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:35.081397+06:00 R624-K2-2512-BMC-test om:   104,2026-03-14 05:02:17,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:35.125394+06:00 R624-K2-2512-BMC-test om:   105,2026-03-14 05:02:21,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:35.167011+06:00 R624-K2-2512-BMC-test om:   106,2026-03-14 05:07:00,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:35.227081+06:00 R624-K2-2512-BMC-test om:   107,2026-03-14 05:07:07,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:35.269356+06:00 R624-K2-2512-BMC-test om:   108,2026-03-14 05:10:07,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:35.312606+06:00 R624-K2-2512-BMC-test om:   109,2026-03-14 05:10:12,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:35.368146+06:00 R624-K2-2512-BMC-test om:   110,2026-03-14 05:13:20,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:35.429965+06:00 R624-K2-2512-BMC-test om:   111,2026-03-14 05:13:23,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:35.485436+06:00 R624-K2-2512-BMC-test om:   112,2026-03-14 05:17:09,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:35.533206+06:00 R624-K2-2512-BMC-test om:   113,2026-03-14 05:17:14,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:35.596907+06:00 R624-K2-2512-BMC-test om:   114,2026-03-14 05:20:35,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:35.655927+06:00 R624-K2-2512-BMC-test om:   115,2026-03-14 05:20:43,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:35.693917+06:00 R624-K2-2512-BMC-test om:   116,2026-03-14 05:25:03,Major,0x000000DD,Asserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (1.01 V) exceeds the overvoltage threshold ( V).
2026-03-14T06:57:35.738059+06:00 R624-K2-2512-BMC-test om:   117,2026-03-14 05:27:17,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:35.797821+06:00 R624-K2-2512-BMC-test om:   118,2026-03-14 05:27:25,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:35.845973+06:00 R624-K2-2512-BMC-test om:   119,2026-03-14 05:30:23,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:35.890131+06:00 R624-K2-2512-BMC-test om:   120,2026-03-14 05:30:28,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:35.939908+06:00 R624-K2-2512-BMC-test om:   121,2026-03-14 05:33:26,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:35.981221+06:00 R624-K2-2512-BMC-test om:   122,2026-03-14 05:33:30,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:36.032453+06:00 R624-K2-2512-BMC-test om:   123,2026-03-14 05:34:35,Major,0x000000DE,Deasserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (1.01 V) exceeds the overvoltage threshold ( V).
2026-03-14T06:57:36.094606+06:00 R624-K2-2512-BMC-test om:   124,2026-03-14 05:36:59,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:36.156062+06:00 R624-K2-2512-BMC-test om:   125,2026-03-14 05:37:38,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:36.218981+06:00 R624-K2-2512-BMC-test om:   126,2026-03-14 05:40:04,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:36.296749+06:00 R624-K2-2512-BMC-test om:   127,2026-03-14 05:40:06,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:36.341119+06:00 R624-K2-2512-BMC-test om:   128,2026-03-14 05:42:51,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:36.377987+06:00 R624-K2-2512-BMC-test om:   129,2026-03-14 05:42:54,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:36.427562+06:00 R624-K2-2512-BMC-test om:   130,2026-03-14 05:43:49,Critical,0x0300000E,Deasserted,The AC/DC input of PSU 3 is lost or out-of-range (SN:G1302262NA241202431, BN:302004098).
2026-03-14T06:57:36.491901+06:00 R624-K2-2512-BMC-test om:   131,2026-03-14 05:43:49,Critical,0x0300000E,Deasserted,The AC/DC input of PSU 4 is lost or out-of-range (SN:G1302262NA241102023, BN:302004098).
2026-03-14T06:57:36.533726+06:00 R624-K2-2512-BMC-test om:   132,2026-03-14 05:48:32,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:36.598986+06:00 R624-K2-2512-BMC-test om:   133,2026-03-14 05:48:39,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:36.651807+06:00 R624-K2-2512-BMC-test om:   134,2026-03-14 05:49:18,Critical,0x0300000D,Asserted,The AC/DC input of PSU 3 is lost or out-of-range (SN:G1302262NA241202431, BN:302004098).
2026-03-14T06:57:36.693383+06:00 R624-K2-2512-BMC-test om:   135,2026-03-14 05:51:48,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:36.736745+06:00 R624-K2-2512-BMC-test om:   136,2026-03-14 05:52:22,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:36.785889+06:00 R624-K2-2512-BMC-test om:   137,2026-03-14 05:52:48,Critical,0x0300000D,Asserted,The AC/DC input of PSU 4 is lost or out-of-range (SN:G1302262NA241102023, BN:302004098).
2026-03-14T06:57:36.854795+06:00 R624-K2-2512-BMC-test om:   138,2026-03-14 05:55:46,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:36.897428+06:00 R624-K2-2512-BMC-test om:   139,2026-03-14 05:56:33,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:36.932383+06:00 R624-K2-2512-BMC-test om:   140,2026-03-14 05:59:14,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:36.977059+06:00 R624-K2-2512-BMC-test om:   141,2026-03-14 05:59:54,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:37.045897+06:00 R624-K2-2512-BMC-test om:   142,2026-03-14 06:00:21,Major,0x000000DD,Asserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T06:57:37.102512+06:00 R624-K2-2512-BMC-test om:   143,2026-03-14 06:00:21,Major,0x000000DD,Asserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T06:57:37.143738+06:00 R624-K2-2512-BMC-test om:   144,2026-03-14 06:02:40,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:37.185903+06:00 R624-K2-2512-BMC-test om:   145,2026-03-14 06:02:44,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:37.234151+06:00 R624-K2-2512-BMC-test om:   146,2026-03-14 06:06:06,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:37.304260+06:00 R624-K2-2512-BMC-test om:   147,2026-03-14 06:06:14,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:37.367367+06:00 R624-K2-2512-BMC-test om:   148,2026-03-14 06:09:43,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:37.423721+06:00 R624-K2-2512-BMC-test om:   149,2026-03-14 06:09:50,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:37.490815+06:00 R624-K2-2512-BMC-test om:   150,2026-03-14 06:12:57,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:37.537073+06:00 R624-K2-2512-BMC-test om:   151,2026-03-14 06:13:43,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:37.578217+06:00 R624-K2-2512-BMC-test om:   152,2026-03-14 06:16:23,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:37.615708+06:00 R624-K2-2512-BMC-test om:   153,2026-03-14 06:17:02,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:37.660730+06:00 R624-K2-2512-BMC-test om:   154,2026-03-14 06:19:47,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:37.724576+06:00 R624-K2-2512-BMC-test om:   155,2026-03-14 06:20:26,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:37.766734+06:00 R624-K2-2512-BMC-test om:   156,2026-03-14 06:20:52,Major,0x000000DE,Deasserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T06:57:37.827310+06:00 R624-K2-2512-BMC-test om:   157,2026-03-14 06:23:18,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:37.883339+06:00 R624-K2-2512-BMC-test om:   158,2026-03-14 06:23:57,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:37.929239+06:00 R624-K2-2512-BMC-test om:   159,2026-03-14 06:24:24,Major,0x000000DD,Asserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T06:57:37.974454+06:00 R624-K2-2512-BMC-test om:   160,2026-03-14 06:26:43,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:38.042160+06:00 R624-K2-2512-BMC-test om:   161,2026-03-14 06:26:47,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:38.114391+06:00 R624-K2-2512-BMC-test om:   162,2026-03-14 06:30:14,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:38.154467+06:00 R624-K2-2512-BMC-test om:   163,2026-03-14 06:30:54,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:38.193852+06:00 R624-K2-2512-BMC-test om:   164,2026-03-14 06:33:45,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:38.238050+06:00 R624-K2-2512-BMC-test om:   165,2026-03-14 06:33:48,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:38.296496+06:00 R624-K2-2512-BMC-test om:   166,2026-03-14 06:34:52,Major,0x000000DE,Deasserted,CPU 1(CpuBoard1 CPU1) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T06:57:38.340760+06:00 R624-K2-2512-BMC-test om:   167,2026-03-14 06:34:53,Major,0x000000DE,Deasserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (0.81 V) exceeds the overvoltage threshold ( V).
2026-03-14T06:57:38.382609+06:00 R624-K2-2512-BMC-test om:   168,2026-03-14 06:37:08,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:38.426876+06:00 R624-K2-2512-BMC-test om:   169,2026-03-14 06:37:15,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:38.471313+06:00 R624-K2-2512-BMC-test om:   170,2026-03-14 06:40:44,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:38.529838+06:00 R624-K2-2512-BMC-test om:   171,2026-03-14 06:40:48,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:38.577008+06:00 R624-K2-2512-BMC-test om:   172,2026-03-14 06:48:17,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:38.667138+06:00 R624-K2-2512-BMC-test om:   173,2026-03-14 06:48:20,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:38.726412+06:00 R624-K2-2512-BMC-test om:   174,2026-03-14 06:51:18,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:38.765698+06:00 R624-K2-2512-BMC-test om:   175,2026-03-14 06:51:25,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:38.805849+06:00 R624-K2-2512-BMC-test om:   176,2026-03-14 06:52:30,Major,0x000000DD,Asserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (1.01 V) exceeds the overvoltage threshold ( V).
2026-03-14T06:57:38.851131+06:00 R624-K2-2512-BMC-test om:   177,2026-03-14 06:54:47,Normal,0x1A000021,Asserted,openUBMC is reset and started.
2026-03-14T06:57:38.895815+06:00 R624-K2-2512-BMC-test om:   178,2026-03-14 06:54:53,Normal,0x1A00006F,Asserted,The openUBMC is reset, with the cause code of 0x0.
2026-03-14T06:57:38.949049+06:00 R624-K2-2512-BMC-test om:   179,2026-03-14 06:55:58,Major,0x000000DE,Deasserted,CPU 2(CpuBoard1 CPU2) Uncore voltage (1.01 V) exceeds the overvoltage threshold ( V).
