s
3>power domain[5] set volt -->  800 mV success
3>============volt post============
3>power domain[0] volt = 1099 mV
3>power domain[1] volt =  763 mV
3>power domain[4] volt =  802 mV
3>power domain[2] volt = 1105 mV
3>power domain[3] volt =  982 mV
3>power domain[5] volt =  800 mV
3>power domain[6] volt = 1101 mV
3>===============end===============
3>Hboot1 Info RAW Dump: [0x01][0x00][0x00][0x14][0x01][0x00][0x01]
3>PowerSensorSupport[1], Cali[5120], Loss[0]
3>Power Sensor Calibration Value[5120]!
3>the power sensor : manu id = 2peak, die id = TPA626
3>power sensor[0] init success
3>die[0] its[0] init done
3>die[0] its[1] init done
3>die[0] its[2] init done
3>die[0] its[3] init done
3>die[0] its[4] init done
3>die[0] its[5] init done
3>die[0] its[6] init done
3>die[0] its[7] init done
3>die[0] its[8] init done
3>die[0] its[9] init done
3>die[1] its[0] init done
3>die[1] its[1] init done
3>die[1] its[2] init done
3>die[1] its[3] init done
3>die[1] its[4] init done
3>die[1] its[5] init done
3>die[1] its[6] init done
3>die[1] its[7] init done
3>die[1] its[8] init done
3>die[1] its[9] init done
3>Totem[0] Core Boot Vol [1099]mv
3>Totem[0] Core Current Vol [1100]mv
3>Totem[1] Core Boot Vol [1105]mv
3>Totem[1] Core Current Vol [1100]mv
3>NA 1620V190
3>NB 1620V190
3>GetCoreBaseFreq [2900000KHZ]
3>GetCoreTurboFreq [2900000KHZ]
3>GetCustomClusterNum [10]
3>Ipu ACG Training Done!
3>AP Last Time:[0.00.01.550]
3>wait UEFI pll init...
3>done
3>acg trim start
3>core trim freq:2000, avs:0 volt:810mv
3>core trim freq:2000, avs:0 volt:810mv
3>core trim freq:2050, avs:1 volt:810mv
3>core trim freq:2050, avs:1 volt:810mv
3>core trim freq:2100, avs:2 volt:810mv
3>core trim freq:2100, avs:2 volt:810mv
3>core trim freq:2150, avs:3 volt:810mv
3>core trim freq:2150, avs:3 volt:810mv
3>core trim freq:2200, avs:4 volt:810mv
3>core trim freq:2200, avs:4 volt:810mv
3>core trim freq:2250, avs:5 volt:813mv
3>core trim freq:2250, avs:5 volt:815mv
3>core trim freq:2300, avs:6 volt:826mv
3>core trim freq:2300, avs:6 volt:827mv
3>core trim freq:2350, avs:7 volt:838mv
3>core trim freq:2350, avs:7 volt:840mv
3>core trim freq:2400, avs:8 volt:851mv
3>core trim freq:2400, avs:8 volt:853mv
3>core trim freq:2450, avs:9 volt:863mv
3>core trim freq:2450, avs:9 volt:865mv
3>core trim freq:2500, avs:10 volt:876mv
3>core trim freq:2500, avs:10 volt:878mv
3>core trim freq:2550, avs:11 volt:888mv
3>core trim freq:2550, avs:11 volt:891mv
3>core trim freq:2600, avs:12 volt:901mv
3>core trim freq:2600, avs:12 volt:903mv
3>core trim freq:2650, avs:13 volt:913mv
3>core trim freq:2650, avs:13 volt:916mv
3>core trim freq:2700, avs:14 volt:926mv
3>core trim freq:2700, avs:14 volt:929mv
3>core trim freq:2750, avs:15 volt:943mv
3>core trim freq:2750, avs:15 volt:946mv
3>core trim freq:2800, avs:16 volt:961mv
3>core trim freq:2800, avs:16 volt:964mv
3>core trim freq:2850, avs:17 volt:979mv
3>core trim freq:2850, avs:17 volt:982mv
3>core trim freq:2900, avs:18 volt:997mv
3>core trim freq:2900, avs:18 volt:1000mv
3>core trim freq:2950, avs:19 volt:1014mv
3>core trim freq:2950, avs:19 volt:1017mv
3>core trim freq:3000, avs:20 volt:1031mv
3>core trim freq:3000, avs:20 volt:1035mv
3>core trim freq:3050, avs:21 volt:1045mv
3>core trim freq:3050, avs:21 volt:1048mv
3>core trim freq:3100, avs:22 volt:1059mv
3>core trim freq:3100, avs:22 volt:1062mv
3>acg trim end
3>LDO disabled
3>[TracePoint] type[  0] cmd[  2] data[  3]
3>Interrupt 423 register OK
3>Interrupt 430 register OK
3>[TracePoint] type[  0] cmd[  2] data[  4]
3>
3>cpu 0 entering scheduler
3>[TracePoint] type[  0] cmd[  3] data[  1]
3>add your ipu app init here!
3>IpuInterfaceTaskStart Entry ...
3>ipu interface task wait parameters from uefi...
3>thermal soc task enabled
3>AP Last Time:[0.00.44.314]
3>ThermalDimmStart Entry ...
3>wait ddr init done...
3>power task start...
3>[TracePoint] type[  0] cmd[  3] data[  2]
3>ufs task wait parameters from uefi...
3>AmuTaskStart Entry ... 
3>amu task wait parameters from uefi...
3>ThermalSiwStart Entry ...
3>ThermalSiwTask idle...
3>DemtTaskStart Entry ...
3>[TracePoint] type[  0] cmd[  3] data[  3]
3>demt task wait parameters from uefi...
3>HiBoostTaskStart Entry ...
3>HiBoost task enabled
3>Waiting for UEFI parameters...
3>[TracePoint] type[  0] cmd[  3] data[  4]
3>[TracePoint] type[  0] cmd[  3] data[  5]
3>uefi parameters ready!
3>UFSProfile[0]
3>PowerPolicy[2] BenchMarkSelection[0]
3>ipu interface task wait ddr init done from uefi...
3>ufs task parameters from uefi ready
3>uncore domain[0] freq:2900
3>uncore domain[1] freq:2900
3>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
3>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
3>======sioe status======
3>thermal soc task restore underclocking_en=1
3>ppu alert temp div init done
3>TA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
3>TA_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
3>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
3>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
3>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
3>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
3>==========end==========
3>sioe init done
3>ufs task enabled
3>--> UFS profile[0]
3>UEFI parameters ready
3>UncoreMaxFreq Set to [2900 MHZ]
3>get TDP from efuse success, value = 357500mw
3>target power set to [357500]mw, brd:[357500]
3>demt task parameters from uefi ready
3>uefi ddr init finish!
3>ipu interface task wait uefi end done from uefi...
3>ddr init done, start thermal dimm task
3>======dimm status======
3>  chl[0] dimm0 2, dimm1 0
3>  chl[1] dimm0 2, dimm1 0
3>  chl[2] dimm0 2, dimm1 0
3>  chl[3] dimm0 2, dimm1 0
3>  chl[4] dimm0 2, dimm1 0
3>  chl[5] dimm0 2, dimm1 0
3>  chl[6] dimm0 2, dimm1 0
3>  chl[7] dimm0 2, dimm1 0
3>==========end==========
3>chl[0] registered, dimm mask = 0x1
3>chl[1] registered, dimm mask = 0x1
3>chl[2] registered, dimm mask = 0x1
3>chl[3] registered, dimm mask = 0x1
3>chl[4] registered, dimm mask = 0x1
3>chl[5] registered, dimm mask = 0x1
3>chl[6] registered, dimm mask = 0x1
3>chl[7] registered, dimm mask = 0x1
3>=====dimm temp params=====
3>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
3>  is_thermal_thro_en  : 1
3>  is_aref_rate_auto   : 1
3>===========end============
3>chl[0] max_temp 27'C, aref_rate 0x5 --> 0x4
3>chl[1] max_temp 27'C, aref_rate 0x5 --> 0x4
3>chl[2] max_temp 27'C, aref_rate 0x5 --> 0x4
3>chl[3] max_temp 27'C, aref_rate 0x5 --> 0x4
3>chl[4] max_temp 27'C, aref_rate 0x5 --> 0x4
3>chl[5] max_temp 27'C, aref_rate 0x5 --> 0x4
3>chl[6] max_temp 27'C, aref_rate 0x5 --> 0x4
3>chl[7] max_temp 27'C, aref_rate 0x5 --> 0x4
3>uefi end finish!
3>ipu interface task exit!
3>amu task parameters from uefi ready
3>amu task activated
3>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
[0.08.47.099]IpmiCmdReportPcieMMIO start
[0.09.03.740]IpmiCmdReportPcieMMIO end
pool addr          pool size    used size     free size    max free node size   used node num     free node num      UsageWaterLine
---------------    --------     -------       --------     --------------       -------------      ------------      ------------
0x840908c350       0x22880      0x189d8       0x9c38       0x9550               0xbf               0x3                0x19330        
core trim freq:2900, avs:18 volt:998mv
2>core trim freq:2900, avs:18 volt:1000mv
2>core trim freq:2950, avs:19 volt:1015mv
2>core trim freq:2950, avs:19 volt:1017mv
2>core trim freq:3000, avs:20 volt:1032mv
2>core trim freq:3000, avs:20 volt:1034mv
2>core trim freq:3050, avs:21 volt:1046mv
2>core trim freq:3050, avs:21 volt:1048mv
2>core trim freq:3100, avs:22 volt:1060mv
2>core trim freq:3100, avs:22 volt:1062mv
2>acg trim end
2>LDO disabled
2>[TracePoint] type[  0] cmd[  2] data[  3]
2>Interrupt 423 register OK
2>Interrupt 430 register OK
2>[TracePoint] type[  0] cmd[  2] data[  4]
2>
2>cpu 0 entering scheduler
2>[TracePoint] type[  0] cmd[  3] data[  1]
2>add your ipu app init here!
2>IpuInterfaceTaskStart Entry ...
2>ipu interface task wait parameters from uefi...
2>thermal soc task enabled
2>AP Last Time:[0.00.44.776]
2>ThermalDimmStart Entry ...
2>wait ddr init done...
2>power task start...
2>[TracePoint] type[  0] cmd[  3] data[  2]
2>ufs task wait parameters from uefi...
2>AmuTaskStart Entry ... 
2>amu task wait parameters from uefi...
2>ThermalSiwStart Entry ...
2>ThermalSiwTask idle...
2>DemtTaskStart Entry ...
2>[TracePoint] type[  0] cmd[  3] data[  3]
2>demt task wait parameters from uefi...
2>HiBoostTaskStart Entry ...
2>HiBoost task enabled
2>Waiting for UEFI parameters...
2>[TracePoint] type[  0] cmd[  3] data[  4]
2>[TracePoint] type[  0] cmd[  3] data[  5]
2>uefi parameters ready!
2>UFSProfile[0]
2>PowerPolicy[2] BenchMarkSelection[0]
2>ipu interface task wait ddr init done from uefi...
2>ufs task parameters from uefi ready
2>uncore domain[0] freq:2900
2>uncore domain[1] freq:2900
2>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
2>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
2>======sioe status======
2>thermal soc task restore underclocking_en=1
2>ppu alert temp div init done
2>TA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
2>TA_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
2>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
2>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
2>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
2>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
2>==========end==========
2>sioe init done
2>ufs task enabled
2>--> UFS profile[0]
2>UEFI parameters ready
2>UncoreMaxFreq Set to [2900 MHZ]
2>get TDP from efuse success, value = 357500mw
2>target power set to [357500]mw, brd:[357500]
2>demt task parameters from uefi ready
2>uefi ddr init finish!
2>ipu interface task wait uefi end done from uefi...
80] mv
3>Totem Uncore 3000MHZ -> Vol[994] mv
3>Core VF curve:
3>[ 400]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 450]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 500]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 550]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 600]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 650]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 700]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 750]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 800]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 850]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 900]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 950]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1000]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1050]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1100]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1150]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1200]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1250]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1300]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1350]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1400]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1450]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1500]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1550]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1600]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1650]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1700]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1750]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1800]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1850]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1900]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1950]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2000]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2050]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2100]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2150]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2200]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2250]MHZ -> Vol TA[ 813]mv TB[ 815]mv
3>[2300]MHZ -> Vol TA[ 826]mv TB[ 827]mv
3>[2350]MHZ -> Vol TA[ 838]mv TB[ 840]mv
3>[2400]MHZ -> Vol TA[ 851]mv TB[ 853]mv
3>[2450]MHZ -> Vol TA[ 863]mv TB[ 865]mv
3>[2500]MHZ -> Vol TA[ 876]mv TB[ 878]mv
3>[2550]MHZ -> Vol TA[ 888]mv TB[ 891]mv
3>[2600]MHZ -> Vol TA[ 901]mv TB[ 903]mv
3>[2650]MHZ -> Vol TA[ 913]mv TB[ 916]mv
3>[2700]MHZ -> Vol TA[ 926]mv TB[ 929]mv
3>[2750]MHZ -> Vol TA[ 943]mv TB[ 946]mv
3>[2800]MHZ -> Vol TA[ 961]mv TB[ 964]mv
3>[2850]MHZ -> Vol TA[ 979]mv TB[ 982]mv
3>[2900]MHZ -> Vol TA[ 997]mv TB[1000]mv
3>[2950]MHZ -> Vol TA[1014]mv TB[1017]mv
3>[3000]MHZ -> Vol TA[1031]mv TB[1035]mv
3>[3050]MHZ -> Vol TA[1045]mv TB[1048]mv
3>[3100]MHZ -> Vol TA[1059]mv TB[1062]mv
3>Uncore VF curve:
3>Uncore [   0]MHZ -> Vol [ 810]mv
3>Uncore [ 100]MHZ -> Vol [ 810]mv
3>Uncore [ 200]MHZ -> Vol [ 810]mv
3>Uncore [ 300]MHZ -> Vol [ 810]mv
3>Uncore [ 400]MHZ -> Vol [ 810]mv
3>Uncore [ 500]MHZ -> Vol [ 877]mv
3>Uncore [ 600]MHZ -> Vol [ 877]mv
3>Uncore [ 700]MHZ -> Vol [ 877]mv
3>Uncore [ 800]MHZ -> Vol [ 877]mv
3>Uncore [ 900]MHZ -> Vol [ 877]mv
3>Uncore [1000]MHZ -> Vol [ 877]mv
3>Uncore [1100]MHZ -> Vol [ 877]mv
3>Uncore [1200]MHZ -> Vol [ 877]mv
3>Uncore [1300]MHZ -> Vol [ 877]mv
3>Uncore [1400]MHZ -> Vol [ 877]mv
3>Uncore [1500]MHZ -> Vol [ 877]mv
3>Uncore [1600]MHZ -> Vol [ 877]mv
3>Uncore [1700]MHZ -> Vol [ 877]mv
3>Uncore [1800]MHZ -> Vol [ 877]mv
3>Uncore [1900]MHZ -> Vol [ 877]mv
3>Uncore [2000]MHZ -> Vol [ 877]mv
3>Uncore [2100]MHZ -> Vol [ 884]mv
3>Uncore [2200]MHZ -> Vol [ 891]mv
3>Uncore [2300]MHZ -> Vol [ 898]mv
3>Uncore [2400]MHZ -> Vol [ 905]mv
3>Uncore [2500]MHZ -> Vol [ 912]mv
3>Uncore [2600]MHZ -> Vol [ 929]mv
3>Uncore [2700]MHZ -> Vol [ 947]mv
3>Uncore [2800]MHZ -> Vol [ 963]mv
3>Uncore [2900]MHZ -> Vol [ 980]mv
3>Uncore [3000]MHZ -> Vol [ 994]mv
3>[TracePoint] type[  0] cmd[  1] data[  6]
3>[TracePoint] type[  0] cmd[  1] data[  7]
3>
********Hello Huawei LiteOS********

KpxxxxIPU Firmware Version : V32.75.0
LiteOS Kernel Version : 5.7.0
3>Run on ChipVersion[0] Node[3] Die[0]
3>build time : Apr 24 2026 18:00:00

3>**********************************
3>
main core booting up...
3>start set affinity
3>
mpidr = 0x810c0000
3>sram ecc state: 0x0, sram ecc cnt: 0x0
3>[TracePoint] type[  0] cmd[  2] data[  1]
3>[TracePoint] type[  0] cmd[  2] data[  2]
3>LRDXSD_LOCK_OFFSET = 0x0
3>LRDXSD_ERRIMSK_OFFSET = 0x0
3>LRDXSD_DBG_OTIMSK_OFFSET = 0x0
3>LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
3>LRDXSD_DBG_EN_OFFSET = 0x1
3>======tsensor params======
3>  is_trimmed       : 1
3>  underclocking_en : 1
3>===========end============
3>soc tsensor init done
3>========vrd info from cpld========
3>vrd_id | u64                | pmbus_en | avsbus_en | loop | pmbus_id | pmbus_addr | avs_sw | pmbus_sw | addr_9545 | domain_type | die_mask | reserved
3>  00   | 0x0001000100002017 | 0x1      | 0x1       | 0x1  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0100   | 0x0
3>  01   | 0x000300030000201b | 0x1      | 0x1       | 0x2  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x3         | 0x0300   | 0x0
3>  02   | 0x0000010500002b15 | 0x1      | 0x0       | 0x1  | 0x1      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0001   | 0x0
3>  03   | 0x0002000100002027 | 0x1      | 0x1       | 0x1  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0200   | 0x0
3>  04   | 0x000300020000202b | 0x1      | 0x1       | 0x2  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x2         | 0x0300   | 0x0
3>  05   | 0x0000020500002b25 | 0x1      | 0x0       | 0x1  | 0x2      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0002   | 0x0
3>  06   | 0x0003000400002b29 | 0x1      | 0x0       | 0x2  | 0x2      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x4         | 0x0300   | 0x0
3>================end===============
3>=============vrd info=============
3>power domain num: 7
3>power domain[00] id:0 | CORE_DVFS_TA       | PMBus NA | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
3>power domain[01] id:1 | DDR_VDD            | PMBus NA | cap:0x3 | rail:1 | addr:0x20 | def_volt: 765 mV | min_volt: 650 mV | max_volt: 850 mV
3>power domain[02] id:4 | IO_DVDD_NA         | PMBus NA | cap:0x1 | rail:0 | addr:0x2b | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
3>power domain[03] id:2 | CORE_DVFS_TB       | PMBus NB | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
3>power domain[04] id:3 | UNCORE_DVFS        | PMBus NB | cap:0x3 | rail:1 | addr:0x20 | def_volt: 980 mV | min_volt: 750 mV | max_volt:1100 mV
3>power domain[05] id:5 | IO_DVDD_NB         | PMBus NB | cap:0x1 | rail:0 | addr:0x2b | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
3>power domain[06] id:6 | DDR_VDDQ           | PMBus NB | cap:0x1 | rail:1 | addr:0x2b | def_volt:1100 mV | min_volt:1000 mV | max_volt:1200 mV
3>================end===============
3>pmbus[0] init done
3>pmbus[1] init done
3>power domain[0] CORE_DVFS_TA       | NA PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
3>power domain[1] DDR_VDD            | NA PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 765 mV | pmu:MP2882
3>power domain[4] IO_DVDD_NA         | NA PMBus        | rail:0 | addr:0x2b | def_volt: 800 mV | pmu:MP2882
3>power domain[2] CORE_DVFS_TB       | NB PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
3>power domain[3] UNCORE_DVFS        | NB PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 980 mV | pmu:MP2882
3>power domain[5] IO_DVDD_NB         | NB PMBus        | rail:0 | addr:0x2b | def_volt: 800 mV | pmu:MP2882
3>power domain[6] DDR_VDDQ           | NB PMBus        | rail:1 | addr:0x2b | def_volt:1100 mV | pmu:MP2882
3>power domain[0] CORE_DVFS_TA       is transferred to AVSBus mode
3>power domain[1] DDR_VDD            is transferred to AVSBus mode
3>power domain[2] CORE_DVFS_TB       is transferred to AVSBus mode
3>power domain[3] UNCORE_DVFS        is transferred to AVSBus mode
3>avsbus resync success
3>avsbus[0] init done
3>avsbus resync success
3>avsbus[1] init done
3>============volt boot============
3>power domain[0] volt = 1099 mV
3>power domain[1] volt =  765 mV
3>power domain[4] volt =  804 mV
3>power domain[2] volt = 1105 mV
3>power domain[3] volt = 1005 mV
3>power domain[5] volt =  802 mV
3>power domain[6] volt = 1103 mV
3>===============end===============
3>--w&h rd rail:0, 1099, CORE_DVFS_TA
3>--w&h rd rail:1, 765, CORE_DVFS_TA
3>power domain[0] set volt --> 1099 mV success
3>--w&h rd rail:0, 1105, CORE_DVFS_TB
3>--w&h rd rail:1, 1007, CORE_DVFS_TB
3>power domain[2] set volt --> 1105 mV success
3>power domain[3] set volt -->  982 mV success
3>power domain[1] set volt -->  763 mV success
3>power domain[4] set volt -->  802 mV success
3>power domain[5] set volt -->  798 mV success
3>============volt post============
3>power domain[0] volt = 1099 mV
3>power domain[1] volt =  763 mV
3>power domain[4] volt =  802 mV
3>power domain[2] volt = 1105 mV
3>power domain[3] volt =  982 mV
3>power domain[5] volt =  798 mV
3>power domain[6] volt = 1101 mV
3>===============end===============
3>Hboot1 Info RAW Dump: [0x01][0x00][0x00][0x14][0x01][0x00][0x01]
3>PowerSensorSupport[1], Cali[5120], Loss[0]
3>Power Sensor Calibration Value[5120]!
3>the power sensor : manu id = 2peak, die id = TPA626
3>power sensor[0] init success
3>die[0] its[0] init done
3>die[0] its[1] init done
3>die[0] its[2] init done
3>die[0] its[3] init done
3>die[0] its[4] init done
3>die[0] its[5] init done
3>die[0] its[6] init done
3>die[0] its[7] init done
3>die[0] its[8] init done
3>die[0] its[9] init done
3>die[1] its[0] init done
3>die[1] its[1] init done
3>die[1] its[2] init done
3>die[1] its[3] init done
3>die[1] its[4] init done
3>die[1] its[5] init done
3>die[1] its[6] init done
3>die[1] its[7] init done
3>die[1] its[8] init done
3>die[1] its[9] init done
3>Totem[0] Core Boot Vol [1099]mv
3>Totem[0] Core Current Vol [1100]mv
3>Totem[1] Core Boot Vol [1105]mv
3>Totem[1] Core Current Vol [1100]mv
3>NA 1620V190
3>NB 1620V190
3>GetCoreBaseFreq [2900000KHZ]
3>GetCoreTurboFreq [2900000KHZ]
3>GetCustomClusterNum [10]
3>Ipu ACG Training Done!
3>AP Last Time:[0.00.01.547]
3>wait UEFI pll init...
3>done
3>acg trim start
3>core trim freq:2000, avs:0 volt:810mv
3>core trim freq:2000, avs:0 volt:810mv
3>core trim freq:2050, avs:1 volt:810mv
3>core trim freq:2050, avs:1 volt:810mv
3>core trim freq:2100, avs:2 volt:810mv
3>core trim freq:2100, avs:2 volt:810mv
3>core trim freq:2150, avs:3 volt:810mv
3>core trim freq:2150, avs:3 volt:810mv
3>core trim freq:2200, avs:4 volt:810mv
3>core trim freq:2200, avs:4 volt:810mv
3>core trim freq:2250, avs:5 volt:813mv
3>core trim freq:2250, avs:5 volt:815mv
3>core trim freq:2300, avs:6 volt:826mv
3>core trim freq:2300, avs:6 volt:827mv
3>core trim freq:2350, avs:7 volt:838mv
3>core trim freq:2350, avs:7 volt:840mv
3>core trim freq:2400, avs:8 volt:851mv
3>core trim freq:2400, avs:8 volt:853mv
3>core trim freq:2450, avs:9 volt:863mv
3>core trim freq:2450, avs:9 volt:865mv
3>core trim freq:2500, avs:10 volt:876mv
3>core trim freq:2500, avs:10 volt:878mv
3>core trim freq:2550, avs:11 volt:888mv
3>core trim freq:2550, avs:11 volt:891mv
3>core trim freq:2600, avs:12 volt:901mv
3>core trim freq:2600, avs:12 volt:903mv
3>core trim freq:2650, avs:13 volt:913mv
3>core trim freq:2650, avs:13 volt:916mv
3>core trim freq:2700, avs:14 volt:926mv
3>core trim freq:2700, avs:14 volt:929mv
3>core trim freq:2750, avs:15 volt:943mv
3>core trim freq:2750, avs:15 volt:946mv
3>core trim freq:2800, avs:16 volt:961mv
3>core trim freq:2800, avs:16 volt:964mv
3>core trim freq:2850, avs:17 volt:979mv
3>core trim freq:2850, avs:17 volt:982mv
3>core trim freq:2900, avs:18 volt:997mv
3>core trim freq:2900, avs:18 volt:1000mv
3>core trim freq:2950, avs:19 volt:1014mv
3>core trim freq:2950, avs:19 volt:1017mv
3>core trim freq:3000, avs:20 volt:1031mv
3>core trim freq:3000, avs:20 volt:1035mv
3>core trim freq:3050, avs:21 volt:1045mv
3>core trim freq:3050, avs:21 volt:1048mv
3>core trim freq:3100, avs:22 volt:1059mv
3>core trim freq:3100, avs:22 volt:1062mv
3>acg trim end
3>LDO disabled
3>[TracePoint] type[  0] cmd[  2] data[  3]
3>Interrupt 423 register OK
3>Interrupt 430 register OK
3>[TracePoint] type[  0] cmd[  2] data[  4]
3>
3>cpu 0 entering scheduler
3>[TracePoint] type[  0] cmd[  3] data[  1]
3>add your ipu app init here!
3>IpuInterfaceTaskStart Entry ...
3>ipu interface task wait parameters from uefi...
3>thermal soc task enabled
3>AP Last Time:[0.00.44.737]
3>ThermalDimmStart Entry ...
3>wait ddr init done...
3>power task start...
3>[TracePoint] type[  0] cmd[  3] data[  2]
3>ufs task wait parameters from uefi...
3>AmuTaskStart Entry ... 
3>amu task wait parameters from uefi...
3>ThermalSiwStart Entry ...
3>ThermalSiwTask idle...
3>DemtTaskStart Entry ...
3>[TracePoint] type[  0] cmd[  3] data[  3]
3>demt task wait parameters from uefi...
3>HiBoostTaskStart Entry ...
3>HiBoost task enabled
3>Waiting for UEFI parameters...
3>[TracePoint] type[  0] cmd[  3] data[  4]
3>[TracePoint] type[  0] cmd[  3] data[  5]
3>uefi parameters ready!
3>UFSProfile[0]
3>PowerPolicy[2] BenchMarkSelection[0]
3>ipu interface task wait ddr init done from uefi...
3>ufs task parameters from uefi ready
3>uncore domain[0] freq:2900
3>uncore domain[1] freq:2900
3>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
3>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
3>======sioe status======
3>thermal soc task restore underclocking_en=1
3>ppu alert temp div init done
3>TA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
3>TA_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
3>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
3>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
3>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
3>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
3>==========end==========
3>sioe init done
3>ufs task enabled
3>--> UFS profile[0]
3>UEFI parameters ready
3>UncoreMaxFreq Set to [2900 MHZ]
3>get TDP from efuse success, value = 357500mw
3>target power set to [357500]mw, brd:[357500]
3>demt task parameters from uefi ready
3>uefi ddr init finish!
3>ipu interface task wait uefi end done from uefi...
0>ddr init done, start thermal dimm task
0>======dimm status======
0>  chl[0] dimm0 2, dimm1 0
0>  chl[1] dimm0 2, dimm1 0
0>  chl[2] dimm0 2, dimm1 0
0>  chl[3] dimm0 2, dimm1 0
0>  chl[4] dimm0 2, dimm1 0
0>  chl[5] dimm0 2, dimm1 0
0>  chl[6] dimm0 2, dimm1 0
0>  chl[7] dimm0 2, dimm1 0
0>==========end==========
0>chl[0] registered, dimm mask = 0x1
0>chl[1] registered, dimm mask = 0x1
0>chl[2] registered, dimm mask = 0x1
0>chl[3] registered, dimm mask = 0x1
0>chl[4] registered, dimm mask = 0x1
0>chl[5] registered, dimm mask = 0x1
0>chl[6] registered, dimm mask = 0x1
0>chl[7] registered, dimm mask = 0x1
0>=====dimm temp params=====
0>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
0>  is_thermal_thro_en  : 1
0>  is_aref_rate_auto   : 1
0>===========end============
1>ddr init done, start thermal dimm task
1>======dimm status======
1>  chl[0] dimm0 2, dimm1 0
1>  chl[1] dimm0 2, dimm1 0
1>  chl[2] dimm0 2, dimm1 0
1>  chl[3] dimm0 2, dimm1 0
1>  chl[4] dimm0 2, dimm1 0
1>  chl[5] dimm0 2, dimm1 0
1>  chl[6] dimm0 2, dimm1 0
1>  chl[7] dimm0 2, dimm1 0
1>==========end==========
1>chl[0] registered, dimm mask = 0x1
1>chl[1] registered, dimm mask = 0x1
1>chl[2] registered, dimm mask = 0x1
1>chl[3] registered, dimm mask = 0x1
1>chl[4] registered, dimm mask = 0x1
1>chl[5] registered, dimm mask = 0x1
1>chl[6] registered, dimm mask = 0x1
1>chl[7] registered, dimm mask = 0x1
1>=====dimm temp params=====
1>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
1>  is_thermal_thro_en  : 1
1>  is_aref_rate_auto   : 1
1>===========end============
2>ddr init done, start thermal dimm task
2>======dimm status======
2>  chl[0] dimm0 2, dimm1 0
2>  chl[1] dimm0 2, dimm1 0
2>  chl[2] dimm0 2, dimm1 0
2>  chl[3] dimm0 2, dimm1 0
2>  chl[4] dimm0 2, dimm1 0
2>  chl[5] dimm0 2, dimm1 0
2>  chl[6] dimm0 2, dimm1 0
2>  chl[7] dimm0 2, dimm1 0
2>==========end==========
2>chl[0] registered, dimm mask = 0x1
2>chl[1] registered, dimm mask = 0x1
2>chl[2] registered, dimm mask = 0x1
2>chl[3] registered, dimm mask = 0x1
2>chl[4] registered, dimm mask = 0x1
2>chl[5] registered, dimm mask = 0x1
2>chl[6] registered, dimm mask = 0x1
2>chl[7] registered, dimm mask = 0x1
2>=====dimm temp params=====
2>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
2>  is_thermal_thro_en  : 1
2>  is_aref_rate_auto   : 1
2>===========end============
3>ddr init done, start thermal dimm task
3>======dimm status======
3>  chl[0] dimm0 2, dimm1 0
3>  chl[1] dimm0 2, dimm1 0
3>  chl[2] dimm0 2, dimm1 0
3>  chl[3] dimm0 2, dimm1 0
3>  chl[4] dimm0 2, dimm1 0
3>  chl[5] dimm0 2, dimm1 0
3>  chl[6] dimm0 2, dimm1 0
3>  chl[7] dimm0 2, dimm1 0
3>==========end==========
3>chl[0] registered, dimm mask = 0x1
3>chl[1] registered, dimm mask = 0x1
3>chl[2] registered, dimm mask = 0x1
3>chl[3] registered, dimm mask = 0x1
3>chl[4] registered, dimm mask = 0x1
3>chl[5] registered, dimm mask = 0x1
3>chl[6] registered, dimm mask = 0x1
3>chl[7] registered, dimm mask = 0x1
3>=====dimm temp params=====
3>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
3>  is_thermal_thro_en  : 1
3>  is_aref_rate_auto   : 1
3>===========end============
[0.01.23.462]DDR Rreserved for IMU: len = 3e00000
[LOG]head = 0x0, tail = 0x4f35, logSize = 0x4f35
copy registry.json file success
Set component all release version to sram end.
ipcMsgSend success
HsmLogInit Ret 1, Len 4, val 0x32022a06
[0.01.23.507]starting ras Init
nodeId = 0, dieId = 0, isSasExist = 0.
nodeId = 0, dieId = 2, isSasExist = 0.
nodeId = 1, dieId = 0, isSasExist = 0.
nodeId = 1, dieId = 2, isSasExist = 0.
nodeId = 2, dieId = 0, isSasExist = 0.
nodeId = 2, dieId = 2, isSasExist = 0.
nodeId = 3, dieId = 0, isSasExist = 0.
nodeId = 3, dieId = 2, isSasExist = 0.
Mce Table head exist!
RasIntRegister init 452 
RasIntRegister init 453 
RasIntRegister init 64 
RasIntRegister init 65 
RasIntRegister init 465 
RasIntRegister init 466 
RasIntRegister init 86 
RasIntRegister init 87 
RasIntRegister init 478 
RasIntRegister init 479 
RasIntRegister init 108 
RasIntRegister init 109 
RasIntRegister init 491 
RasIntRegister init 492 
RasIntRegister init 130 
RasIntRegister init 131 
RasIntRegister init 504 
RasIntRegister init 505 
RasIntRegister init 152 
RasIntRegister init 153 
RasIntRegister init 517 
RasIntRegister init 518 
RasIntRegister init 174 
RasIntRegister init 175 
RasIntRegister init 530 
RasIntRegister init 531 
RasIntRegister init 196 
RasIntRegister init 197 
RasIntRegister init 543 
RasIntRegister init 544 
RasIntRegister init 218 
RasIntRegister init 219 
RasIntRegister init 76 
RasIntRegister init 98 
RasIntRegister init 120 
RasIntRegister init 142 
RasIntRegister init 164 
RasIntRegister init 186 
RasIntRegister init 208 
RasIntRegister init 230 
[0.01.23.629]starting ras end
3>chl[0] max_temp 27'C, aref_rate 0x5 --> 0x4
3>chl[1] max_temp 27'C, aref_rate 0x5 --> 0x4
3>chl[2] max_temp 27'C, aref_rate 0x5 --> 0x4
3>chl[3] max_temp 27'C, aref_rate 0x5 --> 0x4
3>chl[4] max_temp 27'C, aref_rate 0x5 --> 0x4
3>chl[5] max_temp 27'C, aref_rate 0x5 --> 0x4
3>chl[6] max_temp 27'C, aref_rate 0x5 --> 0x4
3>chl[7] max_temp 27'C, aref_rate 0x5 --> 0x4
1>chl[0] max_temp 26'C, aref_rate 0x5 --> 0x4
1>chl[1] max_temp 26'C, aref_rate 0x5 --> 0x4
1>chl[2] max_temp 26'C, aref_rate 0x5 --> 0x4
1>chl[3] max_temp 26'C, aref_rate 0x5 --> 0x4
1>chl[4] max_temp 26'C, aref_rate 0x5 --> 0x4
1>chl[5] max_temp 26'C, aref_rate 0x5 --> 0x4
1>chl[6] max_temp 26'C, aref_rate 0x5 --> 0x4
1>chl[7] max_temp 26'C, aref_rate 0x5 --> 0x4
2>chl[0] max_temp 28'C, aref_rate 0x5 --> 0x4
2>chl[1] max_temp 28'C, aref_rate 0x5 --> 0x4
2>chl[2] max_temp 28'C, aref_rate 0x5 --> 0x4
2>chl[3] max_temp 28'C, aref_rate 0x5 --> 0x4
2>chl[4] max_temp 28'C, aref_rate 0x5 --> 0x4
2>chl[5] max_temp 28'C, aref_rate 0x5 --> 0x4
2>chl[6] max_temp 28'C, aref_rate 0x5 --> 0x4
2>chl[7] max_temp 28'C, aref_rate 0x5 --> 0x4
[ERR]ipc result error, result 0x28010009
ipcMsgSend fail
Send tee measure to HSM respon:0
0>chl[0] max_temp 27'C, aref_rate 0x5 --> 0x4
0>chl[1] max_temp 27'C, aref_rate 0x5 --> 0x4
0>chl[2] max_temp 27'C, aref_rate 0x5 --> 0x4
0>chl[3] max_temp 27'C, aref_rate 0x5 --> 0x4
0>chl[4] max_temp 27'C, aref_rate 0x5 --> 0x4
0>chl[5] max_temp 27'C, aref_rate 0x5 --> 0x4
0>chl[6] max_temp 27'C, aref_rate 0x5 --> 0x4
0>chl[7] max_temp 27'C, aref_rate 0x5 --> 0x4
get mem silk data length: 192
0: skt = 0 logic = 2 phy = 0 
1: skt = 0 logic = 2 phy = 0 
2: skt = 0 logic = 7 phy = 1 
3: skt = 0 logic = 7 phy = 1 
4: skt = 0 logic = 0 phy = 2 
5: skt = 0 logic = 0 phy = 2 
6: skt = 0 logic = 5 phy = 3 
7: skt = 0 logic = 5 phy = 3 
8: skt = 1 logic = 2 phy = 0 
9: skt = 1 logic = 2 phy = 0 
10: skt = 1 logic = 7 phy = 1 
11: skt = 1 logic = 7 phy = 1 
12: skt = 1 logic = 0 phy = 2 
13: skt = 1 logic = 0 phy = 2 
14: skt = 1 logic = 5 phy = 3 
15: skt = 1 logic = 5 phy = 3 
16: skt = 0 logic = 3 phy = 4 
17: skt = 0 logic = 3 phy = 4 
18: skt = 0 logic = 6 phy = 5 
19: skt = 0 logic = 6 phy = 5 
20: skt = 0 logic = 1 phy = 6 
21: skt = 1 logic = 1 phy = 6 
22: skt = 1 logic = 1 phy = 6 
23: skt = 1 logic = 4 phy = 7 
24: skt = 1 logic = 4 phy = 7 
25: skt = 1 logic = 6 phy = 5 
26: skt = 1 logic = 6 phy = 5 
27: skt = 1 logic = 3 phy = 4 
28: skt = 0 logic = 1 phy = 6 
29: skt = 0 logic = 4 phy = 7 
30: skt = 0 logic = 4 phy = 7 
31: skt = 1 logic = 3 phy = 4 
32: skt = 2 logic = 2 phy = 0 
33: skt = 2 logic = 2 phy = 0 
34: skt = 2 logic = 7 phy = 1 
35: skt = 2 logic = 7 phy = 1 
36: skt = 2 logic = 0 phy = 2 
37: skt = 3 logic = 4 phy = 7 
38: skt = 3 logic = 1 phy = 6 
39: skt = 3 logic = 4 phy = 7 
40: skt = 3 logic = 1 phy = 6 
41: skt = 3 logic = 6 phy = 5 
42: skt = 3 logic = 6 phy = 5 
43: skt = 3 logic = 3 phy = 4 
44: skt = 3 logic = 3 phy = 4 
45: skt = 2 logic = 4 phy = 7 
46: skt = 2 logic = 4 phy = 7 
47: skt = 2 logic = 1 phy = 6 
48: skt = 2 logic = 1 phy = 6 
49: skt = 2 logic = 6 phy = 5 
50: skt = 2 logic = 6 phy = 5 
51: skt = 2 logic = 3 phy = 4 
52: skt = 2 logic = 3 phy = 4 
53: skt = 3 logic = 5 phy = 3 
54: skt = 3 logic = 5 phy = 3 
55: skt = 3 logic = 0 phy = 2 
56: skt = 3 logic = 0 phy = 2 
57: skt = 3 logic = 7 phy = 1 
58: skt = 3 logic = 7 phy = 1 
59: skt = 3 logic = 2 phy = 0 
60: skt = 3 logic = 2 phy = 0 
61: skt = 2 logic = 5 phy = 3 
62: skt = 2 logic = 5 phy = 3 
63: skt = 2 logic = 0 phy = 2 
[0.02.07.366]TF Heartbeat Start
[0.02.11.616]PCIE INIT DONE.
g_mctpQueueCount(48) > tabCnt(42)
slotNum = 0x8
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[0] port:20  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[1] port:22  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[2] port:20  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[3] port:22  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[4] port:20  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[5] port:22  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[6] port:24  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[7] port:26  pcieSlotCtrl.data (after)0x14801c0.

Interrupt 454 register OK
Interrupt 467 register OK
Interrupt 480 register OK
Interrupt 493 register OK
Interrupt 506 register OK
Interrupt 519 register OK
Interrupt 532 register OK
Interrupt 545 register OK
data = 0x0
pmt Init done

Add ep: bdf=a200 eid=9 epCnt=1 eid_alloc=a
Add ep: bdf=c400 eid=a epCnt=1 eid_alloc=b
Add ep: bdf=d000 eid=b epCnt=1 eid_alloc=c
[0.02.11.848]slot[0] port:20 begin to power OFF.
[0.02.11.849]slot[1] port:22 begin to power OFF.
[0.02.11.852]slot[2] port:20 begin to power OFF.
[0.02.11.856]slot[3] port:22 begin to power OFF.
[0.02.11.860]slot[4] port:20 begin to power ON.
[0.02.11.865]slot[5] port:22 begin to power ON.
[0.02.11.869]slot[6] port:24 begin to power ON.
[0.02.11.873]slot[7] port:26 begin to power ON.
Add ep: bdf=300 eid=c epCnt=1 eid_alloc=d
mctp task ok.
[0.03.56.607]BIOS POST END.
Create SetReportPcieMmioToBmc ok.
Start SetReportPcieMmioToBmc ok.
0>uefi end finish!
0>ipu interface task exit!
0>amu task parameters from uefi ready
1>uefi end finish!
1>ipu interface task exit!
1>amu task parameters from uefi ready
2>uefi end finish!
2>ipu interface task exit!
3>uefi end finish!
3>ipu interface task exit!
3>amu task parameters from uefi ready
2>amu task parameters from uefi ready
Enter current value process
0>amu task activated
0>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
1>amu task activated
1>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
2>amu task activated
2>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
3>amu task activated
3>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
[0.08.56.606]IpmiCmdReportPcieMMIO start
[0.09.13.255]IpmiCmdReportPcieMMIO end
pool addr          pool size    used size     free size    max free node size   used node num     free node num      UsageWaterLine
---------------    --------     -------       --------     --------------       -------------      ------------      ------------
0x840908c350       0x22880      0x189d8       0x9c38       0x9550               0xbf               0x3                0x19330        

********Hello Huawei LiteOS********

KpxxxxIMU Firmware Version : V32.75.0
LiteOS Kernel Version : 5.7.0
Run on ChipVersion[0] Node[0] Die[2]
build time : Apr 24 2026 18:00:00

**********************************

main core booting up...
start set affinity

mpidr = 0x81020000
sram ecc state: 0x0, sram ecc cnt: 0x0
[0.00.00.033]node 0 begins init all serdes.
BoardInfo->NodeNum 4.
BoardInfo->NodeId 0.
BoardInfo->InfoVersion 5.
BoardInfo->NASerdesSceneMode 3.
BoardInfo->NBSerdesSceneMode 3.
BoardInfo->HccsTopologyType 12.
BoardInfo->BoardId 0.
ChipVersionIsPro: 0.
BoardInfo Node 0, SerdesUseMode: 1 1 12 4 4 4 4  1 1 1 4 4 4 4 
BoardInfo Node 1, SerdesUseMode: 12 13 12 4 4 4 4  1 1 12 4 4 4 4 
BoardInfo Node 2, SerdesUseMode: 1 1 1 4 4 4 4  1 1 1 4 4 4 4 
BoardInfo Node 3, SerdesUseMode: 1 1 1 4 4 4 4  1 1 1 4 4 4 4 
BoardInfo Node 0, SerdesRxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 1, SerdesRxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 2, SerdesRxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 3, SerdesRxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 0, SerdesTxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 1, SerdesTxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 2, SerdesTxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 3, SerdesTxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
serdessdk version: 2.0_5.0_20241203_imu
node_id 0, die 0, ind 0, usemode 1 begin serdes-init.
node_id 0, die 0, ind 1, usemode 1 begin serdes-init.
node_id 0, die 0, ind 2, usemode 12 begin serdes-init.
chip_id 0, die 0, ind 2, usemode 12 don't support, power down macro!
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
node_id 0, die 2, ind 0, usemode 1 begin serdes-init.
node_id 0, die 2, ind 1, usemode 1 begin serdes-init.
chip serdes init status:0x0.
[0.00.00.455]node 0 ends init all serdes.
link[0] freq_type:1 | peer_chip_type:2 | peer_node_id:0 | peer_link_id:0
link[1] freq_type:1 | peer_chip_type:2 | peer_node_id:0 | peer_link_id:0
link[2] freq_type:1 | peer_chip_type:2 | peer_node_id:0 | peer_link_id:0
link[3] freq_type:1 | peer_chip_type:2 | peer_node_id:0 | peer_link_id:0
link[4] freq_type:1 | peer_chip_type:2 | peer_node_id:0 | peer_link_id:0
link[5] freq_type:1 | peer_chip_type:1 | peer_node_id:1 | peer_link_id:4
link[6] freq_type:1 | peer_chip_type:1 | peer_node_id:2 | peer_link_id:7
link[7] freq_type:1 | peer_chip_type:1 | peer_node_id:3 | peer_link_id:5
register hccs done
nodeId 0, dieId 0, linkId 0, FFE info: fir_pre1 -5, fir_main 58, fir_post1 0
node_id 0, die 0, ind 4, usemode 4 begin serdes-init.
nodeId 0, dieId 0, linkId 1, FFE info: fir_pre1 -5, fir_main 58, fir_post1 0
node_id 0, die 0, ind 3, usemode 4 begin serdes-init.
nodeId 0, dieId 0, linkId 2, FFE info: fir_pre1 -5, fir_main 58, fir_post1 0
node_id 0, die 0, ind 5, usemode 4 begin serdes-init.
nodeId 0, dieId 0, linkId 3, FFE info: fir_pre1 -5, fir_main 58, fir_post1 0
node_id 0, die 0, ind 6, usemode 4 begin serdes-init.
nodeId 0, dieId 1, linkId 0, FFE info: fir_pre1 -5, fir_main 58, fir_post1 0
node_id 0, die 2, ind 4, usemode 4 begin serdes-init.
nodeId 0, dieId 1, linkId 1, FFE info: fir_pre1 -5, fir_main 58, fir_post1 0
node_id 0, die 2, ind 3, usemode 4 begin serdes-init.
nodeId 0, dieId 1, linkId 2, FFE info: fir_pre1 -6, fir_main 45, fir_post1 12
node_id 0, die 2, ind 5, usemode 4 begin serdes-init.
nodeId 0, dieId 1, linkId 3, FFE info: fir_pre1 -6, fir_main 45, fir_post1 12
node_id 0, die 2, ind 6, usemode 4 begin serdes-init.
hccs init start...
pa ring link down success
reset pa success
link[0] pcs init success
link[1] pcs init success
link[2] pcs init success
link[3] pcs init success
link[4] pcs init success
link[5] pcs init success
link[6] pcs init success
link[7] pcs init success
release reset pa success
link[0] macro adapt done (lane_mask=0xff) (0ms)
link[1] macro adapt done (lane_mask=0xff) (0ms)
link[2] macro adapt done (lane_mask=0xff) (0ms)
link[3] macro adapt done (lane_mask=0xff) (0ms)
link[4] macro adapt done (lane_mask=0xff) (0ms)
link[5] macro adapt done (lane_mask=0xff) (0ms)
link[6] macro adapt done (lane_mask=0xff) (0ms)
link[7] macro adapt done (lane_mask=0xff) (0ms)
link[5] pcs training success (10ms)
link[6] pcs training success (10ms)
link[7] pcs training success (10ms)
link[5] training success (20ms)
link[6] training success (20ms)
link[7] training success (20ms)
link[1] pcs training success (4760ms)
link[1] training success (4770ms)
link[0] pcs training success (5250ms)
link[0] training success (5260ms)
link[4] pcs training success (5270ms)
link[4] training success (5280ms)
link[3] pcs training success (5710ms)
link[3] training success (5720ms)
link[2] pcs training success (5730ms)
link[2] training success (5740ms)
link[0]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
BWAY_PCS_ST_PCS_LINK_FSM_RECORD = 0x1248
HLLC_ST_FSM_1_REG = 0x3
link[1]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
BWAY_PCS_ST_PCS_LINK_FSM_RECORD = 0x1248
HLLC_ST_FSM_1_REG = 0x3
link[2]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
BWAY_PCS_ST_PCS_LINK_FSM_RECORD = 0x1248
HLLC_ST_FSM_1_REG = 0x3
link[3]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
BWAY_PCS_ST_PCS_LINK_FSM_RECORD = 0x1248
HLLC_ST_FSM_1_REG = 0x3
link[4]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
BWAY_PCS_ST_PCS_LINK_FSM_RECORD = 0x1248
HLLC_ST_FSM_1_REG = 0x3
link[5]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
BWAY_PCS_ST_PCS_LINK_FSM_RECORD = 0x1248
HLLC_ST_FSM_1_REG = 0x3
link[6]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
BWAY_PCS_ST_PCS_LINK_FSM_RECORD = 0x1248
HLLC_ST_FSM_1_REG = 0x3
link[7]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
BWAY_PCS_ST_PCS_LINK_FSM_RECORD = 0x1248
HLLC_ST_FSM_1_REG = 0x3
link training success
pa[0] linkEn = 0xf
pa[0] allNodeLink0 = 0x0
pa[0] allNodeLink1 = 0xf000f
pa[0] connected with sw node
pa[1] linkEn = 0xf
pa[1] allNodeLink0 = 0x8420
pa[1] allNodeLink1 = 0x10001
pa[1] connected with sw node
pa init success
COM_PAID_INTLV_REG = 0xe
paid decode init success
pa[0] PA_PM_BASE_INFO = 0x0
pa[0] PA_PM_MAP_LINK_NUM = 0x1111
pa[1] PA_PM_BASE_INFO = 0xee0842
pa[1] PA_PM_MAP_LINK_NUM = 0x2811
hccs performace config success
pa ring link up success
hccs init done
hccs access test start
node[0] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[2] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[3] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[1] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[1] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
node[2] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
node[3] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
hccs access test success
======hccs status======
  node[0] mask: expected = 0xff, link up = 0xff, width reduction = 0x0, link down = 0x0
  node[1] mask: expected = 0xff, link up = 0xff, width reduction = 0x0, link down = 0x0
  node[2] mask: expected = 0xff, link up = 0xff, width reduction = 0x0, link down = 0x0
  node[3] mask: expected = 0xff, link up = 0xff, width reduction = 0x0, link down = 0x0
==========end==========
report hccs status success
node[0] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
LRDXSD_LOCK_OFFSET = 0x0
LRDXSD_ERRIMSK_OFFSET = 0x0
LRDXSD_DBG_OTIMSK_OFFSET = 0x0
LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
LRDXSD_DBG_EN_OFFSET = 0x1
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
ID[0x1967c8]!
[ERR]Don't support the flash, CS[0] ID[0x1967c8]!!
ID[0xffffff]!
[ERR]Don't support the flash, CS[1] ID[0xffffff]!!
[ERR]Warnning, Select Default flash 
sfdp detect, try to get dummy data from hboot1 first.
ID[0x1967c8]!
flash 0 support sfdp.
Interrupt 423 register OK
Interrupt 425 register OK
Interrupt 427 register OK
Interrupt 429 register OK
Interrupt 430 register OK
Interrupt 431 register OK
Interrupt 436 register OK

cpu 0 entering scheduler
[IMU] Watchdog Initialization done!
ScmiTaskEntry start.
Interrupt 456 register OK
Interrupt 469 register OK
Interrupt 482 register OK
Interrupt 495 register OK
Interrupt 508 register OK
Interrupt 521 register OK
Interrupt 534 register OK
Interrupt 547 register OK
starting Fpc Isolation Task end
starting fdm Err Info Task end
starting Roce recovery Task end
starting Ce_Storm Contrl Task end
starting Ras_Data_Update Task end
Interrupt 459 register OK
Interrupt 472 register OK
Interrupt 485 register OK
Interrupt 498 register OK
Interrupt 511 register OK
Interrupt 524 register OK
Interrupt 537 register OK
Interrupt 550 register OK
[0.00.46.743]Real time now 2026.10.24 19:09:02
NIC CARD[0][0]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[0][1]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[1][0]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[1][1]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[2][0]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[2][1]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[3][0]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[3][1]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
Init heart-beat-task end
pool addr          pool size    used size     free size    max free node size   used node num     free node num      UsageWaterLine
---------------    --------     -------       --------     --------------       -------------      ------------      ------------
0x840908c350       0x22880      0x190c0       0x9550       0x9550               0x5e               0x1                0x19330        
Get Setup Config.
Node 0, Die 0 ImpState is 0 skip exec.
Node 0, Die 2 ImpState is 0 skip exec.
Node 1, Die 0 ImpState is 0 skip exec.
Node 1, Die 2 ImpState is 0 skip exec.
Node 2, Die 0 ImpState is 0 skip exec.
Node 2, Die 2 ImpState is 0 skip exec.
Node 3, Die 0 ImpState is 0 skip exec.
Node 3, Die 2 ImpState is 0 skip exec.
pwr cap[0]: 0, 63
pwr cap[1]: f, 27
pwr cap[2]: 1, 0
[0.01.21.649]DDR Rreserved for IMU: len = 3e00000
[LOG]head = 0x0, tail = 0x30d0, logSize = 0x30d0
copy registry.json file success
Set component all release version to sram end.
ipcMsgSend success
HsmLogInit Ret 1, Len 4, val 0x32022a06
[0.01.21.691]starting ras Init
nodeId = 0, dieId = 0, isSasExist = 0.
nodeId = 0, dieId = 2, isSasExist = 0.
nodeId = 1, dieId = 0, isSasExist = 0.
nodeId = 1, dieId = 2, isSasExist = 0.
nodeId = 2, dieId = 0, isSasExist = 0.
nodeId = 2, dieId = 2, isSasExist = 0.
nodeId = 3, dieId = 0, isSasExist = 0.
nodeId = 3, dieId = 2, isSasExist = 0.
Mce Table head exist!
RasIntRegister init 452 
RasIntRegister init 453 
RasIntRegister init 64 
RasIntRegister init 65 
RasIntRegister init 465 
RasIntRegister init 466 
RasIntRegister init 86 
RasIntRegister init 87 
RasIntRegister init 478 
RasIntRegister init 479 
RasIntRegister init 108 
RasIntRegister init 109 
RasIntRegister init 491 
RasIntRegister init 492 
RasIntRegister init 130 
RasIntRegister init 131 
RasIntRegister init 504 
RasIntRegister init 505 
RasIntRegister init 152 
RasIntRegister init 153 
RasIntRegister init 517 
RasIntRegister init 518 
RasIntRegister init 174 
RasIntRegister init 175 
RasIntRegister init 530 
RasIntRegister init 531 
RasIntRegister init 196 
RasIntRegister init 197 
RasIntRegister init 543 
RasIntRegister init 544 
RasIntRegister init 218 
RasIntRegister init 219 
RasIntRegister init 76 
RasIntRegister init 98 
RasIntRegister init 120 
RasIntRegister init 142 
RasIntRegister init 164 
RasIntRegister init 186 
RasIntRegister init 208 
RasIntRegister init 230 
[0.01.21.813]starting ras end
[ERR]ipc result error, result 0x28010009
ipcMsgSend fail
Send tee measure to HSM respon:0
get mem silk data length: 192
0: skt = 0 logic = 2 phy = 0 
1: skt = 0 logic = 2 phy = 0 
2: skt = 0 logic = 7 phy = 1 
3: skt = 0 logic = 7 phy = 1 
4: skt = 0 logic = 0 phy = 2 
5: skt = 0 logic = 0 phy = 2 
6: skt = 0 logic = 5 phy = 3 
7: skt = 0 logic = 5 phy = 3 
8: skt = 1 logic = 2 phy = 0 
9: skt = 1 logic = 2 phy = 0 
10: skt = 1 logic = 7 phy = 1 
11: skt = 1 logic = 7 phy = 1 
12: skt = 1 logic = 0 phy = 2 
13: skt = 1 logic = 0 phy = 2 
14: skt = 1 logic = 5 phy = 3 
15: skt = 1 logic = 5 phy = 3 
16: skt = 0 logic = 3 phy = 4 
17: skt = 0 logic = 3 phy = 4 
18: skt = 0 logic = 6 phy = 5 
19: skt = 0 logic = 6 phy = 5 
20: skt = 0 logic = 1 phy = 6 
21: skt = 1 logic = 1 phy = 6 
22: skt = 1 logic = 1 phy = 6 
23: skt = 1 logic = 4 phy = 7 
24: skt = 1 logic = 4 phy = 7 
25: skt = 1 logic = 6 phy = 5 
26: skt = 1 logic = 6 phy = 5 
27: skt = 1 logic = 3 phy = 4 
28: skt = 0 logic = 1 phy = 6 
29: skt = 0 logic = 4 phy = 7 
30: skt = 0 logic = 4 phy = 7 
31: skt = 1 logic = 3 phy = 4 
32: skt = 2 logic = 2 phy = 0 
33: skt = 2 logic = 2 phy = 0 
34: skt = 2 logic = 7 phy = 1 
35: skt = 2 logic = 7 phy = 1 
36: skt = 2 logic = 0 phy = 2 
37: skt = 3 logic = 4 phy = 7 
38: skt = 3 logic = 1 phy = 6 
39: skt = 3 logic = 4 phy = 7 
40: skt = 3 logic = 1 phy = 6 
41: skt = 3 logic = 6 phy = 5 
42: skt = 3 logic = 6 phy = 5 
43: skt = 3 logic = 3 phy = 4 
44: skt = 3 logic = 3 phy = 4 
45: skt = 2 logic = 4 phy = 7 
46: skt = 2 logic = 4 phy = 7 
47: skt = 2 logic = 1 phy = 6 
48: skt = 2 logic = 1 phy = 6 
49: skt = 2 logic = 6 phy = 5 
50: skt = 2 logic = 6 phy = 5 
51: skt = 2 logic = 3 phy = 4 
52: skt = 2 logic = 3 phy = 4 
53: skt = 3 logic = 5 phy = 3 
54: skt = 3 logic = 5 phy = 3 
55: skt = 3 logic = 0 phy = 2 
56: skt = 3 logic = 0 phy = 2 
57: skt = 3 logic = 7 phy = 1 
58: skt = 3 logic = 7 phy = 1 
59: skt = 3 logic = 2 phy = 0 
60: skt = 3 logic = 2 phy = 0 
61: skt = 2 logic = 5 phy = 3 
62: skt = 2 logic = 5 phy = 3 
63: skt = 2 logic = 0 phy = 2 
[0.02.05.743]TF Heartbeat Start
[0.02.09.993]PCIE INIT DONE.
g_mctpQueueCount(48) > tabCnt(42)
slotNum = 0x8
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[0] port:20  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[1] port:22  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[2] port:20  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[3] port:22  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[4] port:20  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[5] port:22  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[6] port:24  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[7] port:26  pcieSlotCtrl.data (after)0x14801c0.

Interrupt 454 register OK
Interrupt 467 register OK
Interrupt 480 register OK
Interrupt 493 register OK
Interrupt 506 register OK
Interrupt 519 register OK
Interrupt 532 register OK
Interrupt 545 register OK
data = 0x0
pmt Init done

Add ep: bdf=a200 eid=9 epCnt=1 eid_alloc=a
Add ep: bdf=c400 eid=a epCnt=1 eid_alloc=b
Add ep: bdf=d000 eid=b epCnt=1 eid_alloc=c
Add ep: bdf=300 eid=c epCnt=1 eid_alloc=d
[0.02.10.253]slot[0] port:20 begin to power OFF.
[0.02.10.254]slot[1] port:22 begin to power OFF.
[0.02.10.257]slot[2] port:20 begin to power OFF.
[0.02.10.261]slot[3] port:22 begin to power OFF.
[0.02.10.265]slot[4] port:20 begin to power ON.
[0.02.10.270]slot[5] port:22 begin to power ON.
[0.02.10.274]slot[6] port:24 begin to power ON.
[0.02.10.278]slot[7] port:26 begin to power ON.
mctp task ok.
[0.03.51.232]BIOS POST END.
Create SetReportPcieMmioToBmc ok.
Start SetReportPcieMmioToBmc ok.
Enter current value process
TB[ 810]mv
0>[1950]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[2000]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[2050]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[2100]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[2150]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[2200]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[2250]MHZ -> Vol TA[ 812]mv TB[ 816]mv
0>[2300]MHZ -> Vol TA[ 825]mv TB[ 828]mv
0>[2350]MHZ -> Vol TA[ 837]mv TB[ 841]mv
0>[2400]MHZ -> Vol TA[ 850]mv TB[ 854]mv
0>[2450]MHZ -> Vol TA[ 862]mv TB[ 866]mv
0>[2500]MHZ -> Vol TA[ 875]mv TB[ 879]mv
0>[2550]MHZ -> Vol TA[ 887]mv TB[ 892]mv
0>[2600]MHZ -> Vol TA[ 900]mv TB[ 904]mv
0>[2650]MHZ -> Vol TA[ 912]mv TB[ 917]mv
0>[2700]MHZ -> Vol TA[ 925]mv TB[ 930]mv
0>[2750]MHZ -> Vol TA[ 942]mv TB[ 948]mv
0>[2800]MHZ -> Vol TA[ 960]mv TB[ 966]mv
0>[2850]MHZ -> Vol TA[ 978]mv TB[ 984]mv
0>[2900]MHZ -> Vol TA[ 996]mv TB[1002]mv
0>[2950]MHZ -> Vol TA[1013]mv TB[1019]mv
0>[3000]MHZ -> Vol TA[1030]mv TB[1036]mv
0>[3050]MHZ -> Vol TA[1044]mv TB[1049]mv
0>[3100]MHZ -> Vol TA[1058]mv TB[1063]mv
0>Uncore VF curve:
0>Uncore [   0]MHZ -> Vol [ 810]mv
0>Uncore [ 100]MHZ -> Vol [ 810]mv
0>Uncore [ 200]MHZ -> Vol [ 810]mv
0>Uncore [ 300]MHZ -> Vol [ 810]mv
0>Uncore [ 400]MHZ -> Vol [ 810]mv
0>Uncore [ 500]MHZ -> Vol [ 881]mv
0>Uncore [ 600]MHZ -> Vol [ 881]mv
0>Uncore [ 700]MHZ -> Vol [ 881]mv
0>Uncore [ 800]MHZ -> Vol [ 881]mv
0>Uncore [ 900]MHZ -> Vol [ 881]mv
0>Uncore [1000]MHZ -> Vol [ 881]mv
0>Uncore [1100]MHZ -> Vol [ 881]mv
0>Uncore [1200]MHZ -> Vol [ 881]mv
0>Uncore [1300]MHZ -> Vol [ 881]mv
0>Uncore [1400]MHZ -> Vol [ 881]mv
0>Uncore [1500]MHZ -> Vol [ 881]mv
0>Uncore [1600]MHZ -> Vol [ 881]mv
0>Uncore [1700]MHZ -> Vol [ 881]mv
0>Uncore [1800]MHZ -> Vol [ 881]mv
0>Uncore [1900]MHZ -> Vol [ 881]mv
0>Uncore [2000]MHZ -> Vol [ 881]mv
0>Uncore [2100]MHZ -> Vol [ 888]mv
0>Uncore [2200]MHZ -> Vol [ 896]mv
0>Uncore [2300]MHZ -> Vol [ 904]mv
0>Uncore [2400]MHZ -> Vol [ 912]mv
0>Uncore [2500]MHZ -> Vol [ 920]mv
0>Uncore [2600]MHZ -> Vol [ 937]mv
0>Uncore [2700]MHZ -> Vol [ 955]mv
0>Uncore [2800]MHZ -> Vol [ 972]mv
0>Uncore [2900]MHZ -> Vol [ 990]mv
0>Uncore [3000]MHZ -> Vol [1004]mv
0>[TracePoint] type[  0] cmd[  1] data[  6]
0>[TracePoint] type[  0] cmd[  1] data[  7]
0>
********Hello Huawei LiteOS********

KpxxxxIPU Firmware Version : V32.75.0
LiteOS Kernel Version : 5.7.0
0>Run on ChipVersion[0] Node[0] Die[0]
0>build time : Apr 24 2026 18:00:00

0>**********************************
0>
main core booting up...
0>start set affinity
0>
mpidr = 0x81000000
0>sram ecc state: 0x0, sram ecc cnt: 0x0
0>[TracePoint] type[  0] cmd[  2] data[  1]
0>[TracePoint] type[  0] cmd[  2] data[  2]
0>LRDXSD_LOCK_OFFSET = 0x0
0>LRDXSD_ERRIMSK_OFFSET = 0x0
0>LRDXSD_DBG_OTIMSK_OFFSET = 0x0
0>LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
0>LRDXSD_DBG_EN_OFFSET = 0x1
0>======tsensor params======
0>  is_trimmed       : 1
0>  underclocking_en : 1
0>===========end============
0>soc tsensor init done
0>========vrd info from cpld========
0>vrd_id | u64                | pmbus_en | avsbus_en | loop | pmbus_id | pmbus_addr | avs_sw | pmbus_sw | addr_9545 | domain_type | die_mask | reserved
0>  00   | 0x0001000100002017 | 0x1      | 0x1       | 0x1  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0100   | 0x0
0>  01   | 0x000300030000201b | 0x1      | 0x1       | 0x2  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x3         | 0x0300   | 0x0
0>  02   | 0x0000010500002b15 | 0x1      | 0x0       | 0x1  | 0x1      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0001   | 0x0
0>  03   | 0x0002000100002027 | 0x1      | 0x1       | 0x1  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0200   | 0x0
0>  04   | 0x000300020000202b | 0x1      | 0x1       | 0x2  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x2         | 0x0300   | 0x0
0>  05   | 0x0000020500002b25 | 0x1      | 0x0       | 0x1  | 0x2      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0002   | 0x0
0>  06   | 0x0003000400002b29 | 0x1      | 0x0       | 0x2  | 0x2      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x4         | 0x0300   | 0x0
0>================end===============
0>=============vrd info=============
0>power domain num: 7
0>power domain[00] id:0 | CORE_DVFS_TA       | PMBus NA | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
0>power domain[01] id:1 | DDR_VDD            | PMBus NA | cap:0x3 | rail:1 | addr:0x20 | def_volt: 765 mV | min_volt: 650 mV | max_volt: 850 mV
0>power domain[02] id:4 | IO_DVDD_NA         | PMBus NA | cap:0x1 | rail:0 | addr:0x2b | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
0>power domain[03] id:2 | CORE_DVFS_TB       | PMBus NB | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
0>power domain[04] id:3 | UNCORE_DVFS        | PMBus NB | cap:0x3 | rail:1 | addr:0x20 | def_volt: 990 mV | min_volt: 750 mV | max_volt:1100 mV
0>power domain[05] id:5 | IO_DVDD_NB         | PMBus NB | cap:0x1 | rail:0 | addr:0x2b | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
0>power domain[06] id:6 | DDR_VDDQ           | PMBus NB | cap:0x1 | rail:1 | addr:0x2b | def_volt:1100 mV | min_volt:1000 mV | max_volt:1200 mV
0>================end===============
0>pmbus[0] init done
0>pmbus[1] init done
0>power domain[0] CORE_DVFS_TA       | NA PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
0>power domain[1] DDR_VDD            | NA PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 765 mV | pmu:MP2882
0>power domain[4] IO_DVDD_NA         | NA PMBus        | rail:0 | addr:0x2b | def_volt: 800 mV | pmu:MP2882
0>power domain[2] CORE_DVFS_TB       | NB PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
0>power domain[3] UNCORE_DVFS        | NB PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 990 mV | pmu:MP2882
0>power domain[5] IO_DVDD_NB         | NB PMBus        | rail:0 | addr:0x2b | def_volt: 800 mV | pmu:MP2882
0>power domain[6] DDR_VDDQ           | NB PMBus        | rail:1 | addr:0x2b | def_volt:1100 mV | pmu:MP2882
0>power domain[0] CORE_DVFS_TA       is transferred to AVSBus mode
0>power domain[1] DDR_VDD            is transferred to AVSBus mode
0>power domain[2] CORE_DVFS_TB       is transferred to AVSBus mode
0>power domain[3] UNCORE_DVFS        is transferred to AVSBus mode
0>avsbus resync success
0>avsbus[0] init done
0>avsbus resync success
0>avsbus[1] init done
0>============volt boot============
0>power domain[0] volt = 1101 mV
0>power domain[1] volt =  763 mV
0>power domain[4] volt =  802 mV
0>power domain[2] volt = 1099 mV
0>power domain[3] volt = 1005 mV
0>power domain[5] volt =  804 mV
0>power domain[6] volt = 1103 mV
0>===============end===============
0>--w&h rd rail:0, 1101, CORE_DVFS_TA
0>--w&h rd rail:1, 765, CORE_DVFS_TA
0>power domain[0] set volt --> 1101 mV success
0>--w&h rd rail:0, 1099, CORE_DVFS_TB
0>--w&h rd rail:1, 1003, CORE_DVFS_TB
0>power domain[2] set volt --> 1099 mV success
0>power domain[3] set volt -->  990 mV success
0>power domain[1] set volt -->  761 mV success
0>power domain[4] set volt -->  800 mV success
0>power domain[5] set volt -->  802 mV success
0>============volt post============
0>power domain[0] volt = 1101 mV
0>power domain[1] volt =  761 mV
0>power domain[4] volt =  800 mV
0>power domain[2] volt = 1099 mV
0>power domain[3] volt =  990 mV
0>power domain[5] volt =  802 mV
0>power domain[6] volt = 1103 mV
0>===============end===============
0>Hboot1 Info RAW Dump: [0x91][0x00][0x00][0x14][0x01][0x00][0x01]
0>PowerSensorSupport[1], Cali[5120], Loss[7200]
0>Power Sensor Calibration Value[5120]!
0>the power sensor : manu id = 2peak, die id = TPA626
0>power sensor[0] init success
0>die[0] its[0] init done
0>die[0] its[1] init done
0>die[0] its[2] init done
0>die[0] its[3] init done
0>die[0] its[4] init done
0>die[0] its[5] init done
0>die[0] its[6] init done
0>die[0] its[7] init done
0>die[0] its[8] init done
0>die[0] its[9] init done
0>die[1] its[0] init done
0>die[1] its[1] init done
0>die[1] its[2] init done
0>die[1] its[3] init done
0>die[1] its[4] init done
0>die[1] its[5] init done
0>die[1] its[6] init done
0>die[1] its[7] init done
0>die[1] its[8] init done
0>die[1] its[9] init done
0>Totem[0] Core Boot Vol [1101]mv
0>Totem[0] Core Current Vol [1100]mv
0>Totem[1] Core Boot Vol [1099]mv
0>Totem[1] Core Current Vol [1100]mv
0>NA 1620V190
0>NB 1620V190
0>GetCoreBaseFreq [2900000KHZ]
0>GetCoreTurboFreq [2900000KHZ]
0>GetCustomClusterNum [10]
0>Ipu ACG Training Done!
0>AP Last Time:[0.00.01.774]
0>wait UEFI pll init...
0>done
0>acg trim start
0>core trim freq:2000, avs:0 volt:810mv
0>core trim freq:2000, avs:0 volt:810mv
0>core trim freq:2050, avs:1 volt:810mv
0>core trim freq:2050, avs:1 volt:810mv
0>core trim freq:2100, avs:2 volt:810mv
0>core trim freq:2100, avs:2 volt:810mv
0>core trim freq:2150, avs:3 volt:810mv
0>core trim freq:2150, avs:3 volt:810mv
0>core trim freq:2200, avs:4 volt:810mv
0>core trim freq:2200, avs:4 volt:810mv
0>core trim freq:2250, avs:5 volt:812mv
0>core trim freq:2250, avs:5 volt:816mv
0>core trim freq:2300, avs:6 volt:825mv
0>core trim freq:2300, avs:6 volt:828mv
0>core trim freq:2350, avs:7 volt:837mv
0>core trim freq:2350, avs:7 volt:841mv
0>core trim freq:2400, avs:8 volt:850mv
0>core trim freq:2400, avs:8 volt:854mv
0>core trim freq:2450, avs:9 volt:862mv
0>core trim freq:2450, avs:9 volt:866mv
0>core trim freq:2500, avs:10 volt:875mv
0>core trim freq:2500, avs:10 volt:879mv
0>core trim freq:2550, avs:11 volt:887mv
0>core trim freq:2550, avs:11 volt:892mv
0>core trim freq:2600, avs:12 volt:900mv
0>core trim freq:2600, avs:12 volt:904mv
0>core trim freq:2650, avs:13 volt:912mv
0>core trim freq:2650, avs:13 volt:917mv
0>core trim freq:2700, avs:14 volt:925mv
0>core trim freq:2700, avs:14 volt:930mv
0>core trim freq:2750, avs:15 volt:942mv
0>core trim freq:2750, avs:15 volt:948mv
0>core trim freq:2800, avs:16 volt:960mv
0>core trim freq:2800, avs:16 volt:966mv
0>core trim freq:2850, avs:17 volt:978mv
0>core trim freq:2850, avs:17 volt:984mv
0>core trim freq:2900, avs:18 volt:996mv
0>core trim freq:2900, avs:18 volt:1002mv
0>core trim freq:2950, avs:19 volt:1013mv
0>core trim freq:2950, avs:19 volt:1019mv
0>core trim freq:3000, avs:20 volt:1030mv
0>core trim freq:3000, avs:20 volt:1036mv
0>core trim freq:3050, avs:21 volt:1044mv
0>core trim freq:3050, avs:21 volt:1049mv
0>core trim freq:3100, avs:22 volt:1058mv
0>core trim freq:3100, avs:22 volt:1063mv
0>acg trim end
0>LDO disabled
0>[TracePoint] type[  0] cmd[  2] data[  3]
0>Interrupt 423 register OK
0>Interrupt 430 register OK
0>[TracePoint] type[  0] cmd[  2] data[  4]
0>
0>cpu 0 entering scheduler
0>[TracePoint] type[  0] cmd[  3] data[  1]
0>add your ipu app init here!
0>IpuInterfaceTaskStart Entry ...
0>ipu interface task wait parameters from uefi...
0>thermal soc task enabled
0>AP Last Time:[0.00.44.252]
0>ThermalDimmStart Entry ...
0>wait ddr init done...
0>power task start...
0>[TracePoint] type[  0] cmd[  3] data[  2]
0>ufs task wait parameters from uefi...
0>AmuTaskStart Entry ... 
0>amu task wait parameters from uefi...
0>ThermalSiwStart Entry ...
0>ThermalSiwTask idle...
0>DemtTaskStart Entry ...
0>[TracePoint] type[  0] cmd[  3] data[  3]
0>demt task wait parameters from uefi...
0>HiBoostTaskStart Entry ...
0>HiBoost task enabled
0>Waiting for UEFI parameters...
0>[TracePoint] type[  0] cmd[  3] data[  4]
0>[TracePoint] type[  0] cmd[  3] data[  5]
0>uefi parameters ready!
0>UFSProfile[0]
0>PowerPolicy[2] BenchMarkSelection[0]
0>ipu interface task wait ddr init done from uefi...
0>ufs task parameters from uefi ready
0>uncore domain[0] freq:2900
0>uncore domain[1] freq:2900
0>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
0>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
0>======sioe status======
0>thermal soc task restore underclocking_en=1
0>ppu alert temp div init done
0>TA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TA_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TA_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TA_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
0>TA_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
0>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
0>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
0>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
0>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
0>==========end==========
0>sioe init done
0>ufs task enabled
0>--> UFS profile[0]
0>UEFI parameters ready
0>UncoreMaxFreq Set to [2900 MHZ]
0>get TDP from efuse success, value = 357500mw
0>target power set to [357500]mw, brd:[357500]
0>demt task parameters from uefi ready
0>uefi ddr init finish!
0>ipu interface task wait uefi end done from uefi...
0>ddr init done, start thermal dimm task
0>======dimm status======
0>  chl[0] dimm0 2, dimm1 0
0>  chl[1] dimm0 2, dimm1 0
0>  chl[2] dimm0 2, dimm1 0
0>  chl[3] dimm0 2, dimm1 0
0>  chl[4] dimm0 2, dimm1 0
0>  chl[5] dimm0 2, dimm1 0
0>  chl[6] dimm0 2, dimm1 0
0>  chl[7] dimm0 2, dimm1 0
0>==========end==========
0>chl[0] registered, dimm mask = 0x1
0>chl[1] registered, dimm mask = 0x1
0>chl[2] registered, dimm mask = 0x1
0>chl[3] registered, dimm mask = 0x1
0>chl[4] registered, dimm mask = 0x1
0>chl[5] registered, dimm mask = 0x1
0>chl[6] registered, dimm mask = 0x1
0>chl[7] registered, dimm mask = 0x1
0>=====dimm temp params=====
0>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
0>  is_thermal_thro_en  : 1
0>  is_aref_rate_auto   : 1
0>===========end============
0>chl[0] max_temp 27'C, aref_rate 0x5 --> 0x4
0>chl[1] max_temp 27'C, aref_rate 0x5 --> 0x4
0>chl[2] max_temp 27'C, aref_rate 0x5 --> 0x4
0>chl[3] max_temp 27'C, aref_rate 0x5 --> 0x4
0>chl[4] max_temp 27'C, aref_rate 0x5 --> 0x4
0>chl[5] max_temp 27'C, aref_rate 0x5 --> 0x4
0>chl[6] max_temp 27'C, aref_rate 0x5 --> 0x4
0>chl[7] max_temp 27'C, aref_rate 0x5 --> 0x4
0>uefi end finish!
0>ipu interface task exit!
0>amu task parameters from uefi ready
0>amu task activated
0>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
]mv TB[ 810]mv
1>[1950]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[2000]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[2050]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[2100]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[2150]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[2200]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[2250]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[2300]MHZ -> Vol TA[ 820]mv TB[ 821]mv
1>[2350]MHZ -> Vol TA[ 833]mv TB[ 834]mv
1>[2400]MHZ -> Vol TA[ 845]mv TB[ 846]mv
1>[2450]MHZ -> Vol TA[ 857]mv TB[ 858]mv
1>[2500]MHZ -> Vol TA[ 869]mv TB[ 870]mv
1>[2550]MHZ -> Vol TA[ 882]mv TB[ 883]mv
1>[2600]MHZ -> Vol TA[ 894]mv TB[ 895]mv
1>[2650]MHZ -> Vol TA[ 906]mv TB[ 907]mv
1>[2700]MHZ -> Vol TA[ 919]mv TB[ 920]mv
1>[2750]MHZ -> Vol TA[ 936]mv TB[ 937]mv
1>[2800]MHZ -> Vol TA[ 954]mv TB[ 955]mv
1>[2850]MHZ -> Vol TA[ 971]mv TB[ 973]mv
1>[2900]MHZ -> Vol TA[ 989]mv TB[ 991]mv
1>[2950]MHZ -> Vol TA[1005]mv TB[1007]mv
1>[3000]MHZ -> Vol TA[1022]mv TB[1024]mv
1>[3050]MHZ -> Vol TA[1036]mv TB[1038]mv
1>[3100]MHZ -> Vol TA[1051]mv TB[1053]mv
1>Uncore VF curve:
1>Uncore [   0]MHZ -> Vol [ 810]mv
1>Uncore [ 100]MHZ -> Vol [ 810]mv
1>Uncore [ 200]MHZ -> Vol [ 810]mv
1>Uncore [ 300]MHZ -> Vol [ 810]mv
1>Uncore [ 400]MHZ -> Vol [ 810]mv
1>Uncore [ 500]MHZ -> Vol [ 879]mv
1>Uncore [ 600]MHZ -> Vol [ 879]mv
1>Uncore [ 700]MHZ -> Vol [ 879]mv
1>Uncore [ 800]MHZ -> Vol [ 879]mv
1>Uncore [ 900]MHZ -> Vol [ 879]mv
1>Uncore [1000]MHZ -> Vol [ 879]mv
1>Uncore [1100]MHZ -> Vol [ 879]mv
1>Uncore [1200]MHZ -> Vol [ 879]mv
1>Uncore [1300]MHZ -> Vol [ 879]mv
1>Uncore [1400]MHZ -> Vol [ 879]mv
1>Uncore [1500]MHZ -> Vol [ 879]mv
1>Uncore [1600]MHZ -> Vol [ 879]mv
1>Uncore [1700]MHZ -> Vol [ 879]mv
1>Uncore [1800]MHZ -> Vol [ 879]mv
1>Uncore [1900]MHZ -> Vol [ 879]mv
1>Uncore [2000]MHZ -> Vol [ 879]mv
1>Uncore [2100]MHZ -> Vol [ 886]mv
1>Uncore [2200]MHZ -> Vol [ 893]mv
1>Uncore [2300]MHZ -> Vol [ 901]mv
1>Uncore [2400]MHZ -> Vol [ 908]mv
1>Uncore [2500]MHZ -> Vol [ 916]mv
1>Uncore [2600]MHZ -> Vol [ 933]mv
1>Uncore [2700]MHZ -> Vol [ 951]mv
1>Uncore [2800]MHZ -> Vol [ 968]mv
1>Uncore [2900]MHZ -> Vol [ 985]mv
1>Uncore [3000]MHZ -> Vol [ 999]mv
1>[TracePoint] type[  0] cmd[  1] data[  6]
1>[TracePoint] type[  0] cmd[  1] data[  7]
1>
********Hello Huawei LiteOS********

KpxxxxIPU Firmware Version : V32.75.0
LiteOS Kernel Version : 5.7.0
1>Run on ChipVersion[0] Node[1] Die[0]
1>build time : Apr 24 2026 18:00:00

1>**********************************
1>
main core booting up...
1>start set affinity
1>
mpidr = 0x81040000
1>sram ecc state: 0x0, sram ecc cnt: 0x0
1>[TracePoint] type[  0] cmd[  2] data[  1]
1>[TracePoint] type[  0] cmd[  2] data[  2]
1>LRDXSD_LOCK_OFFSET = 0x0
1>LRDXSD_ERRIMSK_OFFSET = 0x0
1>LRDXSD_DBG_OTIMSK_OFFSET = 0x0
1>LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
1>LRDXSD_DBG_EN_OFFSET = 0x1
1>======tsensor params======
1>  is_trimmed       : 1
1>  underclocking_en : 1
1>===========end============
1>soc tsensor init done
1>========vrd info from cpld========
1>vrd_id | u64                | pmbus_en | avsbus_en | loop | pmbus_id | pmbus_addr | avs_sw | pmbus_sw | addr_9545 | domain_type | die_mask | reserved
1>  00   | 0x0001000100002017 | 0x1      | 0x1       | 0x1  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0100   | 0x0
1>  01   | 0x000300030000201b | 0x1      | 0x1       | 0x2  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x3         | 0x0300   | 0x0
1>  02   | 0x0000010500002b15 | 0x1      | 0x0       | 0x1  | 0x1      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0001   | 0x0
1>  03   | 0x0002000100002027 | 0x1      | 0x1       | 0x1  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0200   | 0x0
1>  04   | 0x000300020000202b | 0x1      | 0x1       | 0x2  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x2         | 0x0300   | 0x0
1>  05   | 0x0000020500002b25 | 0x1      | 0x0       | 0x1  | 0x2      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0002   | 0x0
1>  06   | 0x0003000400002b29 | 0x1      | 0x0       | 0x2  | 0x2      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x4         | 0x0300   | 0x0
1>================end===============
1>=============vrd info=============
1>power domain num: 7
1>power domain[00] id:0 | CORE_DVFS_TA       | PMBus NA | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
1>power domain[01] id:1 | DDR_VDD            | PMBus NA | cap:0x3 | rail:1 | addr:0x20 | def_volt: 765 mV | min_volt: 650 mV | max_volt: 850 mV
1>power domain[02] id:4 | IO_DVDD_NA         | PMBus NA | cap:0x1 | rail:0 | addr:0x2b | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
1>power domain[03] id:2 | CORE_DVFS_TB       | PMBus NB | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
1>power domain[04] id:3 | UNCORE_DVFS        | PMBus NB | cap:0x3 | rail:1 | addr:0x20 | def_volt: 985 mV | min_volt: 750 mV | max_volt:1100 mV
1>power domain[05] id:5 | IO_DVDD_NB         | PMBus NB | cap:0x1 | rail:0 | addr:0x2b | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
1>power domain[06] id:6 | DDR_VDDQ           | PMBus NB | cap:0x1 | rail:1 | addr:0x2b | def_volt:1100 mV | min_volt:1000 mV | max_volt:1200 mV
1>================end===============
1>pmbus[0] init done
1>pmbus[1] init done
1>power domain[0] CORE_DVFS_TA       | NA PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
1>power domain[1] DDR_VDD            | NA PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 765 mV | pmu:MP2882
1>power domain[4] IO_DVDD_NA         | NA PMBus        | rail:0 | addr:0x2b | def_volt: 800 mV | pmu:MP2882
1>power domain[2] CORE_DVFS_TB       | NB PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
1>power domain[3] UNCORE_DVFS        | NB PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 985 mV | pmu:MP2882
1>power domain[5] IO_DVDD_NB         | NB PMBus        | rail:0 | addr:0x2b | def_volt: 800 mV | pmu:MP2882
1>power domain[6] DDR_VDDQ           | NB PMBus        | rail:1 | addr:0x2b | def_volt:1100 mV | pmu:MP2882
1>power domain[0] CORE_DVFS_TA       is transferred to AVSBus mode
1>power domain[1] DDR_VDD            is transferred to AVSBus mode
1>power domain[2] CORE_DVFS_TB       is transferred to AVSBus mode
1>power domain[3] UNCORE_DVFS        is transferred to AVSBus mode
1>avsbus resync success
1>avsbus[0] init done
1>avsbus resync success
1>avsbus[1] init done
1>============volt boot============
1>power domain[0] volt = 1105 mV
1>power domain[1] volt =  771 mV
1>power domain[4] volt =  808 mV
1>power domain[2] volt = 1103 mV
1>power domain[3] volt = 1007 mV
1>power domain[5] volt =  802 mV
1>power domain[6] volt = 1103 mV
1>===============end===============
1>--w&h rd rail:0, 1105, CORE_DVFS_TA
1>--w&h rd rail:1, 765, CORE_DVFS_TA
1>power domain[0] set volt --> 1105 mV success
1>--w&h rd rail:0, 1103, CORE_DVFS_TB
1>--w&h rd rail:1, 1007, CORE_DVFS_TB
1>power domain[2] set volt --> 1103 mV success
1>power domain[3] set volt -->  988 mV success
1>power domain[1] set volt -->  769 mV success
1>power domain[4] set volt -->  806 mV success
1>power domain[5] set volt -->  800 mV success
1>============volt post============
1>power domain[0] volt = 1107 mV
1>power domain[1] volt =  769 mV
1>power domain[4] volt =  808 mV
1>power domain[2] volt = 1105 mV
1>power domain[3] volt =  988 mV
1>power domain[5] volt =  800 mV
1>power domain[6] volt = 1103 mV
1>===============end===============
1>Hboot1 Info RAW Dump: [0x01][0x00][0x00][0x14][0x01][0x00][0x01]
1>PowerSensorSupport[1], Cali[5120], Loss[0]
1>Power Sensor Calibration Value[5120]!
1>the power sensor : manu id = 2peak, die id = TPA626
1>power sensor[0] init success
1>die[0] its[0] init done
1>die[0] its[1] init done
1>die[0] its[2] init done
1>die[0] its[3] init done
1>die[0] its[4] init done
1>die[0] its[5] init done
1>die[0] its[6] init done
1>die[0] its[7] init done
1>die[0] its[8] init done
1>die[0] its[9] init done
1>die[1] its[0] init done
1>die[1] its[1] init done
1>die[1] its[2] init done
1>die[1] its[3] init done
1>die[1] its[4] init done
1>die[1] its[5] init done
1>die[1] its[6] init done
1>die[1] its[7] init done
1>die[1] its[8] init done
1>die[1] its[9] init done
1>Totem[0] Core Boot Vol [1105]mv
1>Totem[0] Core Current Vol [1100]mv
1>Totem[1] Core Boot Vol [1105]mv
1>Totem[1] Core Current Vol [1100]mv
1>NA 1620V190
1>NB 1620V190
1>GetCoreBaseFreq [2900000KHZ]
1>GetCoreTurboFreq [2900000KHZ]
1>GetCustomClusterNum [10]
1>Ipu ACG Training Done!
1>AP Last Time:[0.00.01.545]
1>wait UEFI pll init...
1>done
1>acg trim start
1>core trim freq:2000, avs:0 volt:810mv
1>core trim freq:2000, avs:0 volt:810mv
1>core trim freq:2050, avs:1 volt:810mv
1>core trim freq:2050, avs:1 volt:810mv
1>core trim freq:2100, avs:2 volt:810mv
1>core trim freq:2100, avs:2 volt:810mv
1>core trim freq:2150, avs:3 volt:810mv
1>core trim freq:2150, avs:3 volt:810mv
1>core trim freq:2200, avs:4 volt:810mv
1>core trim freq:2200, avs:4 volt:810mv
1>core trim freq:2250, avs:5 volt:810mv
1>core trim freq:2250, avs:5 volt:810mv
1>core trim freq:2300, avs:6 volt:820mv
1>core trim freq:2300, avs:6 volt:821mv
1>core trim freq:2350, avs:7 volt:833mv
1>core trim freq:2350, avs:7 volt:834mv
1>core trim freq:2400, avs:8 volt:845mv
1>core trim freq:2400, avs:8 volt:846mv
1>core trim freq:2450, avs:9 volt:857mv
1>core trim freq:2450, avs:9 volt:858mv
1>core trim freq:2500, avs:10 volt:869mv
1>core trim freq:2500, avs:10 volt:870mv
1>core trim freq:2550, avs:11 volt:882mv
1>core trim freq:2550, avs:11 volt:883mv
1>core trim freq:2600, avs:12 volt:894mv
1>core trim freq:2600, avs:12 volt:895mv
1>core trim freq:2650, avs:13 volt:906mv
1>core trim freq:2650, avs:13 volt:907mv
1>core trim freq:2700, avs:14 volt:919mv
1>core trim freq:2700, avs:14 volt:920mv
1>core trim freq:2750, avs:15 volt:936mv
1>core trim freq:2750, avs:15 volt:937mv
1>core trim freq:2800, avs:16 volt:954mv
1>core trim freq:2800, avs:16 volt:955mv
1>core trim freq:2850, avs:17 volt:971mv
1>core trim freq:2850, avs:17 volt:973mv
1>core trim freq:2900, avs:18 volt:989mv
1>core trim freq:2900, avs:18 volt:991mv
1>core trim freq:2950, avs:19 volt:1005mv
1>core trim freq:2950, avs:19 volt:1007mv
1>core trim freq:3000, avs:20 volt:1022mv
1>core trim freq:3000, avs:20 volt:1024mv
1>core trim freq:3050, avs:21 volt:1036mv
1>core trim freq:3050, avs:21 volt:1038mv
1>core trim freq:3100, avs:22 volt:1051mv
1>core trim freq:3100, avs:22 volt:1053mv
1>acg trim end
1>LDO disabled
1>[TracePoint] type[  0] cmd[  2] data[  3]
1>Interrupt 423 register OK
1>Interrupt 430 register OK
1>[TracePoint] type[  0] cmd[  2] data[  4]
1>
1>cpu 0 entering scheduler
1>[TracePoint] type[  0] cmd[  3] data[  1]
1>add your ipu app init here!
1>IpuInterfaceTaskStart Entry ...
1>ipu interface task wait parameters from uefi...
1>thermal soc task enabled
1>AP Last Time:[0.00.44.527]
1>ThermalDimmStart Entry ...
1>wait ddr init done...
1>power task start...
1>[TracePoint] type[  0] cmd[  3] data[  2]
1>ufs task wait parameters from uefi...
1>AmuTaskStart Entry ... 
1>amu task wait parameters from uefi...
1>ThermalSiwStart Entry ...
1>ThermalSiwTask idle...
1>DemtTaskStart Entry ...
1>[TracePoint] type[  0] cmd[  3] data[  3]
1>demt task wait parameters from uefi...
1>HiBoostTaskStart Entry ...
1>HiBoost task enabled
1>Waiting for UEFI parameters...
1>[TracePoint] type[  0] cmd[  3] data[  4]
1>[TracePoint] type[  0] cmd[  3] data[  5]
1>uefi parameters ready!
1>UFSProfile[0]
1>PowerPolicy[2] BenchMarkSelection[0]
1>ipu interface task wait ddr init done from uefi...
1>ufs task parameters from uefi ready
1>uncore domain[0] freq:2900
1>uncore domain[1] freq:2900
1>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
1>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
1>======sioe status======
1>thermal soc task restore underclocking_en=1
1>ppu alert temp div init done
1>TA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TA_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TA_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TA_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
1>TA_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
1>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
1>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
1>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
1>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
1>==========end==========
1>sioe init done
1>ufs task enabled
1>--> UFS profile[0]
1>UEFI parameters ready
1>UncoreMaxFreq Set to [2900 MHZ]
1>get TDP from efuse success, value = 357500mw
1>target power set to [357500]mw, brd:[357500]
1>demt task parameters from uefi ready
1>uefi ddr init finish!
1>ipu interface task wait uefi end done from uefi...
1>ddr init done, start thermal dimm task
1>======dimm status======
1>  chl[0] dimm0 2, dimm1 0
1>  chl[1] dimm0 2, dimm1 0
1>  chl[2] dimm0 2, dimm1 0
1>  chl[3] dimm0 2, dimm1 0
1>  chl[4] dimm0 2, dimm1 0
1>  chl[5] dimm0 2, dimm1 0
1>  chl[6] dimm0 2, dimm1 0
1>  chl[7] dimm0 2, dimm1 0
1>==========end==========
1>chl[0] registered, dimm mask = 0x1
1>chl[1] registered, dimm mask = 0x1
1>chl[2] registered, dimm mask = 0x1
1>chl[3] registered, dimm mask = 0x1
1>chl[4] registered, dimm mask = 0x1
1>chl[5] registered, dimm mask = 0x1
1>chl[6] registered, dimm mask = 0x1
1>chl[7] registered, dimm mask = 0x1
1>=====dimm temp params=====
1>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
1>  is_thermal_thro_en  : 1
1>  is_aref_rate_auto   : 1
1>===========end============
1>chl[0] max_temp 26'C, aref_rate 0x5 --> 0x4
1>chl[1] max_temp 26'C, aref_rate 0x5 --> 0x4
1>chl[2] max_temp 26'C, aref_rate 0x5 --> 0x4
1>chl[3] max_temp 26'C, aref_rate 0x5 --> 0x4
1>chl[4] max_temp 26'C, aref_rate 0x5 --> 0x4
1>chl[5] max_temp 26'C, aref_rate 0x5 --> 0x4
1>chl[6] max_temp 26'C, aref_rate 0x5 --> 0x4
1>chl[7] max_temp 26'C, aref_rate 0x5 --> 0x4
1>uefi end finish!
1>ipu interface task exit!
1>amu task parameters from uefi ready
1>amu task activated
1>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
TB[ 810]mv
2>[1950]MHZ -> Vol TA[ 810]mv TB[ 810]mv
2>[2000]MHZ -> Vol TA[ 810]mv TB[ 810]mv
2>[2050]MHZ -> Vol TA[ 810]mv TB[ 810]mv
2>[2100]MHZ -> Vol TA[ 810]mv TB[ 810]mv
2>[2150]MHZ -> Vol TA[ 810]mv TB[ 810]mv
2>[2200]MHZ -> Vol TA[ 810]mv TB[ 810]mv
2>[2250]MHZ -> Vol TA[ 813]mv TB[ 814]mv
2>[2300]MHZ -> Vol TA[ 826]mv TB[ 827]mv
2>[2350]MHZ -> Vol TA[ 838]mv TB[ 840]mv
2>[2400]MHZ -> Vol TA[ 851]mv TB[ 852]mv
2>[2450]MHZ -> Vol TA[ 863]mv TB[ 865]mv
2>[2500]MHZ -> Vol TA[ 876]mv TB[ 877]mv
2>[2550]MHZ -> Vol TA[ 888]mv TB[ 890]mv
2>[2600]MHZ -> Vol TA[ 901]mv TB[ 902]mv
2>[2650]MHZ -> Vol TA[ 913]mv TB[ 915]mv
2>[2700]MHZ -> Vol TA[ 926]mv TB[ 928]mv
2>[2750]MHZ -> Vol TA[ 944]mv TB[ 946]mv
2>[2800]MHZ -> Vol TA[ 962]mv TB[ 964]mv
2>[2850]MHZ -> Vol TA[ 980]mv TB[ 982]mv
2>[2900]MHZ -> Vol TA[ 998]mv TB[1000]mv
2>[2950]MHZ -> Vol TA[1015]mv TB[1017]mv
2>[3000]MHZ -> Vol TA[1032]mv TB[1034]mv
2>[3050]MHZ -> Vol TA[1046]mv TB[1048]mv
2>[3100]MHZ -> Vol TA[1060]mv TB[1062]mv
2>Uncore VF curve:
2>Uncore [   0]MHZ -> Vol [ 810]mv
2>Uncore [ 100]MHZ -> Vol [ 810]mv
2>Uncore [ 200]MHZ -> Vol [ 810]mv
2>Uncore [ 300]MHZ -> Vol [ 810]mv
2>Uncore [ 400]MHZ -> Vol [ 810]mv
2>Uncore [ 500]MHZ -> Vol [ 877]mv
2>Uncore [ 600]MHZ -> Vol [ 877]mv
2>Uncore [ 700]MHZ -> Vol [ 877]mv
2>Uncore [ 800]MHZ -> Vol [ 877]mv
2>Uncore [ 900]MHZ -> Vol [ 877]mv
2>Uncore [1000]MHZ -> Vol [ 877]mv
2>Uncore [1100]MHZ -> Vol [ 877]mv
2>Uncore [1200]MHZ -> Vol [ 877]mv
2>Uncore [1300]MHZ -> Vol [ 877]mv
2>Uncore [1400]MHZ -> Vol [ 877]mv
2>Uncore [1500]MHZ -> Vol [ 877]mv
2>Uncore [1600]MHZ -> Vol [ 877]mv
2>Uncore [1700]MHZ -> Vol [ 877]mv
2>Uncore [1800]MHZ -> Vol [ 877]mv
2>Uncore [1900]MHZ -> Vol [ 877]mv
2>Uncore [2000]MHZ -> Vol [ 877]mv
2>Uncore [2100]MHZ -> Vol [ 883]mv
2>Uncore [2200]MHZ -> Vol [ 890]mv
2>Uncore [2300]MHZ -> Vol [ 897]mv
2>Uncore [2400]MHZ -> Vol [ 904]mv
2>Uncore [2500]MHZ -> Vol [ 911]mv
2>Uncore [2600]MHZ -> Vol [ 928]mv
2>Uncore [2700]MHZ -> Vol [ 946]mv
2>Uncore [2800]MHZ -> Vol [ 962]mv
2>Uncore [2900]MHZ -> Vol [ 978]mv
2>Uncore [3000]MHZ -> Vol [ 992]mv
2>[TracePoint] type[  0] cmd[  1] data[  6]
2>[TracePoint] type[  0] cmd[  1] data[  7]
2>
********Hello Huawei LiteOS********

KpxxxxIPU Firmware Version : V32.75.0
LiteOS Kernel Version : 5.7.0
2>Run on ChipVersion[0] Node[2] Die[0]
2>build time : Apr 24 2026 18:00:00

2>**********************************
2>
main core booting up...
2>start set affinity
2>
mpidr = 0x81080000
2>sram ecc state: 0x0, sram ecc cnt: 0x0
2>[TracePoint] type[  0] cmd[  2] data[  1]
2>[TracePoint] type[  0] cmd[  2] data[  2]
2>LRDXSD_LOCK_OFFSET = 0x0
2>LRDXSD_ERRIMSK_OFFSET = 0x0
2>LRDXSD_DBG_OTIMSK_OFFSET = 0x0
2>LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
2>LRDXSD_DBG_EN_OFFSET = 0x1
2>======tsensor params======
2>  is_trimmed       : 1
2>  underclocking_en : 1
2>===========end============
2>soc tsensor init done
2>========vrd info from cpld========
2>vrd_id | u64                | pmbus_en | avsbus_en | loop | pmbus_id | pmbus_addr | avs_sw | pmbus_sw | addr_9545 | domain_type | die_mask | reserved
2>  00   | 0x0001000100002017 | 0x1      | 0x1       | 0x1  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0100   | 0x0
2>  01   | 0x000300030000201b | 0x1      | 0x1       | 0x2  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x3         | 0x0300   | 0x0
2>  02   | 0x0000010500002b15 | 0x1      | 0x0       | 0x1  | 0x1      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0001   | 0x0
2>  03   | 0x0002000100002027 | 0x1      | 0x1       | 0x1  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0200   | 0x0
2>  04   | 0x000300020000202b | 0x1      | 0x1       | 0x2  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x2         | 0x0300   | 0x0
2>  05   | 0x0000020500002b25 | 0x1      | 0x0       | 0x1  | 0x2      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0002   | 0x0
2>  06   | 0x0003000400002b29 | 0x1      | 0x0       | 0x2  | 0x2      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x4         | 0x0300   | 0x0
2>================end===============
2>=============vrd info=============
2>power domain num: 7
2>power domain[00] id:0 | CORE_DVFS_TA       | PMBus NA | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
2>power domain[01] id:1 | DDR_VDD            | PMBus NA | cap:0x3 | rail:1 | addr:0x20 | def_volt: 765 mV | min_volt: 650 mV | max_volt: 850 mV
2>power domain[02] id:4 | IO_DVDD_NA         | PMBus NA | cap:0x1 | rail:0 | addr:0x2b | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
2>power domain[03] id:2 | CORE_DVFS_TB       | PMBus NB | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
2>power domain[04] id:3 | UNCORE_DVFS        | PMBus NB | cap:0x3 | rail:1 | addr:0x20 | def_volt: 978 mV | min_volt: 750 mV | max_volt:1100 mV
2>power domain[05] id:5 | IO_DVDD_NB         | PMBus NB | cap:0x1 | rail:0 | addr:0x2b | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
2>power domain[06] id:6 | DDR_VDDQ           | PMBus NB | cap:0x1 | rail:1 | addr:0x2b | def_volt:1100 mV | min_volt:1000 mV | max_volt:1200 mV
2>================end===============
2>pmbus[0] init done
2>pmbus[1] init done
2>power domain[0] CORE_DVFS_TA       | NA PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
2>power domain[1] DDR_VDD            | NA PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 765 mV | pmu:MP2882
2>power domain[4] IO_DVDD_NA         | NA PMBus        | rail:0 | addr:0x2b | def_volt: 800 mV | pmu:MP2882
2>power domain[2] CORE_DVFS_TB       | NB PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
2>power domain[3] UNCORE_DVFS        | NB PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 978 mV | pmu:MP2882
2>power domain[5] IO_DVDD_NB         | NB PMBus        | rail:0 | addr:0x2b | def_volt: 800 mV | pmu:MP2882
2>power domain[6] DDR_VDDQ           | NB PMBus        | rail:1 | addr:0x2b | def_volt:1100 mV | pmu:MP2882
2>power domain[0] CORE_DVFS_TA       is transferred to AVSBus mode
2>power domain[1] DDR_VDD            is transferred to AVSBus mode
2>power domain[2] CORE_DVFS_TB       is transferred to AVSBus mode
2>power domain[3] UNCORE_DVFS        is transferred to AVSBus mode
2>avsbus resync success
2>avsbus[0] init done
2>avsbus resync success
2>avsbus[1] init done
2>============volt boot============
2>power domain[0] volt = 1099 mV
2>power domain[1] volt =  765 mV
2>power domain[4] volt =  802 mV
2>power domain[2] volt = 1101 mV
2>power domain[3] volt = 1005 mV
2>power domain[5] volt =  806 mV
2>power domain[6] volt = 1103 mV
2>===============end===============
2>--w&h rd rail:0, 1099, CORE_DVFS_TA
2>--w&h rd rail:1, 765, CORE_DVFS_TA
2>power domain[0] set volt --> 1097 mV success
2>--w&h rd rail:0, 1103, CORE_DVFS_TB
2>--w&h rd rail:1, 1005, CORE_DVFS_TB
2>power domain[2] set volt --> 1101 mV success
2>power domain[3] set volt -->  978 mV success
2>power domain[1] set volt -->  765 mV success
2>power domain[4] set volt -->  800 mV success
2>power domain[5] set volt -->  804 mV success
2>============volt post============
2>power domain[0] volt = 1099 mV
2>power domain[1] volt =  763 mV
2>power domain[4] volt =  800 mV
2>power domain[2] volt = 1101 mV
2>power domain[3] volt =  978 mV
2>power domain[5] volt =  802 mV
2>power domain[6] volt = 1101 mV
2>===============end===============
2>Hboot1 Info RAW Dump: [0x91][0x00][0x00][0x14][0x01][0x00][0x01]
2>PowerSensorSupport[1], Cali[5120], Loss[7200]
2>Power Sensor Calibration Value[5120]!
2>the power sensor : manu id = 2peak, die id = TPA626
2>power sensor[0] init success
2>die[0] its[0] init done
2>die[0] its[1] init done
2>die[0] its[2] init done
2>die[0] its[3] init done
2>die[0] its[4] init done
2>die[0] its[5] init done
2>die[0] its[6] init done
2>die[0] its[7] init done
2>die[0] its[8] init done
2>die[0] its[9] init done
2>die[1] its[0] init done
2>die[1] its[1] init done
2>die[1] its[2] init done
2>die[1] its[3] init done
2>die[1] its[4] init done
2>die[1] its[5] init done
2>die[1] its[6] init done
2>die[1] its[7] init done
2>die[1] its[8] init done
2>die[1] its[9] init done
2>Totem[0] Core Boot Vol [1097]mv
2>Totem[0] Core Current Vol [1100]mv
2>Totem[1] Core Boot Vol [1101]mv
2>Totem[1] Core Current Vol [1100]mv
2>NA 1620V190
2>NB 1620V190
2>GetCoreBaseFreq [2900000KHZ]
2>GetCoreTurboFreq [2900000KHZ]
2>GetCustomClusterNum [10]
2>Ipu ACG Training Done!
2>AP Last Time:[0.00.01.552]
2>wait UEFI pll init...
2>done
2>acg trim start
2>core trim freq:2000, avs:0 volt:810mv
2>core trim freq:2000, avs:0 volt:810mv
2>core trim freq:2050, avs:1 volt:810mv
2>core trim freq:2050, avs:1 volt:810mv
2>core trim freq:2100, avs:2 volt:810mv
2>core trim freq:2100, avs:2 volt:810mv
2>core trim freq:2150, avs:3 volt:810mv
2>core trim freq:2150, avs:3 volt:810mv
2>core trim freq:2200, avs:4 volt:810mv
2>core trim freq:2200, avs:4 volt:810mv
2>core trim freq:2250, avs:5 volt:813mv
2>core trim freq:2250, avs:5 volt:814mv
2>core trim freq:2300, avs:6 volt:826mv
2>core trim freq:2300, avs:6 volt:827mv
2>core trim freq:2350, avs:7 volt:838mv
2>core trim freq:2350, avs:7 volt:840mv
2>core trim freq:2400, avs:8 volt:851mv
2>core trim freq:2400, avs:8 volt:852mv
2>core trim freq:2450, avs:9 volt:863mv
2>core trim freq:2450, avs:9 volt:865mv
2>core trim freq:2500, avs:10 volt:876mv
2>core trim freq:2500, avs:10 volt:877mv
2>core trim freq:2550, avs:11 volt:888mv
2>core trim freq:2550, avs:11 volt:890mv
2>core trim freq:2600, avs:12 volt:901mv
2>core trim freq:2600, avs:12 volt:902mv
2>core trim freq:2650, avs:13 volt:913mv
2>core trim freq:2650, avs:13 volt:915mv
2>core trim freq:2700, avs:14 volt:926mv
2>core trim freq:2700, avs:14 volt:928mv
2>core trim freq:2750, avs:15 volt:944mv
2>core trim freq:2750, avs:15 volt:946mv
2>core trim freq:2800, avs:16 volt:962mv
2>core trim freq:2800, avs:16 volt:964mv
2>core trim freq:2850, avs:17 volt:980mv
2>core trim freq:2850, avs:17 volt:982mv
2>core trim freq:2900, avs:18 volt:998mv
2>core trim freq:2900, avs:18 volt:1000mv
2>core trim freq:2950, avs:19 volt:1015mv
2>core trim freq:2950, avs:19 volt:1017mv
2>core trim freq:3000, avs:20 volt:1032mv
2>core trim freq:3000, avs:20 volt:1034mv
2>core trim freq:3050, avs:21 volt:1046mv
2>core trim freq:3050, avs:21 volt:1048mv
2>core trim freq:3100, avs:22 volt:1060mv
2>core trim freq:3100, avs:22 volt:1062mv
2>acg trim end
2>LDO disabled
2>[TracePoint] type[  0] cmd[  2] data[  3]
2>Interrupt 423 register OK
2>Interrupt 430 register OK
2>[TracePoint] type[  0] cmd[  2] data[  4]
2>
2>cpu 0 entering scheduler
2>[TracePoint] type[  0] cmd[  3] data[  1]
2>add your ipu app init here!
2>IpuInterfaceTaskStart Entry ...
2>ipu interface task wait parameters from uefi...
2>thermal soc task enabled
2>AP Last Time:[0.00.44.570]
2>ThermalDimmStart Entry ...
2>wait ddr init done...
2>power task start...
2>[TracePoint] type[  0] cmd[  3] data[  2]
2>ufs task wait parameters from uefi...
2>AmuTaskStart Entry ... 
2>amu task wait parameters from uefi...
2>ThermalSiwStart Entry ...
2>ThermalSiwTask idle...
2>DemtTaskStart Entry ...
2>[TracePoint] type[  0] cmd[  3] data[  3]
2>demt task wait parameters from uefi...
2>HiBoostTaskStart Entry ...
2>HiBoost task enabled
2>Waiting for UEFI parameters...
2>[TracePoint] type[  0] cmd[  3] data[  4]
2>[TracePoint] type[  0] cmd[  3] data[  5]
2>uefi parameters ready!
2>UFSProfile[0]
2>PowerPolicy[2] BenchMarkSelection[0]
2>ipu interface task wait ddr init done from uefi...
2>ufs task parameters from uefi ready
2>uncore domain[0] freq:2900
2>uncore domain[1] freq:2900
2>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
2>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
2>======sioe status======
2>thermal soc task restore underclocking_en=1
2>ppu alert temp div init done
2>TA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
2>TA_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
2>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
2>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
2>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
2>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
2>==========end==========
2>sioe init done
2>ufs task enabled
2>--> UFS profile[0]
2>UEFI parameters ready
2>UncoreMaxFreq Set to [2900 MHZ]
2>get TDP from efuse success, value = 357500mw
2>target power set to [357500]mw, brd:[357500]
2>demt task parameters from uefi ready
2>uefi ddr init finish!
2>ipu interface task wait uefi end done from uefi...
2>ddr init done, start thermal dimm task
2>======dimm status======
2>  chl[0] dimm0 2, dimm1 0
2>  chl[1] dimm0 2, dimm1 0
2>  chl[2] dimm0 2, dimm1 0
2>  chl[3] dimm0 2, dimm1 0
2>  chl[4] dimm0 2, dimm1 0
2>  chl[5] dimm0 2, dimm1 0
2>  chl[6] dimm0 2, dimm1 0
2>  chl[7] dimm0 2, dimm1 0
2>==========end==========
2>chl[0] registered, dimm mask = 0x1
2>chl[1] registered, dimm mask = 0x1
2>chl[2] registered, dimm mask = 0x1
2>chl[3] registered, dimm mask = 0x1
2>chl[4] registered, dimm mask = 0x1
2>chl[5] registered, dimm mask = 0x1
2>chl[6] registered, dimm mask = 0x1
2>chl[7] registered, dimm mask = 0x1
2>=====dimm temp params=====
2>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
2>  is_thermal_thro_en  : 1
2>  is_aref_rate_auto   : 1
2>===========end============
2>chl[0] max_temp 27'C, aref_rate 0x5 --> 0x4
2>chl[1] max_temp 27'C, aref_rate 0x5 --> 0x4
2>chl[2] max_temp 27'C, aref_rate 0x5 --> 0x4
2>chl[3] max_temp 27'C, aref_rate 0x5 --> 0x4
2>chl[4] max_temp 27'C, aref_rate 0x5 --> 0x4
2>chl[5] max_temp 27'C, aref_rate 0x5 --> 0x4
2>chl[6] max_temp 27'C, aref_rate 0x5 --> 0x4
2>chl[7] max_temp 27'C, aref_rate 0x5 --> 0x4
2>uefi end finish!
2>ipu interface task exit!
2>amu task parameters from uefi ready
2>amu task activated
2>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
mv TB[ 810]mv
3>[1950]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2000]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2050]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2100]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2150]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2200]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2250]MHZ -> Vol TA[ 813]mv TB[ 815]mv
3>[2300]MHZ -> Vol TA[ 826]mv TB[ 827]mv
3>[2350]MHZ -> Vol TA[ 838]mv TB[ 840]mv
3>[2400]MHZ -> Vol TA[ 851]mv TB[ 853]mv
3>[2450]MHZ -> Vol TA[ 863]mv TB[ 865]mv
3>[2500]MHZ -> Vol TA[ 876]mv TB[ 878]mv
3>[2550]MHZ -> Vol TA[ 888]mv TB[ 891]mv
3>[2600]MHZ -> Vol TA[ 901]mv TB[ 903]mv
3>[2650]MHZ -> Vol TA[ 913]mv TB[ 916]mv
3>[2700]MHZ -> Vol TA[ 926]mv TB[ 929]mv
3>[2750]MHZ -> Vol TA[ 943]mv TB[ 946]mv
3>[2800]MHZ -> Vol TA[ 961]mv TB[ 964]mv
3>[2850]MHZ -> Vol TA[ 979]mv TB[ 982]mv
3>[2900]MHZ -> Vol TA[ 997]mv TB[1000]mv
3>[2950]MHZ -> Vol TA[1014]mv TB[1017]mv
3>[3000]MHZ -> Vol TA[1031]mv TB[1035]mv
3>[3050]MHZ -> Vol TA[1045]mv TB[1048]mv
3>[3100]MHZ -> Vol TA[1059]mv TB[1062]mv
3>Uncore VF curve:
3>Uncore [   0]MHZ -> Vol [ 810]mv
3>Uncore [ 100]MHZ -> Vol [ 810]mv
3>Uncore [ 200]MHZ -> Vol [ 810]mv
3>Uncore [ 300]MHZ -> Vol [ 810]mv
3>Uncore [ 400]MHZ -> Vol [ 810]mv
3>Uncore [ 500]MHZ -> Vol [ 877]mv
3>Uncore [ 600]MHZ -> Vol [ 877]mv
3>Uncore [ 700]MHZ -> Vol [ 877]mv
3>Uncore [ 800]MHZ -> Vol [ 877]mv
3>Uncore [ 900]MHZ -> Vol [ 877]mv
3>Uncore [1000]MHZ -> Vol [ 877]mv
3>Uncore [1100]MHZ -> Vol [ 877]mv
3>Uncore [1200]MHZ -> Vol [ 877]mv
3>Uncore [1300]MHZ -> Vol [ 877]mv
3>Uncore [1400]MHZ -> Vol [ 877]mv
3>Uncore [1500]MHZ -> Vol [ 877]mv
3>Uncore [1600]MHZ -> Vol [ 877]mv
3>Uncore [1700]MHZ -> Vol [ 877]mv
3>Uncore [1800]MHZ -> Vol [ 877]mv
3>Uncore [1900]MHZ -> Vol [ 877]mv
3>Uncore [2000]MHZ -> Vol [ 877]mv
3>Uncore [2100]MHZ -> Vol [ 884]mv
3>Uncore [2200]MHZ -> Vol [ 891]mv
3>Uncore [2300]MHZ -> Vol [ 898]mv
3>Uncore [2400]MHZ -> Vol [ 905]mv
3>Uncore [2500]MHZ -> Vol [ 912]mv
3>Uncore [2600]MHZ -> Vol [ 929]mv
3>Uncore [2700]MHZ -> Vol [ 947]mv
3>Uncore [2800]MHZ -> Vol [ 963]mv
3>Uncore [2900]MHZ -> Vol [ 980]mv
3>Uncore [3000]MHZ -> Vol [ 994]mv
3>[TracePoint] type[  0] cmd[  1] data[  6]
3>[TracePoint] type[  0] cmd[  1] data[  7]
3>
********Hello Huawei LiteOS********

KpxxxxIPU Firmware Version : V32.75.0
LiteOS Kernel Version : 5.7.0
3>Run on ChipVersion[0] Node[3] Die[0]
3>build time : Apr 24 2026 18:00:00

3>**********************************
3>
main core booting up...
3>start set affinity
3>
mpidr = 0x810c0000
3>sram ecc state: 0x0, sram ecc cnt: 0x0
3>[TracePoint] type[  0] cmd[  2] data[  1]
3>[TracePoint] type[  0] cmd[  2] data[  2]
3>LRDXSD_LOCK_OFFSET = 0x0
3>LRDXSD_ERRIMSK_OFFSET = 0x0
3>LRDXSD_DBG_OTIMSK_OFFSET = 0x0
3>LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
3>LRDXSD_DBG_EN_OFFSET = 0x1
3>======tsensor params======
3>  is_trimmed       : 1
3>  underclocking_en : 1
3>===========end============
3>soc tsensor init done
3>========vrd info from cpld========
3>vrd_id | u64                | pmbus_en | avsbus_en | loop | pmbus_id | pmbus_addr | avs_sw | pmbus_sw | addr_9545 | domain_type | die_mask | reserved
3>  00   | 0x0001000100002017 | 0x1      | 0x1       | 0x1  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0100   | 0x0
3>  01   | 0x000300030000201b | 0x1      | 0x1       | 0x2  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x3         | 0x0300   | 0x0
3>  02   | 0x0000010500002b15 | 0x1      | 0x0       | 0x1  | 0x1      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0001   | 0x0
3>  03   | 0x0002000100002027 | 0x1      | 0x1       | 0x1  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0200   | 0x0
3>  04   | 0x000300020000202b | 0x1      | 0x1       | 0x2  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x2         | 0x0300   | 0x0
3>  05   | 0x0000020500002b25 | 0x1      | 0x0       | 0x1  | 0x2      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0002   | 0x0
3>  06   | 0x0003000400002b29 | 0x1      | 0x0       | 0x2  | 0x2      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x4         | 0x0300   | 0x0
3>================end===============
3>=============vrd info=============
3>power domain num: 7
3>power domain[00] id:0 | CORE_DVFS_TA       | PMBus NA | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
3>power domain[01] id:1 | DDR_VDD            | PMBus NA | cap:0x3 | rail:1 | addr:0x20 | def_volt: 765 mV | min_volt: 650 mV | max_volt: 850 mV
3>power domain[02] id:4 | IO_DVDD_NA         | PMBus NA | cap:0x1 | rail:0 | addr:0x2b | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
3>power domain[03] id:2 | CORE_DVFS_TB       | PMBus NB | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
3>power domain[04] id:3 | UNCORE_DVFS        | PMBus NB | cap:0x3 | rail:1 | addr:0x20 | def_volt: 980 mV | min_volt: 750 mV | max_volt:1100 mV
3>power domain[05] id:5 | IO_DVDD_NB         | PMBus NB | cap:0x1 | rail:0 | addr:0x2b | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
3>power domain[06] id:6 | DDR_VDDQ           | PMBus NB | cap:0x1 | rail:1 | addr:0x2b | def_volt:1100 mV | min_volt:1000 mV | max_volt:1200 mV
3>================end===============
3>pmbus[0] init done
3>pmbus[1] init done
3>power domain[0] CORE_DVFS_TA       | NA PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
3>power domain[1] DDR_VDD            | NA PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 765 mV | pmu:MP2882
3>power domain[4] IO_DVDD_NA         | NA PMBus        | rail:0 | addr:0x2b | def_volt: 800 mV | pmu:MP2882
3>power domain[2] CORE_DVFS_TB       | NB PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
3>power domain[3] UNCORE_DVFS        | NB PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 980 mV | pmu:MP2882
3>power domain[5] IO_DVDD_NB         | NB PMBus        | rail:0 | addr:0x2b | def_volt: 800 mV | pmu:MP2882
3>power domain[6] DDR_VDDQ           | NB PMBus        | rail:1 | addr:0x2b | def_volt:1100 mV | pmu:MP2882
3>power domain[0] CORE_DVFS_TA       is transferred to AVSBus mode
3>power domain[1] DDR_VDD            is transferred to AVSBus mode
3>power domain[2] CORE_DVFS_TB       is transferred to AVSBus mode
3>power domain[3] UNCORE_DVFS        is transferred to AVSBus mode
3>avsbus resync success
3>avsbus[0] init done
3>avsbus resync success
3>avsbus[1] init done
3>============volt boot============
3>power domain[0] volt = 1101 mV
3>power domain[1] volt =  763 mV
3>power domain[4] volt =  806 mV
3>power domain[2] volt = 1105 mV
3>power domain[3] volt = 1007 mV
3>power domain[5] volt =  800 mV
3>power domain[6] volt = 1101 mV
3>===============end===============
3>--w&h rd rail:0, 1099, CORE_DVFS_TA
3>--w&h rd rail:1, 765, CORE_DVFS_TA
3>power domain[0] set volt --> 1099 mV success
3>--w&h rd rail:0, 1105, CORE_DVFS_TB
3>--w&h rd rail:1, 1009, CORE_DVFS_TB
3>power domain[2] set volt --> 1105 mV success
3>power domain[3] set volt -->  984 mV success
3>power domain[1] set volt -->  763 mV success
3>power domain[4] set volt -->  802 mV success
3>power domain[5] set volt -->  798 mV success
3>============volt post============
3>power domain[0] volt = 1099 mV
3>power domain[1] volt =  763 mV
3>power domain[4] volt =  802 mV
3>power domain[2] volt = 1105 mV
3>power domain[3] volt =  984 mV
3>power domain[5] volt =  798 mV
3>power domain[6] volt = 1103 mV
3>===============end===============
3>Hboot1 Info RAW Dump: [0x01][0x00][0x00][0x14][0x01][0x00][0x01]
3>PowerSensorSupport[1], Cali[5120], Loss[0]
3>Power Sensor Calibration Value[5120]!
3>the power sensor : manu id = 2peak, die id = TPA626
3>power sensor[0] init success
3>die[0] its[0] init done
3>die[0] its[1] init done
3>die[0] its[2] init done
3>die[0] its[3] init done
3>die[0] its[4] init done
3>die[0] its[5] init done
3>die[0] its[6] init done
3>die[0] its[7] init done
3>die[0] its[8] init done
3>die[0] its[9] init done
3>die[1] its[0] init done
3>die[1] its[1] init done
3>die[1] its[2] init done
3>die[1] its[3] init done
3>die[1] its[4] init done
3>die[1] its[5] init done
3>die[1] its[6] init done
3>die[1] its[7] init done
3>die[1] its[8] init done
3>die[1] its[9] init done
3>Totem[0] Core Boot Vol [1099]mv
3>Totem[0] Core Current Vol [1100]mv
3>Totem[1] Core Boot Vol [1105]mv
3>Totem[1] Core Current Vol [1100]mv
3>NA 1620V190
3>NB 1620V190
3>GetCoreBaseFreq [2900000KHZ]
3>GetCoreTurboFreq [2900000KHZ]
3>GetCustomClusterNum [10]
3>Ipu ACG Training Done!
3>AP Last Time:[0.00.01.547]
3>wait UEFI pll init...
3>done
3>acg trim start
3>core trim freq:2000, avs:0 volt:810mv
3>core trim freq:2000, avs:0 volt:810mv
3>core trim freq:2050, avs:1 volt:810mv
3>core trim freq:2050, avs:1 volt:810mv
3>core trim freq:2100, avs:2 volt:810mv
3>core trim freq:2100, avs:2 volt:810mv
3>core trim freq:2150, avs:3 volt:810mv
3>core trim freq:2150, avs:3 volt:810mv
3>core trim freq:2200, avs:4 volt:810mv
3>core trim freq:2200, avs:4 volt:810mv
3>core trim freq:2250, avs:5 volt:813mv
3>core trim freq:2250, avs:5 volt:815mv
3>core trim freq:2300, avs:6 volt:826mv
3>core trim freq:2300, avs:6 volt:827mv
3>core trim freq:2350, avs:7 volt:838mv
3>core trim freq:2350, avs:7 volt:840mv
3>core trim freq:2400, avs:8 volt:851mv
3>core trim freq:2400, avs:8 volt:853mv
3>core trim freq:2450, avs:9 volt:863mv
3>core trim freq:2450, avs:9 volt:865mv
3>core trim freq:2500, avs:10 volt:876mv
3>core trim freq:2500, avs:10 volt:878mv
3>core trim freq:2550, avs:11 volt:888mv
3>core trim freq:2550, avs:11 volt:891mv
3>core trim freq:2600, avs:12 volt:901mv
3>core trim freq:2600, avs:12 volt:903mv
3>core trim freq:2650, avs:13 volt:913mv
3>core trim freq:2650, avs:13 volt:916mv
3>core trim freq:2700, avs:14 volt:926mv
3>core trim freq:2700, avs:14 volt:929mv
3>core trim freq:2750, avs:15 volt:943mv
3>core trim freq:2750, avs:15 volt:946mv
3>core trim freq:2800, avs:16 volt:961mv
3>core trim freq:2800, avs:16 volt:964mv
3>core trim freq:2850, avs:17 volt:979mv
3>core trim freq:2850, avs:17 volt:982mv
3>core trim freq:2900, avs:18 volt:997mv
3>core trim freq:2900, avs:18 volt:1000mv
3>core trim freq:2950, avs:19 volt:1014mv
3>core trim freq:2950, avs:19 volt:1017mv
3>core trim freq:3000, avs:20 volt:1031mv
3>core trim freq:3000, avs:20 volt:1035mv
3>core trim freq:3050, avs:21 volt:1045mv
3>core trim freq:3050, avs:21 volt:1048mv
3>core trim freq:3100, avs:22 volt:1059mv
3>core trim freq:3100, avs:22 volt:1062mv
3>acg trim end
3>LDO disabled
3>[TracePoint] type[  0] cmd[  2] data[  3]
3>Interrupt 423 register OK
3>Interrupt 430 register OK
3>[TracePoint] type[  0] cmd[  2] data[  4]
3>
3>cpu 0 entering scheduler
3>[TracePoint] type[  0] cmd[  3] data[  1]
3>add your ipu app init here!
3>IpuInterfaceTaskStart Entry ...
3>ipu interface task wait parameters from uefi...
3>thermal soc task enabled
3>AP Last Time:[0.00.44.520]
3>ThermalDimmStart Entry ...
3>wait ddr init done...
3>power task start...
3>[TracePoint] type[  0] cmd[  3] data[  2]
3>ufs task wait parameters from uefi...
3>AmuTaskStart Entry ... 
3>amu task wait parameters from uefi...
3>ThermalSiwStart Entry ...
3>ThermalSiwTask idle...
3>DemtTaskStart Entry ...
3>[TracePoint] type[  0] cmd[  3] data[  3]
3>demt task wait parameters from uefi...
3>HiBoostTaskStart Entry ...
3>HiBoost task enabled
3>Waiting for UEFI parameters...
3>[TracePoint] type[  0] cmd[  3] data[  4]
3>[TracePoint] type[  0] cmd[  3] data[  5]
3>uefi parameters ready!
3>UFSProfile[0]
3>PowerPolicy[2] BenchMarkSelection[0]
3>ipu interface task wait ddr init done from uefi...
3>ufs task parameters from uefi ready
3>uncore domain[0] freq:2900
3>uncore domain[1] freq:2900
3>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
3>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
3>======sioe status======
3>thermal soc task restore underclocking_en=1
3>ppu alert temp div init done
3>TA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
3>TA_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
3>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
3>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
3>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
3>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
3>==========end==========
3>sioe init done
3>ufs task enabled
3>--> UFS profile[0]
3>UEFI parameters ready
3>UncoreMaxFreq Set to [2900 MHZ]
3>get TDP from efuse success, value = 357500mw
3>target power set to [357500]mw, brd:[357500]
3>demt task parameters from uefi ready
3>uefi ddr init finish!
3>ipu interface task wait uefi end done from uefi...
3>ddr init done, start thermal dimm task
3>======dimm status======
3>  chl[0] dimm0 2, dimm1 0
3>  chl[1] dimm0 2, dimm1 0
3>  chl[2] dimm0 2, dimm1 0
3>  chl[3] dimm0 2, dimm1 0
3>  chl[4] dimm0 2, dimm1 0
3>  chl[5] dimm0 2, dimm1 0
3>  chl[6] dimm0 2, dimm1 0
3>  chl[7] dimm0 2, dimm1 0
3>==========end==========
3>chl[0] registered, dimm mask = 0x1
3>chl[1] registered, dimm mask = 0x1
3>chl[2] registered, dimm mask = 0x1
3>chl[3] registered, dimm mask = 0x1
3>chl[4] registered, dimm mask = 0x1
3>chl[5] registered, dimm mask = 0x1
3>chl[6] registered, dimm mask = 0x1
3>chl[7] registered, dimm mask = 0x1
3>=====dimm temp params=====
3>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
3>  is_thermal_thro_en  : 1
3>  is_aref_rate_auto   : 1
3>===========end============
3>chl[0] max_temp 27'C, aref_rate 0x5 --> 0x4
3>chl[1] max_temp 27'C, aref_rate 0x5 --> 0x4
3>chl[2] max_temp 27'C, aref_rate 0x5 --> 0x4
3>chl[3] max_temp 27'C, aref_rate 0x5 --> 0x4
3>chl[4] max_temp 27'C, aref_rate 0x5 --> 0x4
3>chl[5] max_temp 27'C, aref_rate 0x5 --> 0x4
3>chl[6] max_temp 27'C, aref_rate 0x5 --> 0x4
3>chl[7] max_temp 27'C, aref_rate 0x5 --> 0x4
3>uefi end finish!
3>ipu interface task exit!
3>amu task parameters from uefi ready
3>amu task activated
3>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
[0.08.51.232]IpmiCmdReportPcieMMIO start
[0.09.07.872]IpmiCmdReportPcieMMIO end
pool addr          pool size    used size     free size    max free node size   used node num     free node num      UsageWaterLine
---------------    --------     -------       --------     --------------       -------------      ------------      ------------
0x840908c350       0x22880      0x189d8       0x9c38       0x9550               0xbf               0x3                0x19330        

********Hello Huawei LiteOS********

KpxxxxIMU Firmware Version : V32.75.0
LiteOS Kernel Version : 5.7.0
Run on ChipVersion[0] Node[0] Die[2]
build time : Apr 24 2026 18:00:00

**********************************

main core booting up...
start set affinity

mpidr = 0x81020000
sram ecc state: 0x0, sram ecc cnt: 0x0
[0.00.00.033]node 0 begins init all serdes.
BoardInfo->NodeNum 4.
BoardInfo->NodeId 0.
BoardInfo->InfoVersion 5.
BoardInfo->NASerdesSceneMode 3.
BoardInfo->NBSerdesSceneMode 3.
BoardInfo->HccsTopologyType 12.
BoardInfo->BoardId 0.
ChipVersionIsPro: 0.
BoardInfo Node 0, SerdesUseMode: 1 1 12 4 4 4 4  1 1 1 4 4 4 4 
BoardInfo Node 1, SerdesUseMode: 12 13 12 4 4 4 4  1 1 12 4 4 4 4 
BoardInfo Node 2, SerdesUseMode: 1 1 1 4 4 4 4  1 1 1 4 4 4 4 
BoardInfo Node 3, SerdesUseMode: 1 1 1 4 4 4 4  1 1 1 4 4 4 4 
BoardInfo Node 0, SerdesRxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 1, SerdesRxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 2, SerdesRxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 3, SerdesRxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 0, SerdesTxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 1, SerdesTxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 2, SerdesTxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 3, SerdesTxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
serdessdk version: 2.0_5.0_20241203_imu
node_id 0, die 0, ind 0, usemode 1 begin serdes-init.
node_id 0, die 0, ind 1, usemode 1 begin serdes-init.
node_id 0, die 0, ind 2, usemode 12 begin serdes-init.
chip_id 0, die 0, ind 2, usemode 12 don't support, power down macro!
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
node_id 0, die 2, ind 0, usemode 1 begin serdes-init.
node_id 0, die 2, ind 1, usemode 1 begin serdes-init.
chip serdes init status:0x0.
[0.00.00.454]node 0 ends init all serdes.
link[0] freq_type:1 | peer_chip_type:2 | peer_node_id:0 | peer_link_id:0
link[1] freq_type:1 | peer_chip_type:2 | peer_node_id:0 | peer_link_id:0
link[2] freq_type:1 | peer_chip_type:2 | peer_node_id:0 | peer_link_id:0
link[3] freq_type:1 | peer_chip_type:2 | peer_node_id:0 | peer_link_id:0
link[4] freq_type:1 | peer_chip_type:2 | peer_node_id:0 | peer_link_id:0
link[5] freq_type:1 | peer_chip_type:1 | peer_node_id:1 | peer_link_id:4
link[6] freq_type:1 | peer_chip_type:1 | peer_node_id:2 | peer_link_id:7
link[7] freq_type:1 | peer_chip_type:1 | peer_node_id:3 | peer_link_id:5
register hccs done
nodeId 0, dieId 0, linkId 0, FFE info: fir_pre1 -5, fir_main 58, fir_post1 0
node_id 0, die 0, ind 4, usemode 4 begin serdes-init.
nodeId 0, dieId 0, linkId 1, FFE info: fir_pre1 -5, fir_main 58, fir_post1 0
node_id 0, die 0, ind 3, usemode 4 begin serdes-init.
nodeId 0, dieId 0, linkId 2, FFE info: fir_pre1 -5, fir_main 58, fir_post1 0
node_id 0, die 0, ind 5, usemode 4 begin serdes-init.
nodeId 0, dieId 0, linkId 3, FFE info: fir_pre1 -5, fir_main 58, fir_post1 0
node_id 0, die 0, ind 6, usemode 4 begin serdes-init.
nodeId 0, dieId 1, linkId 0, FFE info: fir_pre1 -5, fir_main 58, fir_post1 0
node_id 0, die 2, ind 4, usemode 4 begin serdes-init.
nodeId 0, dieId 1, linkId 1, FFE info: fir_pre1 -5, fir_main 58, fir_post1 0
node_id 0, die 2, ind 3, usemode 4 begin serdes-init.
nodeId 0, dieId 1, linkId 2, FFE info: fir_pre1 -6, fir_main 45, fir_post1 12
node_id 0, die 2, ind 5, usemode 4 begin serdes-init.
nodeId 0, dieId 1, linkId 3, FFE info: fir_pre1 -6, fir_main 45, fir_post1 12
node_id 0, die 2, ind 6, usemode 4 begin serdes-init.
hccs init start...
pa ring link down success
reset pa success
link[0] pcs init success
link[1] pcs init success
link[2] pcs init success
link[3] pcs init success
link[4] pcs init success
link[5] pcs init success
link[6] pcs init success
link[7] pcs init success
release reset pa success
link[0] macro adapt done (lane_mask=0xff) (0ms)
link[1] macro adapt done (lane_mask=0xff) (0ms)
link[2] macro adapt done (lane_mask=0xff) (0ms)
link[3] macro adapt done (lane_mask=0xff) (0ms)
link[4] macro adapt done (lane_mask=0xff) (0ms)
link[5] macro adapt done (lane_mask=0xff) (0ms)
link[6] macro adapt done (lane_mask=0xff) (0ms)
link[7] macro adapt done (lane_mask=0xff) (0ms)
link[5] pcs training success (10ms)
link[6] pcs training success (10ms)
link[7] pcs training success (10ms)
link[5] training success (20ms)
link[6] training success (20ms)
link[7] training success (20ms)
link[3] pcs training success (4730ms)
link[3] training success (4740ms)
link[4] pcs training success (4770ms)
link[4] training success (4780ms)
link[2] pcs training success (4920ms)
link[2] training success (4930ms)
link[0] pcs training success (5270ms)
link[0] training success (5280ms)
link[1] pcs training success (5380ms)
link[1] training success (5390ms)
link[0]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
BWAY_PCS_ST_PCS_LINK_FSM_RECORD = 0x1248
HLLC_ST_FSM_1_REG = 0x3
link[1]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
BWAY_PCS_ST_PCS_LINK_FSM_RECORD = 0x1248
HLLC_ST_FSM_1_REG = 0x3
link[2]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
BWAY_PCS_ST_PCS_LINK_FSM_RECORD = 0x1248
HLLC_ST_FSM_1_REG = 0x3
link[3]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
BWAY_PCS_ST_PCS_LINK_FSM_RECORD = 0x1248
HLLC_ST_FSM_1_REG = 0x3
link[4]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
BWAY_PCS_ST_PCS_LINK_FSM_RECORD = 0x1248
HLLC_ST_FSM_1_REG = 0x3
link[5]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
BWAY_PCS_ST_PCS_LINK_FSM_RECORD = 0x1248
HLLC_ST_FSM_1_REG = 0x3
link[6]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
BWAY_PCS_ST_PCS_LINK_FSM_RECORD = 0x1248
HLLC_ST_FSM_1_REG = 0x3
link[7]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
BWAY_PCS_ST_PCS_LINK_FSM_RECORD = 0x1248
HLLC_ST_FSM_1_REG = 0x3
link training success
pa[0] linkEn = 0xf
pa[0] allNodeLink0 = 0x0
pa[0] allNodeLink1 = 0xf000f
pa[0] connected with sw node
pa[1] linkEn = 0xf
pa[1] allNodeLink0 = 0x8420
pa[1] allNodeLink1 = 0x10001
pa[1] connected with sw node
pa init success
COM_PAID_INTLV_REG = 0xe
paid decode init success
pa[0] PA_PM_BASE_INFO = 0x0
pa[0] PA_PM_MAP_LINK_NUM = 0x1111
pa[1] PA_PM_BASE_INFO = 0xee0842
pa[1] PA_PM_MAP_LINK_NUM = 0x2811
hccs performace config success
pa ring link up success
hccs init done
hccs access test start
node[0] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[1] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[2] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[3] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[1] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
node[2] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
node[3] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
hccs access test success
======hccs status======
  node[0] mask: expected = 0xff, link up = 0xff, width reduction = 0x0, link down = 0x0
  node[1] mask: expected = 0xff, link up = 0xff, width reduction = 0x0, link down = 0x0
  node[2] mask: expected = 0xff, link up = 0xff, width reduction = 0x0, link down = 0x0
  node[3] mask: expected = 0xff, link up = 0xff, width reduction = 0x0, link down = 0x0
==========end==========
report hccs status success
node[0] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
LRDXSD_LOCK_OFFSET = 0x0
LRDXSD_ERRIMSK_OFFSET = 0x0
LRDXSD_DBG_OTIMSK_OFFSET = 0x0
LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
LRDXSD_DBG_EN_OFFSET = 0x1
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
ID[0x1967c8]!
[ERR]Don't support the flash, CS[0] ID[0x1967c8]!!
ID[0xffffff]!
[ERR]Don't support the flash, CS[1] ID[0xffffff]!!
[ERR]Warnning, Select Default flash 
sfdp detect, try to get dummy data from hboot1 first.
ID[0x1967c8]!
flash 0 support sfdp.
Interrupt 423 register OK
Interrupt 425 register OK
Interrupt 427 register OK
Interrupt 429 register OK
Interrupt 430 register OK
Interrupt 431 register OK
Interrupt 436 register OK

cpu 0 entering scheduler
[IMU] Watchdog Initialization done!
ScmiTaskEntry start.
Interrupt 456 register OK
Interrupt 469 register OK
Interrupt 482 register OK
Interrupt 495 register OK
Interrupt 508 register OK
Interrupt 521 register OK
Interrupt 534 register OK
Interrupt 547 register OK
starting Fpc Isolation Task end
starting fdm Err Info Task end
starting Roce recovery Task end
starting Ce_Storm Contrl Task end
starting Ras_Data_Update Task end
Interrupt 459 register OK
Interrupt 472 register OK
Interrupt 485 register OK
Interrupt 498 register OK
Interrupt 511 register OK
Interrupt 524 register OK
Interrupt 537 register OK
Interrupt 550 register OK
[0.00.46.377]Real time now 2026.10.24 19:42:05
NIC CARD[0][0]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[0][1]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[1][0]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[1][1]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[2][0]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[2][1]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[3][0]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[3][1]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
Init heart-beat-task end
pool addr          pool size    used size     free size    max free node size   used node num     free node num      UsageWaterLine
---------------    --------     -------       --------     --------------       -------------      ------------      ------------
0x840908c350       0x22880      0x190c0       0x9550       0x9550               0x5e               0x1                0x19330        
Get Setup Config.
Node 0, Die 0 ImpState is 0 skip exec.
Node 0, Die 2 ImpState is 0 skip exec.
Node 1, Die 0 ImpState is 0 skip exec.
Node 1, Die 2 ImpState is 0 skip exec.
Node 2, Die 0 ImpState is 0 skip exec.
Node 2, Die 2 ImpState is 0 skip exec.
Node 3, Die 0 ImpState is 0 skip exec.
Node 3, Die 2 ImpState is 0 skip exec.
pwr cap[0]: 0, 63
pwr cap[1]: f, 27
pwr cap[2]: 1, 0
[0.01.20.858]DDR Rreserved for IMU: len = 3e00000
[LOG]head = 0x0, tail = 0x30d0, logSize = 0x30d0
copy registry.json file success
Set component all release version to sram end.
ipcMsgSend success
HsmLogInit Ret 1, Len 4, val 0x32022a06
[0.01.20.901]starting ras Init
nodeId = 0, dieId = 0, isSasExist = 0.
nodeId = 0, dieId = 2, isSasExist = 0.
nodeId = 1, dieId = 0, isSasExist = 0.
nodeId = 1, dieId = 2, isSasExist = 0.
nodeId = 2, dieId = 0, isSasExist = 0.
nodeId = 2, dieId = 2, isSasExist = 0.
nodeId = 3, dieId = 0, isSasExist = 0.
nodeId = 3, dieId = 2, isSasExist = 0.
Mce Table head exist!
RasIntRegister init 452 
RasIntRegister init 453 
RasIntRegister init 64 
RasIntRegister init 65 
RasIntRegister init 465 
RasIntRegister init 466 
RasIntRegister init 86 
RasIntRegister init 87 
RasIntRegister init 478 
RasIntRegister init 479 
RasIntRegister init 108 
RasIntRegister init 109 
RasIntRegister init 491 
RasIntRegister init 492 
RasIntRegister init 130 
RasIntRegister init 131 
RasIntRegister init 504 
RasIntRegister init 505 
RasIntRegister init 152 
RasIntRegister init 153 
RasIntRegister init 517 
RasIntRegister init 518 
RasIntRegister init 174 
RasIntRegister init 175 
RasIntRegister init 530 
RasIntRegister init 531 
RasIntRegister init 196 
RasIntRegister init 197 
RasIntRegister init 543 
RasIntRegister init 544 
RasIntRegister init 218 
RasIntRegister init 219 
RasIntRegister init 76 
RasIntRegister init 98 
RasIntRegister init 120 
RasIntRegister init 142 
RasIntRegister init 164 
RasIntRegister init 186 
RasIntRegister init 208 
RasIntRegister init 230 
[0.01.21.023]starting ras end
[ERR]ipc result error, result 0x28010009
ipcMsgSend fail
Send tee measure to HSM respon:0
get mem silk data length: 192
0: skt = 0 logic = 2 phy = 0 
1: skt = 0 logic = 2 phy = 0 
2: skt = 0 logic = 7 phy = 1 
3: skt = 0 logic = 7 phy = 1 
4: skt = 0 logic = 0 phy = 2 
5: skt = 0 logic = 0 phy = 2 
6: skt = 0 logic = 5 phy = 3 
7: skt = 0 logic = 5 phy = 3 
8: skt = 1 logic = 2 phy = 0 
9: skt = 1 logic = 2 phy = 0 
10: skt = 1 logic = 7 phy = 1 
11: skt = 1 logic = 7 phy = 1 
12: skt = 1 logic = 0 phy = 2 
13: skt = 1 logic = 0 phy = 2 
14: skt = 1 logic = 5 phy = 3 
15: skt = 1 logic = 5 phy = 3 
16: skt = 0 logic = 3 phy = 4 
17: skt = 0 logic = 3 phy = 4 
18: skt = 0 logic = 6 phy = 5 
19: skt = 0 logic = 6 phy = 5 
20: skt = 0 logic = 1 phy = 6 
21: skt = 1 logic = 1 phy = 6 
22: skt = 1 logic = 1 phy = 6 
23: skt = 1 logic = 4 phy = 7 
24: skt = 1 logic = 4 phy = 7 
25: skt = 1 logic = 6 phy = 5 
26: skt = 1 logic = 6 phy = 5 
27: skt = 1 logic = 3 phy = 4 
28: skt = 0 logic = 1 phy = 6 
29: skt = 0 logic = 4 phy = 7 
30: skt = 0 logic = 4 phy = 7 
31: skt = 1 logic = 3 phy = 4 
32: skt = 2 logic = 2 phy = 0 
33: skt = 2 logic = 2 phy = 0 
34: skt = 2 logic = 7 phy = 1 
35: skt = 2 logic = 7 phy = 1 
36: skt = 2 logic = 0 phy = 2 
37: skt = 3 logic = 4 phy = 7 
38: skt = 3 logic = 1 phy = 6 
39: skt = 3 logic = 4 phy = 7 
40: skt = 3 logic = 1 phy = 6 
41: skt = 3 logic = 6 phy = 5 
42: skt = 3 logic = 6 phy = 5 
43: skt = 3 logic = 3 phy = 4 
44: skt = 3 logic = 3 phy = 4 
45: skt = 2 logic = 4 phy = 7 
46: skt = 2 logic = 4 phy = 7 
47: skt = 2 logic = 1 phy = 6 
48: skt = 2 logic = 1 phy = 6 
49: skt = 2 logic = 6 phy = 5 
50: skt = 2 logic = 6 phy = 5 
51: skt = 2 logic = 3 phy = 4 
52: skt = 2 logic = 3 phy = 4 
53: skt = 3 logic = 5 phy = 3 
54: skt = 3 logic = 5 phy = 3 
55: skt = 3 logic = 0 phy = 2 
56: skt = 3 logic = 0 phy = 2 
57: skt = 3 logic = 7 phy = 1 
58: skt = 3 logic = 7 phy = 1 
59: skt = 3 logic = 2 phy = 0 
60: skt = 3 logic = 2 phy = 0 
61: skt = 2 logic = 5 phy = 3 
62: skt = 2 logic = 5 phy = 3 
63: skt = 2 logic = 0 phy = 2 
[0.02.02.530]TF Heartbeat Start
[0.02.07.212]PCIE INIT DONE.
g_mctpQueueCount(48) > tabCnt(42)
slotNum = 0x8
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[0] port:20  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[1] port:22  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[2] port:20  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[3] port:22  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[4] port:20  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[5] port:22  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[6] port:24  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[7] port:26  pcieSlotCtrl.data (after)0x14801c0.

Interrupt 454 register OK
Interrupt 467 register OK
Interrupt 480 register OK
Interrupt 493 register OK
Interrupt 506 register OK
Interrupt 519 register OK
Interrupt 532 register OK
Interrupt 545 register OK
data = 0x0
pmt Init done

Add ep: bdf=a200 eid=9 epCnt=1 eid_alloc=a
Add ep: bdf=c400 eid=a epCnt=1 eid_alloc=b
Add ep: bdf=d000 eid=b epCnt=1 eid_alloc=c
Add ep: bdf=300 eid=c epCnt=1 eid_alloc=d
[0.02.07.450]slot[0] port:20 begin to power OFF.
[0.02.07.451]slot[1] port:22 begin to power OFF.
[0.02.07.455]slot[2] port:20 begin to power OFF.
[0.02.07.459]slot[3] port:22 begin to power OFF.
[0.02.07.463]slot[4] port:20 begin to power ON.
[0.02.07.467]slot[5] port:22 begin to power ON.
[0.02.07.471]slot[6] port:24 begin to power ON.
[0.02.07.475]slot[7] port:26 begin to power ON.
mctp task ok.
[0.03.35.083]BIOS POST END.
Create SetReportPcieMmioToBmc ok.
Start SetReportPcieMmioToBmc ok.
Enter current value process
TB[ 810]mv
0>[1950]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[2000]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[2050]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[2100]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[2150]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[2200]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[2250]MHZ -> Vol TA[ 812]mv TB[ 816]mv
0>[2300]MHZ -> Vol TA[ 825]mv TB[ 828]mv
0>[2350]MHZ -> Vol TA[ 837]mv TB[ 841]mv
0>[2400]MHZ -> Vol TA[ 850]mv TB[ 854]mv
0>[2450]MHZ -> Vol TA[ 862]mv TB[ 866]mv
0>[2500]MHZ -> Vol TA[ 875]mv TB[ 879]mv
0>[2550]MHZ -> Vol TA[ 887]mv TB[ 892]mv
0>[2600]MHZ -> Vol TA[ 900]mv TB[ 904]mv
0>[2650]MHZ -> Vol TA[ 912]mv TB[ 917]mv
0>[2700]MHZ -> Vol TA[ 925]mv TB[ 930]mv
0>[2750]MHZ -> Vol TA[ 942]mv TB[ 948]mv
0>[2800]MHZ -> Vol TA[ 960]mv TB[ 966]mv
0>[2850]MHZ -> Vol TA[ 978]mv TB[ 984]mv
0>[2900]MHZ -> Vol TA[ 996]mv TB[1002]mv
0>[2950]MHZ -> Vol TA[1013]mv TB[1019]mv
0>[3000]MHZ -> Vol TA[1030]mv TB[1036]mv
0>[3050]MHZ -> Vol TA[1044]mv TB[1049]mv
0>[3100]MHZ -> Vol TA[1058]mv TB[1063]mv
0>Uncore VF curve:
0>Uncore [   0]MHZ -> Vol [ 810]mv
0>Uncore [ 100]MHZ -> Vol [ 810]mv
0>Uncore [ 200]MHZ -> Vol [ 810]mv
0>Uncore [ 300]MHZ -> Vol [ 810]mv
0>Uncore [ 400]MHZ -> Vol [ 810]mv
0>Uncore [ 500]MHZ -> Vol [ 881]mv
0>Uncore [ 600]MHZ -> Vol [ 881]mv
0>Uncore [ 700]MHZ -> Vol [ 881]mv
0>Uncore [ 800]MHZ -> Vol [ 881]mv
0>Uncore [ 900]MHZ -> Vol [ 881]mv
0>Uncore [1000]MHZ -> Vol [ 881]mv
0>Uncore [1100]MHZ -> Vol [ 881]mv
0>Uncore [1200]MHZ -> Vol [ 881]mv
0>Uncore [1300]MHZ -> Vol [ 881]mv
0>Uncore [1400]MHZ -> Vol [ 881]mv
0>Uncore [1500]MHZ -> Vol [ 881]mv
0>Uncore [1600]MHZ -> Vol [ 881]mv
0>Uncore [1700]MHZ -> Vol [ 881]mv
0>Uncore [1800]MHZ -> Vol [ 881]mv
0>Uncore [1900]MHZ -> Vol [ 881]mv
0>Uncore [2000]MHZ -> Vol [ 881]mv
0>Uncore [2100]MHZ -> Vol [ 888]mv
0>Uncore [2200]MHZ -> Vol [ 896]mv
0>Uncore [2300]MHZ -> Vol [ 904]mv
0>Uncore [2400]MHZ -> Vol [ 912]mv
0>Uncore [2500]MHZ -> Vol [ 920]mv
0>Uncore [2600]MHZ -> Vol [ 937]mv
0>Uncore [2700]MHZ -> Vol [ 955]mv
0>Uncore [2800]MHZ -> Vol [ 972]mv
0>Uncore [2900]MHZ -> Vol [ 990]mv
0>Uncore [3000]MHZ -> Vol [1004]mv
0>[TracePoint] type[  0] cmd[  1] data[  6]
0>[TracePoint] type[  0] cmd[  1] data[  7]
0>
********Hello Huawei LiteOS********

KpxxxxIPU Firmware Version : V32.75.0
LiteOS Kernel Version : 5.7.0
0>Run on ChipVersion[0] Node[0] Die[0]
0>build time : Apr 24 2026 18:00:00

0>**********************************
0>
main core booting up...
0>start set affinity
0>
mpidr = 0x81000000
0>sram ecc state: 0x0, sram ecc cnt: 0x0
0>[TracePoint] type[  0] cmd[  2] data[  1]
0>[TracePoint] type[  0] cmd[  2] data[  2]
0>LRDXSD_LOCK_OFFSET = 0x0
0>LRDXSD_ERRIMSK_OFFSET = 0x0
0>LRDXSD_DBG_OTIMSK_OFFSET = 0x0
0>LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
0>LRDXSD_DBG_EN_OFFSET = 0x1
0>======tsensor params======
0>  is_trimmed       : 1
0>  underclocking_en : 1
0>===========end============
0>soc tsensor init done
0>========vrd info from cpld========
0>vrd_id | u64                | pmbus_en | avsbus_en | loop | pmbus_id | pmbus_addr | avs_sw | pmbus_sw | addr_9545 | domain_type | die_mask | reserved
0>  00   | 0x0001000100002017 | 0x1      | 0x1       | 0x1  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0100   | 0x0
0>  01   | 0x000300030000201b | 0x1      | 0x1       | 0x2  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x3         | 0x0300   | 0x0
0>  02   | 0x0000010500002b15 | 0x1      | 0x0       | 0x1  | 0x1      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0001   | 0x0
0>  03   | 0x0002000100002027 | 0x1      | 0x1       | 0x1  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0200   | 0x0
0>  04   | 0x000300020000202b | 0x1      | 0x1       | 0x2  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x2         | 0x0300   | 0x0
0>  05   | 0x0000020500002b25 | 0x1      | 0x0       | 0x1  | 0x2      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0002   | 0x0
0>  06   | 0x0003000400002b29 | 0x1      | 0x0       | 0x2  | 0x2      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x4         | 0x0300   | 0x0
0>================end===============
0>=============vrd info=============
0>power domain num: 7
0>power domain[00] id:0 | CORE_DVFS_TA       | PMBus NA | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
0>power domain[01] id:1 | DDR_VDD            | PMBus NA | cap:0x3 | rail:1 | addr:0x20 | def_volt: 765 mV | min_volt: 650 mV | max_volt: 850 mV
0>power domain[02] id:4 | IO_DVDD_NA         | PMBus NA | cap:0x1 | rail:0 | addr:0x2b | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
0>power domain[03] id:2 | CORE_DVFS_TB       | PMBus NB | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
0>power domain[04] id:3 | UNCORE_DVFS        | PMBus NB | cap:0x3 | rail:1 | addr:0x20 | def_volt: 990 mV | min_volt: 750 mV | max_volt:1100 mV
0>power domain[05] id:5 | IO_DVDD_NB         | PMBus NB | cap:0x1 | rail:0 | addr:0x2b | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
0>power domain[06] id:6 | DDR_VDDQ           | PMBus NB | cap:0x1 | rail:1 | addr:0x2b | def_volt:1100 mV | min_volt:1000 mV | max_volt:1200 mV
0>================end===============
0>pmbus[0] init done
0>pmbus[1] init done
0>power domain[0] CORE_DVFS_TA       | NA PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
0>power domain[1] DDR_VDD            | NA PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 765 mV | pmu:MP2882
0>power domain[4] IO_DVDD_NA         | NA PMBus        | rail:0 | addr:0x2b | def_volt: 800 mV | pmu:MP2882
0>power domain[2] CORE_DVFS_TB       | NB PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
0>power domain[3] UNCORE_DVFS        | NB PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 990 mV | pmu:MP2882
0>power domain[5] IO_DVDD_NB         | NB PMBus        | rail:0 | addr:0x2b | def_volt: 800 mV | pmu:MP2882
0>power domain[6] DDR_VDDQ           | NB PMBus        | rail:1 | addr:0x2b | def_volt:1100 mV | pmu:MP2882
0>power domain[0] CORE_DVFS_TA       is transferred to AVSBus mode
0>power domain[1] DDR_VDD            is transferred to AVSBus mode
0>power domain[2] CORE_DVFS_TB       is transferred to AVSBus mode
0>power domain[3] UNCORE_DVFS        is transferred to AVSBus mode
0>avsbus resync success
0>avsbus[0] init done
0>avsbus resync success
0>avsbus[1] init done
0>============volt boot============
0>power domain[0] volt = 1101 mV
0>power domain[1] volt =  763 mV
0>power domain[4] volt =  802 mV
0>power domain[2] volt = 1099 mV
0>power domain[3] volt = 1005 mV
0>power domain[5] volt =  804 mV
0>power domain[6] volt = 1103 mV
0>===============end===============
0>--w&h rd rail:0, 1103, CORE_DVFS_TA
0>--w&h rd rail:1, 765, CORE_DVFS_TA
0>power domain[0] set volt --> 1101 mV success
0>--w&h rd rail:0, 1099, CORE_DVFS_TB
0>--w&h rd rail:1, 1005, CORE_DVFS_TB
0>power domain[2] set volt --> 1099 mV success
0>power domain[3] set volt -->  990 mV success
0>power domain[1] set volt -->  763 mV success
0>power domain[4] set volt -->  800 mV success
0>power domain[5] set volt -->  804 mV success
0>============volt post============
0>power domain[0] volt = 1103 mV
0>power domain[1] volt =  763 mV
0>power domain[4] volt =  800 mV
0>power domain[2] volt = 1099 mV
0>power domain[3] volt =  992 mV
0>power domain[5] volt =  802 mV
0>power domain[6] volt = 1105 mV
0>===============end===============
0>Hboot1 Info RAW Dump: [0x91][0x00][0x00][0x14][0x01][0x00][0x01]
0>PowerSensorSupport[1], Cali[5120], Loss[7200]
0>Power Sensor Calibration Value[5120]!
0>the power sensor : manu id = 2peak, die id = TPA626
0>power sensor[0] init success
0>die[0] its[0] init done
0>die[0] its[1] init done
0>die[0] its[2] init done
0>die[0] its[3] init done
0>die[0] its[4] init done
0>die[0] its[5] init done
0>die[0] its[6] init done
0>die[0] its[7] init done
0>die[0] its[8] init done
0>die[0] its[9] init done
0>die[1] its[0] init done
0>die[1] its[1] init done
0>die[1] its[2] init done
0>die[1] its[3] init done
0>die[1] its[4] init done
0>die[1] its[5] init done
0>die[1] its[6] init done
0>die[1] its[7] init done
0>die[1] its[8] init done
0>die[1] its[9] init done
0>Totem[0] Core Boot Vol [1101]mv
0>Totem[0] Core Current Vol [1100]mv
0>Totem[1] Core Boot Vol [1099]mv
0>Totem[1] Core Current Vol [1100]mv
0>NA 1620V190
0>NB 1620V190
0>GetCoreBaseFreq [2900000KHZ]
0>GetCoreTurboFreq [2900000KHZ]
0>GetCustomClusterNum [10]
0>Ipu ACG Training Done!
0>AP Last Time:[0.00.01.774]
0>wait UEFI pll init...
0>done
0>acg trim start
0>core trim freq:2000, avs:0 volt:810mv
0>core trim freq:2000, avs:0 volt:810mv
0>core trim freq:2050, avs:1 volt:810mv
0>core trim freq:2050, avs:1 volt:810mv
0>core trim freq:2100, avs:2 volt:810mv
0>core trim freq:2100, avs:2 volt:810mv
0>core trim freq:2150, avs:3 volt:810mv
0>core trim freq:2150, avs:3 volt:810mv
0>core trim freq:2200, avs:4 volt:810mv
0>core trim freq:2200, avs:4 volt:810mv
0>core trim freq:2250, avs:5 volt:812mv
0>core trim freq:2250, avs:5 volt:816mv
0>core trim freq:2300, avs:6 volt:825mv
0>core trim freq:2300, avs:6 volt:828mv
0>core trim freq:2350, avs:7 volt:837mv
0>core trim freq:2350, avs:7 volt:841mv
0>core trim freq:2400, avs:8 volt:850mv
0>core trim freq:2400, avs:8 volt:854mv
0>core trim freq:2450, avs:9 volt:862mv
0>core trim freq:2450, avs:9 volt:866mv
0>core trim freq:2500, avs:10 volt:875mv
0>core trim freq:2500, avs:10 volt:879mv
0>core trim freq:2550, avs:11 volt:887mv
0>core trim freq:2550, avs:11 volt:892mv
0>core trim freq:2600, avs:12 volt:900mv
0>core trim freq:2600, avs:12 volt:904mv
0>core trim freq:2650, avs:13 volt:912mv
0>core trim freq:2650, avs:13 volt:917mv
0>core trim freq:2700, avs:14 volt:925mv
0>core trim freq:2700, avs:14 volt:930mv
0>core trim freq:2750, avs:15 volt:942mv
0>core trim freq:2750, avs:15 volt:948mv
0>core trim freq:2800, avs:16 volt:960mv
0>core trim freq:2800, avs:16 volt:966mv
0>core trim freq:2850, avs:17 volt:978mv
0>core trim freq:2850, avs:17 volt:984mv
0>core trim freq:2900, avs:18 volt:996mv
0>core trim freq:2900, avs:18 volt:1002mv
0>core trim freq:2950, avs:19 volt:1013mv
0>core trim freq:2950, avs:19 volt:1019mv
0>core trim freq:3000, avs:20 volt:1030mv
0>core trim freq:3000, avs:20 volt:1036mv
0>core trim freq:3050, avs:21 volt:1044mv
0>core trim freq:3050, avs:21 volt:1049mv
0>core trim freq:3100, avs:22 volt:1058mv
0>core trim freq:3100, avs:22 volt:1063mv
0>acg trim end
0>LDO disabled
0>[TracePoint] type[  0] cmd[  2] data[  3]
0>Interrupt 423 register OK
0>Interrupt 430 register OK
0>[TracePoint] type[  0] cmd[  2] data[  4]
0>
0>cpu 0 entering scheduler
0>[TracePoint] type[  0] cmd[  3] data[  1]
0>add your ipu app init here!
0>IpuInterfaceTaskStart Entry ...
0>ipu interface task wait parameters from uefi...
0>thermal soc task enabled
0>AP Last Time:[0.00.43.932]
0>ThermalDimmStart Entry ...
0>wait ddr init done...
0>power task start...
0>[TracePoint] type[  0] cmd[  3] data[  2]
0>ufs task wait parameters from uefi...
0>AmuTaskStart Entry ... 
0>amu task wait parameters from uefi...
0>ThermalSiwStart Entry ...
0>ThermalSiwTask idle...
0>DemtTaskStart Entry ...
0>[TracePoint] type[  0] cmd[  3] data[  3]
0>demt task wait parameters from uefi...
0>HiBoostTaskStart Entry ...
0>HiBoost task enabled
0>Waiting for UEFI parameters...
0>[TracePoint] type[  0] cmd[  3] data[  4]
0>[TracePoint] type[  0] cmd[  3] data[  5]
0>uefi parameters ready!
0>UFSProfile[0]
0>PowerPolicy[2] BenchMarkSelection[0]
0>ipu interface task wait ddr init done from uefi...
0>ufs task parameters from uefi ready
0>uncore domain[0] freq:2900
0>uncore domain[1] freq:2900
0>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
0>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
0>======sioe status======
0>thermal soc task restore underclocking_en=1
0>ppu alert temp div init done
0>TA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TA_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TA_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TA_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
0>TA_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
0>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
0>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
0>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
0>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
0>==========end==========
0>sioe init done
0>ufs task enabled
0>--> UFS profile[0]
0>UEFI parameters ready
0>UncoreMaxFreq Set to [2900 MHZ]
0>get TDP from efuse success, value = 357500mw
0>target power set to [357500]mw, brd:[357500]
0>demt task parameters from uefi ready
0>uefi ddr init finish!
0>ipu interface task wait uefi end done from uefi...
0>ddr init done, start thermal dimm task
0>======dimm status======
0>  chl[0] dimm0 2, dimm1 0
0>  chl[1] dimm0 2, dimm1 0
0>  chl[2] dimm0 2, dimm1 0
0>  chl[3] dimm0 2, dimm1 0
0>  chl[4] dimm0 2, dimm1 0
0>  chl[5] dimm0 2, dimm1 0
0>  chl[6] dimm0 2, dimm1 0
0>  chl[7] dimm0 2, dimm1 0
0>==========end==========
0>chl[0] registered, dimm mask = 0x1
0>chl[1] registered, dimm mask = 0x1
0>chl[2] registered, dimm mask = 0x1
0>chl[3] registered, dimm mask = 0x1
0>chl[4] registered, dimm mask = 0x1
0>chl[5] registered, dimm mask = 0x1
0>chl[6] registered, dimm mask = 0x1
0>chl[7] registered, dimm mask = 0x1
0>=====dimm temp params=====
0>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
0>  is_thermal_thro_en  : 1
0>  is_aref_rate_auto   : 1
0>===========end============
0>chl[0] max_temp 31'C, aref_rate 0x5 --> 0x4
0>chl[1] max_temp 31'C, aref_rate 0x5 --> 0x4
0>chl[2] max_temp 31'C, aref_rate 0x5 --> 0x4
0>chl[3] max_temp 31'C, aref_rate 0x5 --> 0x4
0>chl[4] max_temp 31'C, aref_rate 0x5 --> 0x4
0>chl[5] max_temp 31'C, aref_rate 0x5 --> 0x4
0>chl[6] max_temp 31'C, aref_rate 0x5 --> 0x4
0>chl[7] max_temp 31'C, aref_rate 0x5 --> 0x4
0>uefi end finish!
0>ipu interface task exit!
0>amu task parameters from uefi ready
0>amu task activated
0>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
]mv TB[ 810]mv
1>[1950]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[2000]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[2050]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[2100]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[2150]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[2200]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[2250]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[2300]MHZ -> Vol TA[ 820]mv TB[ 821]mv
1>[2350]MHZ -> Vol TA[ 833]mv TB[ 834]mv
1>[2400]MHZ -> Vol TA[ 845]mv TB[ 846]mv
1>[2450]MHZ -> Vol TA[ 857]mv TB[ 858]mv
1>[2500]MHZ -> Vol TA[ 869]mv TB[ 870]mv
1>[2550]MHZ -> Vol TA[ 882]mv TB[ 883]mv
1>[2600]MHZ -> Vol TA[ 894]mv TB[ 895]mv
1>[2650]MHZ -> Vol TA[ 906]mv TB[ 907]mv
1>[2700]MHZ -> Vol TA[ 919]mv TB[ 920]mv
1>[2750]MHZ -> Vol TA[ 936]mv TB[ 937]mv
1>[2800]MHZ -> Vol TA[ 954]mv TB[ 955]mv
1>[2850]MHZ -> Vol TA[ 971]mv TB[ 973]mv
1>[2900]MHZ -> Vol TA[ 989]mv TB[ 991]mv
1>[2950]MHZ -> Vol TA[1005]mv TB[1007]mv
1>[3000]MHZ -> Vol TA[1022]mv TB[1024]mv
1>[3050]MHZ -> Vol TA[1036]mv TB[1038]mv
1>[3100]MHZ -> Vol TA[1051]mv TB[1053]mv
1>Uncore VF curve:
1>Uncore [   0]MHZ -> Vol [ 810]mv
1>Uncore [ 100]MHZ -> Vol [ 810]mv
1>Uncore [ 200]MHZ -> Vol [ 810]mv
1>Uncore [ 300]MHZ -> Vol [ 810]mv
1>Uncore [ 400]MHZ -> Vol [ 810]mv
1>Uncore [ 500]MHZ -> Vol [ 879]mv
1>Uncore [ 600]MHZ -> Vol [ 879]mv
1>Uncore [ 700]MHZ -> Vol [ 879]mv
1>Uncore [ 800]MHZ -> Vol [ 879]mv
1>Uncore [ 900]MHZ -> Vol [ 879]mv
1>Uncore [1000]MHZ -> Vol [ 879]mv
1>Uncore [1100]MHZ -> Vol [ 879]mv
1>Uncore [1200]MHZ -> Vol [ 879]mv
1>Uncore [1300]MHZ -> Vol [ 879]mv
1>Uncore [1400]MHZ -> Vol [ 879]mv
1>Uncore [1500]MHZ -> Vol [ 879]mv
1>Uncore [1600]MHZ -> Vol [ 879]mv
1>Uncore [1700]MHZ -> Vol [ 879]mv
1>Uncore [1800]MHZ -> Vol [ 879]mv
1>Uncore [1900]MHZ -> Vol [ 879]mv
1>Uncore [2000]MHZ -> Vol [ 879]mv
1>Uncore [2100]MHZ -> Vol [ 886]mv
1>Uncore [2200]MHZ -> Vol [ 893]mv
1>Uncore [2300]MHZ -> Vol [ 901]mv
1>Uncore [2400]MHZ -> Vol [ 908]mv
1>Uncore [2500]MHZ -> Vol [ 916]mv
1>Uncore [2600]MHZ -> Vol [ 933]mv
1>Uncore [2700]MHZ -> Vol [ 951]mv
1>Uncore [2800]MHZ -> Vol [ 968]mv
1>Uncore [2900]MHZ -> Vol [ 985]mv
1>Uncore [3000]MHZ -> Vol [ 999]mv
1>[TracePoint] type[  0] cmd[  1] data[  6]
1>[TracePoint] type[  0] cmd[  1] data[  7]
1>
********Hello Huawei LiteOS********

KpxxxxIPU Firmware Version : V32.75.0
LiteOS Kernel Version : 5.7.0
1>Run on ChipVersion[0] Node[1] Die[0]
1>build time : Apr 24 2026 18:00:00

1>**********************************
1>
main core booting up...
1>start set affinity
1>
mpidr = 0x81040000
1>sram ecc state: 0x0, sram ecc cnt: 0x0
1>[TracePoint] type[  0] cmd[  2] data[  1]
1>[TracePoint] type[  0] cmd[  2] data[  2]
1>LRDXSD_LOCK_OFFSET = 0x0
1>LRDXSD_ERRIMSK_OFFSET = 0x0
1>LRDXSD_DBG_OTIMSK_OFFSET = 0x0
1>LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
1>LRDXSD_DBG_EN_OFFSET = 0x1
1>======tsensor params======
1>  is_trimmed       : 1
1>  underclocking_en : 1
1>===========end============
1>soc tsensor init done
1>========vrd info from cpld========
1>vrd_id | u64                | pmbus_en | avsbus_en | loop | pmbus_id | pmbus_addr | avs_sw | pmbus_sw | addr_9545 | domain_type | die_mask | reserved
1>  00   | 0x0001000100002017 | 0x1      | 0x1       | 0x1  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0100   | 0x0
1>  01   | 0x000300030000201b | 0x1      | 0x1       | 0x2  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x3         | 0x0300   | 0x0
1>  02   | 0x0000010500002b15 | 0x1      | 0x0       | 0x1  | 0x1      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0001   | 0x0
1>  03   | 0x0002000100002027 | 0x1      | 0x1       | 0x1  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0200   | 0x0
1>  04   | 0x000300020000202b | 0x1      | 0x1       | 0x2  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x2         | 0x0300   | 0x0
1>  05   | 0x0000020500002b25 | 0x1      | 0x0       | 0x1  | 0x2      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0002   | 0x0
1>  06   | 0x0003000400002b29 | 0x1      | 0x0       | 0x2  | 0x2      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x4         | 0x0300   | 0x0
1>================end===============
1>=============vrd info=============
1>power domain num: 7
1>power domain[00] id:0 | CORE_DVFS_TA       | PMBus NA | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
1>power domain[01] id:1 | DDR_VDD            | PMBus NA | cap:0x3 | rail:1 | addr:0x20 | def_volt: 765 mV | min_volt: 650 mV | max_volt: 850 mV
1>power domain[02] id:4 | IO_DVDD_NA         | PMBus NA | cap:0x1 | rail:0 | addr:0x2b | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
1>power domain[03] id:2 | CORE_DVFS_TB       | PMBus NB | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
1>power domain[04] id:3 | UNCORE_DVFS        | PMBus NB | cap:0x3 | rail:1 | addr:0x20 | def_volt: 985 mV | min_volt: 750 mV | max_volt:1100 mV
1>power domain[05] id:5 | IO_DVDD_NB         | PMBus NB | cap:0x1 | rail:0 | addr:0x2b | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
1>power domain[06] id:6 | DDR_VDDQ           | PMBus NB | cap:0x1 | rail:1 | addr:0x2b | def_volt:1100 mV | min_volt:1000 mV | max_volt:1200 mV
1>================end===============
1>pmbus[0] init done
1>pmbus[1] init done
1>power domain[0] CORE_DVFS_TA       | NA PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
1>power domain[1] DDR_VDD            | NA PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 765 mV | pmu:MP2882
1>power domain[4] IO_DVDD_NA         | NA PMBus        | rail:0 | addr:0x2b | def_volt: 800 mV | pmu:MP2882
1>power domain[2] CORE_DVFS_TB       | NB PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
1>power domain[3] UNCORE_DVFS        | NB PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 985 mV | pmu:MP2882
1>power domain[5] IO_DVDD_NB         | NB PMBus        | rail:0 | addr:0x2b | def_volt: 800 mV | pmu:MP2882
1>power domain[6] DDR_VDDQ           | NB PMBus        | rail:1 | addr:0x2b | def_volt:1100 mV | pmu:MP2882
1>power domain[0] CORE_DVFS_TA       is transferred to AVSBus mode
1>power domain[1] DDR_VDD            is transferred to AVSBus mode
1>power domain[2] CORE_DVFS_TB       is transferred to AVSBus mode
1>power domain[3] UNCORE_DVFS        is transferred to AVSBus mode
1>avsbus resync success
1>avsbus[0] init done
1>avsbus resync success
1>avsbus[1] init done
1>============volt boot============
1>power domain[0] volt = 1107 mV
1>power domain[1] volt =  771 mV
1>power domain[4] volt =  808 mV
1>power domain[2] volt = 1103 mV
1>power domain[3] volt = 1009 mV
1>power domain[5] volt =  802 mV
1>power domain[6] volt = 1105 mV
1>===============end===============
1>--w&h rd rail:0, 1107, CORE_DVFS_TA
1>--w&h rd rail:1, 765, CORE_DVFS_TA
1>power domain[0] set volt --> 1107 mV success
1>--w&h rd rail:0, 1103, CORE_DVFS_TB
1>--w&h rd rail:1, 1009, CORE_DVFS_TB
1>power domain[2] set volt --> 1103 mV success
1>power domain[3] set volt -->  990 mV success
1>power domain[1] set volt -->  769 mV success
1>power domain[4] set volt -->  806 mV success
1>power domain[5] set volt -->  800 mV success
1>============volt post============
1>power domain[0] volt = 1105 mV
1>power domain[1] volt =  769 mV
1>power domain[4] volt =  806 mV
1>power domain[2] volt = 1103 mV
1>power domain[3] volt =  990 mV
1>power domain[5] volt =  800 mV
1>power domain[6] volt = 1105 mV
1>===============end===============
1>Hboot1 Info RAW Dump: [0x01][0x00][0x00][0x14][0x01][0x00][0x01]
1>PowerSensorSupport[1], Cali[5120], Loss[0]
1>Power Sensor Calibration Value[5120]!
1>the power sensor : manu id = 2peak, die id = TPA626
1>power sensor[0] init success
1>die[0] its[0] init done
1>die[0] its[1] init done
1>die[0] its[2] init done
1>die[0] its[3] init done
1>die[0] its[4] init done
1>die[0] its[5] init done
1>die[0] its[6] init done
1>die[0] its[7] init done
1>die[0] its[8] init done
1>die[0] its[9] init done
1>die[1] its[0] init done
1>die[1] its[1] init done
1>die[1] its[2] init done
1>die[1] its[3] init done
1>die[1] its[4] init done
1>die[1] its[5] init done
1>die[1] its[6] init done
1>die[1] its[7] init done
1>die[1] its[8] init done
1>die[1] its[9] init done
1>Totem[0] Core Boot Vol [1107]mv
1>Totem[0] Core Current Vol [1100]mv
1>Totem[1] Core Boot Vol [1103]mv
1>Totem[1] Core Current Vol [1100]mv
1>NA 1620V190
1>NB 1620V190
1>GetCoreBaseFreq [2900000KHZ]
1>GetCoreTurboFreq [2900000KHZ]
1>GetCustomClusterNum [10]
1>Ipu ACG Training Done!
1>AP Last Time:[0.00.01.545]
1>wait UEFI pll init...
1>done
1>acg trim start
1>core trim freq:2000, avs:0 volt:810mv
1>core trim freq:2000, avs:0 volt:810mv
1>core trim freq:2050, avs:1 volt:810mv
1>core trim freq:2050, avs:1 volt:810mv
1>core trim freq:2100, avs:2 volt:810mv
1>core trim freq:2100, avs:2 volt:810mv
1>core trim freq:2150, avs:3 volt:810mv
1>core trim freq:2150, avs:3 volt:810mv
1>core trim freq:2200, avs:4 volt:810mv
1>core trim freq:2200, avs:4 volt:810mv
1>core trim freq:2250, avs:5 volt:810mv
1>core trim freq:2250, avs:5 volt:810mv
1>core trim freq:2300, avs:6 volt:820mv
1>core trim freq:2300, avs:6 volt:821mv
1>core trim freq:2350, avs:7 volt:833mv
1>core trim freq:2350, avs:7 volt:834mv
1>core trim freq:2400, avs:8 volt:845mv
1>core trim freq:2400, avs:8 volt:846mv
1>core trim freq:2450, avs:9 volt:857mv
1>core trim freq:2450, avs:9 volt:858mv
1>core trim freq:2500, avs:10 volt:869mv
1>core trim freq:2500, avs:10 volt:870mv
1>core trim freq:2550, avs:11 volt:882mv
1>core trim freq:2550, avs:11 volt:883mv
1>core trim freq:2600, avs:12 volt:894mv
1>core trim freq:2600, avs:12 volt:895mv
1>core trim freq:2650, avs:13 volt:906mv
1>core trim freq:2650, avs:13 volt:907mv
1>core trim freq:2700, avs:14 volt:919mv
1>core trim freq:2700, avs:14 volt:920mv
1>core trim freq:2750, avs:15 volt:936mv
1>core trim freq:2750, avs:15 volt:937mv
1>core trim freq:2800, avs:16 volt:954mv
1>core trim freq:2800, avs:16 volt:955mv
1>core trim freq:2850, avs:17 volt:971mv
1>core trim freq:2850, avs:17 volt:973mv
1>core trim freq:2900, avs:18 volt:989mv
1>core trim freq:2900, avs:18 volt:991mv
1>core trim freq:2950, avs:19 volt:1005mv
1>core trim freq:2950, avs:19 volt:1007mv
1>core trim freq:3000, avs:20 volt:1022mv
1>core trim freq:3000, avs:20 volt:1024mv
1>core trim freq:3050, avs:21 volt:1036mv
1>core trim freq:3050, avs:21 volt:1038mv
1>core trim freq:3100, avs:22 volt:1051mv
1>core trim freq:3100, avs:22 volt:1053mv
1>acg trim end
1>LDO disabled
1>[TracePoint] type[  0] cmd[  2] data[  3]
1>Interrupt 423 register OK
1>Interrupt 430 register OK
1>[TracePoint] type[  0] cmd[  2] data[  4]
1>
1>cpu 0 entering scheduler
1>[TracePoint] type[  0] cmd[  3] data[  1]
1>add your ipu app init here!
1>IpuInterfaceTaskStart Entry ...
1>ipu interface task wait parameters from uefi...
1>thermal soc task enabled
1>AP Last Time:[0.00.44.204]
1>ThermalDimmStart Entry ...
1>wait ddr init done...
1>power task start...
1>[TracePoint] type[  0] cmd[  3] data[  2]
1>ufs task wait parameters from uefi...
1>AmuTaskStart Entry ... 
1>amu task wait parameters from uefi...
1>ThermalSiwStart Entry ...
1>ThermalSiwTask idle...
1>DemtTaskStart Entry ...
1>[TracePoint] type[  0] cmd[  3] data[  3]
1>demt task wait parameters from uefi...
1>HiBoostTaskStart Entry ...
1>HiBoost task enabled
1>Waiting for UEFI parameters...
1>[TracePoint] type[  0] cmd[  3] data[  4]
1>[TracePoint] type[  0] cmd[  3] data[  5]
1>uefi parameters ready!
1>UFSProfile[0]
1>PowerPolicy[2] BenchMarkSelection[0]
1>ipu interface task wait ddr init done from uefi...
1>ufs task parameters from uefi ready
1>uncore domain[0] freq:2900
1>uncore domain[1] freq:2900
1>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
1>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
1>======sioe status======
1>thermal soc task restore underclocking_en=1
1>ppu alert temp div init done
1>TA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TA_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TA_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TA_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
1>TA_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
1>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
1>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
1>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
1>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
1>==========end==========
1>sioe init done
1>ufs task enabled
1>--> UFS profile[0]
1>UEFI parameters ready
1>UncoreMaxFreq Set to [2900 MHZ]
1>get TDP from efuse success, value = 357500mw
1>target power set to [357500]mw, brd:[357500]
1>demt task parameters from uefi ready
1>uefi ddr init finish!
1>ipu interface task wait uefi end done from uefi...
1>ddr init done, start thermal dimm task
1>======dimm status======
1>  chl[0] dimm0 2, dimm1 0
1>  chl[1] dimm0 2, dimm1 0
1>  chl[2] dimm0 2, dimm1 0
1>  chl[3] dimm0 2, dimm1 0
1>  chl[4] dimm0 2, dimm1 0
1>  chl[5] dimm0 2, dimm1 0
1>  chl[6] dimm0 2, dimm1 0
1>  chl[7] dimm0 2, dimm1 0
1>==========end==========
1>chl[0] registered, dimm mask = 0x1
1>chl[1] registered, dimm mask = 0x1
1>chl[2] registered, dimm mask = 0x1
1>chl[3] registered, dimm mask = 0x1
1>chl[4] registered, dimm mask = 0x1
1>chl[5] registered, dimm mask = 0x1
1>chl[6] registered, dimm mask = 0x1
1>chl[7] registered, dimm mask = 0x1
1>=====dimm temp params=====
1>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
1>  is_thermal_thro_en  : 1
1>  is_aref_rate_auto   : 1
1>===========end============
1>chl[0] max_temp 30'C, aref_rate 0x5 --> 0x4
1>chl[1] max_temp 30'C, aref_rate 0x5 --> 0x4
1>chl[2] max_temp 30'C, aref_rate 0x5 --> 0x4
1>chl[3] max_temp 30'C, aref_rate 0x5 --> 0x4
1>chl[4] max_temp 30'C, aref_rate 0x5 --> 0x4
1>chl[5] max_temp 30'C, aref_rate 0x5 --> 0x4
1>chl[6] max_temp 30'C, aref_rate 0x5 --> 0x4
1>chl[7] max_temp 30'C, aref_rate 0x5 --> 0x4
1>uefi end finish!
1>ipu interface task exit!
1>amu task parameters from uefi ready
1>amu task activated
1>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
TB[ 810]mv
2>[1950]MHZ -> Vol TA[ 810]mv TB[ 810]mv
2>[2000]MHZ -> Vol TA[ 810]mv TB[ 810]mv
2>[2050]MHZ -> Vol TA[ 810]mv TB[ 810]mv
2>[2100]MHZ -> Vol TA[ 810]mv TB[ 810]mv
2>[2150]MHZ -> Vol TA[ 810]mv TB[ 810]mv
2>[2200]MHZ -> Vol TA[ 810]mv TB[ 810]mv
2>[2250]MHZ -> Vol TA[ 813]mv TB[ 814]mv
2>[2300]MHZ -> Vol TA[ 826]mv TB[ 827]mv
2>[2350]MHZ -> Vol TA[ 838]mv TB[ 840]mv
2>[2400]MHZ -> Vol TA[ 851]mv TB[ 852]mv
2>[2450]MHZ -> Vol TA[ 863]mv TB[ 865]mv
2>[2500]MHZ -> Vol TA[ 876]mv TB[ 877]mv
2>[2550]MHZ -> Vol TA[ 888]mv TB[ 890]mv
2>[2600]MHZ -> Vol TA[ 901]mv TB[ 902]mv
2>[2650]MHZ -> Vol TA[ 913]mv TB[ 915]mv
2>[2700]MHZ -> Vol TA[ 926]mv TB[ 928]mv
2>[2750]MHZ -> Vol TA[ 944]mv TB[ 946]mv
2>[2800]MHZ -> Vol TA[ 962]mv TB[ 964]mv
2>[2850]MHZ -> Vol TA[ 980]mv TB[ 982]mv
2>[2900]MHZ -> Vol TA[ 998]mv TB[1000]mv
2>[2950]MHZ -> Vol TA[1015]mv TB[1017]mv
2>[3000]MHZ -> Vol TA[1032]mv TB[1034]mv
2>[3050]MHZ -> Vol TA[1046]mv TB[1048]mv
2>[3100]MHZ -> Vol TA[1060]mv TB[1062]mv
2>Uncore VF curve:
2>Uncore [   0]MHZ -> Vol [ 810]mv
2>Uncore [ 100]MHZ -> Vol [ 810]mv
2>Uncore [ 200]MHZ -> Vol [ 810]mv
2>Uncore [ 300]MHZ -> Vol [ 810]mv
2>Uncore [ 400]MHZ -> Vol [ 810]mv
2>Uncore [ 500]MHZ -> Vol [ 877]mv
2>Uncore [ 600]MHZ -> Vol [ 877]mv
2>Uncore [ 700]MHZ -> Vol [ 877]mv
2>Uncore [ 800]MHZ -> Vol [ 877]mv
2>Uncore [ 900]MHZ -> Vol [ 877]mv
2>Uncore [1000]MHZ -> Vol [ 877]mv
2>Uncore [1100]MHZ -> Vol [ 877]mv
2>Uncore [1200]MHZ -> Vol [ 877]mv
2>Uncore [1300]MHZ -> Vol [ 877]mv
2>Uncore [1400]MHZ -> Vol [ 877]mv
2>Uncore [1500]MHZ -> Vol [ 877]mv
2>Uncore [1600]MHZ -> Vol [ 877]mv
2>Uncore [1700]MHZ -> Vol [ 877]mv
2>Uncore [1800]MHZ -> Vol [ 877]mv
2>Uncore [1900]MHZ -> Vol [ 877]mv
2>Uncore [2000]MHZ -> Vol [ 877]mv
2>Uncore [2100]MHZ -> Vol [ 883]mv
2>Uncore [2200]MHZ -> Vol [ 890]mv
2>Uncore [2300]MHZ -> Vol [ 897]mv
2>Uncore [2400]MHZ -> Vol [ 904]mv
2>Uncore [2500]MHZ -> Vol [ 911]mv
2>Uncore [2600]MHZ -> Vol [ 928]mv
2>Uncore [2700]MHZ -> Vol [ 946]mv
2>Uncore [2800]MHZ -> Vol [ 962]mv
2>Uncore [2900]MHZ -> Vol [ 978]mv
2>Uncore [3000]MHZ -> Vol [ 992]mv
2>[TracePoint] type[  0] cmd[  1] data[  6]
2>[TracePoint] type[  0] cmd[  1] data[  7]
2>
********Hello Huawei LiteOS********

KpxxxxIPU Firmware Version : V32.75.0
LiteOS Kernel Version : 5.7.0
2>Run on ChipVersion[0] Node[2] Die[0]
2>build time : Apr 24 2026 18:00:00

2>**********************************
2>
main core booting up...
2>start set affinity
2>
mpidr = 0x81080000
2>sram ecc state: 0x0, sram ecc cnt: 0x0
2>[TracePoint] type[  0] cmd[  2] data[  1]
2>[TracePoint] type[  0] cmd[  2] data[  2]
2>LRDXSD_LOCK_OFFSET = 0x0
2>LRDXSD_ERRIMSK_OFFSET = 0x0
2>LRDXSD_DBG_OTIMSK_OFFSET = 0x0
2>LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
2>LRDXSD_DBG_EN_OFFSET = 0x1
2>======tsensor params======
2>  is_trimmed       : 1
2>  underclocking_en : 1
2>===========end============
2>soc tsensor init done
2>========vrd info from cpld========
2>vrd_id | u64                | pmbus_en | avsbus_en | loop | pmbus_id | pmbus_addr | avs_sw | pmbus_sw | addr_9545 | domain_type | die_mask | reserved
2>  00   | 0x0001000100002017 | 0x1      | 0x1       | 0x1  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0100   | 0x0
2>  01   | 0x000300030000201b | 0x1      | 0x1       | 0x2  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x3         | 0x0300   | 0x0
2>  02   | 0x0000010500002b15 | 0x1      | 0x0       | 0x1  | 0x1      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0001   | 0x0
2>  03   | 0x0002000100002027 | 0x1      | 0x1       | 0x1  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0200   | 0x0
2>  04   | 0x000300020000202b | 0x1      | 0x1       | 0x2  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x2         | 0x0300   | 0x0
2>  05   | 0x0000020500002b25 | 0x1      | 0x0       | 0x1  | 0x2      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0002   | 0x0
2>  06   | 0x0003000400002b29 | 0x1      | 0x0       | 0x2  | 0x2      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x4         | 0x0300   | 0x0
2>================end===============
2>=============vrd info=============
2>power domain num: 7
2>power domain[00] id:0 | CORE_DVFS_TA       | PMBus NA | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
2>power domain[01] id:1 | DDR_VDD            | PMBus NA | cap:0x3 | rail:1 | addr:0x20 | def_volt: 765 mV | min_volt: 650 mV | max_volt: 850 mV
2>power domain[02] id:4 | IO_DVDD_NA         | PMBus NA | cap:0x1 | rail:0 | addr:0x2b | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
2>power domain[03] id:2 | CORE_DVFS_TB       | PMBus NB | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
2>power domain[04] id:3 | UNCORE_DVFS        | PMBus NB | cap:0x3 | rail:1 | addr:0x20 | def_volt: 978 mV | min_volt: 750 mV | max_volt:1100 mV
2>power domain[05] id:5 | IO_DVDD_NB         | PMBus NB | cap:0x1 | rail:0 | addr:0x2b | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
2>power domain[06] id:6 | DDR_VDDQ           | PMBus NB | cap:0x1 | rail:1 | addr:0x2b | def_volt:1100 mV | min_volt:1000 mV | max_volt:1200 mV
2>================end===============
2>pmbus[0] init done
2>pmbus[1] init done
2>power domain[0] CORE_DVFS_TA       | NA PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
2>power domain[1] DDR_VDD            | NA PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 765 mV | pmu:MP2882
2>power domain[4] IO_DVDD_NA         | NA PMBus        | rail:0 | addr:0x2b | def_volt: 800 mV | pmu:MP2882
2>power domain[2] CORE_DVFS_TB       | NB PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
2>power domain[3] UNCORE_DVFS        | NB PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 978 mV | pmu:MP2882
2>power domain[5] IO_DVDD_NB         | NB PMBus        | rail:0 | addr:0x2b | def_volt: 800 mV | pmu:MP2882
2>power domain[6] DDR_VDDQ           | NB PMBus        | rail:1 | addr:0x2b | def_volt:1100 mV | pmu:MP2882
2>power domain[0] CORE_DVFS_TA       is transferred to AVSBus mode
2>power domain[1] DDR_VDD            is transferred to AVSBus mode
2>power domain[2] CORE_DVFS_TB       is transferred to AVSBus mode
2>power domain[3] UNCORE_DVFS        is transferred to AVSBus mode
2>avsbus resync success
2>avsbus[0] init done
2>avsbus resync success
2>avsbus[1] init done
2>============volt boot============
2>power domain[0] volt = 1099 mV
2>power domain[1] volt =  767 mV
2>power domain[4] volt =  802 mV
2>power domain[2] volt = 1101 mV
2>power domain[3] volt = 1005 mV
2>power domain[5] volt =  806 mV
2>power domain[6] volt = 1103 mV
2>===============end===============
2>--w&h rd rail:0, 1097, CORE_DVFS_TA
2>--w&h rd rail:1, 765, CORE_DVFS_TA
2>power domain[0] set volt --> 1097 mV success
2>--w&h rd rail:0, 1103, CORE_DVFS_TB
2>--w&h rd rail:1, 1005, CORE_DVFS_TB
2>power domain[2] set volt --> 1103 mV success
2>power domain[3] set volt -->  978 mV success
2>power domain[1] set volt -->  765 mV success
2>power domain[4] set volt -->  800 mV success
2>power domain[5] set volt -->  804 mV success
2>============volt post============
2>power domain[0] volt = 1099 mV
2>power domain[1] volt =  765 mV
2>power domain[4] volt =  800 mV
2>power domain[2] volt = 1103 mV
2>power domain[3] volt =  980 mV
2>power domain[5] volt =  802 mV
2>power domain[6] volt = 1103 mV
2>===============end===============
2>Hboot1 Info RAW Dump: [0x91][0x00][0x00][0x14][0x01][0x00][0x01]
2>PowerSensorSupport[1], Cali[5120], Loss[7200]
2>Power Sensor Calibration Value[5120]!
2>the power sensor : manu id = 2peak, die id = TPA626
2>power sensor[0] init success
2>die[0] its[0] init done
2>die[0] its[1] init done
2>die[0] its[2] init done
2>die[0] its[3] init done
2>die[0] its[4] init done
2>die[0] its[5] init done
2>die[0] its[6] init done
2>die[0] its[7] init done
2>die[0] its[8] init done
2>die[0] its[9] init done
2>die[1] its[0] init done
2>die[1] its[1] init done
2>die[1] its[2] init done
2>die[1] its[3] init done
2>die[1] its[4] init done
2>die[1] its[5] init done
2>die[1] its[6] init done
2>die[1] its[7] init done
2>die[1] its[8] init done
2>die[1] its[9] init done
2>Totem[0] Core Boot Vol [1097]mv
2>Totem[0] Core Current Vol [1100]mv
2>Totem[1] Core Boot Vol [1103]mv
2>Totem[1] Core Current Vol [1100]mv
2>NA 1620V190
2>NB 1620V190
2>GetCoreBaseFreq [2900000KHZ]
2>GetCoreTurboFreq [2900000KHZ]
2>GetCustomClusterNum [10]
2>Ipu ACG Training Done!
2>AP Last Time:[0.00.01.552]
2>wait UEFI pll init...
2>done
2>acg trim start
2>core trim freq:2000, avs:0 volt:810mv
2>core trim freq:2000, avs:0 volt:810mv
2>core trim freq:2050, avs:1 volt:810mv
2>core trim freq:2050, avs:1 volt:810mv
2>core trim freq:2100, avs:2 volt:810mv
2>core trim freq:2100, avs:2 volt:810mv
2>core trim freq:2150, avs:3 volt:810mv
2>core trim freq:2150, avs:3 volt:810mv
2>core trim freq:2200, avs:4 volt:810mv
2>core trim freq:2200, avs:4 volt:810mv
2>core trim freq:2250, avs:5 volt:813mv
2>core trim freq:2250, avs:5 volt:814mv
2>core trim freq:2300, avs:6 volt:826mv
2>core trim freq:2300, avs:6 volt:827mv
2>core trim freq:2350, avs:7 volt:838mv
2>core trim freq:2350, avs:7 volt:840mv
2>core trim freq:2400, avs:8 volt:851mv
2>core trim freq:2400, avs:8 volt:852mv
2>core trim freq:2450, avs:9 volt:863mv
2>core trim freq:2450, avs:9 volt:865mv
2>core trim freq:2500, avs:10 volt:876mv
2>core trim freq:2500, avs:10 volt:877mv
2>core trim freq:2550, avs:11 volt:888mv
2>core trim freq:2550, avs:11 volt:890mv
2>core trim freq:2600, avs:12 volt:901mv
2>core trim freq:2600, avs:12 volt:902mv
2>core trim freq:2650, avs:13 volt:913mv
2>core trim freq:2650, avs:13 volt:915mv
2>core trim freq:2700, avs:14 volt:926mv
2>core trim freq:2700, avs:14 volt:928mv
2>core trim freq:2750, avs:15 volt:944mv
2>core trim freq:2750, avs:15 volt:946mv
2>core trim freq:2800, avs:16 volt:962mv
2>core trim freq:2800, avs:16 volt:964mv
2>core trim freq:2850, avs:17 volt:980mv
2>core trim freq:2850, avs:17 volt:982mv
2>core trim freq:2900, avs:18 volt:998mv
2>core trim freq:2900, avs:18 volt:1000mv
2>core trim freq:2950, avs:19 volt:1015mv
2>core trim freq:2950, avs:19 volt:1017mv
2>core trim freq:3000, avs:20 volt:1032mv
2>core trim freq:3000, avs:20 volt:1034mv
2>core trim freq:3050, avs:21 volt:1046mv
2>core trim freq:3050, avs:21 volt:1048mv
2>core trim freq:3100, avs:22 volt:1060mv
2>core trim freq:3100, avs:22 volt:1062mv
2>acg trim end
2>LDO disabled
2>[TracePoint] type[  0] cmd[  2] data[  3]
2>Interrupt 423 register OK
2>Interrupt 430 register OK
2>[TracePoint] type[  0] cmd[  2] data[  4]
2>
2>cpu 0 entering scheduler
2>[TracePoint] type[  0] cmd[  3] data[  1]
2>add your ipu app init here!
2>IpuInterfaceTaskStart Entry ...
2>ipu interface task wait parameters from uefi...
2>thermal soc task enabled
2>AP Last Time:[0.00.44.241]
2>ThermalDimmStart Entry ...
2>wait ddr init done...
2>power task start...
2>[TracePoint] type[  0] cmd[  3] data[  2]
2>ufs task wait parameters from uefi...
2>AmuTaskStart Entry ... 
2>amu task wait parameters from uefi...
2>ThermalSiwStart Entry ...
2>ThermalSiwTask idle...
2>DemtTaskStart Entry ...
2>[TracePoint] type[  0] cmd[  3] data[  3]
2>demt task wait parameters from uefi...
2>HiBoostTaskStart Entry ...
2>HiBoost task enabled
2>Waiting for UEFI parameters...
2>[TracePoint] type[  0] cmd[  3] data[  4]
2>[TracePoint] type[  0] cmd[  3] data[  5]
2>uefi parameters ready!
2>UFSProfile[0]
2>PowerPolicy[2] BenchMarkSelection[0]
2>ipu interface task wait ddr init done from uefi...
2>ufs task parameters from uefi ready
2>uncore domain[0] freq:2900
2>uncore domain[1] freq:2900
2>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
2>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
2>======sioe status======
2>thermal soc task restore underclocking_en=1
2>ppu alert temp div init done
2>TA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
2>TA_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
2>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
2>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
2>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
2>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
2>==========end==========
2>sioe init done
2>ufs task enabled
2>--> UFS profile[0]
2>UEFI parameters ready
2>UncoreMaxFreq Set to [2900 MHZ]
2>get TDP from efuse success, value = 357500mw
2>target power set to [357500]mw, brd:[357500]
2>demt task parameters from uefi ready
2>uefi ddr init finish!
2>ipu interface task wait uefi end done from uefi...
2>ddr init done, start thermal dimm task
2>======dimm status======
2>  chl[0] dimm0 2, dimm1 0
2>  chl[1] dimm0 2, dimm1 0
2>  chl[2] dimm0 2, dimm1 0
2>  chl[3] dimm0 2, dimm1 0
2>  chl[4] dimm0 2, dimm1 0
2>  chl[5] dimm0 2, dimm1 0
2>  chl[6] dimm0 2, dimm1 0
2>  chl[7] dimm0 2, dimm1 0
2>==========end==========
2>chl[0] registered, dimm mask = 0x1
2>chl[1] registered, dimm mask = 0x1
2>chl[2] registered, dimm mask = 0x1
2>chl[3] registered, dimm mask = 0x1
2>chl[4] registered, dimm mask = 0x1
2>chl[5] registered, dimm mask = 0x1
2>chl[6] registered, dimm mask = 0x1
2>chl[7] registered, dimm mask = 0x1
2>=====dimm temp params=====
2>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
2>  is_thermal_thro_en  : 1
2>  is_aref_rate_auto   : 1
2>===========end============
2>chl[0] max_temp 31'C, aref_rate 0x5 --> 0x4
2>chl[1] max_temp 31'C, aref_rate 0x5 --> 0x4
2>chl[2] max_temp 31'C, aref_rate 0x5 --> 0x4
2>chl[3] max_temp 31'C, aref_rate 0x5 --> 0x4
2>chl[4] max_temp 31'C, aref_rate 0x5 --> 0x4
2>chl[5] max_temp 31'C, aref_rate 0x5 --> 0x4
2>chl[6] max_temp 31'C, aref_rate 0x5 --> 0x4
2>chl[7] max_temp 31'C, aref_rate 0x5 --> 0x4
2>uefi end finish!
2>ipu interface task exit!
2>amu task parameters from uefi ready
2>amu task activated
2>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
mv TB[ 810]mv
3>[1950]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2000]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2050]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2100]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2150]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2200]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2250]MHZ -> Vol TA[ 813]mv TB[ 815]mv
3>[2300]MHZ -> Vol TA[ 826]mv TB[ 827]mv
3>[2350]MHZ -> Vol TA[ 838]mv TB[ 840]mv
3>[2400]MHZ -> Vol TA[ 851]mv TB[ 853]mv
3>[2450]MHZ -> Vol TA[ 863]mv TB[ 865]mv
3>[2500]MHZ -> Vol TA[ 876]mv TB[ 878]mv
3>[2550]MHZ -> Vol TA[ 888]mv TB[ 891]mv
3>[2600]MHZ -> Vol TA[ 901]mv TB[ 903]mv
3>[2650]MHZ -> Vol TA[ 913]mv TB[ 916]mv
3>[2700]MHZ -> Vol TA[ 926]mv TB[ 929]mv
3>[2750]MHZ -> Vol TA[ 943]mv TB[ 946]mv
3>[2800]MHZ -> Vol TA[ 961]mv TB[ 964]mv
3>[2850]MHZ -> Vol TA[ 979]mv TB[ 982]mv
3>[2900]MHZ -> Vol TA[ 997]mv TB[1000]mv
3>[2950]MHZ -> Vol TA[1014]mv TB[1017]mv
3>[3000]MHZ -> Vol TA[1031]mv TB[1035]mv
3>[3050]MHZ -> Vol TA[1045]mv TB[1048]mv
3>[3100]MHZ -> Vol TA[1059]mv TB[1062]mv
3>Uncore VF curve:
3>Uncore [   0]MHZ -> Vol [ 810]mv
3>Uncore [ 100]MHZ -> Vol [ 810]mv
3>Uncore [ 200]MHZ -> Vol [ 810]mv
3>Uncore [ 300]MHZ -> Vol [ 810]mv
3>Uncore [ 400]MHZ -> Vol [ 810]mv
3>Uncore [ 500]MHZ -> Vol [ 877]mv
3>Uncore [ 600]MHZ -> Vol [ 877]mv
3>Uncore [ 700]MHZ -> Vol [ 877]mv
3>Uncore [ 800]MHZ -> Vol [ 877]mv
3>Uncore [ 900]MHZ -> Vol [ 877]mv
3>Uncore [1000]MHZ -> Vol [ 877]mv
3>Uncore [1100]MHZ -> Vol [ 877]mv
3>Uncore [1200]MHZ -> Vol [ 877]mv
3>Uncore [1300]MHZ -> Vol [ 877]mv
3>Uncore [1400]MHZ -> Vol [ 877]mv
3>Uncore [1500]MHZ -> Vol [ 877]mv
3>Uncore [1600]MHZ -> Vol [ 877]mv
3>Uncore [1700]MHZ -> Vol [ 877]mv
3>Uncore [1800]MHZ -> Vol [ 877]mv
3>Uncore [1900]MHZ -> Vol [ 877]mv
3>Uncore [2000]MHZ -> Vol [ 877]mv
3>Uncore [2100]MHZ -> Vol [ 884]mv
3>Uncore [2200]MHZ -> Vol [ 891]mv
3>Uncore [2300]MHZ -> Vol [ 898]mv
3>Uncore [2400]MHZ -> Vol [ 905]mv
3>Uncore [2500]MHZ -> Vol [ 912]mv
3>Uncore [2600]MHZ -> Vol [ 929]mv
3>Uncore [2700]MHZ -> Vol [ 947]mv
3>Uncore [2800]MHZ -> Vol [ 963]mv
3>Uncore [2900]MHZ -> Vol [ 980]mv
3>Uncore [3000]MHZ -> Vol [ 994]mv
3>[TracePoint] type[  0] cmd[  1] data[  6]
3>[TracePoint] type[  0] cmd[  1] data[  7]
3>
********Hello Huawei LiteOS********

KpxxxxIPU Firmware Version : V32.75.0
LiteOS Kernel Version : 5.7.0
3>Run on ChipVersion[0] Node[3] Die[0]
3>build time : Apr 24 2026 18:00:00

3>**********************************
3>
main core booting up...
3>start set affinity
3>
mpidr = 0x810c0000
3>sram ecc state: 0x0, sram ecc cnt: 0x0
3>[TracePoint] type[  0] cmd[  2] data[  1]
3>[TracePoint] type[  0] cmd[  2] data[  2]
3>LRDXSD_LOCK_OFFSET = 0x0
3>LRDXSD_ERRIMSK_OFFSET = 0x0
3>LRDXSD_DBG_OTIMSK_OFFSET = 0x0
3>LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
3>LRDXSD_DBG_EN_OFFSET = 0x1
3>======tsensor params======
3>  is_trimmed       : 1
3>  underclocking_en : 1
3>===========end============
3>soc tsensor init done
3>========vrd info from cpld========
3>vrd_id | u64                | pmbus_en | avsbus_en | loop | pmbus_id | pmbus_addr | avs_sw | pmbus_sw | addr_9545 | domain_type | die_mask | reserved
3>  00   | 0x0001000100002017 | 0x1      | 0x1       | 0x1  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0100   | 0x0
3>  01   | 0x000300030000201b | 0x1      | 0x1       | 0x2  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x3         | 0x0300   | 0x0
3>  02   | 0x0000010500002b15 | 0x1      | 0x0       | 0x1  | 0x1      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0001   | 0x0
3>  03   | 0x0002000100002027 | 0x1      | 0x1       | 0x1  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0200   | 0x0
3>  04   | 0x000300020000202b | 0x1      | 0x1       | 0x2  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x2         | 0x0300   | 0x0
3>  05   | 0x0000020500002b25 | 0x1      | 0x0       | 0x1  | 0x2      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0002   | 0x0
3>  06   | 0x0003000400002b29 | 0x1      | 0x0       | 0x2  | 0x2      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x4         | 0x0300   | 0x0
3>================end===============
3>=============vrd info=============
3>power domain num: 7
3>power domain[00] id:0 | CORE_DVFS_TA       | PMBus NA | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
3>power domain[01] id:1 | DDR_VDD            | PMBus NA | cap:0x3 | rail:1 | addr:0x20 | def_volt: 765 mV | min_volt: 650 mV | max_volt: 850 mV
3>power domain[02] id:4 | IO_DVDD_NA         | PMBus NA | cap:0x1 | rail:0 | addr:0x2b | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
3>power domain[03] id:2 | CORE_DVFS_TB       | PMBus NB | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
3>power domain[04] id:3 | UNCORE_DVFS        | PMBus NB | cap:0x3 | rail:1 | addr:0x20 | def_volt: 980 mV | min_volt: 750 mV | max_volt:1100 mV
3>power domain[05] id:5 | IO_DVDD_NB         | PMBus NB | cap:0x1 | rail:0 | addr:0x2b | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
3>power domain[06] id:6 | DDR_VDDQ           | PMBus NB | cap:0x1 | rail:1 | addr:0x2b | def_volt:1100 mV | min_volt:1000 mV | max_volt:1200 mV
3>================end===============
3>pmbus[0] init done
3>pmbus[1] init done
3>power domain[0] CORE_DVFS_TA       | NA PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
3>power domain[1] DDR_VDD            | NA PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 765 mV | pmu:MP2882
3>power domain[4] IO_DVDD_NA         | NA PMBus        | rail:0 | addr:0x2b | def_volt: 800 mV | pmu:MP2882
3>power domain[2] CORE_DVFS_TB       | NB PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
3>power domain[3] UNCORE_DVFS        | NB PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 980 mV | pmu:MP2882
3>power domain[5] IO_DVDD_NB         | NB PMBus        | rail:0 | addr:0x2b | def_volt: 800 mV | pmu:MP2882
3>power domain[6] DDR_VDDQ           | NB PMBus        | rail:1 | addr:0x2b | def_volt:1100 mV | pmu:MP2882
3>power domain[0] CORE_DVFS_TA       is transferred to AVSBus mode
3>power domain[1] DDR_VDD            is transferred to AVSBus mode
3>power domain[2] CORE_DVFS_TB       is transferred to AVSBus mode
3>power domain[3] UNCORE_DVFS        is transferred to AVSBus mode
3>avsbus resync success
3>avsbus[0] init done
3>avsbus resync success
3>avsbus[1] init done
3>============volt boot============
3>power domain[0] volt = 1099 mV
3>power domain[1] volt =  765 mV
3>power domain[4] volt =  804 mV
3>power domain[2] volt = 1107 mV
3>power domain[3] volt = 1007 mV
3>power domain[5] volt =  800 mV
3>power domain[6] volt = 1101 mV
3>===============end===============
3>--w&h rd rail:0, 1099, CORE_DVFS_TA
3>--w&h rd rail:1, 765, CORE_DVFS_TA
3>power domain[0] set volt --> 1099 mV success
3>--w&h rd rail:0, 1107, CORE_DVFS_TB
3>--w&h rd rail:1, 1009, CORE_DVFS_TB
3>power domain[2] set volt --> 1107 mV success
3>power domain[3] set volt -->  982 mV success
3>power domain[1] set volt -->  763 mV success
3>power domain[4] set volt -->  802 mV success
3>power domain[5] set volt -->  800 mV success
3>============volt post============
3>power domain[0] volt = 1099 mV
3>power domain[1] volt =  763 mV
3>power domain[4] volt =  804 mV
3>power domain[2] volt = 1107 mV
3>power domain[3] volt =  984 mV
3>power domain[5] volt =  798 mV
3>power domain[6] volt = 1103 mV
3>===============end===============
3>Hboot1 Info RAW Dump: [0x01][0x00][0x00][0x14][0x01][0x00][0x01]
3>PowerSensorSupport[1], Cali[5120], Loss[0]
3>Power Sensor Calibration Value[5120]!
3>the power sensor : manu id = 2peak, die id = TPA626
3>power sensor[0] init success
3>die[0] its[0] init done
3>die[0] its[1] init done
3>die[0] its[2] init done
3>die[0] its[3] init done
3>die[0] its[4] init done
3>die[0] its[5] init done
3>die[0] its[6] init done
3>die[0] its[7] init done
3>die[0] its[8] init done
3>die[0] its[9] init done
3>die[1] its[0] init done
3>die[1] its[1] init done
3>die[1] its[2] init done
3>die[1] its[3] init done
3>die[1] its[4] init done
3>die[1] its[5] init done
3>die[1] its[6] init done
3>die[1] its[7] init done
3>die[1] its[8] init done
3>die[1] its[9] init done
3>Totem[0] Core Boot Vol [1099]mv
3>Totem[0] Core Current Vol [1100]mv
3>Totem[1] Core Boot Vol [1107]mv
3>Totem[1] Core Current Vol [1100]mv
3>NA 1620V190
3>NB 1620V190
3>GetCoreBaseFreq [2900000KHZ]
3>GetCoreTurboFreq [2900000KHZ]
3>GetCustomClusterNum [10]
3>Ipu ACG Training Done!
3>AP Last Time:[0.00.01.548]
3>wait UEFI pll init...
3>done
3>acg trim start
3>core trim freq:2000, avs:0 volt:810mv
3>core trim freq:2000, avs:0 volt:810mv
3>core trim freq:2050, avs:1 volt:810mv
3>core trim freq:2050, avs:1 volt:810mv
3>core trim freq:2100, avs:2 volt:810mv
3>core trim freq:2100, avs:2 volt:810mv
3>core trim freq:2150, avs:3 volt:810mv
3>core trim freq:2150, avs:3 volt:810mv
3>core trim freq:2200, avs:4 volt:810mv
3>core trim freq:2200, avs:4 volt:810mv
3>core trim freq:2250, avs:5 volt:813mv
3>core trim freq:2250, avs:5 volt:815mv
3>core trim freq:2300, avs:6 volt:826mv
3>core trim freq:2300, avs:6 volt:827mv
3>core trim freq:2350, avs:7 volt:838mv
3>core trim freq:2350, avs:7 volt:840mv
3>core trim freq:2400, avs:8 volt:851mv
3>core trim freq:2400, avs:8 volt:853mv
3>core trim freq:2450, avs:9 volt:863mv
3>core trim freq:2450, avs:9 volt:865mv
3>core trim freq:2500, avs:10 volt:876mv
3>core trim freq:2500, avs:10 volt:878mv
3>core trim freq:2550, avs:11 volt:888mv
3>core trim freq:2550, avs:11 volt:891mv
3>core trim freq:2600, avs:12 volt:901mv
3>core trim freq:2600, avs:12 volt:903mv
3>core trim freq:2650, avs:13 volt:913mv
3>core trim freq:2650, avs:13 volt:916mv
3>core trim freq:2700, avs:14 volt:926mv
3>core trim freq:2700, avs:14 volt:929mv
3>core trim freq:2750, avs:15 volt:943mv
3>core trim freq:2750, avs:15 volt:946mv
3>core trim freq:2800, avs:16 volt:961mv
3>core trim freq:2800, avs:16 volt:964mv
3>core trim freq:2850, avs:17 volt:979mv
3>core trim freq:2850, avs:17 volt:982mv
3>core trim freq:2900, avs:18 volt:997mv
3>core trim freq:2900, avs:18 volt:1000mv
3>core trim freq:2950, avs:19 volt:1014mv
3>core trim freq:2950, avs:19 volt:1017mv
3>core trim freq:3000, avs:20 volt:1031mv
3>core trim freq:3000, avs:20 volt:1035mv
3>core trim freq:3050, avs:21 volt:1045mv
3>core trim freq:3050, avs:21 volt:1048mv
3>core trim freq:3100, avs:22 volt:1059mv
3>core trim freq:3100, avs:22 volt:1062mv
3>acg trim end
3>LDO disabled
3>[TracePoint] type[  0] cmd[  2] data[  3]
3>Interrupt 423 register OK
3>Interrupt 430 register OK
3>[TracePoint] type[  0] cmd[  2] data[  4]
3>
3>cpu 0 entering scheduler
3>[TracePoint] type[  0] cmd[  3] data[  1]
3>add your ipu app init here!
3>IpuInterfaceTaskStart Entry ...
3>ipu interface task wait parameters from uefi...
3>thermal soc task enabled
3>AP Last Time:[0.00.44.197]
3>ThermalDimmStart Entry ...
3>wait ddr init done...
3>power task start...
3>[TracePoint] type[  0] cmd[  3] data[  2]
3>ufs task wait parameters from uefi...
3>AmuTaskStart Entry ... 
3>amu task wait parameters from uefi...
3>ThermalSiwStart Entry ...
3>ThermalSiwTask idle...
3>DemtTaskStart Entry ...
3>[TracePoint] type[  0] cmd[  3] data[  3]
3>demt task wait parameters from uefi...
3>HiBoostTaskStart Entry ...
3>HiBoost task enabled
3>Waiting for UEFI parameters...
3>[TracePoint] type[  0] cmd[  3] data[  4]
3>[TracePoint] type[  0] cmd[  3] data[  5]
3>uefi parameters ready!
3>UFSProfile[0]
3>PowerPolicy[2] BenchMarkSelection[0]
3>ipu interface task wait ddr init done from uefi...
3>ufs task parameters from uefi ready
3>uncore domain[0] freq:2900
3>uncore domain[1] freq:2900
3>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
3>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
3>======sioe status======
3>thermal soc task restore underclocking_en=1
3>ppu alert temp div init done
3>TA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
3>TA_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
3>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
3>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
3>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
3>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
3>==========end==========
3>sioe init done
3>ufs task enabled
3>--> UFS profile[0]
3>UEFI parameters ready
3>UncoreMaxFreq Set to [2900 MHZ]
3>get TDP from efuse success, value = 357500mw
3>target power set to [357500]mw, brd:[357500]
3>demt task parameters from uefi ready
3>uefi ddr init finish!
3>ipu interface task wait uefi end done from uefi...
3>ddr init done, start thermal dimm task
3>======dimm status======
3>  chl[0] dimm0 2, dimm1 0
3>  chl[1] dimm0 2, dimm1 0
3>  chl[2] dimm0 2, dimm1 0
3>  chl[3] dimm0 2, dimm1 0
3>  chl[4] dimm0 2, dimm1 0
3>  chl[5] dimm0 2, dimm1 0
3>  chl[6] dimm0 2, dimm1 0
3>  chl[7] dimm0 2, dimm1 0
3>==========end==========
3>chl[0] registered, dimm mask = 0x1
3>chl[1] registered, dimm mask = 0x1
3>chl[2] registered, dimm mask = 0x1
3>chl[3] registered, dimm mask = 0x1
3>chl[4] registered, dimm mask = 0x1
3>chl[5] registered, dimm mask = 0x1
3>chl[6] registered, dimm mask = 0x1
3>chl[7] registered, dimm mask = 0x1
3>=====dimm temp params=====
3>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
3>  is_thermal_thro_en  : 1
3>  is_aref_rate_auto   : 1
3>===========end============
3>chl[0] max_temp 33'C, aref_rate 0x5 --> 0x4
3>chl[1] max_temp 33'C, aref_rate 0x5 --> 0x4
3>chl[2] max_temp 33'C, aref_rate 0x5 --> 0x4
3>chl[3] max_temp 33'C, aref_rate 0x5 --> 0x4
3>chl[4] max_temp 33'C, aref_rate 0x5 --> 0x4
3>chl[5] max_temp 33'C, aref_rate 0x5 --> 0x4
3>chl[6] max_temp 33'C, aref_rate 0x5 --> 0x4
3>chl[7] max_temp 33'C, aref_rate 0x5 --> 0x4
3>uefi end finish!
3>ipu interface task exit!
3>amu task parameters from uefi ready
3>amu task activated
3>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
[0.08.35.084]IpmiCmdReportPcieMMIO start
[0.08.51.731]IpmiCmdReportPcieMMIO end
pool addr          pool size    used size     free size    max free node size   used node num     free node num      UsageWaterLine
---------------    --------     -------       --------     --------------       -------------      ------------      ------------
0x840908c350       0x22880      0x189d8       0x9c38       0x9550               0xbf               0x3                0x19330        

********Hello Huawei LiteOS********

KpxxxxIMU Firmware Version : V32.75.0
LiteOS Kernel Version : 5.7.0
Run on ChipVersion[0] Node[0] Die[2]
build time : Apr 24 2026 18:00:00

**********************************

main core booting up...
start set affinity

mpidr = 0x81020000
sram ecc state: 0x0, sram ecc cnt: 0x0
[0.00.00.033]node 0 begins init all serdes.
BoardInfo->NodeNum 4.
BoardInfo->NodeId 0.
BoardInfo->InfoVersion 5.
BoardInfo->NASerdesSceneMode 3.
BoardInfo->NBSerdesSceneMode 3.
BoardInfo->HccsTopologyType 12.
BoardInfo->BoardId 0.
ChipVersionIsPro: 0.
BoardInfo Node 0, SerdesUseMode: 1 1 12 4 4 4 4  1 1 1 4 4 4 4 
BoardInfo Node 1, SerdesUseMode: 12 13 12 4 4 4 4  1 1 12 4 4 4 4 
BoardInfo Node 2, SerdesUseMode: 1 1 1 4 4 4 4  1 1 1 4 4 4 4 
BoardInfo Node 3, SerdesUseMode: 1 1 1 4 4 4 4  1 1 1 4 4 4 4 
BoardInfo Node 0, SerdesRxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 1, SerdesRxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 2, SerdesRxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 3, SerdesRxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 0, SerdesTxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 1, SerdesTxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 2, SerdesTxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
BoardInfo Node 3, SerdesTxPolarityReverse: 0 0 0 0 0 0 0  0 0 0 0 0 0 0 
serdessdk version: 2.0_5.0_20241203_imu
node_id 0, die 0, ind 0, usemode 1 begin serdes-init.
node_id 0, die 0, ind 1, usemode 1 begin serdes-init.
node_id 0, die 0, ind 2, usemode 12 begin serdes-init.
chip_id 0, die 0, ind 2, usemode 12 don't support, power down macro!
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
NodeId 0, DieId 0, Macro 2, power-down DS succeed.
node_id 0, die 2, ind 0, usemode 1 begin serdes-init.
node_id 0, die 2, ind 1, usemode 1 begin serdes-init.
chip serdes init status:0x0.
[0.00.00.455]node 0 ends init all serdes.
link[0] freq_type:1 | peer_chip_type:2 | peer_node_id:0 | peer_link_id:0
link[1] freq_type:1 | peer_chip_type:2 | peer_node_id:0 | peer_link_id:0
link[2] freq_type:1 | peer_chip_type:2 | peer_node_id:0 | peer_link_id:0
link[3] freq_type:1 | peer_chip_type:2 | peer_node_id:0 | peer_link_id:0
link[4] freq_type:1 | peer_chip_type:2 | peer_node_id:0 | peer_link_id:0
link[5] freq_type:1 | peer_chip_type:1 | peer_node_id:1 | peer_link_id:4
link[6] freq_type:1 | peer_chip_type:1 | peer_node_id:2 | peer_link_id:7
link[7] freq_type:1 | peer_chip_type:1 | peer_node_id:3 | peer_link_id:5
register hccs done
nodeId 0, dieId 0, linkId 0, FFE info: fir_pre1 -5, fir_main 58, fir_post1 0
node_id 0, die 0, ind 4, usemode 4 begin serdes-init.
nodeId 0, dieId 0, linkId 1, FFE info: fir_pre1 -5, fir_main 58, fir_post1 0
node_id 0, die 0, ind 3, usemode 4 begin serdes-init.
nodeId 0, dieId 0, linkId 2, FFE info: fir_pre1 -5, fir_main 58, fir_post1 0
node_id 0, die 0, ind 5, usemode 4 begin serdes-init.
nodeId 0, dieId 0, linkId 3, FFE info: fir_pre1 -5, fir_main 58, fir_post1 0
node_id 0, die 0, ind 6, usemode 4 begin serdes-init.
nodeId 0, dieId 1, linkId 0, FFE info: fir_pre1 -5, fir_main 58, fir_post1 0
node_id 0, die 2, ind 4, usemode 4 begin serdes-init.
nodeId 0, dieId 1, linkId 1, FFE info: fir_pre1 -5, fir_main 58, fir_post1 0
node_id 0, die 2, ind 3, usemode 4 begin serdes-init.
nodeId 0, dieId 1, linkId 2, FFE info: fir_pre1 -6, fir_main 45, fir_post1 12
node_id 0, die 2, ind 5, usemode 4 begin serdes-init.
nodeId 0, dieId 1, linkId 3, FFE info: fir_pre1 -6, fir_main 45, fir_post1 12
node_id 0, die 2, ind 6, usemode 4 begin serdes-init.
hccs init start...
pa ring link down success
reset pa success
link[0] pcs init success
link[1] pcs init success
link[2] pcs init success
link[3] pcs init success
link[4] pcs init success
link[5] pcs init success
link[6] pcs init success
link[7] pcs init success
release reset pa success
link[0] macro adapt done (lane_mask=0xff) (0ms)
link[1] macro adapt done (lane_mask=0xff) (0ms)
link[2] macro adapt done (lane_mask=0xff) (0ms)
link[3] macro adapt done (lane_mask=0xff) (0ms)
link[4] macro adapt done (lane_mask=0xff) (0ms)
link[5] macro adapt done (lane_mask=0xff) (0ms)
link[6] macro adapt done (lane_mask=0xff) (0ms)
link[7] macro adapt done (lane_mask=0xff) (0ms)
link[5] pcs training success (10ms)
link[6] pcs training success (10ms)
link[7] pcs training success (10ms)
link[5] training success (20ms)
link[6] training success (20ms)
link[7] training success (20ms)
link[0] pcs training success (4600ms)
link[0] training success (4610ms)
link[2] pcs training success (4820ms)
link[2] training success (4830ms)
link[1] pcs training success (5010ms)
link[1] training success (5020ms)
link[3] pcs training success (5260ms)
link[3] training success (5270ms)
link[4] pcs training success (5640ms)
link[4] training success (5650ms)
link[0]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
BWAY_PCS_ST_PCS_LINK_FSM_RECORD = 0x1248
HLLC_ST_FSM_1_REG = 0x3
link[1]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
BWAY_PCS_ST_PCS_LINK_FSM_RECORD = 0x1248
HLLC_ST_FSM_1_REG = 0x3
link[2]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
BWAY_PCS_ST_PCS_LINK_FSM_RECORD = 0x1248
HLLC_ST_FSM_1_REG = 0x3
link[3]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
BWAY_PCS_ST_PCS_LINK_FSM_RECORD = 0x1248
HLLC_ST_FSM_1_REG = 0x3
link[4]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
BWAY_PCS_ST_PCS_LINK_FSM_RECORD = 0x1248
HLLC_ST_FSM_1_REG = 0x3
link[5]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
BWAY_PCS_ST_PCS_LINK_FSM_RECORD = 0x1248
HLLC_ST_FSM_1_REG = 0x3
link[6]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
BWAY_PCS_ST_PCS_LINK_FSM_RECORD = 0x1248
HLLC_ST_FSM_1_REG = 0x3
link[7]:
BWAY_PCS_ST_FSM_0_REG = 0x118
BWAY_PCS_ST_PCS_LANE_MODE_CHANGE_REG = 0xff31
BWAY_PCS_ST_PCS_LINK_FSM_RECORD = 0x1248
HLLC_ST_FSM_1_REG = 0x3
link training success
pa[0] linkEn = 0xf
pa[0] allNodeLink0 = 0x0
pa[0] allNodeLink1 = 0xf000f
pa[0] connected with sw node
pa[1] linkEn = 0xf
pa[1] allNodeLink0 = 0x8420
pa[1] allNodeLink1 = 0x10001
pa[1] connected with sw node
pa init success
COM_PAID_INTLV_REG = 0xe
paid decode init success
pa[0] PA_PM_BASE_INFO = 0x0
pa[0] PA_PM_MAP_LINK_NUM = 0x1111
pa[1] PA_PM_BASE_INFO = 0xee0842
pa[1] PA_PM_MAP_LINK_NUM = 0x2811
hccs performace config success
pa ring link up success
hccs init done
hccs access test start
node[0] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[1] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[2] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[3] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0x5a5a5a5a
node[1] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
node[2] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
node[3] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
hccs access test success
======hccs status======
  node[0] mask: expected = 0xff, link up = 0xff, width reduction = 0x0, link down = 0x0
  node[1] mask: expected = 0xff, link up = 0xff, width reduction = 0x0, link down = 0x0
  node[2] mask: expected = 0xff, link up = 0xff, width reduction = 0x0, link down = 0x0
  node[3] mask: expected = 0xff, link up = 0xff, width reduction = 0x0, link down = 0x0
==========end==========
report hccs status success
node[0] IOMGMT_ICL_SUBCTRL_SC_IMU_MULTI_CTRL2 = 0xa5a5a5a5
LRDXSD_LOCK_OFFSET = 0x0
LRDXSD_ERRIMSK_OFFSET = 0x0
LRDXSD_DBG_OTIMSK_OFFSET = 0x0
LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
LRDXSD_DBG_EN_OFFSET = 0x1
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
Master Imu wait the UEFI to finish some-init done.
ID[0x1967c8]!
[ERR]Don't support the flash, CS[0] ID[0x1967c8]!!
ID[0xffffff]!
[ERR]Don't support the flash, CS[1] ID[0xffffff]!!
[ERR]Warnning, Select Default flash 
sfdp detect, try to get dummy data from hboot1 first.
ID[0x1967c8]!
flash 0 support sfdp.
Interrupt 423 register OK
Interrupt 425 register OK
Interrupt 427 register OK
Interrupt 429 register OK
Interrupt 430 register OK
Interrupt 431 register OK
Interrupt 436 register OK

cpu 0 entering scheduler
[IMU] Watchdog Initialization done!
ScmiTaskEntry start.
Interrupt 456 register OK
Interrupt 469 register OK
Interrupt 482 register OK
Interrupt 495 register OK
Interrupt 508 register OK
Interrupt 521 register OK
Interrupt 534 register OK
Interrupt 547 register OK
starting Fpc Isolation Task end
starting fdm Err Info Task end
starting Roce recovery Task end
starting Ce_Storm Contrl Task end
starting Ras_Data_Update Task end
Interrupt 459 register OK
Interrupt 472 register OK
Interrupt 485 register OK
Interrupt 498 register OK
Interrupt 511 register OK
Interrupt 524 register OK
Interrupt 537 register OK
Interrupt 550 register OK
[0.00.46.641]Real time now 2026.10.24 20:16:15
NIC CARD[0][0]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[0][1]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[1][0]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[1][1]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[2][0]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[2][1]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[3][0]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
NIC CARD[3][1]: nicPresent = 0x0, nicType = 0x0, nicSfpPresent = 0x0
Init heart-beat-task end
pool addr          pool size    used size     free size    max free node size   used node num     free node num      UsageWaterLine
---------------    --------     -------       --------     --------------       -------------      ------------      ------------
0x840908c350       0x22880      0x190c0       0x9550       0x9550               0x5e               0x1                0x19330        
Get Setup Config.
Node 0, Die 0 ImpState is 0 skip exec.
Node 0, Die 2 ImpState is 0 skip exec.
Node 1, Die 0 ImpState is 0 skip exec.
Node 1, Die 2 ImpState is 0 skip exec.
Node 2, Die 0 ImpState is 0 skip exec.
Node 2, Die 2 ImpState is 0 skip exec.
Node 3, Die 0 ImpState is 0 skip exec.
Node 3, Die 2 ImpState is 0 skip exec.
pwr cap[0]: 0, 63
pwr cap[1]: f, 27
pwr cap[2]: 1, 0
[0.01.21.385]DDR Rreserved for IMU: len = 3e00000
[LOG]head = 0x0, tail = 0x30d0, logSize = 0x30d0
copy registry.json file success
Set component all release version to sram end.
ipcMsgSend success
HsmLogInit Ret 1, Len 4, val 0x32022a06
[0.01.21.429]starting ras Init
nodeId = 0, dieId = 0, isSasExist = 0.
nodeId = 0, dieId = 2, isSasExist = 0.
nodeId = 1, dieId = 0, isSasExist = 0.
nodeId = 1, dieId = 2, isSasExist = 0.
nodeId = 2, dieId = 0, isSasExist = 0.
nodeId = 2, dieId = 2, isSasExist = 0.
nodeId = 3, dieId = 0, isSasExist = 0.
nodeId = 3, dieId = 2, isSasExist = 0.
Mce Table head exist!
RasIntRegister init 452 
RasIntRegister init 453 
RasIntRegister init 64 
RasIntRegister init 65 
RasIntRegister init 465 
RasIntRegister init 466 
RasIntRegister init 86 
RasIntRegister init 87 
RasIntRegister init 478 
RasIntRegister init 479 
RasIntRegister init 108 
RasIntRegister init 109 
RasIntRegister init 491 
RasIntRegister init 492 
RasIntRegister init 130 
RasIntRegister init 131 
RasIntRegister init 504 
RasIntRegister init 505 
RasIntRegister init 152 
RasIntRegister init 153 
RasIntRegister init 517 
RasIntRegister init 518 
RasIntRegister init 174 
RasIntRegister init 175 
RasIntRegister init 530 
RasIntRegister init 531 
RasIntRegister init 196 
RasIntRegister init 197 
RasIntRegister init 543 
RasIntRegister init 544 
RasIntRegister init 218 
RasIntRegister init 219 
RasIntRegister init 76 
RasIntRegister init 98 
RasIntRegister init 120 
RasIntRegister init 142 
RasIntRegister init 164 
RasIntRegister init 186 
RasIntRegister init 208 
RasIntRegister init 230 
[0.01.21.551]starting ras end
[ERR]ipc result error, result 0x28010009
ipcMsgSend fail
Send tee measure to HSM respon:0
get mem silk data length: 192
0: skt = 0 logic = 2 phy = 0 
1: skt = 0 logic = 2 phy = 0 
2: skt = 0 logic = 7 phy = 1 
3: skt = 0 logic = 7 phy = 1 
4: skt = 0 logic = 0 phy = 2 
5: skt = 0 logic = 0 phy = 2 
6: skt = 0 logic = 5 phy = 3 
7: skt = 0 logic = 5 phy = 3 
8: skt = 1 logic = 2 phy = 0 
9: skt = 1 logic = 2 phy = 0 
10: skt = 1 logic = 7 phy = 1 
11: skt = 1 logic = 7 phy = 1 
12: skt = 1 logic = 0 phy = 2 
13: skt = 1 logic = 0 phy = 2 
14: skt = 1 logic = 5 phy = 3 
15: skt = 1 logic = 5 phy = 3 
16: skt = 0 logic = 3 phy = 4 
17: skt = 0 logic = 3 phy = 4 
18: skt = 0 logic = 6 phy = 5 
19: skt = 0 logic = 6 phy = 5 
20: skt = 0 logic = 1 phy = 6 
21: skt = 1 logic = 1 phy = 6 
22: skt = 1 logic = 1 phy = 6 
23: skt = 1 logic = 4 phy = 7 
24: skt = 1 logic = 4 phy = 7 
25: skt = 1 logic = 6 phy = 5 
26: skt = 1 logic = 6 phy = 5 
27: skt = 1 logic = 3 phy = 4 
28: skt = 0 logic = 1 phy = 6 
29: skt = 0 logic = 4 phy = 7 
30: skt = 0 logic = 4 phy = 7 
31: skt = 1 logic = 3 phy = 4 
32: skt = 2 logic = 2 phy = 0 
33: skt = 2 logic = 2 phy = 0 
34: skt = 2 logic = 7 phy = 1 
35: skt = 2 logic = 7 phy = 1 
36: skt = 2 logic = 0 phy = 2 
37: skt = 3 logic = 4 phy = 7 
38: skt = 3 logic = 1 phy = 6 
39: skt = 3 logic = 4 phy = 7 
40: skt = 3 logic = 1 phy = 6 
41: skt = 3 logic = 6 phy = 5 
42: skt = 3 logic = 6 phy = 5 
43: skt = 3 logic = 3 phy = 4 
44: skt = 3 logic = 3 phy = 4 
45: skt = 2 logic = 4 phy = 7 
46: skt = 2 logic = 4 phy = 7 
47: skt = 2 logic = 1 phy = 6 
48: skt = 2 logic = 1 phy = 6 
49: skt = 2 logic = 6 phy = 5 
50: skt = 2 logic = 6 phy = 5 
51: skt = 2 logic = 3 phy = 4 
52: skt = 2 logic = 3 phy = 4 
53: skt = 3 logic = 5 phy = 3 
54: skt = 3 logic = 5 phy = 3 
55: skt = 3 logic = 0 phy = 2 
56: skt = 3 logic = 0 phy = 2 
57: skt = 3 logic = 7 phy = 1 
58: skt = 3 logic = 7 phy = 1 
59: skt = 3 logic = 2 phy = 0 
60: skt = 3 logic = 2 phy = 0 
61: skt = 2 logic = 5 phy = 3 
62: skt = 2 logic = 5 phy = 3 
63: skt = 2 logic = 0 phy = 2 
[0.02.04.590]TF Heartbeat Start
[0.02.09.606]PCIE INIT DONE.
g_mctpQueueCount(48) > tabCnt(42)
slotNum = 0x8
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[0] port:20  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[1] port:22  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[2] port:20  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[3] port:22  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[4] port:20  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[5] port:22  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[6] port:24  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[7] port:26  pcieSlotCtrl.data (after)0x14801c0.

Interrupt 454 register OK
Interrupt 467 register OK
Interrupt 480 register OK
Interrupt 493 register OK
Interrupt 506 register OK
Interrupt 519 register OK
Interrupt 532 register OK
Interrupt 545 register OK
data = 0x0
pmt Init done

Add ep: bdf=a200 eid=9 epCnt=1 eid_alloc=a
Add ep: bdf=c400 eid=a epCnt=1 eid_alloc=b
Add ep: bdf=d000 eid=b epCnt=1 eid_alloc=c
[0.02.09.839]slot[0] port:20 begin to power OFF.
[0.02.09.840]slot[1] port:22 begin to power OFF.
[0.02.09.843]slot[2] port:20 begin to power OFF.
[0.02.09.847]slot[3] port:22 begin to power OFF.
[0.02.09.851]slot[4] port:20 begin to power ON.
[0.02.09.856]slot[5] port:22 begin to power ON.
[0.02.09.860]slot[6] port:24 begin to power ON.
[0.02.09.864]slot[7] port:26 begin to power ON.
Add ep: bdf=300 eid=c epCnt=1 eid_alloc=d
mctp task ok.
[0.03.23.829]BIOS POST END.
Create SetReportPcieMmioToBmc ok.
Start SetReportPcieMmioToBmc ok.
Enter current value process
TB[ 810]mv
0>[1950]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[2000]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[2050]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[2100]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[2150]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[2200]MHZ -> Vol TA[ 810]mv TB[ 810]mv
0>[2250]MHZ -> Vol TA[ 812]mv TB[ 816]mv
0>[2300]MHZ -> Vol TA[ 825]mv TB[ 828]mv
0>[2350]MHZ -> Vol TA[ 837]mv TB[ 841]mv
0>[2400]MHZ -> Vol TA[ 850]mv TB[ 854]mv
0>[2450]MHZ -> Vol TA[ 862]mv TB[ 866]mv
0>[2500]MHZ -> Vol TA[ 875]mv TB[ 879]mv
0>[2550]MHZ -> Vol TA[ 887]mv TB[ 892]mv
0>[2600]MHZ -> Vol TA[ 900]mv TB[ 904]mv
0>[2650]MHZ -> Vol TA[ 912]mv TB[ 917]mv
0>[2700]MHZ -> Vol TA[ 925]mv TB[ 930]mv
0>[2750]MHZ -> Vol TA[ 942]mv TB[ 948]mv
0>[2800]MHZ -> Vol TA[ 960]mv TB[ 966]mv
0>[2850]MHZ -> Vol TA[ 978]mv TB[ 984]mv
0>[2900]MHZ -> Vol TA[ 996]mv TB[1002]mv
0>[2950]MHZ -> Vol TA[1013]mv TB[1019]mv
0>[3000]MHZ -> Vol TA[1030]mv TB[1036]mv
0>[3050]MHZ -> Vol TA[1044]mv TB[1049]mv
0>[3100]MHZ -> Vol TA[1058]mv TB[1063]mv
0>Uncore VF curve:
0>Uncore [   0]MHZ -> Vol [ 810]mv
0>Uncore [ 100]MHZ -> Vol [ 810]mv
0>Uncore [ 200]MHZ -> Vol [ 810]mv
0>Uncore [ 300]MHZ -> Vol [ 810]mv
0>Uncore [ 400]MHZ -> Vol [ 810]mv
0>Uncore [ 500]MHZ -> Vol [ 881]mv
0>Uncore [ 600]MHZ -> Vol [ 881]mv
0>Uncore [ 700]MHZ -> Vol [ 881]mv
0>Uncore [ 800]MHZ -> Vol [ 881]mv
0>Uncore [ 900]MHZ -> Vol [ 881]mv
0>Uncore [1000]MHZ -> Vol [ 881]mv
0>Uncore [1100]MHZ -> Vol [ 881]mv
0>Uncore [1200]MHZ -> Vol [ 881]mv
0>Uncore [1300]MHZ -> Vol [ 881]mv
0>Uncore [1400]MHZ -> Vol [ 881]mv
0>Uncore [1500]MHZ -> Vol [ 881]mv
0>Uncore [1600]MHZ -> Vol [ 881]mv
0>Uncore [1700]MHZ -> Vol [ 881]mv
0>Uncore [1800]MHZ -> Vol [ 881]mv
0>Uncore [1900]MHZ -> Vol [ 881]mv
0>Uncore [2000]MHZ -> Vol [ 881]mv
0>Uncore [2100]MHZ -> Vol [ 888]mv
0>Uncore [2200]MHZ -> Vol [ 896]mv
0>Uncore [2300]MHZ -> Vol [ 904]mv
0>Uncore [2400]MHZ -> Vol [ 912]mv
0>Uncore [2500]MHZ -> Vol [ 920]mv
0>Uncore [2600]MHZ -> Vol [ 937]mv
0>Uncore [2700]MHZ -> Vol [ 955]mv
0>Uncore [2800]MHZ -> Vol [ 972]mv
0>Uncore [2900]MHZ -> Vol [ 990]mv
0>Uncore [3000]MHZ -> Vol [1004]mv
0>[TracePoint] type[  0] cmd[  1] data[  6]
0>[TracePoint] type[  0] cmd[  1] data[  7]
0>
********Hello Huawei LiteOS********

KpxxxxIPU Firmware Version : V32.75.0
LiteOS Kernel Version : 5.7.0
0>Run on ChipVersion[0] Node[0] Die[0]
0>build time : Apr 24 2026 18:00:00

0>**********************************
0>
main core booting up...
0>start set affinity
0>
mpidr = 0x81000000
0>sram ecc state: 0x0, sram ecc cnt: 0x0
0>[TracePoint] type[  0] cmd[  2] data[  1]
0>[TracePoint] type[  0] cmd[  2] data[  2]
0>LRDXSD_LOCK_OFFSET = 0x0
0>LRDXSD_ERRIMSK_OFFSET = 0x0
0>LRDXSD_DBG_OTIMSK_OFFSET = 0x0
0>LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
0>LRDXSD_DBG_EN_OFFSET = 0x1
0>======tsensor params======
0>  is_trimmed       : 1
0>  underclocking_en : 1
0>===========end============
0>soc tsensor init done
0>========vrd info from cpld========
0>vrd_id | u64                | pmbus_en | avsbus_en | loop | pmbus_id | pmbus_addr | avs_sw | pmbus_sw | addr_9545 | domain_type | die_mask | reserved
0>  00   | 0x0001000100002017 | 0x1      | 0x1       | 0x1  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0100   | 0x0
0>  01   | 0x000300030000201b | 0x1      | 0x1       | 0x2  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x3         | 0x0300   | 0x0
0>  02   | 0x0000010500002b15 | 0x1      | 0x0       | 0x1  | 0x1      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0001   | 0x0
0>  03   | 0x0002000100002027 | 0x1      | 0x1       | 0x1  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0200   | 0x0
0>  04   | 0x000300020000202b | 0x1      | 0x1       | 0x2  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x2         | 0x0300   | 0x0
0>  05   | 0x0000020500002b25 | 0x1      | 0x0       | 0x1  | 0x2      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0002   | 0x0
0>  06   | 0x0003000400002b29 | 0x1      | 0x0       | 0x2  | 0x2      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x4         | 0x0300   | 0x0
0>================end===============
0>=============vrd info=============
0>power domain num: 7
0>power domain[00] id:0 | CORE_DVFS_TA       | PMBus NA | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
0>power domain[01] id:1 | DDR_VDD            | PMBus NA | cap:0x3 | rail:1 | addr:0x20 | def_volt: 765 mV | min_volt: 650 mV | max_volt: 850 mV
0>power domain[02] id:4 | IO_DVDD_NA         | PMBus NA | cap:0x1 | rail:0 | addr:0x2b | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
0>power domain[03] id:2 | CORE_DVFS_TB       | PMBus NB | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
0>power domain[04] id:3 | UNCORE_DVFS        | PMBus NB | cap:0x3 | rail:1 | addr:0x20 | def_volt: 990 mV | min_volt: 750 mV | max_volt:1100 mV
0>power domain[05] id:5 | IO_DVDD_NB         | PMBus NB | cap:0x1 | rail:0 | addr:0x2b | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
0>power domain[06] id:6 | DDR_VDDQ           | PMBus NB | cap:0x1 | rail:1 | addr:0x2b | def_volt:1100 mV | min_volt:1000 mV | max_volt:1200 mV
0>================end===============
0>pmbus[0] init done
0>pmbus[1] init done
0>power domain[0] CORE_DVFS_TA       | NA PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
0>power domain[1] DDR_VDD            | NA PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 765 mV | pmu:MP2882
0>power domain[4] IO_DVDD_NA         | NA PMBus        | rail:0 | addr:0x2b | def_volt: 800 mV | pmu:MP2882
0>power domain[2] CORE_DVFS_TB       | NB PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
0>power domain[3] UNCORE_DVFS        | NB PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 990 mV | pmu:MP2882
0>power domain[5] IO_DVDD_NB         | NB PMBus        | rail:0 | addr:0x2b | def_volt: 800 mV | pmu:MP2882
0>power domain[6] DDR_VDDQ           | NB PMBus        | rail:1 | addr:0x2b | def_volt:1100 mV | pmu:MP2882
0>power domain[0] CORE_DVFS_TA       is transferred to AVSBus mode
0>power domain[1] DDR_VDD            is transferred to AVSBus mode
0>power domain[2] CORE_DVFS_TB       is transferred to AVSBus mode
0>power domain[3] UNCORE_DVFS        is transferred to AVSBus mode
0>avsbus resync success
0>avsbus[0] init done
0>avsbus resync success
0>avsbus[1] init done
0>============volt boot============
0>power domain[0] volt = 1101 mV
0>power domain[1] volt =  763 mV
0>power domain[4] volt =  804 mV
0>power domain[2] volt = 1099 mV
0>power domain[3] volt = 1005 mV
0>power domain[5] volt =  804 mV
0>power domain[6] volt = 1103 mV
0>===============end===============
0>--w&h rd rail:0, 1101, CORE_DVFS_TA
0>--w&h rd rail:1, 765, CORE_DVFS_TA
0>power domain[0] set volt --> 1103 mV success
0>--w&h rd rail:0, 1099, CORE_DVFS_TB
0>--w&h rd rail:1, 1005, CORE_DVFS_TB
0>power domain[2] set volt --> 1101 mV success
0>power domain[3] set volt -->  990 mV success
0>power domain[1] set volt -->  761 mV success
0>power domain[4] set volt -->  800 mV success
0>power domain[5] set volt -->  804 mV success
0>============volt post============
0>power domain[0] volt = 1101 mV
0>power domain[1] volt =  761 mV
0>power domain[4] volt =  800 mV
0>power domain[2] volt = 1099 mV
0>power domain[3] volt =  990 mV
0>power domain[5] volt =  802 mV
0>power domain[6] volt = 1105 mV
0>===============end===============
0>Hboot1 Info RAW Dump: [0x91][0x00][0x00][0x14][0x01][0x00][0x01]
0>PowerSensorSupport[1], Cali[5120], Loss[7200]
0>Power Sensor Calibration Value[5120]!
0>the power sensor : manu id = 2peak, die id = TPA626
0>power sensor[0] init success
0>die[0] its[0] init done
0>die[0] its[1] init done
0>die[0] its[2] init done
0>die[0] its[3] init done
0>die[0] its[4] init done
0>die[0] its[5] init done
0>die[0] its[6] init done
0>die[0] its[7] init done
0>die[0] its[8] init done
0>die[0] its[9] init done
0>die[1] its[0] init done
0>die[1] its[1] init done
0>die[1] its[2] init done
0>die[1] its[3] init done
0>die[1] its[4] init done
0>die[1] its[5] init done
0>die[1] its[6] init done
0>die[1] its[7] init done
0>die[1] its[8] init done
0>die[1] its[9] init done
0>Totem[0] Core Boot Vol [1103]mv
0>Totem[0] Core Current Vol [1100]mv
0>Totem[1] Core Boot Vol [1099]mv
0>Totem[1] Core Current Vol [1100]mv
0>NA 1620V190
0>NB 1620V190
0>GetCoreBaseFreq [2900000KHZ]
0>GetCoreTurboFreq [2900000KHZ]
0>GetCustomClusterNum [10]
0>Ipu ACG Training Done!
0>AP Last Time:[0.00.01.776]
0>wait UEFI pll init...
0>done
0>acg trim start
0>core trim freq:2000, avs:0 volt:810mv
0>core trim freq:2000, avs:0 volt:810mv
0>core trim freq:2050, avs:1 volt:810mv
0>core trim freq:2050, avs:1 volt:810mv
0>core trim freq:2100, avs:2 volt:810mv
0>core trim freq:2100, avs:2 volt:810mv
0>core trim freq:2150, avs:3 volt:810mv
0>core trim freq:2150, avs:3 volt:810mv
0>core trim freq:2200, avs:4 volt:810mv
0>core trim freq:2200, avs:4 volt:810mv
0>core trim freq:2250, avs:5 volt:812mv
0>core trim freq:2250, avs:5 volt:816mv
0>core trim freq:2300, avs:6 volt:825mv
0>core trim freq:2300, avs:6 volt:828mv
0>core trim freq:2350, avs:7 volt:837mv
0>core trim freq:2350, avs:7 volt:841mv
0>core trim freq:2400, avs:8 volt:850mv
0>core trim freq:2400, avs:8 volt:854mv
0>core trim freq:2450, avs:9 volt:862mv
0>core trim freq:2450, avs:9 volt:866mv
0>core trim freq:2500, avs:10 volt:875mv
0>core trim freq:2500, avs:10 volt:879mv
0>core trim freq:2550, avs:11 volt:887mv
0>core trim freq:2550, avs:11 volt:892mv
0>core trim freq:2600, avs:12 volt:900mv
0>core trim freq:2600, avs:12 volt:904mv
0>core trim freq:2650, avs:13 volt:912mv
0>core trim freq:2650, avs:13 volt:917mv
0>core trim freq:2700, avs:14 volt:925mv
0>core trim freq:2700, avs:14 volt:930mv
0>core trim freq:2750, avs:15 volt:942mv
0>core trim freq:2750, avs:15 volt:948mv
0>core trim freq:2800, avs:16 volt:960mv
0>core trim freq:2800, avs:16 volt:966mv
0>core trim freq:2850, avs:17 volt:978mv
0>core trim freq:2850, avs:17 volt:984mv
0>core trim freq:2900, avs:18 volt:996mv
0>core trim freq:2900, avs:18 volt:1002mv
0>core trim freq:2950, avs:19 volt:1013mv
0>core trim freq:2950, avs:19 volt:1019mv
0>core trim freq:3000, avs:20 volt:1030mv
0>core trim freq:3000, avs:20 volt:1036mv
0>core trim freq:3050, avs:21 volt:1044mv
0>core trim freq:3050, avs:21 volt:1049mv
0>core trim freq:3100, avs:22 volt:1058mv
0>core trim freq:3100, avs:22 volt:1063mv
0>acg trim end
0>LDO disabled
0>[TracePoint] type[  0] cmd[  2] data[  3]
0>Interrupt 423 register OK
0>Interrupt 430 register OK
0>[TracePoint] type[  0] cmd[  2] data[  4]
0>
0>cpu 0 entering scheduler
0>[TracePoint] type[  0] cmd[  3] data[  1]
0>add your ipu app init here!
0>IpuInterfaceTaskStart Entry ...
0>ipu interface task wait parameters from uefi...
0>thermal soc task enabled
0>AP Last Time:[0.00.44.149]
0>ThermalDimmStart Entry ...
0>wait ddr init done...
0>power task start...
0>[TracePoint] type[  0] cmd[  3] data[  2]
0>ufs task wait parameters from uefi...
0>AmuTaskStart Entry ... 
0>amu task wait parameters from uefi...
0>ThermalSiwStart Entry ...
0>ThermalSiwTask idle...
0>DemtTaskStart Entry ...
0>[TracePoint] type[  0] cmd[  3] data[  3]
0>demt task wait parameters from uefi...
0>HiBoostTaskStart Entry ...
0>HiBoost task enabled
0>Waiting for UEFI parameters...
0>[TracePoint] type[  0] cmd[  3] data[  4]
0>[TracePoint] type[  0] cmd[  3] data[  5]
0>uefi parameters ready!
0>UFSProfile[0]
0>PowerPolicy[2] BenchMarkSelection[0]
0>ipu interface task wait ddr init done from uefi...
0>ufs task parameters from uefi ready
0>uncore domain[0] freq:2900
0>uncore domain[1] freq:2900
0>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
0>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
0>======sioe status======
0>thermal soc task restore underclocking_en=1
0>ppu alert temp div init done
0>TA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TA_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TA_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TA_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
0>TA_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
0>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
0>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
0>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
0>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
0>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
0>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
0>==========end==========
0>sioe init done
0>ufs task enabled
0>--> UFS profile[0]
0>UEFI parameters ready
0>UncoreMaxFreq Set to [2900 MHZ]
0>get TDP from efuse success, value = 357500mw
0>target power set to [357500]mw, brd:[357500]
0>demt task parameters from uefi ready
0>uefi ddr init finish!
0>ipu interface task wait uefi end done from uefi...
0>ddr init done, start thermal dimm task
0>======dimm status======
0>  chl[0] dimm0 2, dimm1 0
0>  chl[1] dimm0 2, dimm1 0
0>  chl[2] dimm0 2, dimm1 0
0>  chl[3] dimm0 2, dimm1 0
0>  chl[4] dimm0 2, dimm1 0
0>  chl[5] dimm0 2, dimm1 0
0>  chl[6] dimm0 2, dimm1 0
0>  chl[7] dimm0 2, dimm1 0
0>==========end==========
0>chl[0] registered, dimm mask = 0x1
0>chl[1] registered, dimm mask = 0x1
0>chl[2] registered, dimm mask = 0x1
0>chl[3] registered, dimm mask = 0x1
0>chl[4] registered, dimm mask = 0x1
0>chl[5] registered, dimm mask = 0x1
0>chl[6] registered, dimm mask = 0x1
0>chl[7] registered, dimm mask = 0x1
0>=====dimm temp params=====
0>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
0>  is_thermal_thro_en  : 1
0>  is_aref_rate_auto   : 1
0>===========end============
0>chl[0] max_temp 30'C, aref_rate 0x5 --> 0x4
0>chl[1] max_temp 30'C, aref_rate 0x5 --> 0x4
0>chl[2] max_temp 30'C, aref_rate 0x5 --> 0x4
0>chl[3] max_temp 30'C, aref_rate 0x5 --> 0x4
0>chl[4] max_temp 30'C, aref_rate 0x5 --> 0x4
0>chl[5] max_temp 30'C, aref_rate 0x5 --> 0x4
0>chl[6] max_temp 30'C, aref_rate 0x5 --> 0x4
0>chl[7] max_temp 30'C, aref_rate 0x5 --> 0x4
0>uefi end finish!
0>ipu interface task exit!
0>amu task parameters from uefi ready
0>amu task activated
0>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
]mv TB[ 810]mv
1>[1950]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[2000]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[2050]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[2100]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[2150]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[2200]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[2250]MHZ -> Vol TA[ 810]mv TB[ 810]mv
1>[2300]MHZ -> Vol TA[ 820]mv TB[ 821]mv
1>[2350]MHZ -> Vol TA[ 833]mv TB[ 834]mv
1>[2400]MHZ -> Vol TA[ 845]mv TB[ 846]mv
1>[2450]MHZ -> Vol TA[ 857]mv TB[ 858]mv
1>[2500]MHZ -> Vol TA[ 869]mv TB[ 870]mv
1>[2550]MHZ -> Vol TA[ 882]mv TB[ 883]mv
1>[2600]MHZ -> Vol TA[ 894]mv TB[ 895]mv
1>[2650]MHZ -> Vol TA[ 906]mv TB[ 907]mv
1>[2700]MHZ -> Vol TA[ 919]mv TB[ 920]mv
1>[2750]MHZ -> Vol TA[ 936]mv TB[ 937]mv
1>[2800]MHZ -> Vol TA[ 954]mv TB[ 955]mv
1>[2850]MHZ -> Vol TA[ 971]mv TB[ 973]mv
1>[2900]MHZ -> Vol TA[ 989]mv TB[ 991]mv
1>[2950]MHZ -> Vol TA[1005]mv TB[1007]mv
1>[3000]MHZ -> Vol TA[1022]mv TB[1024]mv
1>[3050]MHZ -> Vol TA[1036]mv TB[1038]mv
1>[3100]MHZ -> Vol TA[1051]mv TB[1053]mv
1>Uncore VF curve:
1>Uncore [   0]MHZ -> Vol [ 810]mv
1>Uncore [ 100]MHZ -> Vol [ 810]mv
1>Uncore [ 200]MHZ -> Vol [ 810]mv
1>Uncore [ 300]MHZ -> Vol [ 810]mv
1>Uncore [ 400]MHZ -> Vol [ 810]mv
1>Uncore [ 500]MHZ -> Vol [ 879]mv
1>Uncore [ 600]MHZ -> Vol [ 879]mv
1>Uncore [ 700]MHZ -> Vol [ 879]mv
1>Uncore [ 800]MHZ -> Vol [ 879]mv
1>Uncore [ 900]MHZ -> Vol [ 879]mv
1>Uncore [1000]MHZ -> Vol [ 879]mv
1>Uncore [1100]MHZ -> Vol [ 879]mv
1>Uncore [1200]MHZ -> Vol [ 879]mv
1>Uncore [1300]MHZ -> Vol [ 879]mv
1>Uncore [1400]MHZ -> Vol [ 879]mv
1>Uncore [1500]MHZ -> Vol [ 879]mv
1>Uncore [1600]MHZ -> Vol [ 879]mv
1>Uncore [1700]MHZ -> Vol [ 879]mv
1>Uncore [1800]MHZ -> Vol [ 879]mv
1>Uncore [1900]MHZ -> Vol [ 879]mv
1>Uncore [2000]MHZ -> Vol [ 879]mv
1>Uncore [2100]MHZ -> Vol [ 886]mv
1>Uncore [2200]MHZ -> Vol [ 893]mv
1>Uncore [2300]MHZ -> Vol [ 901]mv
1>Uncore [2400]MHZ -> Vol [ 908]mv
1>Uncore [2500]MHZ -> Vol [ 916]mv
1>Uncore [2600]MHZ -> Vol [ 933]mv
1>Uncore [2700]MHZ -> Vol [ 951]mv
1>Uncore [2800]MHZ -> Vol [ 968]mv
1>Uncore [2900]MHZ -> Vol [ 985]mv
1>Uncore [3000]MHZ -> Vol [ 999]mv
1>[TracePoint] type[  0] cmd[  1] data[  6]
1>[TracePoint] type[  0] cmd[  1] data[  7]
1>
********Hello Huawei LiteOS********

KpxxxxIPU Firmware Version : V32.75.0
LiteOS Kernel Version : 5.7.0
1>Run on ChipVersion[0] Node[1] Die[0]
1>build time : Apr 24 2026 18:00:00

1>**********************************
1>
main core booting up...
1>start set affinity
1>
mpidr = 0x81040000
1>sram ecc state: 0x0, sram ecc cnt: 0x0
1>[TracePoint] type[  0] cmd[  2] data[  1]
1>[TracePoint] type[  0] cmd[  2] data[  2]
1>LRDXSD_LOCK_OFFSET = 0x0
1>LRDXSD_ERRIMSK_OFFSET = 0x0
1>LRDXSD_DBG_OTIMSK_OFFSET = 0x0
1>LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
1>LRDXSD_DBG_EN_OFFSET = 0x1
1>======tsensor params======
1>  is_trimmed       : 1
1>  underclocking_en : 1
1>===========end============
1>soc tsensor init done
1>========vrd info from cpld========
1>vrd_id | u64                | pmbus_en | avsbus_en | loop | pmbus_id | pmbus_addr | avs_sw | pmbus_sw | addr_9545 | domain_type | die_mask | reserved
1>  00   | 0x0001000100002017 | 0x1      | 0x1       | 0x1  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0100   | 0x0
1>  01   | 0x000300030000201b | 0x1      | 0x1       | 0x2  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x3         | 0x0300   | 0x0
1>  02   | 0x0000010500002b15 | 0x1      | 0x0       | 0x1  | 0x1      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0001   | 0x0
1>  03   | 0x0002000100002027 | 0x1      | 0x1       | 0x1  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0200   | 0x0
1>  04   | 0x000300020000202b | 0x1      | 0x1       | 0x2  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x2         | 0x0300   | 0x0
1>  05   | 0x0000020500002b25 | 0x1      | 0x0       | 0x1  | 0x2      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0002   | 0x0
1>  06   | 0x0003000400002b29 | 0x1      | 0x0       | 0x2  | 0x2      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x4         | 0x0300   | 0x0
1>================end===============
1>=============vrd info=============
1>power domain num: 7
1>power domain[00] id:0 | CORE_DVFS_TA       | PMBus NA | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
1>power domain[01] id:1 | DDR_VDD            | PMBus NA | cap:0x3 | rail:1 | addr:0x20 | def_volt: 765 mV | min_volt: 650 mV | max_volt: 850 mV
1>power domain[02] id:4 | IO_DVDD_NA         | PMBus NA | cap:0x1 | rail:0 | addr:0x2b | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
1>power domain[03] id:2 | CORE_DVFS_TB       | PMBus NB | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
1>power domain[04] id:3 | UNCORE_DVFS        | PMBus NB | cap:0x3 | rail:1 | addr:0x20 | def_volt: 985 mV | min_volt: 750 mV | max_volt:1100 mV
1>power domain[05] id:5 | IO_DVDD_NB         | PMBus NB | cap:0x1 | rail:0 | addr:0x2b | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
1>power domain[06] id:6 | DDR_VDDQ           | PMBus NB | cap:0x1 | rail:1 | addr:0x2b | def_volt:1100 mV | min_volt:1000 mV | max_volt:1200 mV
1>================end===============
1>pmbus[0] init done
1>pmbus[1] init done
1>power domain[0] CORE_DVFS_TA       | NA PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
1>power domain[1] DDR_VDD            | NA PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 765 mV | pmu:MP2882
1>power domain[4] IO_DVDD_NA         | NA PMBus        | rail:0 | addr:0x2b | def_volt: 800 mV | pmu:MP2882
1>power domain[2] CORE_DVFS_TB       | NB PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
1>power domain[3] UNCORE_DVFS        | NB PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 985 mV | pmu:MP2882
1>power domain[5] IO_DVDD_NB         | NB PMBus        | rail:0 | addr:0x2b | def_volt: 800 mV | pmu:MP2882
1>power domain[6] DDR_VDDQ           | NB PMBus        | rail:1 | addr:0x2b | def_volt:1100 mV | pmu:MP2882
1>power domain[0] CORE_DVFS_TA       is transferred to AVSBus mode
1>power domain[1] DDR_VDD            is transferred to AVSBus mode
1>power domain[2] CORE_DVFS_TB       is transferred to AVSBus mode
1>power domain[3] UNCORE_DVFS        is transferred to AVSBus mode
1>avsbus resync success
1>avsbus[0] init done
1>avsbus resync success
1>avsbus[1] init done
1>============volt boot============
1>power domain[0] volt = 1105 mV
1>power domain[1] volt =  769 mV
1>power domain[4] volt =  810 mV
1>power domain[2] volt = 1103 mV
1>power domain[3] volt = 1009 mV
1>power domain[5] volt =  802 mV
1>power domain[6] volt = 1103 mV
1>===============end===============
1>--w&h rd rail:0, 1105, CORE_DVFS_TA
1>--w&h rd rail:1, 765, CORE_DVFS_TA
1>power domain[0] set volt --> 1107 mV success
1>--w&h rd rail:0, 1103, CORE_DVFS_TB
1>--w&h rd rail:1, 1007, CORE_DVFS_TB
1>power domain[2] set volt --> 1103 mV success
1>power domain[3] set volt -->  988 mV success
1>power domain[1] set volt -->  767 mV success
1>power domain[4] set volt -->  808 mV success
1>power domain[5] set volt -->  800 mV success
1>============volt post============
1>power domain[0] volt = 1107 mV
1>power domain[1] volt =  769 mV
1>power domain[4] volt =  806 mV
1>power domain[2] volt = 1103 mV
1>power domain[3] volt =  990 mV
1>power domain[5] volt =  800 mV
1>power domain[6] volt = 1105 mV
1>===============end===============
1>Hboot1 Info RAW Dump: [0x01][0x00][0x00][0x14][0x01][0x00][0x01]
1>PowerSensorSupport[1], Cali[5120], Loss[0]
1>Power Sensor Calibration Value[5120]!
1>the power sensor : manu id = 2peak, die id = TPA626
1>power sensor[0] init success
1>die[0] its[0] init done
1>die[0] its[1] init done
1>die[0] its[2] init done
1>die[0] its[3] init done
1>die[0] its[4] init done
1>die[0] its[5] init done
1>die[0] its[6] init done
1>die[0] its[7] init done
1>die[0] its[8] init done
1>die[0] its[9] init done
1>die[1] its[0] init done
1>die[1] its[1] init done
1>die[1] its[2] init done
1>die[1] its[3] init done
1>die[1] its[4] init done
1>die[1] its[5] init done
1>die[1] its[6] init done
1>die[1] its[7] init done
1>die[1] its[8] init done
1>die[1] its[9] init done
1>Totem[0] Core Boot Vol [1107]mv
1>Totem[0] Core Current Vol [1100]mv
1>Totem[1] Core Boot Vol [1103]mv
1>Totem[1] Core Current Vol [1100]mv
1>NA 1620V190
1>NB 1620V190
1>GetCoreBaseFreq [2900000KHZ]
1>GetCoreTurboFreq [2900000KHZ]
1>GetCustomClusterNum [10]
1>Ipu ACG Training Done!
1>AP Last Time:[0.00.01.551]
1>wait UEFI pll init...
1>done
1>acg trim start
1>core trim freq:2000, avs:0 volt:810mv
1>core trim freq:2000, avs:0 volt:810mv
1>core trim freq:2050, avs:1 volt:810mv
1>core trim freq:2050, avs:1 volt:810mv
1>core trim freq:2100, avs:2 volt:810mv
1>core trim freq:2100, avs:2 volt:810mv
1>core trim freq:2150, avs:3 volt:810mv
1>core trim freq:2150, avs:3 volt:810mv
1>core trim freq:2200, avs:4 volt:810mv
1>core trim freq:2200, avs:4 volt:810mv
1>core trim freq:2250, avs:5 volt:810mv
1>core trim freq:2250, avs:5 volt:810mv
1>core trim freq:2300, avs:6 volt:820mv
1>core trim freq:2300, avs:6 volt:821mv
1>core trim freq:2350, avs:7 volt:833mv
1>core trim freq:2350, avs:7 volt:834mv
1>core trim freq:2400, avs:8 volt:845mv
1>core trim freq:2400, avs:8 volt:846mv
1>core trim freq:2450, avs:9 volt:857mv
1>core trim freq:2450, avs:9 volt:858mv
1>core trim freq:2500, avs:10 volt:869mv
1>core trim freq:2500, avs:10 volt:870mv
1>core trim freq:2550, avs:11 volt:882mv
1>core trim freq:2550, avs:11 volt:883mv
1>core trim freq:2600, avs:12 volt:894mv
1>core trim freq:2600, avs:12 volt:895mv
1>core trim freq:2650, avs:13 volt:906mv
1>core trim freq:2650, avs:13 volt:907mv
1>core trim freq:2700, avs:14 volt:919mv
1>core trim freq:2700, avs:14 volt:920mv
1>core trim freq:2750, avs:15 volt:936mv
1>core trim freq:2750, avs:15 volt:937mv
1>core trim freq:2800, avs:16 volt:954mv
1>core trim freq:2800, avs:16 volt:955mv
1>core trim freq:2850, avs:17 volt:971mv
1>core trim freq:2850, avs:17 volt:973mv
1>core trim freq:2900, avs:18 volt:989mv
1>core trim freq:2900, avs:18 volt:991mv
1>core trim freq:2950, avs:19 volt:1005mv
1>core trim freq:2950, avs:19 volt:1007mv
1>core trim freq:3000, avs:20 volt:1022mv
1>core trim freq:3000, avs:20 volt:1024mv
1>core trim freq:3050, avs:21 volt:1036mv
1>core trim freq:3050, avs:21 volt:1038mv
1>core trim freq:3100, avs:22 volt:1051mv
1>core trim freq:3100, avs:22 volt:1053mv
1>acg trim end
1>LDO disabled
1>[TracePoint] type[  0] cmd[  2] data[  3]
1>Interrupt 423 register OK
1>Interrupt 430 register OK
1>[TracePoint] type[  0] cmd[  2] data[  4]
1>
1>cpu 0 entering scheduler
1>[TracePoint] type[  0] cmd[  3] data[  1]
1>add your ipu app init here!
1>IpuInterfaceTaskStart Entry ...
1>ipu interface task wait parameters from uefi...
1>thermal soc task enabled
1>AP Last Time:[0.00.44.424]
1>ThermalDimmStart Entry ...
1>wait ddr init done...
1>power task start...
1>[TracePoint] type[  0] cmd[  3] data[  2]
1>ufs task wait parameters from uefi...
1>AmuTaskStart Entry ... 
1>amu task wait parameters from uefi...
1>ThermalSiwStart Entry ...
1>ThermalSiwTask idle...
1>DemtTaskStart Entry ...
1>[TracePoint] type[  0] cmd[  3] data[  3]
1>demt task wait parameters from uefi...
1>HiBoostTaskStart Entry ...
1>HiBoost task enabled
1>Waiting for UEFI parameters...
1>[TracePoint] type[  0] cmd[  3] data[  4]
1>[TracePoint] type[  0] cmd[  3] data[  5]
1>uefi parameters ready!
1>UFSProfile[0]
1>PowerPolicy[2] BenchMarkSelection[0]
1>ipu interface task wait ddr init done from uefi...
1>ufs task parameters from uefi ready
1>uncore domain[0] freq:2900
1>uncore domain[1] freq:2900
1>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
1>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
1>======sioe status======
1>thermal soc task restore underclocking_en=1
1>ppu alert temp div init done
1>TA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TA_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TA_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TA_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
1>TA_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
1>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
1>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
1>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
1>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
1>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
1>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
1>==========end==========
1>sioe init done
1>ufs task enabled
1>--> UFS profile[0]
1>UEFI parameters ready
1>UncoreMaxFreq Set to [2900 MHZ]
1>get TDP from efuse success, value = 357500mw
1>target power set to [357500]mw, brd:[357500]
1>demt task parameters from uefi ready
1>uefi ddr init finish!
1>ipu interface task wait uefi end done from uefi...
1>ddr init done, start thermal dimm task
1>======dimm status======
1>  chl[0] dimm0 2, dimm1 0
1>  chl[1] dimm0 2, dimm1 0
1>  chl[2] dimm0 2, dimm1 0
1>  chl[3] dimm0 2, dimm1 0
1>  chl[4] dimm0 2, dimm1 0
1>  chl[5] dimm0 2, dimm1 0
1>  chl[6] dimm0 2, dimm1 0
1>  chl[7] dimm0 2, dimm1 0
1>==========end==========
1>chl[0] registered, dimm mask = 0x1
1>chl[1] registered, dimm mask = 0x1
1>chl[2] registered, dimm mask = 0x1
1>chl[3] registered, dimm mask = 0x1
1>chl[4] registered, dimm mask = 0x1
1>chl[5] registered, dimm mask = 0x1
1>chl[6] registered, dimm mask = 0x1
1>chl[7] registered, dimm mask = 0x1
1>=====dimm temp params=====
1>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
1>  is_thermal_thro_en  : 1
1>  is_aref_rate_auto   : 1
1>===========end============
1>chl[0] max_temp 29'C, aref_rate 0x5 --> 0x4
1>chl[1] max_temp 29'C, aref_rate 0x5 --> 0x4
1>chl[2] max_temp 29'C, aref_rate 0x5 --> 0x4
1>chl[3] max_temp 29'C, aref_rate 0x5 --> 0x4
1>chl[4] max_temp 29'C, aref_rate 0x5 --> 0x4
1>chl[5] max_temp 29'C, aref_rate 0x5 --> 0x4
1>chl[6] max_temp 29'C, aref_rate 0x5 --> 0x4
1>chl[7] max_temp 29'C, aref_rate 0x5 --> 0x4
1>uefi end finish!
1>ipu interface task exit!
1>amu task parameters from uefi ready
1>amu task activated
1>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
TB[ 810]mv
2>[1950]MHZ -> Vol TA[ 810]mv TB[ 810]mv
2>[2000]MHZ -> Vol TA[ 810]mv TB[ 810]mv
2>[2050]MHZ -> Vol TA[ 810]mv TB[ 810]mv
2>[2100]MHZ -> Vol TA[ 810]mv TB[ 810]mv
2>[2150]MHZ -> Vol TA[ 810]mv TB[ 810]mv
2>[2200]MHZ -> Vol TA[ 810]mv TB[ 810]mv
2>[2250]MHZ -> Vol TA[ 813]mv TB[ 814]mv
2>[2300]MHZ -> Vol TA[ 826]mv TB[ 827]mv
2>[2350]MHZ -> Vol TA[ 838]mv TB[ 840]mv
2>[2400]MHZ -> Vol TA[ 851]mv TB[ 852]mv
2>[2450]MHZ -> Vol TA[ 863]mv TB[ 865]mv
2>[2500]MHZ -> Vol TA[ 876]mv TB[ 877]mv
2>[2550]MHZ -> Vol TA[ 888]mv TB[ 890]mv
2>[2600]MHZ -> Vol TA[ 901]mv TB[ 902]mv
2>[2650]MHZ -> Vol TA[ 913]mv TB[ 915]mv
2>[2700]MHZ -> Vol TA[ 926]mv TB[ 928]mv
2>[2750]MHZ -> Vol TA[ 944]mv TB[ 946]mv
2>[2800]MHZ -> Vol TA[ 962]mv TB[ 964]mv
2>[2850]MHZ -> Vol TA[ 980]mv TB[ 982]mv
2>[2900]MHZ -> Vol TA[ 998]mv TB[1000]mv
2>[2950]MHZ -> Vol TA[1015]mv TB[1017]mv
2>[3000]MHZ -> Vol TA[1032]mv TB[1034]mv
2>[3050]MHZ -> Vol TA[1046]mv TB[1048]mv
2>[3100]MHZ -> Vol TA[1060]mv TB[1062]mv
2>Uncore VF curve:
2>Uncore [   0]MHZ -> Vol [ 810]mv
2>Uncore [ 100]MHZ -> Vol [ 810]mv
2>Uncore [ 200]MHZ -> Vol [ 810]mv
2>Uncore [ 300]MHZ -> Vol [ 810]mv
2>Uncore [ 400]MHZ -> Vol [ 810]mv
2>Uncore [ 500]MHZ -> Vol [ 877]mv
2>Uncore [ 600]MHZ -> Vol [ 877]mv
2>Uncore [ 700]MHZ -> Vol [ 877]mv
2>Uncore [ 800]MHZ -> Vol [ 877]mv
2>Uncore [ 900]MHZ -> Vol [ 877]mv
2>Uncore [1000]MHZ -> Vol [ 877]mv
2>Uncore [1100]MHZ -> Vol [ 877]mv
2>Uncore [1200]MHZ -> Vol [ 877]mv
2>Uncore [1300]MHZ -> Vol [ 877]mv
2>Uncore [1400]MHZ -> Vol [ 877]mv
2>Uncore [1500]MHZ -> Vol [ 877]mv
2>Uncore [1600]MHZ -> Vol [ 877]mv
2>Uncore [1700]MHZ -> Vol [ 877]mv
2>Uncore [1800]MHZ -> Vol [ 877]mv
2>Uncore [1900]MHZ -> Vol [ 877]mv
2>Uncore [2000]MHZ -> Vol [ 877]mv
2>Uncore [2100]MHZ -> Vol [ 883]mv
2>Uncore [2200]MHZ -> Vol [ 890]mv
2>Uncore [2300]MHZ -> Vol [ 897]mv
2>Uncore [2400]MHZ -> Vol [ 904]mv
2>Uncore [2500]MHZ -> Vol [ 911]mv
2>Uncore [2600]MHZ -> Vol [ 928]mv
2>Uncore [2700]MHZ -> Vol [ 946]mv
2>Uncore [2800]MHZ -> Vol [ 962]mv
2>Uncore [2900]MHZ -> Vol [ 978]mv
2>Uncore [3000]MHZ -> Vol [ 992]mv
2>[TracePoint] type[  0] cmd[  1] data[  6]
2>[TracePoint] type[  0] cmd[  1] data[  7]
2>
********Hello Huawei LiteOS********

KpxxxxIPU Firmware Version : V32.75.0
LiteOS Kernel Version : 5.7.0
2>Run on ChipVersion[0] Node[2] Die[0]
2>build time : Apr 24 2026 18:00:00

2>**********************************
2>
main core booting up...
2>start set affinity
2>
mpidr = 0x81080000
2>sram ecc state: 0x0, sram ecc cnt: 0x0
2>[TracePoint] type[  0] cmd[  2] data[  1]
2>[TracePoint] type[  0] cmd[  2] data[  2]
2>LRDXSD_LOCK_OFFSET = 0x0
2>LRDXSD_ERRIMSK_OFFSET = 0x0
2>LRDXSD_DBG_OTIMSK_OFFSET = 0x0
2>LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
2>LRDXSD_DBG_EN_OFFSET = 0x1
2>======tsensor params======
2>  is_trimmed       : 1
2>  underclocking_en : 1
2>===========end============
2>soc tsensor init done
2>========vrd info from cpld========
2>vrd_id | u64                | pmbus_en | avsbus_en | loop | pmbus_id | pmbus_addr | avs_sw | pmbus_sw | addr_9545 | domain_type | die_mask | reserved
2>  00   | 0x0001000100002017 | 0x1      | 0x1       | 0x1  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0100   | 0x0
2>  01   | 0x000300030000201b | 0x1      | 0x1       | 0x2  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x3         | 0x0300   | 0x0
2>  02   | 0x0000010500002b15 | 0x1      | 0x0       | 0x1  | 0x1      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0001   | 0x0
2>  03   | 0x0002000100002027 | 0x1      | 0x1       | 0x1  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0200   | 0x0
2>  04   | 0x000300020000202b | 0x1      | 0x1       | 0x2  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x2         | 0x0300   | 0x0
2>  05   | 0x0000020500002b25 | 0x1      | 0x0       | 0x1  | 0x2      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0002   | 0x0
2>  06   | 0x0003000400002b29 | 0x1      | 0x0       | 0x2  | 0x2      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x4         | 0x0300   | 0x0
2>================end===============
2>=============vrd info=============
2>power domain num: 7
2>power domain[00] id:0 | CORE_DVFS_TA       | PMBus NA | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
2>power domain[01] id:1 | DDR_VDD            | PMBus NA | cap:0x3 | rail:1 | addr:0x20 | def_volt: 765 mV | min_volt: 650 mV | max_volt: 850 mV
2>power domain[02] id:4 | IO_DVDD_NA         | PMBus NA | cap:0x1 | rail:0 | addr:0x2b | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
2>power domain[03] id:2 | CORE_DVFS_TB       | PMBus NB | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
2>power domain[04] id:3 | UNCORE_DVFS        | PMBus NB | cap:0x3 | rail:1 | addr:0x20 | def_volt: 978 mV | min_volt: 750 mV | max_volt:1100 mV
2>power domain[05] id:5 | IO_DVDD_NB         | PMBus NB | cap:0x1 | rail:0 | addr:0x2b | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
2>power domain[06] id:6 | DDR_VDDQ           | PMBus NB | cap:0x1 | rail:1 | addr:0x2b | def_volt:1100 mV | min_volt:1000 mV | max_volt:1200 mV
2>================end===============
2>pmbus[0] init done
2>pmbus[1] init done
2>power domain[0] CORE_DVFS_TA       | NA PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
2>power domain[1] DDR_VDD            | NA PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 765 mV | pmu:MP2882
2>power domain[4] IO_DVDD_NA         | NA PMBus        | rail:0 | addr:0x2b | def_volt: 800 mV | pmu:MP2882
2>power domain[2] CORE_DVFS_TB       | NB PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
2>power domain[3] UNCORE_DVFS        | NB PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 978 mV | pmu:MP2882
2>power domain[5] IO_DVDD_NB         | NB PMBus        | rail:0 | addr:0x2b | def_volt: 800 mV | pmu:MP2882
2>power domain[6] DDR_VDDQ           | NB PMBus        | rail:1 | addr:0x2b | def_volt:1100 mV | pmu:MP2882
2>power domain[0] CORE_DVFS_TA       is transferred to AVSBus mode
2>power domain[1] DDR_VDD            is transferred to AVSBus mode
2>power domain[2] CORE_DVFS_TB       is transferred to AVSBus mode
2>power domain[3] UNCORE_DVFS        is transferred to AVSBus mode
2>avsbus resync success
2>avsbus[0] init done
2>avsbus resync success
2>avsbus[1] init done
2>============volt boot============
2>power domain[0] volt = 1097 mV
2>power domain[1] volt =  767 mV
2>power domain[4] volt =  802 mV
2>power domain[2] volt = 1103 mV
2>power domain[3] volt = 1005 mV
2>power domain[5] volt =  806 mV
2>power domain[6] volt = 1103 mV
2>===============end===============
2>--w&h rd rail:0, 1099, CORE_DVFS_TA
2>--w&h rd rail:1, 765, CORE_DVFS_TA
2>power domain[0] set volt --> 1097 mV success
2>--w&h rd rail:0, 1103, CORE_DVFS_TB
2>--w&h rd rail:1, 1005, CORE_DVFS_TB
2>power domain[2] set volt --> 1103 mV success
2>power domain[3] set volt -->  980 mV success
2>power domain[1] set volt -->  763 mV success
2>power domain[4] set volt -->  800 mV success
2>power domain[5] set volt -->  804 mV success
2>============volt post============
2>power domain[0] volt = 1097 mV
2>power domain[1] volt =  765 mV
2>power domain[4] volt =  800 mV
2>power domain[2] volt = 1103 mV
2>power domain[3] volt =  980 mV
2>power domain[5] volt =  804 mV
2>power domain[6] volt = 1103 mV
2>===============end===============
2>Hboot1 Info RAW Dump: [0x91][0x00][0x00][0x14][0x01][0x00][0x01]
2>PowerSensorSupport[1], Cali[5120], Loss[7200]
2>Power Sensor Calibration Value[5120]!
2>the power sensor : manu id = 2peak, die id = TPA626
2>power sensor[0] init success
2>die[0] its[0] init done
2>die[0] its[1] init done
2>die[0] its[2] init done
2>die[0] its[3] init done
2>die[0] its[4] init done
2>die[0] its[5] init done
2>die[0] its[6] init done
2>die[0] its[7] init done
2>die[0] its[8] init done
2>die[0] its[9] init done
2>die[1] its[0] init done
2>die[1] its[1] init done
2>die[1] its[2] init done
2>die[1] its[3] init done
2>die[1] its[4] init done
2>die[1] its[5] init done
2>die[1] its[6] init done
2>die[1] its[7] init done
2>die[1] its[8] init done
2>die[1] its[9] init done
2>Totem[0] Core Boot Vol [1097]mv
2>Totem[0] Core Current Vol [1100]mv
2>Totem[1] Core Boot Vol [1101]mv
2>Totem[1] Core Current Vol [1100]mv
2>NA 1620V190
2>NB 1620V190
2>GetCoreBaseFreq [2900000KHZ]
2>GetCoreTurboFreq [2900000KHZ]
2>GetCustomClusterNum [10]
2>Ipu ACG Training Done!
2>AP Last Time:[0.00.01.558]
2>wait UEFI pll init...
2>done
2>acg trim start
2>core trim freq:2000, avs:0 volt:810mv
2>core trim freq:2000, avs:0 volt:810mv
2>core trim freq:2050, avs:1 volt:810mv
2>core trim freq:2050, avs:1 volt:810mv
2>core trim freq:2100, avs:2 volt:810mv
2>core trim freq:2100, avs:2 volt:810mv
2>core trim freq:2150, avs:3 volt:810mv
2>core trim freq:2150, avs:3 volt:810mv
2>core trim freq:2200, avs:4 volt:810mv
2>core trim freq:2200, avs:4 volt:810mv
2>core trim freq:2250, avs:5 volt:813mv
2>core trim freq:2250, avs:5 volt:814mv
2>core trim freq:2300, avs:6 volt:826mv
2>core trim freq:2300, avs:6 volt:827mv
2>core trim freq:2350, avs:7 volt:838mv
2>core trim freq:2350, avs:7 volt:840mv
2>core trim freq:2400, avs:8 volt:851mv
2>core trim freq:2400, avs:8 volt:852mv
2>core trim freq:2450, avs:9 volt:863mv
2>core trim freq:2450, avs:9 volt:865mv
2>core trim freq:2500, avs:10 volt:876mv
2>core trim freq:2500, avs:10 volt:877mv
2>core trim freq:2550, avs:11 volt:888mv
2>core trim freq:2550, avs:11 volt:890mv
2>core trim freq:2600, avs:12 volt:901mv
2>core trim freq:2600, avs:12 volt:902mv
2>core trim freq:2650, avs:13 volt:913mv
2>core trim freq:2650, avs:13 volt:915mv
2>core trim freq:2700, avs:14 volt:926mv
2>core trim freq:2700, avs:14 volt:928mv
2>core trim freq:2750, avs:15 volt:944mv
2>core trim freq:2750, avs:15 volt:946mv
2>core trim freq:2800, avs:16 volt:962mv
2>core trim freq:2800, avs:16 volt:964mv
2>core trim freq:2850, avs:17 volt:980mv
2>core trim freq:2850, avs:17 volt:982mv
2>core trim freq:2900, avs:18 volt:998mv
2>core trim freq:2900, avs:18 volt:1000mv
2>core trim freq:2950, avs:19 volt:1015mv
2>core trim freq:2950, avs:19 volt:1017mv
2>core trim freq:3000, avs:20 volt:1032mv
2>core trim freq:3000, avs:20 volt:1034mv
2>core trim freq:3050, avs:21 volt:1046mv
2>core trim freq:3050, avs:21 volt:1048mv
2>core trim freq:3100, avs:22 volt:1060mv
2>core trim freq:3100, avs:22 volt:1062mv
2>acg trim end
2>LDO disabled
2>[TracePoint] type[  0] cmd[  2] data[  3]
2>Interrupt 423 register OK
2>Interrupt 430 register OK
2>[TracePoint] type[  0] cmd[  2] data[  4]
2>
2>cpu 0 entering scheduler
2>[TracePoint] type[  0] cmd[  3] data[  1]
2>add your ipu app init here!
2>IpuInterfaceTaskStart Entry ...
2>ipu interface task wait parameters from uefi...
2>thermal soc task enabled
2>AP Last Time:[0.00.44.465]
2>ThermalDimmStart Entry ...
2>wait ddr init done...
2>power task start...
2>[TracePoint] type[  0] cmd[  3] data[  2]
2>ufs task wait parameters from uefi...
2>AmuTaskStart Entry ... 
2>amu task wait parameters from uefi...
2>ThermalSiwStart Entry ...
2>ThermalSiwTask idle...
2>DemtTaskStart Entry ...
2>[TracePoint] type[  0] cmd[  3] data[  3]
2>demt task wait parameters from uefi...
2>HiBoostTaskStart Entry ...
2>HiBoost task enabled
2>Waiting for UEFI parameters...
2>[TracePoint] type[  0] cmd[  3] data[  4]
2>[TracePoint] type[  0] cmd[  3] data[  5]
2>uefi parameters ready!
2>UFSProfile[0]
2>PowerPolicy[2] BenchMarkSelection[0]
2>ipu interface task wait ddr init done from uefi...
2>ufs task parameters from uefi ready
2>uncore domain[0] freq:2900
2>uncore domain[1] freq:2900
2>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
2>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
2>======sioe status======
2>thermal soc task restore underclocking_en=1
2>ppu alert temp div init done
2>TA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
2>TA_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
2>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
2>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
2>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
2>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
2>==========end==========
2>sioe init done
2>ufs task enabled
2>--> UFS profile[0]
2>UEFI parameters ready
2>UncoreMaxFreq Set to [2900 MHZ]
2>get TDP from efuse success, value = 357500mw
2>target power set to [357500]mw, brd:[357500]
2>demt task parameters from uefi ready
2>uefi ddr init finish!
2>ipu interface task wait uefi end done from uefi...
2>ddr init done, start thermal dimm task
2>======dimm status======
2>  chl[0] dimm0 2, dimm1 0
2>  chl[1] dimm0 2, dimm1 0
2>  chl[2] dimm0 2, dimm1 0
2>  chl[3] dimm0 2, dimm1 0
2>  chl[4] dimm0 2, dimm1 0
2>  chl[5] dimm0 2, dimm1 0
2>  chl[6] dimm0 2, dimm1 0
2>  chl[7] dimm0 2, dimm1 0
2>==========end==========
2>chl[0] registered, dimm mask = 0x1
2>chl[1] registered, dimm mask = 0x1
2>chl[2] registered, dimm mask = 0x1
2>chl[3] registered, dimm mask = 0x1
2>chl[4] registered, dimm mask = 0x1
2>chl[5] registered, dimm mask = 0x1
2>chl[6] registered, dimm mask = 0x1
2>chl[7] registered, dimm mask = 0x1
2>=====dimm temp params=====
2>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
2>  is_thermal_thro_en  : 1
2>  is_aref_rate_auto   : 1
2>===========end============
2>chl[0] max_temp 30'C, aref_rate 0x5 --> 0x4
2>chl[1] max_temp 30'C, aref_rate 0x5 --> 0x4
2>chl[2] max_temp 30'C, aref_rate 0x5 --> 0x4
2>chl[3] max_temp 30'C, aref_rate 0x5 --> 0x4
2>chl[4] max_temp 30'C, aref_rate 0x5 --> 0x4
2>chl[5] max_temp 30'C, aref_rate 0x5 --> 0x4
2>chl[6] max_temp 30'C, aref_rate 0x5 --> 0x4
2>chl[7] max_temp 30'C, aref_rate 0x5 --> 0x4
2>uefi end finish!
2>ipu interface task exit!
2>amu task parameters from uefi ready
2>amu task activated
2>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
mv TB[ 810]mv
3>[1950]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2000]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2050]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2100]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2150]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2200]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2250]MHZ -> Vol TA[ 813]mv TB[ 815]mv
3>[2300]MHZ -> Vol TA[ 826]mv TB[ 827]mv
3>[2350]MHZ -> Vol TA[ 838]mv TB[ 840]mv
3>[2400]MHZ -> Vol TA[ 851]mv TB[ 853]mv
3>[2450]MHZ -> Vol TA[ 863]mv TB[ 865]mv
3>[2500]MHZ -> Vol TA[ 876]mv TB[ 878]mv
3>[2550]MHZ -> Vol TA[ 888]mv TB[ 891]mv
3>[2600]MHZ -> Vol TA[ 901]mv TB[ 903]mv
3>[2650]MHZ -> Vol TA[ 913]mv TB[ 916]mv
3>[2700]MHZ -> Vol TA[ 926]mv TB[ 929]mv
3>[2750]MHZ -> Vol TA[ 943]mv TB[ 946]mv
3>[2800]MHZ -> Vol TA[ 961]mv TB[ 964]mv
3>[2850]MHZ -> Vol TA[ 979]mv TB[ 982]mv
3>[2900]MHZ -> Vol TA[ 997]mv TB[1000]mv
3>[2950]MHZ -> Vol TA[1014]mv TB[1017]mv
3>[3000]MHZ -> Vol TA[1031]mv TB[1035]mv
3>[3050]MHZ -> Vol TA[1045]mv TB[1048]mv
3>[3100]MHZ -> Vol TA[1059]mv TB[1062]mv
3>Uncore VF curve:
3>Uncore [   0]MHZ -> Vol [ 810]mv
3>Uncore [ 100]MHZ -> Vol [ 810]mv
3>Uncore [ 200]MHZ -> Vol [ 810]mv
3>Uncore [ 300]MHZ -> Vol [ 810]mv
3>Uncore [ 400]MHZ -> Vol [ 810]mv
3>Uncore [ 500]MHZ -> Vol [ 877]mv
3>Uncore [ 600]MHZ -> Vol [ 877]mv
3>Uncore [ 700]MHZ -> Vol [ 877]mv
3>Uncore [ 800]MHZ -> Vol [ 877]mv
3>Uncore [ 900]MHZ -> Vol [ 877]mv
3>Uncore [1000]MHZ -> Vol [ 877]mv
3>Uncore [1100]MHZ -> Vol [ 877]mv
3>Uncore [1200]MHZ -> Vol [ 877]mv
3>Uncore [1300]MHZ -> Vol [ 877]mv
3>Uncore [1400]MHZ -> Vol [ 877]mv
3>Uncore [1500]MHZ -> Vol [ 877]mv
3>Uncore [1600]MHZ -> Vol [ 877]mv
3>Uncore [1700]MHZ -> Vol [ 877]mv
3>Uncore [1800]MHZ -> Vol [ 877]mv
3>Uncore [1900]MHZ -> Vol [ 877]mv
3>Uncore [2000]MHZ -> Vol [ 877]mv
3>Uncore [2100]MHZ -> Vol [ 884]mv
3>Uncore [2200]MHZ -> Vol [ 891]mv
3>Uncore [2300]MHZ -> Vol [ 898]mv
3>Uncore [2400]MHZ -> Vol [ 905]mv
3>Uncore [2500]MHZ -> Vol [ 912]mv
3>Uncore [2600]MHZ -> Vol [ 929]mv
3>Uncore [2700]MHZ -> Vol [ 947]mv
3>Uncore [2800]MHZ -> Vol [ 963]mv
3>Uncore [2900]MHZ -> Vol [ 980]mv
3>Uncore [3000]MHZ -> Vol [ 994]mv
3>[TracePoint] type[  0] cmd[  1] data[  6]
3>[TracePoint] type[  0] cmd[  1] data[  7]
3>
********Hello Huawei LiteOS********

KpxxxxIPU Firmware Version : V32.75.0
LiteOS Kernel Version : 5.7.0
3>Run on ChipVersion[0] Node[3] Die[0]
3>build time : Apr 24 2026 18:00:00

3>**********************************
3>
main core booting up...
3>start set affinity
3>
mpidr = 0x810c0000
3>sram ecc state: 0x0, sram ecc cnt: 0x0
3>[TracePoint] type[  0] cmd[  2] data[  1]
3>[TracePoint] type[  0] cmd[  2] data[  2]
3>LRDXSD_LOCK_OFFSET = 0x0
3>LRDXSD_ERRIMSK_OFFSET = 0x0
3>LRDXSD_DBG_OTIMSK_OFFSET = 0x0
3>LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
3>LRDXSD_DBG_EN_OFFSET = 0x1
3>======tsensor params======
3>  is_trimmed       : 1
3>  underclocking_en : 1
3>===========end============
3>soc tsensor init done
3>========vrd info from cpld========
3>vrd_id | u64                | pmbus_en | avsbus_en | loop | pmbus_id | pmbus_addr | avs_sw | pmbus_sw | addr_9545 | domain_type | die_mask | reserved
3>  00   | 0x0001000100002017 | 0x1      | 0x1       | 0x1  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0100   | 0x0
3>  01   | 0x000300030000201b | 0x1      | 0x1       | 0x2  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x3         | 0x0300   | 0x0
3>  02   | 0x0000010500002b15 | 0x1      | 0x0       | 0x1  | 0x1      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0001   | 0x0
3>  03   | 0x0002000100002027 | 0x1      | 0x1       | 0x1  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0200   | 0x0
3>  04   | 0x000300020000202b | 0x1      | 0x1       | 0x2  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x2         | 0x0300   | 0x0
3>  05   | 0x0000020500002b25 | 0x1      | 0x0       | 0x1  | 0x2      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0002   | 0x0
3>  06   | 0x0003000400002b29 | 0x1      | 0x0       | 0x2  | 0x2      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x4         | 0x0300   | 0x0
3>================end===============
3>=============vrd info=============
3>power domain num: 7
3>power domain[00] id:0 | CORE_DVFS_TA       | PMBus NA | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
3>power domain[01] id:1 | DDR_VDD            | PMBus NA | cap:0x3 | rail:1 | addr:0x20 | def_volt: 765 mV | min_volt: 650 mV | max_volt: 850 mV
3>power domain[02] id:4 | IO_DVDD_NA         | PMBus NA | cap:0x1 | rail:0 | addr:0x2b | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
3>power domain[03] id:2 | CORE_DVFS_TB       | PMBus NB | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
3>power domain[04] id:3 | UNCORE_DVFS        | PMBus NB | cap:0x3 | rail:1 | addr:0x20 | def_volt: 980 mV | min_volt: 750 mV | max_volt:1100 mV
3>power domain[05] id:5 | IO_DVDD_NB         | PMBus NB | cap:0x1 | rail:0 | addr:0x2b | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
3>power domain[06] id:6 | DDR_VDDQ           | PMBus NB | cap:0x1 | rail:1 | addr:0x2b | def_volt:1100 mV | min_volt:1000 mV | max_volt:1200 mV
3>================end===============
3>pmbus[0] init done
3>pmbus[1] init done
3>power domain[0] CORE_DVFS_TA       | NA PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
3>power domain[1] DDR_VDD            | NA PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 765 mV | pmu:MP2882
3>power domain[4] IO_DVDD_NA         | NA PMBus        | rail:0 | addr:0x2b | def_volt: 800 mV | pmu:MP2882
3>power domain[2] CORE_DVFS_TB       | NB PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
3>power domain[3] UNCORE_DVFS        | NB PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 980 mV | pmu:MP2882
3>power domain[5] IO_DVDD_NB         | NB PMBus        | rail:0 | addr:0x2b | def_volt: 800 mV | pmu:MP2882
3>power domain[6] DDR_VDDQ           | NB PMBus        | rail:1 | addr:0x2b | def_volt:1100 mV | pmu:MP2882
3>power domain[0] CORE_DVFS_TA       is transferred to AVSBus mode
3>power domain[1] DDR_VDD            is transferred to AVSBus mode
3>power domain[2] CORE_DVFS_TB       is transferred to AVSBus mode
3>power domain[3] UNCORE_DVFS        is transferred to AVSBus mode
3>avsbus resync success
3>avsbus[0] init done
3>avsbus resync success
3>avsbus[1] init done
3>============volt boot============
3>power domain[0] volt = 1099 mV
3>power domain[1] volt =  765 mV
3>power domain[4] volt =  806 mV
3>power domain[2] volt = 1107 mV
3>power domain[3] volt = 1007 mV
3>power domain[5] volt =  800 mV
3>power domain[6] volt = 1103 mV
3>===============end===============
3>--w&h rd rail:0, 1099, CORE_DVFS_TA
3>--w&h rd rail:1, 765, CORE_DVFS_TA
3>power domain[0] set volt --> 1099 mV success
3>--w&h rd rail:0, 1105, CORE_DVFS_TB
3>--w&h rd rail:1, 1009, CORE_DVFS_TB
3>power domain[2] set volt --> 1107 mV success
3>power domain[3] set volt -->  984 mV success
3>power domain[1] set volt -->  763 mV success
3>power domain[4] set volt -->  804 mV success
3>power domain[5] set volt -->  798 mV success
3>============volt post============
3>power domain[0] volt = 1099 mV
3>power domain[1] volt =  763 mV
3>power domain[4] volt =  804 mV
3>power domain[2] volt = 1107 mV
3>power domain[3] volt =  984 mV
3>power domain[5] volt =  798 mV
3>power domain[6] volt = 1103 mV
3>===============end===============
3>Hboot1 Info RAW Dump: [0x01][0x00][0x00][0x14][0x01][0x00][0x01]
3>PowerSensorSupport[1], Cali[5120], Loss[0]
3>Power Sensor Calibration Value[5120]!
3>the power sensor : manu id = 2peak, die id = TPA626
3>power sensor[0] init success
3>die[0] its[0] init done
3>die[0] its[1] init done
3>die[0] its[2] init done
3>die[0] its[3] init done
3>die[0] its[4] init done
3>die[0] its[5] init done
3>die[0] its[6] init done
3>die[0] its[7] init done
3>die[0] its[8] init done
3>die[0] its[9] init done
3>die[1] its[0] init done
3>die[1] its[1] init done
3>die[1] its[2] init done
3>die[1] its[3] init done
3>die[1] its[4] init done
3>die[1] its[5] init done
3>die[1] its[6] init done
3>die[1] its[7] init done
3>die[1] its[8] init done
3>die[1] its[9] init done
3>Totem[0] Core Boot Vol [1101]mv
3>Totem[0] Core Current Vol [1100]mv
3>Totem[1] Core Boot Vol [1105]mv
3>Totem[1] Core Current Vol [1100]mv
3>NA 1620V190
3>NB 1620V190
3>GetCoreBaseFreq [2900000KHZ]
3>GetCoreTurboFreq [2900000KHZ]
3>GetCustomClusterNum [10]
3>Ipu ACG Training Done!
3>AP Last Time:[0.00.01.550]
3>wait UEFI pll init...
3>done
3>acg trim start
3>core trim freq:2000, avs:0 volt:810mv
3>core trim freq:2000, avs:0 volt:810mv
3>core trim freq:2050, avs:1 volt:810mv
3>core trim freq:2050, avs:1 volt:810mv
3>core trim freq:2100, avs:2 volt:810mv
3>core trim freq:2100, avs:2 volt:810mv
3>core trim freq:2150, avs:3 volt:810mv
3>core trim freq:2150, avs:3 volt:810mv
3>core trim freq:2200, avs:4 volt:810mv
3>core trim freq:2200, avs:4 volt:810mv
3>core trim freq:2250, avs:5 volt:813mv
3>core trim freq:2250, avs:5 volt:815mv
3>core trim freq:2300, avs:6 volt:826mv
3>core trim freq:2300, avs:6 volt:827mv
3>core trim freq:2350, avs:7 volt:838mv
3>core trim freq:2350, avs:7 volt:840mv
3>core trim freq:2400, avs:8 volt:851mv
3>core trim freq:2400, avs:8 volt:853mv
3>core trim freq:2450, avs:9 volt:863mv
3>core trim freq:2450, avs:9 volt:865mv
3>core trim freq:2500, avs:10 volt:876mv
3>core trim freq:2500, avs:10 volt:878mv
3>core trim freq:2550, avs:11 volt:888mv
3>core trim freq:2550, avs:11 volt:891mv
3>core trim freq:2600, avs:12 volt:901mv
3>core trim freq:2600, avs:12 volt:903mv
3>core trim freq:2650, avs:13 volt:913mv
3>core trim freq:2650, avs:13 volt:916mv
3>core trim freq:2700, avs:14 volt:926mv
3>core trim freq:2700, avs:14 volt:929mv
3>core trim freq:2750, avs:15 volt:943mv
3>core trim freq:2750, avs:15 volt:946mv
3>core trim freq:2800, avs:16 volt:961mv
3>core trim freq:2800, avs:16 volt:964mv
3>core trim freq:2850, avs:17 volt:979mv
3>core trim freq:2850, avs:17 volt:982mv
3>core trim freq:2900, avs:18 volt:997mv
3>core trim freq:2900, avs:18 volt:1000mv
3>core trim freq:2950, avs:19 volt:1014mv
3>core trim freq:2950, avs:19 volt:1017mv
3>core trim freq:3000, avs:20 volt:1031mv
3>core trim freq:3000, avs:20 volt:1035mv
3>core trim freq:3050, avs:21 volt:1045mv
3>core trim freq:3050, avs:21 volt:1048mv
3>core trim freq:3100, avs:22 volt:1059mv
3>core trim freq:3100, avs:22 volt:1062mv
3>acg trim end
3>LDO disabled
3>[TracePoint] type[  0] cmd[  2] data[  3]
3>Interrupt 423 register OK
3>Interrupt 430 register OK
3>[TracePoint] type[  0] cmd[  2] data[  4]
3>
3>cpu 0 entering scheduler
3>[TracePoint] type[  0] cmd[  3] data[  1]
3>add your ipu app init here!
3>IpuInterfaceTaskStart Entry ...
3>ipu interface task wait parameters from uefi...
3>thermal soc task enabled
3>AP Last Time:[0.00.44.412]
3>ThermalDimmStart Entry ...
3>wait ddr init done...
3>power task start...
3>[TracePoint] type[  0] cmd[  3] data[  2]
3>ufs task wait parameters from uefi...
3>AmuTaskStart Entry ... 
3>amu task wait parameters from uefi...
3>ThermalSiwStart Entry ...
3>ThermalSiwTask idle...
3>DemtTaskStart Entry ...
3>[TracePoint] type[  0] cmd[  3] data[  3]
3>demt task wait parameters from uefi...
3>HiBoostTaskStart Entry ...
3>HiBoost task enabled
3>Waiting for UEFI parameters...
3>[TracePoint] type[  0] cmd[  3] data[  4]
3>[TracePoint] type[  0] cmd[  3] data[  5]
3>uefi parameters ready!
3>UFSProfile[0]
3>PowerPolicy[2] BenchMarkSelection[0]
3>ipu interface task wait ddr init done from uefi...
3>ufs task parameters from uefi ready
3>uncore domain[0] freq:2900
3>uncore domain[1] freq:2900
3>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
3>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
3>======sioe status======
3>thermal soc task restore underclocking_en=1
3>ppu alert temp div init done
3>TA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
3>TA_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
3>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
3>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
3>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
3>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
3>==========end==========
3>sioe init done
3>ufs task enabled
3>--> UFS profile[0]
3>UEFI parameters ready
3>UncoreMaxFreq Set to [2900 MHZ]
3>get TDP from efuse success, value = 357500mw
3>target power set to [357500]mw, brd:[357500]
3>demt task parameters from uefi ready
3>uefi ddr init finish!
3>ipu interface task wait uefi end done from uefi...
3>ddr init done, start thermal dimm task
3>======dimm status======
3>  chl[0] dimm0 2, dimm1 0
3>  chl[1] dimm0 2, dimm1 0
3>  chl[2] dimm0 2, dimm1 0
3>  chl[3] dimm0 2, dimm1 0
3>  chl[4] dimm0 2, dimm1 0
3>  chl[5] dimm0 2, dimm1 0
3>  chl[6] dimm0 2, dimm1 0
3>  chl[7] dimm0 2, dimm1 0
3>==========end==========
3>chl[0] registered, dimm mask = 0x1
3>chl[1] registered, dimm mask = 0x1
3>chl[2] registered, dimm mask = 0x1
3>chl[3] registered, dimm mask = 0x1
3>chl[4] registered, dimm mask = 0x1
3>chl[5] registered, dimm mask = 0x1
3>chl[6] registered, dimm mask = 0x1
3>chl[7] registered, dimm mask = 0x1
3>=====dimm temp params=====
3>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
3>  is_thermal_thro_en  : 1
3>  is_aref_rate_auto   : 1
3>===========end============
3>chl[0] max_temp 32'C, aref_rate 0x5 --> 0x4
3>chl[1] max_temp 32'C, aref_rate 0x5 --> 0x4
3>chl[2] max_temp 32'C, aref_rate 0x5 --> 0x4
3>chl[3] max_temp 32'C, aref_rate 0x5 --> 0x4
3>chl[4] max_temp 32'C, aref_rate 0x5 --> 0x4
3>chl[5] max_temp 32'C, aref_rate 0x5 --> 0x4
3>chl[6] max_temp 32'C, aref_rate 0x5 --> 0x4
3>chl[7] max_temp 32'C, aref_rate 0x5 --> 0x4
3>uefi end finish!
3>ipu interface task exit!
3>amu task parameters from uefi ready
3>amu task activated
3>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
[0.08.23.829]IpmiCmdReportPcieMMIO start
[0.08.40.469]IpmiCmdReportPcieMMIO end
pool addr          pool size    used size     free size    max free node size   used node num     free node num      UsageWaterLine
---------------    --------     -------       --------     --------------       -------------      ------------      ------------
0x840908c350       0x22880      0x189d8       0x9c38       0x9550               0xbf               0x3                0x19330        
>power domain[0] set volt --> 1099 mV success
2>--w&h rd rail:0, 1101, CORE_DVFS_TB
2>--w&h rd rail:1, 1005, CORE_DVFS_TB
2>power domain[2] set volt --> 1103 mV success
2>power domain[3] set volt -->  976 mV success
2>power domain[1] set volt -->  763 mV success
2>power domain[4] set volt -->  800 mV success
2>power domain[5] set volt -->  802 mV success
2>============volt post============
2>power domain[0] volt = 1097 mV
2>power domain[1] volt =  763 mV
2>power domain[4] volt =  800 mV
2>power domain[2] volt = 1103 mV
2>power domain[3] volt =  978 mV
2>power domain[5] volt =  802 mV
2>power domain[6] volt = 1103 mV
2>===============end===============
2>Hboot1 Info RAW Dump: [0x91][0x00][0x00][0x14][0x01][0x00][0x01]
2>PowerSensorSupport[1], Cali[5120], Loss[7200]
2>Power Sensor Calibration Value[5120]!
2>the power sensor : manu id = 2peak, die id = TPA626
2>power sensor[0] init success
2>die[0] its[0] init done
2>die[0] its[1] init done
2>die[0] its[2] init done
2>die[0] its[3] init done
2>die[0] its[4] init done
2>die[0] its[5] init done
2>die[0] its[6] init done
2>die[0] its[7] init done
2>die[0] its[8] init done
2>die[0] its[9] init done
2>die[1] its[0] init done
2>die[1] its[1] init done
2>die[1] its[2] init done
2>die[1] its[3] init done
2>die[1] its[4] init done
2>die[1] its[5] init done
2>die[1] its[6] init done
2>die[1] its[7] init done
2>die[1] its[8] init done
2>die[1] its[9] init done
2>Totem[0] Core Boot Vol [1099]mv
2>Totem[0] Core Current Vol [1100]mv
2>Totem[1] Core Boot Vol [1103]mv
2>Totem[1] Core Current Vol [1100]mv
2>NA 1620V190
2>NB 1620V190
2>GetCoreBaseFreq [2900000KHZ]
2>GetCoreTurboFreq [2900000KHZ]
2>GetCustomClusterNum [10]
2>Ipu ACG Training Done!
2>AP Last Time:[0.00.01.557]
2>wait UEFI pll init...
2>done
2>acg trim start
2>core trim freq:2000, avs:0 volt:810mv
2>core trim freq:2000, avs:0 volt:810mv
2>core trim freq:2050, avs:1 volt:810mv
2>core trim freq:2050, avs:1 volt:810mv
2>core trim freq:2100, avs:2 volt:810mv
2>core trim freq:2100, avs:2 volt:810mv
2>core trim freq:2150, avs:3 volt:810mv
2>core trim freq:2150, avs:3 volt:810mv
2>core trim freq:2200, avs:4 volt:810mv
2>core trim freq:2200, avs:4 volt:810mv
2>core trim freq:2250, avs:5 volt:813mv
2>core trim freq:2250, avs:5 volt:814mv
2>core trim freq:2300, avs:6 volt:826mv
2>core trim freq:2300, avs:6 volt:827mv
2>core trim freq:2350, avs:7 volt:838mv
2>core trim freq:2350, avs:7 volt:840mv
2>core trim freq:2400, avs:8 volt:851mv
2>core trim freq:2400, avs:8 volt:852mv
2>core trim freq:2450, avs:9 volt:863mv
2>core trim freq:2450, avs:9 volt:865mv
2>core trim freq:2500, avs:10 volt:876mv
2>core trim freq:2500, avs:10 volt:877mv
2>core trim freq:2550, avs:11 volt:888mv
2>core trim freq:2550, avs:11 volt:890mv
2>core trim freq:2600, avs:12 volt:901mv
2>core trim freq:2600, avs:12 volt:902mv
2>core trim freq:2650, avs:13 volt:913mv
2>core trim freq:2650, avs:13 volt:915mv
2>core trim freq:2700, avs:14 volt:926mv
2>core trim freq:2700, avs:14 volt:928mv
2>core trim freq:2750, avs:15 volt:944mv
2>core trim freq:2750, avs:15 volt:946mv
2>core trim freq:2800, avs:16 volt:962mv
2>core trim freq:2800, avs:16 volt:964mv
2>core trim freq:2850, avs:17 volt:980mv
2>core trim freq:2850, avs:17 volt:982mv
2>core trim freq:2900, avs:18 volt:998mv
2>core trim freq:2900, avs:18 volt:1000mv
2>core trim freq:2950, avs:19 volt:1015mv
2>core trim freq:2950, avs:19 volt:1017mv
2>core trim freq:3000, avs:20 volt:1032mv
2>core trim freq:3000, avs:20 volt:1034mv
2>core trim freq:3050, avs:21 volt:1046mv
2>core trim freq:3050, avs:21 volt:1048mv
2>core trim freq:3100, avs:22 volt:1060mv
2>core trim freq:3100, avs:22 volt:1062mv
2>acg trim end
2>LDO disabled
2>[TracePoint] type[  0] cmd[  2] data[  3]
2>Interrupt 423 register OK
2>Interrupt 430 register OK
2>[TracePoint] type[  0] cmd[  2] data[  4]
2>
2>cpu 0 entering scheduler
2>[TracePoint] type[  0] cmd[  3] data[  1]
2>add your ipu app init here!
2>IpuInterfaceTaskStart Entry ...
2>ipu interface task wait parameters from uefi...
2>thermal soc task enabled
2>AP Last Time:[0.00.44.148]
2>ThermalDimmStart Entry ...
2>wait ddr init done...
2>power task start...
2>[TracePoint] type[  0] cmd[  3] data[  2]
2>ufs task wait parameters from uefi...
2>AmuTaskStart Entry ... 
2>amu task wait parameters from uefi...
2>ThermalSiwStart Entry ...
2>ThermalSiwTask idle...
2>DemtTaskStart Entry ...
2>[TracePoint] type[  0] cmd[  3] data[  3]
2>demt task wait parameters from uefi...
2>HiBoostTaskStart Entry ...
2>HiBoost task enabled
2>Waiting for UEFI parameters...
2>[TracePoint] type[  0] cmd[  3] data[  4]
2>[TracePoint] type[  0] cmd[  3] data[  5]
2>uefi parameters ready!
2>UFSProfile[0]
2>PowerPolicy[2] BenchMarkSelection[0]
2>ipu interface task wait ddr init done from uefi...
2>ufs task parameters from uefi ready
2>uncore domain[0] freq:2900
2>uncore domain[1] freq:2900
2>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
2>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
2>======sioe status======
2>thermal soc task restore underclocking_en=1
2>ppu alert temp div init done
2>TA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
2>TA_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
2>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
2>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
2>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
2>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
2>==========end==========
2>sioe init done
2>ufs task enabled
2>--> UFS profile[0]
2>UEFI parameters ready
2>UncoreMaxFreq Set to [2900 MHZ]
2>get TDP from efuse success, value = 357500mw
2>target power set to [357500]mw, brd:[357500]
2>demt task parameters from uefi ready
912] mv
3>Totem Uncore 2700MHZ -> Vol[947] mv
3>Totem Uncore 2900MHZ -> Vol[980] mv
3>Totem Uncore 3000MHZ -> Vol[994] mv
3>Core VF curve:
3>[ 400]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 450]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 500]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 550]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 600]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 650]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 700]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 750]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 800]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 850]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 900]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 950]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1000]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1050]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1100]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1150]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1200]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1250]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1300]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1350]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1400]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1450]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1500]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1550]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1600]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1650]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1700]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1750]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1800]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1850]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1900]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1950]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2000]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2050]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2100]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2150]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2200]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2250]MHZ -> Vol TA[ 813]mv TB[ 815]mv
3>[2300]MHZ -> Vol TA[ 826]mv TB[ 827]mv
3>[2350]MHZ -> Vol TA[ 838]mv TB[ 840]mv
3>[2400]MHZ -> Vol TA[ 851]mv TB[ 853]mv
3>[2450]MHZ -> Vol TA[ 863]mv TB[ 865]mv
3>[2500]MHZ -> Vol TA[ 876]mv TB[ 878]mv
3>[2550]MHZ -> Vol TA[ 888]mv TB[ 891]mv
3>[2600]MHZ -> Vol TA[ 901]mv TB[ 903]mv
3>[2650]MHZ -> Vol TA[ 913]mv TB[ 916]mv
3>[2700]MHZ -> Vol TA[ 926]mv TB[ 929]mv
3>[2750]MHZ -> Vol TA[ 943]mv TB[ 946]mv
3>[2800]MHZ -> Vol TA[ 961]mv TB[ 964]mv
3>[2850]MHZ -> Vol TA[ 979]mv TB[ 982]mv
3>[2900]MHZ -> Vol TA[ 997]mv TB[1000]mv
3>[2950]MHZ -> Vol TA[1014]mv TB[1017]mv
3>[3000]MHZ -> Vol TA[1031]mv TB[1035]mv
3>[3050]MHZ -> Vol TA[1045]mv TB[1048]mv
3>[3100]MHZ -> Vol TA[1059]mv TB[1062]mv
3>Uncore VF curve:
3>Uncore [   0]MHZ -> Vol [ 810]mv
3>Uncore [ 100]MHZ -> Vol [ 810]mv
3>Uncore [ 200]MHZ -> Vol [ 810]mv
3>Uncore [ 300]MHZ -> Vol [ 810]mv
3>Uncore [ 400]MHZ -> Vol [ 810]mv
3>Uncore [ 500]MHZ -> Vol [ 877]mv
3>Uncore [ 600]MHZ -> Vol [ 877]mv
3>Uncore [ 700]MHZ -> Vol [ 877]mv
3>Uncore [ 800]MHZ -> Vol [ 877]mv
3>Uncore [ 900]MHZ -> Vol [ 877]mv
3>Uncore [1000]MHZ -> Vol [ 877]mv
3>Uncore [1100]MHZ -> Vol [ 877]mv
3>Uncore [1200]MHZ -> Vol [ 877]mv
3>Uncore [1300]MHZ -> Vol [ 877]mv
3>Uncore [1400]MHZ -> Vol [ 877]mv
3>Uncore [1500]MHZ -> Vol [ 877]mv
3>Uncore [1600]MHZ -> Vol [ 877]mv
3>Uncore [1700]MHZ -> Vol [ 877]mv
3>Uncore [1800]MHZ -> Vol [ 877]mv
3>Uncore [1900]MHZ -> Vol [ 877]mv
3>Uncore [2000]MHZ -> Vol [ 877]mv
3>Uncore [2100]MHZ -> Vol [ 884]mv
3>Uncore [2200]MHZ -> Vol [ 891]mv
3>Uncore [2300]MHZ -> Vol [ 898]mv
3>Uncore [2400]MHZ -> Vol [ 905]mv
3>Uncore [2500]MHZ -> Vol [ 912]mv
3>Uncore [2600]MHZ -> Vol [ 929]mv
3>Uncore [2700]MHZ -> Vol [ 947]mv
3>Uncore [2800]MHZ -> Vol [ 963]mv
3>Uncore [2900]MHZ -> Vol [ 980]mv
3>Uncore [3000]MHZ -> Vol [ 994]mv
3>[TracePoint] type[  0] cmd[  1] data[  6]
3>[TracePoint] type[  0] cmd[  1] data[  7]
3>
********Hello Huawei LiteOS********

KpxxxxIPU Firmware Version : V32.75.0
LiteOS Kernel Version : 5.7.0
3>Run on ChipVersion[0] Node[3] Die[0]
3>build time : Apr 24 2026 18:00:00

3>**********************************
3>
main core booting up...
3>start set affinity
3>
mpidr = 0x810c0000
3>sram ecc state: 0x0, sram ecc cnt: 0x0
3>[TracePoint] type[  0] cmd[  2] data[  1]
3>[TracePoint] type[  0] cmd[  2] data[  2]
3>LRDXSD_LOCK_OFFSET = 0x0
3>LRDXSD_ERRIMSK_OFFSET = 0x0
3>LRDXSD_DBG_OTIMSK_OFFSET = 0x0
3>LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
3>LRDXSD_DBG_EN_OFFSET = 0x1
3>======tsensor params======
3>  is_trimmed       : 1
3>  underclocking_en : 1
3>===========end============
3>soc tsensor init done
3>========vrd info from cpld========
3>vrd_id | u64                | pmbus_en | avsbus_en | loop | pmbus_id | pmbus_addr | avs_sw | pmbus_sw | addr_9545 | domain_type | die_mask | reserved
3>  00   | 0x0001000100002017 | 0x1      | 0x1       | 0x1  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0100   | 0x0
3>  01   | 0x000300030000201b | 0x1      | 0x1       | 0x2  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x3         | 0x0300   | 0x0
3>  02   | 0x0000010500002b15 | 0x1      | 0x0       | 0x1  | 0x1      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0001   | 0x0
3>  03   | 0x0002000100002027 | 0x1      | 0x1       | 0x1  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0200   | 0x0
3>  04   | 0x000300020000202b | 0x1      | 0x1       | 0x2  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x2         | 0x0300   | 0x0
3>  05   | 0x0000020500002b25 | 0x1      | 0x0       | 0x1  | 0x2      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0002   | 0x0
3>  06   | 0x0003000400002b29 | 0x1      | 0x0       | 0x2  | 0x2      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x4         | 0x0300   | 0x0
3>================end===============
3>=============vrd info=============
3>power domain num: 7
3>power domain[00] id:0 | CORE_DVFS_TA       | PMBus NA | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
3>power domain[01] id:1 | DDR_VDD            | PMBus NA | cap:0x3 | rail:1 | addr:0x20 | def_volt: 765 mV | min_volt: 650 mV | max_volt: 850 mV
3>power domain[02] id:4 | IO_DVDD_NA         | PMBus NA | cap:0x1 | rail:0 | addr:0x2b | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
3>power domain[03] id:2 | CORE_DVFS_TB       | PMBus NB | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
3>power domain[04] id:3 | UNCORE_DVFS        | PMBus NB | cap:0x3 | rail:1 | addr:0x20 | def_volt: 980 mV | min_volt: 750 mV | max_volt:1100 mV
3>power domain[05] id:5 | IO_DVDD_NB         | PMBus NB | cap:0x1 | rail:0 | addr:0x2b | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
3>power domain[06] id:6 | DDR_VDDQ           | PMBus NB | cap:0x1 | rail:1 | addr:0x2b | def_volt:1100 mV | min_volt:1000 mV | max_volt:1200 mV
3>================end===============
3>pmbus[0] init done
3>pmbus[1] init done
3>power domain[0] CORE_DVFS_TA       | NA PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
3>power domain[1] DDR_VDD            | NA PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 765 mV | pmu:MP2882
3>power domain[4] IO_DVDD_NA         | NA PMBus        | rail:0 | addr:0x2b | def_volt: 800 mV | pmu:MP2882
3>power domain[2] CORE_DVFS_TB       | NB PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
3>power domain[3] UNCORE_DVFS        | NB PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 980 mV | pmu:MP2882
3>power domain[5] IO_DVDD_NB         | NB PMBus        | rail:0 | addr:0x2b | def_volt: 800 mV | pmu:MP2882
3>power domain[6] DDR_VDDQ           | NB PMBus        | rail:1 | addr:0x2b | def_volt:1100 mV | pmu:MP2882
3>power domain[0] CORE_DVFS_TA       is transferred to AVSBus mode
3>power domain[1] DDR_VDD            is transferred to AVSBus mode
3>power domain[2] CORE_DVFS_TB       is transferred to AVSBus mode
3>power domain[3] UNCORE_DVFS        is transferred to AVSBus mode
3>avsbus resync success
3>avsbus[0] init done
3>avsbus resync success
3>avsbus[1] init done
3>============volt boot============
3>power domain[0] volt = 1099 mV
3>power domain[1] volt =  765 mV
3>power domain[4] volt =  806 mV
3>power domain[2] volt = 1105 mV
3>power domain[3] volt = 1007 mV
3>power domain[5] volt =  800 mV
3>power domain[6] volt = 1103 mV
3>===============end===============
3>--w&h rd rail:0, 1099, CORE_DVFS_TA
3>--w&h rd rail:1, 765, CORE_DVFS_TA
3>power domain[0] set volt --> 1099 mV success
3>--w&h rd rail:0, 1105, CORE_DVFS_TB
3>--w&h rd rail:1, 1007, CORE_DVFS_TB
3>power domain[2] set volt --> 1105 mV success
3>power domain[3] set volt -->  982 mV success
3>power domain[1] set volt -->  761 mV success
3>power domain[4] set volt -->  804 mV success
3>power domain[5] set volt -->  800 mV success
3>============volt post============
3>power domain[0] volt = 1099 mV
3>power domain[1] volt =  763 mV
3>power domain[4] volt =  804 mV
3>power domain[2] volt = 1105 mV
3>power domain[3] volt =  984 mV
3>power domain[5] volt =  798 mV
3>power domain[6] volt = 1101 mV
3>===============end===============
3>Hboot1 Info RAW Dump: [0x01][0x00][0x00][0x14][0x01][0x00][0x01]
3>PowerSensorSupport[1], Cali[5120], Loss[0]
3>Power Sensor Calibration Value[5120]!
3>the power sensor : manu id = 2peak, die id = TPA626
3>power sensor[0] init success
3>die[0] its[0] init done
3>die[0] its[1] init done
3>die[0] its[2] init done
3>die[0] its[3] init done
3>die[0] its[4] init done
3>die[0] its[5] init done
3>die[0] its[6] init done
3>die[0] its[7] init done
3>die[0] its[8] init done
3>die[0] its[9] init done
3>die[1] its[0] init done
3>die[1] its[1] init done
3>die[1] its[2] init done
3>die[1] its[3] init done
3>die[1] its[4] init done
3>die[1] its[5] init done
3>die[1] its[6] init done
3>die[1] its[7] init done
3>die[1] its[8] init done
3>die[1] its[9] init done
3>Totem[0] Core Boot Vol [1099]mv
3>Totem[0] Core Current Vol [1100]mv
3>Totem[1] Core Boot Vol [1105]mv
3>Totem[1] Core Current Vol [1100]mv
3>NA 1620V190
3>NB 1620V190
3>GetCoreBaseFreq [2900000KHZ]
3>GetCoreTurboFreq [2900000KHZ]
3>GetCustomClusterNum [10]
3>Ipu ACG Training Done!
3>AP Last Time:[0.00.01.547]
3>wait UEFI pll init...
3>done
3>acg trim start
3>core trim freq:2000, avs:0 volt:810mv
3>core trim freq:2000, avs:0 volt:810mv
3>core trim freq:2050, avs:1 volt:810mv
3>core trim freq:2050, avs:1 volt:810mv
3>core trim freq:2100, avs:2 volt:810mv
3>core trim freq:2100, avs:2 volt:810mv
3>core trim freq:2150, avs:3 volt:810mv
3>core trim freq:2150, avs:3 volt:810mv
3>core trim freq:2200, avs:4 volt:810mv
3>core trim freq:2200, avs:4 volt:810mv
3>core trim freq:2250, avs:5 volt:813mv
3>core trim freq:2250, avs:5 volt:815mv
3>core trim freq:2300, avs:6 volt:826mv
3>core trim freq:2300, avs:6 volt:827mv
3>core trim freq:2350, avs:7 volt:838mv
3>core trim freq:2350, avs:7 volt:840mv
3>core trim freq:2400, avs:8 volt:851mv
3>core trim freq:2400, avs:8 volt:853mv
3>core trim freq:2450, avs:9 volt:863mv
3>core trim freq:2450, avs:9 volt:865mv
3>core trim freq:2500, avs:10 volt:876mv
3>core trim freq:2500, avs:10 volt:878mv
3>core trim freq:2550, avs:11 volt:888mv
3>core trim freq:2550, avs:11 volt:891mv
3>core trim freq:2600, avs:12 volt:901mv
3>core trim freq:2600, avs:12 volt:903mv
3>core trim freq:2650, avs:13 volt:913mv
3>core trim freq:2650, avs:13 volt:916mv
3>core trim freq:2700, avs:14 volt:926mv
3>core trim freq:2700, avs:14 volt:929mv
3>core trim freq:2750, avs:15 volt:943mv
3>core trim freq:2750, avs:15 volt:946mv
3>core trim freq:2800, avs:16 volt:961mv
3>core trim freq:2800, avs:16 volt:964mv
3>core trim freq:2850, avs:17 volt:979mv
3>core trim freq:2850, avs:17 volt:982mv
3>core trim freq:2900, avs:18 volt:997mv
3>core trim freq:2900, avs:18 volt:1000mv
3>core trim freq:2950, avs:19 volt:1014mv
3>core trim freq:2950, avs:19 volt:1017mv
3>core trim freq:3000, avs:20 volt:1031mv
3>core trim freq:3000, avs:20 volt:1035mv
3>core trim freq:3050, avs:21 volt:1045mv
3>core trim freq:3050, avs:21 volt:1048mv
3>core trim freq:3100, avs:22 volt:1059mv
3>core trim freq:3100, avs:22 volt:1062mv
3>acg trim end
3>LDO disabled
3>[TracePoint] type[  0] cmd[  2] data[  3]
3>Interrupt 423 register OK
3>Interrupt 430 register OK
3>[TracePoint] type[  0] cmd[  2] data[  4]
3>
3>cpu 0 entering scheduler
3>[TracePoint] type[  0] cmd[  3] data[  1]
3>add your ipu app init here!
3>IpuInterfaceTaskStart Entry ...
3>ipu interface task wait parameters from uefi...
3>thermal soc task enabled
3>AP Last Time:[0.00.44.095]
3>ThermalDimmStart Entry ...
3>wait ddr init done...
3>power task start...
3>[TracePoint] type[  0] cmd[  3] data[  2]
3>ufs task wait parameters from uefi...
3>AmuTaskStart Entry ... 
3>amu task wait parameters from uefi...
3>ThermalSiwStart Entry ...
3>ThermalSiwTask idle...
3>DemtTaskStart Entry ...
3>[TracePoint] type[  0] cmd[  3] data[  3]
3>demt task wait parameters from uefi...
3>HiBoostTaskStart Entry ...
3>HiBoost task enabled
3>Waiting for UEFI parameters...
3>[TracePoint] type[  0] cmd[  3] data[  4]
3>[TracePoint] type[  0] cmd[  3] data[  5]
3>uefi parameters ready!
3>UFSProfile[0]
3>PowerPolicy[2] BenchMarkSelection[0]
3>ipu interface task wait ddr init done from uefi...
3>ufs task parameters from uefi ready
3>uncore domain[0] freq:2900
3>uncore domain[1] freq:2900
3>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
3>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
3>======sioe status======
3>thermal soc task restore underclocking_en=1
3>ppu alert temp div init done
3>TA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
3>TA_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
3>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
3>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
3>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
3>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
3>==========end==========
3>sioe init done
3>ufs task enabled
3>--> UFS profile[0]
3>UEFI parameters ready
3>UncoreMaxFreq Set to [2900 MHZ]
3>get TDP from efuse success, value = 357500mw
3>target power set to [357500]mw, brd:[357500]
3>demt task parameters from uefi ready
pwr cap[0]: 0, 63
pwr cap[1]: f, 27
pwr cap[2]: 1, 0
0>uefi ddr init finish!
0>ipu interface task wait uefi end done from uefi...
0>ddr init done, start thermal dimm task
0>======dimm status======
0>  chl[0] dimm0 2, dimm1 0
0>  chl[1] dimm0 2, dimm1 0
0>  chl[2] dimm0 2, dimm1 0
0>  chl[3] dimm0 2, dimm1 0
0>  chl[4] dimm0 2, dimm1 0
0>  chl[5] dimm0 2, dimm1 0
0>  chl[6] dimm0 2, dimm1 0
0>  chl[7] dimm0 2, dimm1 0
0>==========end==========
0>chl[0] registered, dimm mask = 0x1
0>chl[1] registered, dimm mask = 0x1
0>chl[2] registered, dimm mask = 0x1
0>chl[3] registered, dimm mask = 0x1
0>chl[4] registered, dimm mask = 0x1
0>chl[5] registered, dimm mask = 0x1
0>chl[6] registered, dimm mask = 0x1
0>chl[7] registered, dimm mask = 0x1
0>=====dimm temp params=====
0>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
0>  is_thermal_thro_en  : 1
0>  is_aref_rate_auto   : 1
0>===========end============
1>uefi ddr init finish!
1>ipu interface task wait uefi end done from uefi...
1>ddr init done, start thermal dimm task
1>======dimm status======
1>  chl[0] dimm0 2, dimm1 0
1>  chl[1] dimm0 2, dimm1 0
1>  chl[2] dimm0 2, dimm1 0
1>  chl[3] dimm0 2, dimm1 0
1>  chl[4] dimm0 2, dimm1 0
1>  chl[5] dimm0 2, dimm1 0
1>  chl[6] dimm0 2, dimm1 0
1>  chl[7] dimm0 2, dimm1 0
1>==========end==========
1>chl[0] registered, dimm mask = 0x1
1>chl[1] registered, dimm mask = 0x1
1>chl[2] registered, dimm mask = 0x1
1>chl[3] registered, dimm mask = 0x1
1>chl[4] registered, dimm mask = 0x1
2>uefi ddr init finish!
2>ipu interface task wait uefi end done from uefi...
3>uefi ddr init finish!
3>ipu interface task wait uefi end done from uefi...
3>ddr init done, start thermal dimm task
3>======dimm status======
3>  chl[0] dimm0 2, dimm1 0
3>  chl[1] dimm0 2, dimm1 0
3>  chl[2] dimm0 2, dimm1 0
3>  chl[3] dimm0 2, dimm1 0
3>  chl[4] dimm0 2, dimm1 0
3>  chl[5] dimm0 2, dimm1 0
3>  chl[6] dimm0 2, dimm1 0
3>  chl[7] dimm0 2, dimm1 0
3>==========end==========
3>chl[0] registered, dimm mask = 0x1
3>chl[1] registered, dimm mask = 0x1
3>chl[2] registered, dimm mask = 0x1
3>chl[3] registered, dimm mask = 0x1
3>chl[4] registered, dimm mask = 0x1
3>chl[5] registered, dimm mask = 0x1
3>chl[6] registered, dimm mask = 0x1
3>chl[7] registered, dimm mask = 0x1
1>chl[5] registered, dimm mask = 0x1
1>chl[6] registered, dimm mask = 0x1
1>chl[7] registered, dimm mask = 0x1
1>=====dimm temp params=====
1>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
1>  is_thermal_thro_en  : 1
1>  is_aref_rate_auto   : 1
1>===========end============
2>ddr init done, start thermal dimm task
2>======dimm status======
2>  chl[0] dimm0 2, dimm1 0
2>  chl[1] dimm0 2, dimm1 0
2>  chl[2] dimm0 2, dimm1 0
2>  chl[3] dimm0 2, dimm1 0
2>  chl[4] dimm0 2, dimm1 0
2>  chl[5] dimm0 2, dimm1 0
2>  chl[6] dimm0 2, dimm1 0
2>  chl[7] dimm0 2, dimm1 0
2>==========end==========
2>chl[0] registered, dimm mask = 0x1
2>chl[1] registered, dimm mask = 0x1
2>chl[2] registered, dimm mask = 0x1
2>chl[3] registered, dimm mask = 0x1
2>chl[4] registered, dimm mask = 0x1
2>chl[5] registered, dimm mask = 0x1
2>chl[6] registered, dimm mask = 0x1
2>chl[7] registered, dimm mask = 0x1
2>=====dimm temp params=====
2>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
2>  is_thermal_thro_en  : 1
2>  is_aref_rate_auto   : 1
2>===========end============
3>=====dimm temp params=====
3>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
3>  is_thermal_thro_en  : 1
3>  is_aref_rate_auto   : 1
3>===========end============
[0.01.21.963]DDR Rreserved for IMU: len = 3e00000
[LOG]head = 0x0, tail = 0x4f1b, logSize = 0x4f1b
copy registry.json file success
Set component all release version to sram end.
ipcMsgSend success
HsmLogInit Ret 1, Len 4, val 0x32022a06
[0.01.22.008]starting ras Init
nodeId = 0, dieId = 0, isSasExist = 0.
nodeId = 0, dieId = 2, isSasExist = 0.
nodeId = 1, dieId = 0, isSasExist = 0.
nodeId = 1, dieId = 2, isSasExist = 0.
nodeId = 2, dieId = 0, isSasExist = 0.
nodeId = 2, dieId = 2, isSasExist = 0.
nodeId = 3, dieId = 0, isSasExist = 0.
nodeId = 3, dieId = 2, isSasExist = 0.
Mce Table head exist!
RasIntRegister init 452 
RasIntRegister init 453 
RasIntRegister init 64 
RasIntRegister init 65 
RasIntRegister init 465 
RasIntRegister init 466 
RasIntRegister init 86 
RasIntRegister init 87 
RasIntRegister init 478 
RasIntRegister init 479 
RasIntRegister init 108 
RasIntRegister init 109 
RasIntRegister init 491 
RasIntRegister init 492 
RasIntRegister init 130 
RasIntRegister init 131 
RasIntRegister init 504 
RasIntRegister init 505 
RasIntRegister init 152 
RasIntRegister init 153 
RasIntRegister init 517 
RasIntRegister init 518 
RasIntRegister init 174 
RasIntRegister init 175 
RasIntRegister init 530 
RasIntRegister init 531 
RasIntRegister init 196 
RasIntRegister init 197 
RasIntRegister init 543 
RasIntRegister init 544 
RasIntRegister init 218 
RasIntRegister init 219 
RasIntRegister init 76 
RasIntRegister init 98 
RasIntRegister init 120 
RasIntRegister init 142 
RasIntRegister init 164 
RasIntRegister init 186 
RasIntRegister init 208 
RasIntRegister init 230 
[0.01.22.130]starting ras end
2>chl[0] max_temp 26'C, aref_rate 0x5 --> 0x4
2>chl[1] max_temp 26'C, aref_rate 0x5 --> 0x4
2>chl[2] max_temp 26'C, aref_rate 0x5 --> 0x4
2>chl[3] max_temp 26'C, aref_rate 0x5 --> 0x4
2>chl[4] max_temp 26'C, aref_rate 0x5 --> 0x4
2>chl[5] max_temp 26'C, aref_rate 0x5 --> 0x4
2>chl[6] max_temp 26'C, aref_rate 0x5 --> 0x4
2>chl[7] max_temp 26'C, aref_rate 0x5 --> 0x4
3>chl[0] max_temp 26'C, aref_rate 0x5 --> 0x4
3>chl[1] max_temp 26'C, aref_rate 0x5 --> 0x4
3>chl[2] max_temp 26'C, aref_rate 0x5 --> 0x4
3>chl[3] max_temp 26'C, aref_rate 0x5 --> 0x4
3>chl[4] max_temp 26'C, aref_rate 0x5 --> 0x4
3>chl[5] max_temp 26'C, aref_rate 0x5 --> 0x4
3>chl[6] max_temp 26'C, aref_rate 0x5 --> 0x4
3>chl[7] max_temp 26'C, aref_rate 0x5 --> 0x4
0>chl[0] max_temp 26'C, aref_rate 0x5 --> 0x4
0>chl[1] max_temp 26'C, aref_rate 0x5 --> 0x4
0>chl[2] max_temp 26'C, aref_rate 0x5 --> 0x4
0>chl[3] max_temp 26'C, aref_rate 0x5 --> 0x4
0>chl[4] max_temp 26'C, aref_rate 0x5 --> 0x4
0>chl[5] max_temp 26'C, aref_rate 0x5 --> 0x4
0>chl[6] max_temp 26'C, aref_rate 0x5 --> 0x4
0>chl[7] max_temp 26'C, aref_rate 0x5 --> 0x4
1>chl[0] max_temp 25'C, aref_rate 0x5 --> 0x4
1>chl[1] max_temp 25'C, aref_rate 0x5 --> 0x4
1>chl[2] max_temp 25'C, aref_rate 0x5 --> 0x4
1>chl[3] max_temp 25'C, aref_rate 0x5 --> 0x4
1>chl[4] max_temp 25'C, aref_rate 0x5 --> 0x4
1>chl[5] max_temp 25'C, aref_rate 0x5 --> 0x4
1>chl[6] max_temp 25'C, aref_rate 0x5 --> 0x4
1>chl[7] max_temp 25'C, aref_rate 0x5 --> 0x4
[ERR]ipc result error, result 0x28010009
ipcMsgSend fail
Send tee measure to HSM respon:0
get mem silk data length: 192
0: skt = 0 logic = 2 phy = 0 
1: skt = 0 logic = 2 phy = 0 
2: skt = 0 logic = 7 phy = 1 
3: skt = 0 logic = 7 phy = 1 
4: skt = 0 logic = 0 phy = 2 
5: skt = 0 logic = 0 phy = 2 
6: skt = 0 logic = 5 phy = 3 
7: skt = 0 logic = 5 phy = 3 
8: skt = 1 logic = 2 phy = 0 
9: skt = 1 logic = 2 phy = 0 
10: skt = 1 logic = 7 phy = 1 
11: skt = 1 logic = 7 phy = 1 
12: skt = 1 logic = 0 phy = 2 
13: skt = 1 logic = 0 phy = 2 
14: skt = 1 logic = 5 phy = 3 
15: skt = 1 logic = 5 phy = 3 
16: skt = 0 logic = 3 phy = 4 
17: skt = 0 logic = 3 phy = 4 
18: skt = 0 logic = 6 phy = 5 
19: skt = 0 logic = 6 phy = 5 
20: skt = 0 logic = 1 phy = 6 
21: skt = 1 logic = 1 phy = 6 
22: skt = 1 logic = 1 phy = 6 
23: skt = 1 logic = 4 phy = 7 
24: skt = 1 logic = 4 phy = 7 
25: skt = 1 logic = 6 phy = 5 
26: skt = 1 logic = 6 phy = 5 
27: skt = 1 logic = 3 phy = 4 
28: skt = 0 logic = 1 phy = 6 
29: skt = 0 logic = 4 phy = 7 
30: skt = 0 logic = 4 phy = 7 
31: skt = 1 logic = 3 phy = 4 
32: skt = 2 logic = 2 phy = 0 
33: skt = 2 logic = 2 phy = 0 
34: skt = 2 logic = 7 phy = 1 
35: skt = 2 logic = 7 phy = 1 
36: skt = 2 logic = 0 phy = 2 
37: skt = 3 logic = 4 phy = 7 
38: skt = 3 logic = 1 phy = 6 
39: skt = 3 logic = 4 phy = 7 
40: skt = 3 logic = 1 phy = 6 
41: skt = 3 logic = 6 phy = 5 
42: skt = 3 logic = 6 phy = 5 
43: skt = 3 logic = 3 phy = 4 
44: skt = 3 logic = 3 phy = 4 
45: skt = 2 logic = 4 phy = 7 
46: skt = 2 logic = 4 phy = 7 
47: skt = 2 logic = 1 phy = 6 
48: skt = 2 logic = 1 phy = 6 
49: skt = 2 logic = 6 phy = 5 
50: skt = 2 logic = 6 phy = 5 
51: skt = 2 logic = 3 phy = 4 
52: skt = 2 logic = 3 phy = 4 
53: skt = 3 logic = 5 phy = 3 
54: skt = 3 logic = 5 phy = 3 
55: skt = 3 logic = 0 phy = 2 
56: skt = 3 logic = 0 phy = 2 
57: skt = 3 logic = 7 phy = 1 
58: skt = 3 logic = 7 phy = 1 
59: skt = 3 logic = 2 phy = 0 
60: skt = 3 logic = 2 phy = 0 
61: skt = 2 logic = 5 phy = 3 
62: skt = 2 logic = 5 phy = 3 
63: skt = 2 logic = 0 phy = 2 
[0.02.06.405]TF Heartbeat Start
[0.02.11.407]PCIE INIT DONE.
g_mctpQueueCount(48) > tabCnt(42)
slotNum = 0x8
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[0] port:20  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[1] port:22  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[2] port:20  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[3] port:22  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[4] port:20  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[5] port:22  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[6] port:24  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[7] port:26  pcieSlotCtrl.data (after)0x14801c0.

Interrupt 454 register OK
Interrupt 467 register OK
Interrupt 480 register OK
Interrupt 493 register OK
Interrupt 506 register OK
Interrupt 519 register OK
Interrupt 532 register OK
Interrupt 545 register OK
data = 0x0
pmt Init done

Add ep: bdf=a200 eid=9 epCnt=1 eid_alloc=a
Add ep: bdf=c400 eid=a epCnt=1 eid_alloc=b
Add ep: bdf=d000 eid=b epCnt=1 eid_alloc=c
[0.02.11.635]slot[0] port:20 begin to power OFF.
[0.02.11.636]slot[1] port:22 begin to power OFF.
[0.02.11.639]slot[2] port:20 begin to power OFF.
[0.02.11.643]slot[3] port:22 begin to power OFF.
[0.02.11.647]slot[4] port:20 begin to power ON.
[0.02.11.652]slot[5] port:22 begin to power ON.
[0.02.11.656]slot[6] port:24 begin to power ON.
[0.02.11.660]slot[7] port:26 begin to power ON.
Add ep: bdf=300 eid=c epCnt=1 eid_alloc=d
mctp task ok.
[0.03.29.784]BIOS POST END.
Create SetReportPcieMmioToBmc ok.
Start SetReportPcieMmioToBmc ok.
Enter current value process
0>uefi end finish!
0>ipu interface task exit!
0>amu task parameters from uefi ready
1>uefi end finish!
1>ipu interface task exit!
1>amu task parameters from uefi ready
2>uefi end finish!
2>ipu interface task exit!
2>amu task parameters from uefi ready
3>uefi end finish!
3>ipu interface task exit!
3>amu task parameters from uefi ready
0>amu task activated
0>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
1>amu task activated
1>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
2>amu task activated
2>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
3>amu task activated
3>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
[0.08.29.784]IpmiCmdReportPcieMMIO start
[0.08.46.429]IpmiCmdReportPcieMMIO end
pool addr          pool size    used size     free size    max free node size   used node num     free node num      UsageWaterLine
---------------    --------     -------       --------     --------------       -------------      ------------      ------------
0x840908c350       0x22880      0x189d8       0x9c38       0x9550               0xbf               0x3                0x19330        
>power domain[0] set volt --> 1099 mV success
2>--w&h rd rail:0, 1103, CORE_DVFS_TB
2>--w&h rd rail:1, 1005, CORE_DVFS_TB
2>power domain[2] set volt --> 1103 mV success
2>power domain[3] set volt -->  978 mV success
2>power domain[1] set volt -->  763 mV success
2>power domain[4] set volt -->  800 mV success
2>power domain[5] set volt -->  802 mV success
2>============volt post============
2>power domain[0] volt = 1097 mV
2>power domain[1] volt =  765 mV
2>power domain[4] volt =  800 mV
2>power domain[2] volt = 1101 mV
2>power domain[3] volt =  980 mV
2>power domain[5] volt =  802 mV
2>power domain[6] volt = 1101 mV
2>===============end===============
2>Hboot1 Info RAW Dump: [0x91][0x00][0x00][0x14][0x01][0x00][0x01]
2>PowerSensorSupport[1], Cali[5120], Loss[7200]
2>Power Sensor Calibration Value[5120]!
2>the power sensor : manu id = 2peak, die id = TPA626
2>power sensor[0] init success
2>die[0] its[0] init done
2>die[0] its[1] init done
2>die[0] its[2] init done
2>die[0] its[3] init done
2>die[0] its[4] init done
2>die[0] its[5] init done
2>die[0] its[6] init done
2>die[0] its[7] init done
2>die[0] its[8] init done
2>die[0] its[9] init done
2>die[1] its[0] init done
2>die[1] its[1] init done
2>die[1] its[2] init done
2>die[1] its[3] init done
2>die[1] its[4] init done
2>die[1] its[5] init done
2>die[1] its[6] init done
2>die[1] its[7] init done
2>die[1] its[8] init done
2>die[1] its[9] init done
2>Totem[0] Core Boot Vol [1097]mv
2>Totem[0] Core Current Vol [1100]mv
2>Totem[1] Core Boot Vol [1101]mv
2>Totem[1] Core Current Vol [1100]mv
2>NA 1620V190
2>NB 1620V190
2>GetCoreBaseFreq [2900000KHZ]
2>GetCoreTurboFreq [2900000KHZ]
2>GetCustomClusterNum [10]
2>Ipu ACG Training Done!
2>AP Last Time:[0.00.01.551]
2>wait UEFI pll init...
2>done
2>acg trim start
2>core trim freq:2000, avs:0 volt:810mv
2>core trim freq:2000, avs:0 volt:810mv
2>core trim freq:2050, avs:1 volt:810mv
2>core trim freq:2050, avs:1 volt:810mv
2>core trim freq:2100, avs:2 volt:810mv
2>core trim freq:2100, avs:2 volt:810mv
2>core trim freq:2150, avs:3 volt:810mv
2>core trim freq:2150, avs:3 volt:810mv
2>core trim freq:2200, avs:4 volt:810mv
2>core trim freq:2200, avs:4 volt:810mv
2>core trim freq:2250, avs:5 volt:813mv
2>core trim freq:2250, avs:5 volt:814mv
2>core trim freq:2300, avs:6 volt:826mv
2>core trim freq:2300, avs:6 volt:827mv
2>core trim freq:2350, avs:7 volt:838mv
2>core trim freq:2350, avs:7 volt:840mv
2>core trim freq:2400, avs:8 volt:851mv
2>core trim freq:2400, avs:8 volt:852mv
2>core trim freq:2450, avs:9 volt:863mv
2>core trim freq:2450, avs:9 volt:865mv
2>core trim freq:2500, avs:10 volt:876mv
2>core trim freq:2500, avs:10 volt:877mv
2>core trim freq:2550, avs:11 volt:888mv
2>core trim freq:2550, avs:11 volt:890mv
2>core trim freq:2600, avs:12 volt:901mv
2>core trim freq:2600, avs:12 volt:902mv
2>core trim freq:2650, avs:13 volt:913mv
2>core trim freq:2650, avs:13 volt:915mv
2>core trim freq:2700, avs:14 volt:926mv
2>core trim freq:2700, avs:14 volt:928mv
2>core trim freq:2750, avs:15 volt:944mv
2>core trim freq:2750, avs:15 volt:946mv
2>core trim freq:2800, avs:16 volt:962mv
2>core trim freq:2800, avs:16 volt:964mv
2>core trim freq:2850, avs:17 volt:980mv
2>core trim freq:2850, avs:17 volt:982mv
2>core trim freq:2900, avs:18 volt:998mv
2>core trim freq:2900, avs:18 volt:1000mv
2>core trim freq:2950, avs:19 volt:1015mv
2>core trim freq:2950, avs:19 volt:1017mv
2>core trim freq:3000, avs:20 volt:1032mv
2>core trim freq:3000, avs:20 volt:1034mv
2>core trim freq:3050, avs:21 volt:1046mv
2>core trim freq:3050, avs:21 volt:1048mv
2>core trim freq:3100, avs:22 volt:1060mv
2>core trim freq:3100, avs:22 volt:1062mv
2>acg trim end
2>LDO disabled
2>[TracePoint] type[  0] cmd[  2] data[  3]
2>Interrupt 423 register OK
2>Interrupt 430 register OK
2>[TracePoint] type[  0] cmd[  2] data[  4]
2>
2>cpu 0 entering scheduler
2>[TracePoint] type[  0] cmd[  3] data[  1]
2>add your ipu app init here!
2>IpuInterfaceTaskStart Entry ...
2>ipu interface task wait parameters from uefi...
2>thermal soc task enabled
2>AP Last Time:[0.00.44.570]
2>ThermalDimmStart Entry ...
2>wait ddr init done...
2>power task start...
2>[TracePoint] type[  0] cmd[  3] data[  2]
2>ufs task wait parameters from uefi...
2>AmuTaskStart Entry ... 
2>amu task wait parameters from uefi...
2>ThermalSiwStart Entry ...
2>ThermalSiwTask idle...
2>DemtTaskStart Entry ...
2>[TracePoint] type[  0] cmd[  3] data[  3]
2>demt task wait parameters from uefi...
2>HiBoostTaskStart Entry ...
2>HiBoost task enabled
2>Waiting for UEFI parameters...
2>[TracePoint] type[  0] cmd[  3] data[  4]
2>[TracePoint] type[  0] cmd[  3] data[  5]
2>uefi parameters ready!
2>UFSProfile[0]
2>PowerPolicy[2] BenchMarkSelection[0]
2>ipu interface task wait ddr init done from uefi...
2>ufs task parameters from uefi ready
2>uncore domain[0] freq:2900
2>uncore domain[1] freq:2900
2>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
2>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
2>======sioe status======
2>thermal soc task restore underclocking_en=1
2>ppu alert temp div init done
2>TA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
2>TA_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
2>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
2>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
2>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
2>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
2>==========end==========
2>sioe init done
2>ufs task enabled
2>--> UFS profile[0]
2>UEFI parameters ready
2>UncoreMaxFreq Set to [2900 MHZ]
2>get TDP from efuse success, value = 357500mw
2>target power set to [357500]mw, brd:[357500]
2>demt task parameters from uefi ready
912] mv
3>Totem Uncore 2700MHZ -> Vol[947] mv
3>Totem Uncore 2900MHZ -> Vol[980] mv
3>Totem Uncore 3000MHZ -> Vol[994] mv
3>Core VF curve:
3>[ 400]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 450]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 500]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 550]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 600]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 650]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 700]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 750]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 800]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 850]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 900]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 950]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1000]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1050]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1100]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1150]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1200]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1250]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1300]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1350]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1400]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1450]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1500]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1550]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1600]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1650]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1700]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1750]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1800]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1850]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1900]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1950]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2000]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2050]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2100]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2150]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2200]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2250]MHZ -> Vol TA[ 813]mv TB[ 815]mv
3>[2300]MHZ -> Vol TA[ 826]mv TB[ 827]mv
3>[2350]MHZ -> Vol TA[ 838]mv TB[ 840]mv
3>[2400]MHZ -> Vol TA[ 851]mv TB[ 853]mv
3>[2450]MHZ -> Vol TA[ 863]mv TB[ 865]mv
3>[2500]MHZ -> Vol TA[ 876]mv TB[ 878]mv
3>[2550]MHZ -> Vol TA[ 888]mv TB[ 891]mv
3>[2600]MHZ -> Vol TA[ 901]mv TB[ 903]mv
3>[2650]MHZ -> Vol TA[ 913]mv TB[ 916]mv
3>[2700]MHZ -> Vol TA[ 926]mv TB[ 929]mv
3>[2750]MHZ -> Vol TA[ 943]mv TB[ 946]mv
3>[2800]MHZ -> Vol TA[ 961]mv TB[ 964]mv
3>[2850]MHZ -> Vol TA[ 979]mv TB[ 982]mv
3>[2900]MHZ -> Vol TA[ 997]mv TB[1000]mv
3>[2950]MHZ -> Vol TA[1014]mv TB[1017]mv
3>[3000]MHZ -> Vol TA[1031]mv TB[1035]mv
3>[3050]MHZ -> Vol TA[1045]mv TB[1048]mv
3>[3100]MHZ -> Vol TA[1059]mv TB[1062]mv
3>Uncore VF curve:
3>Uncore [   0]MHZ -> Vol [ 810]mv
3>Uncore [ 100]MHZ -> Vol [ 810]mv
3>Uncore [ 200]MHZ -> Vol [ 810]mv
3>Uncore [ 300]MHZ -> Vol [ 810]mv
3>Uncore [ 400]MHZ -> Vol [ 810]mv
3>Uncore [ 500]MHZ -> Vol [ 877]mv
3>Uncore [ 600]MHZ -> Vol [ 877]mv
3>Uncore [ 700]MHZ -> Vol [ 877]mv
3>Uncore [ 800]MHZ -> Vol [ 877]mv
3>Uncore [ 900]MHZ -> Vol [ 877]mv
3>Uncore [1000]MHZ -> Vol [ 877]mv
3>Uncore [1100]MHZ -> Vol [ 877]mv
3>Uncore [1200]MHZ -> Vol [ 877]mv
3>Uncore [1300]MHZ -> Vol [ 877]mv
3>Uncore [1400]MHZ -> Vol [ 877]mv
3>Uncore [1500]MHZ -> Vol [ 877]mv
3>Uncore [1600]MHZ -> Vol [ 877]mv
3>Uncore [1700]MHZ -> Vol [ 877]mv
3>Uncore [1800]MHZ -> Vol [ 877]mv
3>Uncore [1900]MHZ -> Vol [ 877]mv
3>Uncore [2000]MHZ -> Vol [ 877]mv
3>Uncore [2100]MHZ -> Vol [ 884]mv
3>Uncore [2200]MHZ -> Vol [ 891]mv
3>Uncore [2300]MHZ -> Vol [ 898]mv
3>Uncore [2400]MHZ -> Vol [ 905]mv
3>Uncore [2500]MHZ -> Vol [ 912]mv
3>Uncore [2600]MHZ -> Vol [ 929]mv
3>Uncore [2700]MHZ -> Vol [ 947]mv
3>Uncore [2800]MHZ -> Vol [ 963]mv
3>Uncore [2900]MHZ -> Vol [ 980]mv
3>Uncore [3000]MHZ -> Vol [ 994]mv
3>[TracePoint] type[  0] cmd[  1] data[  6]
3>[TracePoint] type[  0] cmd[  1] data[  7]
3>
********Hello Huawei LiteOS********

KpxxxxIPU Firmware Version : V32.75.0
LiteOS Kernel Version : 5.7.0
3>Run on ChipVersion[0] Node[3] Die[0]
3>build time : Apr 24 2026 18:00:00

3>**********************************
3>
main core booting up...
3>start set affinity
3>
mpidr = 0x810c0000
3>sram ecc state: 0x0, sram ecc cnt: 0x0
3>[TracePoint] type[  0] cmd[  2] data[  1]
3>[TracePoint] type[  0] cmd[  2] data[  2]
3>LRDXSD_LOCK_OFFSET = 0x0
3>LRDXSD_ERRIMSK_OFFSET = 0x0
3>LRDXSD_DBG_OTIMSK_OFFSET = 0x0
3>LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
3>LRDXSD_DBG_EN_OFFSET = 0x1
3>======tsensor params======
3>  is_trimmed       : 1
3>  underclocking_en : 1
3>===========end============
3>soc tsensor init done
3>========vrd info from cpld========
3>vrd_id | u64                | pmbus_en | avsbus_en | loop | pmbus_id | pmbus_addr | avs_sw | pmbus_sw | addr_9545 | domain_type | die_mask | reserved
3>  00   | 0x0001000100002017 | 0x1      | 0x1       | 0x1  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0100   | 0x0
3>  01   | 0x000300030000201b | 0x1      | 0x1       | 0x2  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x3         | 0x0300   | 0x0
3>  02   | 0x0000010500002b15 | 0x1      | 0x0       | 0x1  | 0x1      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0001   | 0x0
3>  03   | 0x0002000100002027 | 0x1      | 0x1       | 0x1  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0200   | 0x0
3>  04   | 0x000300020000202b | 0x1      | 0x1       | 0x2  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x2         | 0x0300   | 0x0
3>  05   | 0x0000020500002b25 | 0x1      | 0x0       | 0x1  | 0x2      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0002   | 0x0
3>  06   | 0x0003000400002b29 | 0x1      | 0x0       | 0x2  | 0x2      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x4         | 0x0300   | 0x0
3>================end===============
3>=============vrd info=============
3>power domain num: 7
3>power domain[00] id:0 | CORE_DVFS_TA       | PMBus NA | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
3>power domain[01] id:1 | DDR_VDD            | PMBus NA | cap:0x3 | rail:1 | addr:0x20 | def_volt: 765 mV | min_volt: 650 mV | max_volt: 850 mV
3>power domain[02] id:4 | IO_DVDD_NA         | PMBus NA | cap:0x1 | rail:0 | addr:0x2b | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
3>power domain[03] id:2 | CORE_DVFS_TB       | PMBus NB | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
3>power domain[04] id:3 | UNCORE_DVFS        | PMBus NB | cap:0x3 | rail:1 | addr:0x20 | def_volt: 980 mV | min_volt: 750 mV | max_volt:1100 mV
3>power domain[05] id:5 | IO_DVDD_NB         | PMBus NB | cap:0x1 | rail:0 | addr:0x2b | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
3>power domain[06] id:6 | DDR_VDDQ           | PMBus NB | cap:0x1 | rail:1 | addr:0x2b | def_volt:1100 mV | min_volt:1000 mV | max_volt:1200 mV
3>================end===============
3>pmbus[0] init done
3>pmbus[1] init done
3>power domain[0] CORE_DVFS_TA       | NA PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
3>power domain[1] DDR_VDD            | NA PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 765 mV | pmu:MP2882
3>power domain[4] IO_DVDD_NA         | NA PMBus        | rail:0 | addr:0x2b | def_volt: 800 mV | pmu:MP2882
3>power domain[2] CORE_DVFS_TB       | NB PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
3>power domain[3] UNCORE_DVFS        | NB PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 980 mV | pmu:MP2882
3>power domain[5] IO_DVDD_NB         | NB PMBus        | rail:0 | addr:0x2b | def_volt: 800 mV | pmu:MP2882
3>power domain[6] DDR_VDDQ           | NB PMBus        | rail:1 | addr:0x2b | def_volt:1100 mV | pmu:MP2882
3>power domain[0] CORE_DVFS_TA       is transferred to AVSBus mode
3>power domain[1] DDR_VDD            is transferred to AVSBus mode
3>power domain[2] CORE_DVFS_TB       is transferred to AVSBus mode
3>power domain[3] UNCORE_DVFS        is transferred to AVSBus mode
3>avsbus resync success
3>avsbus[0] init done
3>avsbus resync success
3>avsbus[1] init done
3>============volt boot============
3>power domain[0] volt = 1099 mV
3>power domain[1] volt =  765 mV
3>power domain[4] volt =  806 mV
3>power domain[2] volt = 1105 mV
3>power domain[3] volt = 1007 mV
3>power domain[5] volt =  800 mV
3>power domain[6] volt = 1101 mV
3>===============end===============
3>--w&h rd rail:0, 1099, CORE_DVFS_TA
3>--w&h rd rail:1, 765, CORE_DVFS_TA
3>power domain[0] set volt --> 1099 mV success
3>--w&h rd rail:0, 1105, CORE_DVFS_TB
3>--w&h rd rail:1, 1007, CORE_DVFS_TB
3>power domain[2] set volt --> 1105 mV success
3>power domain[3] set volt -->  984 mV success
3>power domain[1] set volt -->  761 mV success
3>power domain[4] set volt -->  802 mV success
3>power domain[5] set volt -->  798 mV success
3>============volt post============
3>power domain[0] volt = 1099 mV
3>power domain[1] volt =  763 mV
3>power domain[4] volt =  804 mV
3>power domain[2] volt = 1105 mV
3>power domain[3] volt =  982 mV
3>power domain[5] volt =  798 mV
3>power domain[6] volt = 1103 mV
3>===============end===============
3>Hboot1 Info RAW Dump: [0x01][0x00][0x00][0x14][0x01][0x00][0x01]
3>PowerSensorSupport[1], Cali[5120], Loss[0]
3>Power Sensor Calibration Value[5120]!
3>the power sensor : manu id = 2peak, die id = TPA626
3>power sensor[0] init success
3>die[0] its[0] init done
3>die[0] its[1] init done
3>die[0] its[2] init done
3>die[0] its[3] init done
3>die[0] its[4] init done
3>die[0] its[5] init done
3>die[0] its[6] init done
3>die[0] its[7] init done
3>die[0] its[8] init done
3>die[0] its[9] init done
3>die[1] its[0] init done
3>die[1] its[1] init done
3>die[1] its[2] init done
3>die[1] its[3] init done
3>die[1] its[4] init done
3>die[1] its[5] init done
3>die[1] its[6] init done
3>die[1] its[7] init done
3>die[1] its[8] init done
3>die[1] its[9] init done
3>Totem[0] Core Boot Vol [1099]mv
3>Totem[0] Core Current Vol [1100]mv
3>Totem[1] Core Boot Vol [1105]mv
3>Totem[1] Core Current Vol [1100]mv
3>NA 1620V190
3>NB 1620V190
3>GetCoreBaseFreq [2900000KHZ]
3>GetCoreTurboFreq [2900000KHZ]
3>GetCustomClusterNum [10]
3>Ipu ACG Training Done!
3>AP Last Time:[0.00.01.551]
3>wait UEFI pll init...
3>done
3>acg trim start
3>core trim freq:2000, avs:0 volt:810mv
3>core trim freq:2000, avs:0 volt:810mv
3>core trim freq:2050, avs:1 volt:810mv
3>core trim freq:2050, avs:1 volt:810mv
3>core trim freq:2100, avs:2 volt:810mv
3>core trim freq:2100, avs:2 volt:810mv
3>core trim freq:2150, avs:3 volt:810mv
3>core trim freq:2150, avs:3 volt:810mv
3>core trim freq:2200, avs:4 volt:810mv
3>core trim freq:2200, avs:4 volt:810mv
3>core trim freq:2250, avs:5 volt:813mv
3>core trim freq:2250, avs:5 volt:815mv
3>core trim freq:2300, avs:6 volt:826mv
3>core trim freq:2300, avs:6 volt:827mv
3>core trim freq:2350, avs:7 volt:838mv
3>core trim freq:2350, avs:7 volt:840mv
3>core trim freq:2400, avs:8 volt:851mv
3>core trim freq:2400, avs:8 volt:853mv
3>core trim freq:2450, avs:9 volt:863mv
3>core trim freq:2450, avs:9 volt:865mv
3>core trim freq:2500, avs:10 volt:876mv
3>core trim freq:2500, avs:10 volt:878mv
3>core trim freq:2550, avs:11 volt:888mv
3>core trim freq:2550, avs:11 volt:891mv
3>core trim freq:2600, avs:12 volt:901mv
3>core trim freq:2600, avs:12 volt:903mv
3>core trim freq:2650, avs:13 volt:913mv
3>core trim freq:2650, avs:13 volt:916mv
3>core trim freq:2700, avs:14 volt:926mv
3>core trim freq:2700, avs:14 volt:929mv
3>core trim freq:2750, avs:15 volt:943mv
3>core trim freq:2750, avs:15 volt:946mv
3>core trim freq:2800, avs:16 volt:961mv
3>core trim freq:2800, avs:16 volt:964mv
3>core trim freq:2850, avs:17 volt:979mv
3>core trim freq:2850, avs:17 volt:982mv
3>core trim freq:2900, avs:18 volt:997mv
3>core trim freq:2900, avs:18 volt:1000mv
3>core trim freq:2950, avs:19 volt:1014mv
3>core trim freq:2950, avs:19 volt:1017mv
3>core trim freq:3000, avs:20 volt:1031mv
3>core trim freq:3000, avs:20 volt:1035mv
3>core trim freq:3050, avs:21 volt:1045mv
3>core trim freq:3050, avs:21 volt:1048mv
3>core trim freq:3100, avs:22 volt:1059mv
3>core trim freq:3100, avs:22 volt:1062mv
3>acg trim end
3>LDO disabled
3>[TracePoint] type[  0] cmd[  2] data[  3]
3>Interrupt 423 register OK
3>Interrupt 430 register OK
3>[TracePoint] type[  0] cmd[  2] data[  4]
3>
3>cpu 0 entering scheduler
3>[TracePoint] type[  0] cmd[  3] data[  1]
3>add your ipu app init here!
3>IpuInterfaceTaskStart Entry ...
3>ipu interface task wait parameters from uefi...
3>thermal soc task enabled
3>AP Last Time:[0.00.44.527]
3>ThermalDimmStart Entry ...
3>wait ddr init done...
3>power task start...
3>[TracePoint] type[  0] cmd[  3] data[  2]
3>ufs task wait parameters from uefi...
3>AmuTaskStart Entry ... 
3>amu task wait parameters from uefi...
3>ThermalSiwStart Entry ...
3>ThermalSiwTask idle...
3>DemtTaskStart Entry ...
3>[TracePoint] type[  0] cmd[  3] data[  3]
3>demt task wait parameters from uefi...
3>HiBoostTaskStart Entry ...
3>HiBoost task enabled
3>Waiting for UEFI parameters...
3>[TracePoint] type[  0] cmd[  3] data[  4]
3>[TracePoint] type[  0] cmd[  3] data[  5]
3>uefi parameters ready!
3>UFSProfile[0]
3>PowerPolicy[2] BenchMarkSelection[0]
3>ipu interface task wait ddr init done from uefi...
3>ufs task parameters from uefi ready
3>uncore domain[0] freq:2900
3>uncore domain[1] freq:2900
3>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
3>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
3>======sioe status======
3>thermal soc task restore underclocking_en=1
3>ppu alert temp div init done
3>TA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
3>TA_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
3>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
3>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
3>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
3>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
3>==========end==========
3>sioe init done
3>ufs task enabled
3>--> UFS profile[0]
3>UEFI parameters ready
3>UncoreMaxFreq Set to [2900 MHZ]
3>get TDP from efuse success, value = 357500mw
3>target power set to [357500]mw, brd:[357500]
3>demt task parameters from uefi ready
pwr cap[0]: 0, 63
pwr cap[1]: f, 27
pwr cap[2]: 1, 0
0>uefi ddr init finish!
0>ipu interface task wait uefi end done from uefi...
1>uefi ddr init finish!
1>ipu interface task wait uefi end done from uefi...
2>uefi ddr init finish!
2>ipu interface task wait uefi end done from uefi...
3>uefi ddr init finish!
3>ipu interface task wait uefi end done from uefi...
0>ddr init done, start thermal dimm task
0>======dimm status======
0>  chl[0] dimm0 2, dimm1 0
0>  chl[1] dimm0 2, dimm1 0
0>  chl[2] dimm0 2, dimm1 0
0>  chl[3] dimm0 2, dimm1 0
0>  chl[4] dimm0 2, dimm1 0
0>  chl[5] dimm0 2, dimm1 0
0>  chl[6] dimm0 2, dimm1 0
0>  chl[7] dimm0 2, dimm1 0
0>==========end==========
0>chl[0] registered, dimm mask = 0x1
0>chl[1] registered, dimm mask = 0x1
0>chl[2] registered, dimm mask = 0x1
0>chl[3] registered, dimm mask = 0x1
0>chl[4] registered, dimm mask = 0x1
0>chl[5] registered, dimm mask = 0x1
0>chl[6] registered, dimm mask = 0x1
0>chl[7] registered, dimm mask = 0x1
0>=====dimm temp params=====
0>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
0>  is_thermal_thro_en  : 1
0>  is_aref_rate_auto   : 1
0>===========end============
1>ddr init done, start thermal dimm task
1>======dimm status======
1>  chl[0] dimm0 2, dimm1 0
1>  chl[1] dimm0 2, dimm1 0
1>  chl[2] dimm0 2, dimm1 0
1>  chl[3] dimm0 2, dimm1 0
1>  chl[4] dimm0 2, dimm1 0
1>  chl[5] dimm0 2, dimm1 0
1>  chl[6] dimm0 2, dimm1 0
1>  chl[7] dimm0 2, dimm1 0
1>==========end==========
1>chl[0] registered, dimm mask = 0x1
1>chl[1] registered, dimm mask = 0x1
1>chl[2] registered, dimm mask = 0x1
1>chl[3] registered, dimm mask = 0x1
1>chl[4] registered, dimm mask = 0x1
1>chl[5] registered, dimm mask = 0x1
1>chl[6] registered, dimm mask = 0x1
1>chl[7] registered, dimm mask = 0x1
1>=====dimm temp params=====
1>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
1>  is_thermal_thro_en  : 1
1>  is_aref_rate_auto   : 1
1>===========end============
2>ddr init done, start thermal dimm task
2>======dimm status======
2>  chl[0] dimm0 2, dimm1 0
2>  chl[1] dimm0 2, dimm1 0
2>  chl[2] dimm0 2, dimm1 0
2>  chl[3] dimm0 2, dimm1 0
2>  chl[4] dimm0 2, dimm1 0
2>  chl[5] dimm0 2, dimm1 0
2>  chl[6] dimm0 2, dimm1 0
2>  chl[7] dimm0 2, dimm1 0
2>==========end==========
2>chl[0] registered, dimm mask = 0x1
2>chl[1] registered, dimm mask = 0x1
2>chl[2] registered, dimm mask = 0x1
2>chl[3] registered, dimm mask = 0x1
2>chl[4] registered, dimm mask = 0x1
2>chl[5] registered, dimm mask = 0x1
2>chl[6] registered, dimm mask = 0x1
2>chl[7] registered, dimm mask = 0x1
2>=====dimm temp params=====
2>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
2>  is_thermal_thro_en  : 1
2>  is_aref_rate_auto   : 1
2>===========end============
3>ddr init done, start thermal dimm task
3>======dimm status======
3>  chl[0] dimm0 2, dimm1 0
3>  chl[1] dimm0 2, dimm1 0
3>  chl[2] dimm0 2, dimm1 0
3>  chl[3] dimm0 2, dimm1 0
3>  chl[4] dimm0 2, dimm1 0
3>  chl[5] dimm0 2, dimm1 0
3>  chl[6] dimm0 2, dimm1 0
3>  chl[7] dimm0 2, dimm1 0
3>==========end==========
3>chl[0] registered, dimm mask = 0x1
3>chl[1] registered, dimm mask = 0x1
3>chl[2] registered, dimm mask = 0x1
3>chl[3] registered, dimm mask = 0x1
3>chl[4] registered, dimm mask = 0x1
3>chl[5] registered, dimm mask = 0x1
3>chl[6] registered, dimm mask = 0x1
3>chl[7] registered, dimm mask = 0x1
3>=====dimm temp params=====
3>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
3>  is_thermal_thro_en  : 1
3>  is_aref_rate_auto   : 1
3>===========end============
[0.01.22.820]DDR Rreserved for IMU: len = 3e00000
[LOG]head = 0x0, tail = 0x4f1b, logSize = 0x4f1b
copy registry.json file success
Set component all release version to sram end.
ipcMsgSend success
HsmLogInit Ret 1, Len 4, val 0x32022a06
[0.01.22.865]starting ras Init
nodeId = 0, dieId = 0, isSasExist = 0.
nodeId = 0, dieId = 2, isSasExist = 0.
nodeId = 1, dieId = 0, isSasExist = 0.
nodeId = 1, dieId = 2, isSasExist = 0.
nodeId = 2, dieId = 0, isSasExist = 0.
nodeId = 2, dieId = 2, isSasExist = 0.
nodeId = 3, dieId = 0, isSasExist = 0.
nodeId = 3, dieId = 2, isSasExist = 0.
Mce Table head exist!
RasIntRegister init 452 
RasIntRegister init 453 
RasIntRegister init 64 
RasIntRegister init 65 
RasIntRegister init 465 
RasIntRegister init 466 
RasIntRegister init 86 
RasIntRegister init 87 
RasIntRegister init 478 
RasIntRegister init 479 
RasIntRegister init 108 
RasIntRegister init 109 
RasIntRegister init 491 
RasIntRegister init 492 
RasIntRegister init 130 
RasIntRegister init 131 
RasIntRegister init 504 
RasIntRegister init 505 
RasIntRegister init 152 
RasIntRegister init 153 
RasIntRegister init 517 
RasIntRegister init 518 
RasIntRegister init 174 
RasIntRegister init 175 
RasIntRegister init 530 
RasIntRegister init 531 
RasIntRegister init 196 
RasIntRegister init 197 
RasIntRegister init 543 
RasIntRegister init 544 
RasIntRegister init 218 
RasIntRegister init 219 
RasIntRegister init 76 
RasIntRegister init 98 
RasIntRegister init 120 
RasIntRegister init 142 
RasIntRegister init 164 
RasIntRegister init 186 
RasIntRegister init 208 
RasIntRegister init 230 
[0.01.22.987]starting ras end
3>chl[0] max_temp 27'C, aref_rate 0x5 --> 0x4
3>chl[1] max_temp 27'C, aref_rate 0x5 --> 0x4
3>chl[2] max_temp 27'C, aref_rate 0x5 --> 0x4
3>chl[3] max_temp 27'C, aref_rate 0x5 --> 0x4
3>chl[4] max_temp 27'C, aref_rate 0x5 --> 0x4
3>chl[5] max_temp 27'C, aref_rate 0x5 --> 0x4
3>chl[6] max_temp 27'C, aref_rate 0x5 --> 0x4
3>chl[7] max_temp 27'C, aref_rate 0x5 --> 0x4
1>chl[0] max_temp 26'C, aref_rate 0x5 --> 0x4
1>chl[1] max_temp 26'C, aref_rate 0x5 --> 0x4
1>chl[2] max_temp 26'C, aref_rate 0x5 --> 0x4
1>chl[3] max_temp 26'C, aref_rate 0x5 --> 0x4
1>chl[4] max_temp 26'C, aref_rate 0x5 --> 0x4
1>chl[5] max_temp 26'C, aref_rate 0x5 --> 0x4
1>chl[6] max_temp 26'C, aref_rate 0x5 --> 0x4
1>chl[7] max_temp 26'C, aref_rate 0x5 --> 0x4
2>chl[0] max_temp 27'C, aref_rate 0x5 --> 0x4
2>chl[1] max_temp 27'C, aref_rate 0x5 --> 0x4
2>chl[2] max_temp 27'C, aref_rate 0x5 --> 0x4
2>chl[3] max_temp 27'C, aref_rate 0x5 --> 0x4
2>chl[4] max_temp 27'C, aref_rate 0x5 --> 0x4
2>chl[5] max_temp 27'C, aref_rate 0x5 --> 0x4
2>chl[6] max_temp 27'C, aref_rate 0x5 --> 0x4
2>chl[7] max_temp 27'C, aref_rate 0x5 --> 0x4
[ERR]ipc result error, result 0x28010009
ipcMsgSend fail
Send tee measure to HSM respon:0
0>chl[0] max_temp 26'C, aref_rate 0x5 --> 0x4
0>chl[1] max_temp 26'C, aref_rate 0x5 --> 0x4
0>chl[2] max_temp 26'C, aref_rate 0x5 --> 0x4
0>chl[3] max_temp 26'C, aref_rate 0x5 --> 0x4
0>chl[4] max_temp 26'C, aref_rate 0x5 --> 0x4
0>chl[5] max_temp 26'C, aref_rate 0x5 --> 0x4
0>chl[6] max_temp 26'C, aref_rate 0x5 --> 0x4
0>chl[7] max_temp 26'C, aref_rate 0x5 --> 0x4
get mem silk data length: 192
0: skt = 0 logic = 2 phy = 0 
1: skt = 0 logic = 2 phy = 0 
2: skt = 0 logic = 7 phy = 1 
3: skt = 0 logic = 7 phy = 1 
4: skt = 0 logic = 0 phy = 2 
5: skt = 0 logic = 0 phy = 2 
6: skt = 0 logic = 5 phy = 3 
7: skt = 0 logic = 5 phy = 3 
8: skt = 1 logic = 2 phy = 0 
9: skt = 1 logic = 2 phy = 0 
10: skt = 1 logic = 7 phy = 1 
11: skt = 1 logic = 7 phy = 1 
12: skt = 1 logic = 0 phy = 2 
13: skt = 1 logic = 0 phy = 2 
14: skt = 1 logic = 5 phy = 3 
15: skt = 1 logic = 5 phy = 3 
16: skt = 0 logic = 3 phy = 4 
17: skt = 0 logic = 3 phy = 4 
18: skt = 0 logic = 6 phy = 5 
19: skt = 0 logic = 6 phy = 5 
20: skt = 0 logic = 1 phy = 6 
21: skt = 1 logic = 1 phy = 6 
22: skt = 1 logic = 1 phy = 6 
23: skt = 1 logic = 4 phy = 7 
24: skt = 1 logic = 4 phy = 7 
25: skt = 1 logic = 6 phy = 5 
26: skt = 1 logic = 6 phy = 5 
27: skt = 1 logic = 3 phy = 4 
28: skt = 0 logic = 1 phy = 6 
29: skt = 0 logic = 4 phy = 7 
30: skt = 0 logic = 4 phy = 7 
31: skt = 1 logic = 3 phy = 4 
32: skt = 2 logic = 2 phy = 0 
33: skt = 2 logic = 2 phy = 0 
34: skt = 2 logic = 7 phy = 1 
35: skt = 2 logic = 7 phy = 1 
36: skt = 2 logic = 0 phy = 2 
37: skt = 3 logic = 4 phy = 7 
38: skt = 3 logic = 1 phy = 6 
39: skt = 3 logic = 4 phy = 7 
40: skt = 3 logic = 1 phy = 6 
41: skt = 3 logic = 6 phy = 5 
42: skt = 3 logic = 6 phy = 5 
43: skt = 3 logic = 3 phy = 4 
44: skt = 3 logic = 3 phy = 4 
45: skt = 2 logic = 4 phy = 7 
46: skt = 2 logic = 4 phy = 7 
47: skt = 2 logic = 1 phy = 6 
48: skt = 2 logic = 1 phy = 6 
49: skt = 2 logic = 6 phy = 5 
50: skt = 2 logic = 6 phy = 5 
51: skt = 2 logic = 3 phy = 4 
52: skt = 2 logic = 3 phy = 4 
53: skt = 3 logic = 5 phy = 3 
54: skt = 3 logic = 5 phy = 3 
55: skt = 3 logic = 0 phy = 2 
56: skt = 3 logic = 0 phy = 2 
57: skt = 3 logic = 7 phy = 1 
58: skt = 3 logic = 7 phy = 1 
59: skt = 3 logic = 2 phy = 0 
60: skt = 3 logic = 2 phy = 0 
61: skt = 2 logic = 5 phy = 3 
62: skt = 2 logic = 5 phy = 3 
63: skt = 2 logic = 0 phy = 2 
[0.02.05.674]TF Heartbeat Start
[0.02.10.761]PCIE INIT DONE.
g_mctpQueueCount(48) > tabCnt(42)
slotNum = 0x8
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[0] port:20  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[1] port:22  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[2] port:20  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[3] port:22  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[4] port:20  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[5] port:22  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[6] port:24  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[7] port:26  pcieSlotCtrl.data (after)0x14801c0.

Interrupt 454 register OK
Interrupt 467 register OK
Interrupt 480 register OK
Interrupt 493 register OK
Interrupt 506 register OK
Interrupt 519 register OK
Interrupt 532 register OK
Interrupt 545 register OK
data = 0x0
pmt Init done

Add ep: bdf=a200 eid=9 epCnt=1 eid_alloc=a
Add ep: bdf=c400 eid=a epCnt=1 eid_alloc=b
Add ep: bdf=d000 eid=b epCnt=1 eid_alloc=c
[0.02.10.994]slot[0] port:20 begin to power OFF.
[0.02.10.995]slot[1] port:22 begin to power OFF.
[0.02.10.998]slot[2] port:20 begin to power OFF.
[0.02.11.002]slot[3] port:22 begin to power OFF.
[0.02.11.006]slot[4] port:20 begin to power ON.
[0.02.11.011]slot[5] port:22 begin to power ON.
[0.02.11.015]slot[6] port:24 begin to power ON.
[0.02.11.019]slot[7] port:26 begin to power ON.
Add ep: bdf=300 eid=c epCnt=1 eid_alloc=d
mctp task ok.
[0.03.35.287]BIOS POST END.
Create SetReportPcieMmioToBmc ok.
Start SetReportPcieMmioToBmc ok.
0>uefi end finish!
0>ipu interface task exit!
0>amu task parameters from uefi ready
1>uefi end finish!
1>ipu interface task exit!
1>amu task parameters from uefi ready
2>uefi end finish!
2>ipu interface task exit!
2>amu task parameters from uefi ready
3>uefi end finish!
3>ipu interface task exit!
3>amu task parameters from uefi ready
Enter current value process
0>amu task activated
0>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
1>amu task activated
1>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
2>amu task activated
2>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
3>amu task activated
3>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
[0.08.35.287]IpmiCmdReportPcieMMIO start
[0.08.51.926]IpmiCmdReportPcieMMIO end
pool addr          pool size    used size     free size    max free node size   used node num     free node num      UsageWaterLine
---------------    --------     -------       --------     --------------       -------------      ------------      ------------
0x840908c350       0x22880      0x189d8       0x9c38       0x9550               0xbf               0x3                0x19330        
765, CORE_DVFS_TA
2>power domain[0] set volt --> 1099 mV success
2>--w&h rd rail:0, 1103, CORE_DVFS_TB
2>--w&h rd rail:1, 1005, CORE_DVFS_TB
2>power domain[2] set volt --> 1101 mV success
2>power domain[3] set volt -->  976 mV success
2>power domain[1] set volt -->  765 mV success
2>power domain[4] set volt -->  800 mV success
2>power domain[5] set volt -->  802 mV success
2>============volt post============
2>power domain[0] volt = 1097 mV
2>power domain[1] volt =  763 mV
2>power domain[4] volt =  800 mV
2>power domain[2] volt = 1103 mV
2>power domain[3] volt =  978 mV
2>power domain[5] volt =  802 mV
2>power domain[6] volt = 1103 mV
2>===============end===============
2>Hboot1 Info RAW Dump: [0x91][0x00][0x00][0x14][0x01][0x00][0x01]
2>PowerSensorSupport[1], Cali[5120], Loss[7200]
2>Power Sensor Calibration Value[5120]!
2>the power sensor : manu id = 2peak, die id = TPA626
2>power sensor[0] init success
2>die[0] its[0] init done
2>die[0] its[1] init done
2>die[0] its[2] init done
2>die[0] its[3] init done
2>die[0] its[4] init done
2>die[0] its[5] init done
2>die[0] its[6] init done
2>die[0] its[7] init done
2>die[0] its[8] init done
2>die[0] its[9] init done
2>die[1] its[0] init done
2>die[1] its[1] init done
2>die[1] its[2] init done
2>die[1] its[3] init done
2>die[1] its[4] init done
2>die[1] its[5] init done
2>die[1] its[6] init done
2>die[1] its[7] init done
2>die[1] its[8] init done
2>die[1] its[9] init done
2>Totem[0] Core Boot Vol [1099]mv
2>Totem[0] Core Current Vol [1100]mv
2>Totem[1] Core Boot Vol [1101]mv
2>Totem[1] Core Current Vol [1100]mv
2>NA 1620V190
2>NB 1620V190
2>GetCoreBaseFreq [2900000KHZ]
2>GetCoreTurboFreq [2900000KHZ]
2>GetCustomClusterNum [10]
2>Ipu ACG Training Done!
2>AP Last Time:[0.00.01.547]
2>wait UEFI pll init...
2>done
2>acg trim start
2>core trim freq:2000, avs:0 volt:810mv
2>core trim freq:2000, avs:0 volt:810mv
2>core trim freq:2050, avs:1 volt:810mv
2>core trim freq:2050, avs:1 volt:810mv
2>core trim freq:2100, avs:2 volt:810mv
2>core trim freq:2100, avs:2 volt:810mv
2>core trim freq:2150, avs:3 volt:810mv
2>core trim freq:2150, avs:3 volt:810mv
2>core trim freq:2200, avs:4 volt:810mv
2>core trim freq:2200, avs:4 volt:810mv
2>core trim freq:2250, avs:5 volt:813mv
2>core trim freq:2250, avs:5 volt:814mv
2>core trim freq:2300, avs:6 volt:826mv
2>core trim freq:2300, avs:6 volt:827mv
2>core vs:20 volt:1034mv
2>core trim freq:3050, avs:21 volt:1046mv
2>core trim freq:3050, avs:21 volt:1048mv
2>core trim freq:3100, avs:22 volt:1060mv
2>core trim freq:3100, avs:22 volt:1062mv
2>acg trim end
2>LDO disabled
2>[TracePoint] type[  0] cmd[  2] data[  3]
2>Interrupt 423 register OK
2>Interrupt 430 register OK
2>[TracePoint] type[  0] cmd[  2] data[  4]
2>
2>cpu 0 entering scheduler
2>[TracePoint] type[  0] cmd[  3] data[  1]
2>add your ipu app init here!
2>IpuInterfaceTaskStart Entry ...
2>ipu interface task wait parameters from uefi...
2>thermal soc task enabled
2>AP Last Time:[0.00.44.993]
2>ThermalDimmStart Entry ...
2>wait ddr init done...
2>power task start...
2>[TracePoint] type[  0] cmd[  3] data[  2]
2>ufs task wait parameters from uefi...
2>AmuTaskStart Entry ... 
2>amu task wait parameters from uefi...
2>ThermalSiwStart Entry ...
2>ThermalSiwTask idle...
2>DemtTaskStart Entry ...
2>[TracePoint] type[  0] cmd[  3] data[  3]
2>demt task wait parameters from uefi...
2>HiBoostTaskStart Entry ...
2>HiBoost task enabled
2>Waiting for UEFI parameters...
2>[TracePoint] type[  0] cmd[  3] data[  4]
2>[TracePoint] type[  0] cmd[  3] data[  5]
2>uefi parameters ready!
2>UFSProfile[0]
2>PowerPolicy[2] BenchMarkSelection[0]
2>ipu interface task wait ddr init done from uefi...
2>ufs task parameters from uefi ready
2>uncore domain[0] freq:2900
2>uncore domain[1] freq:2900
2>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
2>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
2>======sioe status======
2>thermal soc task restore underclocking_en=1
2>ppu alert temp div init done
2>TA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
2>TA_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
2>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
2>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
2>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
2>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
2>==========end==========
2>sioe init done
2>ufs task enabled
2>--> UFS profile[0]
2>UEFI parameters ready
2>UncoreMaxFreq Set to [2900 MHZ]
2>get TDP from efuse success, value = 357500mw
2>target power set to [357500]mw, brd:[357500]
2>demt task parameters from uefi ready
912] mv
3>Totem Uncore 2700MHZ -> Vol[947] mv
3>Totem Uncore 2900MHZ -> Vol[980] mv
3>Totem Uncore 3000MHZ -> Vol[994] mv
3>Core VF curve:
3>[ 400]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 450]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 500]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 550]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 600]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 650]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 700]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 750]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 800]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 850]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 900]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 950]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1000]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1050]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1100]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1150]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1200]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1250]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1300]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1350]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1400]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1450]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1500]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1550]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1600]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1650]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1700]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1750]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1800]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1850]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1900]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1950]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2000]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2050]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2100]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2150]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2200]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2250]MHZ -> Vol TA[ 813]mv TB[ 815]mv
3>[2300]MHZ -> Vol TA[ 826]mv TB[ 827]mv
3>[2350]MHZ -> Vol TA[ 838]mv TB[ 840]mv
3>[2400]MHZ -> Vol TA[ 851]mv TB[ 853]mv
3>[2450]MHZ -> Vol TA[ 863]mv TB[ 865]mv
3>[2500]MHZ -> Vol TA[ 876]mv TB[ 878]mv
3>[2550]MHZ -> Vol TA[ 888]mv TB[ 891]mv
3>[2600]MHZ -> Vol TA[ 901]mv TB[ 903]mv
3>[2650]MHZ -> Vol TA[ 913]mv TB[ 916]mv
3>[2700]MHZ -> Vol TA[ 926]mv TB[ 929]mv
3>[2750]MHZ -> Vol TA[ 943]mv TB[ 946]mv
3>[2800]MHZ -> Vol TA[ 961]mv TB[ 964]mv
3>[2850]MHZ -> Vol TA[ 979]mv TB[ 982]mv
3>[2900]MHZ -> Vol TA[ 997]mv TB[1000]mv
3>[2950]MHZ -> Vol TA[1014]mv TB[1017]mv
3>[3000]MHZ -> Vol TA[1031]mv TB[1035]mv
3>[3050]MHZ -> Vol TA[1045]mv TB[1048]mv
3>[3100]MHZ -> Vol TA[1059]mv TB[1062]mv
3>Uncore VF curve:
3>Uncore [   0]MHZ -> Vol [ 810]mv
3>Uncore [ 100]MHZ -> Vol [ 810]mv
3>Uncore [ 200]MHZ -> Vol [ 810]mv
3>Uncore [ 300]MHZ -> Vol [ 810]mv
3>Uncore [ 400]MHZ -> Vol [ 810]mv
3>Uncore [ 500]MHZ -> Vol [ 877]mv
3>Uncore [ 600]MHZ -> Vol [ 877]mv
3>Uncore [ 700]MHZ -> Vol [ 877]mv
3>Uncore [ 800]MHZ -> Vol [ 877]mv
3>Uncore [ 900]MHZ -> Vol [ 877]mv
3>Uncore [1000]MHZ -> Vol [ 877]mv
3>Uncore [1100]MHZ -> Vol [ 877]mv
3>Uncore [1200]MHZ -> Vol [ 877]mv
3>Uncore [1300]MHZ -> Vol [ 877]mv
3>Uncore [1400]MHZ -> Vol [ 877]mv
3>Uncore [1500]MHZ -> Vol [ 877]mv
3>Uncore [1600]MHZ -> Vol [ 877]mv
3>Uncore [1700]MHZ -> Vol [ 877]mv
3>Uncore [1800]MHZ -> Vol [ 877]mv
3>Uncore [1900]MHZ -> Vol [ 877]mv
3>Uncore [2000]MHZ -> Vol [ 877]mv
3>Uncore [2100]MHZ -> Vol [ 884]mv
3>Uncore [2200]MHZ -> Vol [ 891]mv
3>Uncore [2300]MHZ -> Vol [ 898]mv
3>Uncore [2400]MHZ -> Vol [ 905]mv
3>Uncore [2500]MHZ -> Vol [ 912]mv
3>Uncore [2600]MHZ -> Vol [ 929]mv
3>Uncore [2700]MHZ -> Vol [ 947]mv
3>Uncore [2800]MHZ -> Vol [ 963]mv
3>Uncore [2900]MHZ -> Vol [ 980]mv
3>Uncore [3000]MHZ -> Vol [ 994]mv
3>[TracePoint] type[  0] cmd[  1] data[  6]
3>[TracePoint] type[  0] cmd[  1] data[  7]
3>
********Hello Huawei LiteOS********

KpxxxxIPU Firmware Version : V32.75.0
LiteOS Kernel Version : 5.7.0
3>Run on ChipVersion[0] Node[3] Die[0]
3>build time : Apr 24 2026 18:00:00

3>**********************************
3>
main core booting up...
3>start set affinity
3>
mpidr = 0x810c0000
3>sram ecc state: 0x0, sram ecc cnt: 0x0
3>[TracePoint] type[  0] cmd[  2] data[  1]
3>[TracePoint] type[  0] cmd[  2] data[  2]
3>LRDXSD_LOCK_OFFSET = 0x0
3>LRDXSD_ERRIMSK_OFFSET = 0x0
3>LRDXSD_DBG_OTIMSK_OFFSET = 0x0
3>LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
3>LRDXSD_DBG_EN_OFFSET = 0x1
3>======tsensor params======
3>  is_trimmed       : 1
3>  underclocking_en : 1
3>===========end============
3>soc tsensor init done
3>========vrd info from cpld========
3>vrd_id | u64                | pmbus_en | avsbus_en | loop | pmbus_id | pmbus_addr | avs_sw | pmbus_sw | addr_9545 | domain_type | die_mask | reserved
3>  00   | 0x0001000100002017 | 0x1      | 0x1       | 0x1  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0100   | 0x0
3>  01   | 0x000300030000201b | 0x1      | 0x1       | 0x2  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x3         | 0x0300   | 0x0
3>  02   | 0x0000010500002b15 | 0x1      | 0x0       | 0x1  | 0x1      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0001   | 0x0
3>  03   | 0x0002000100002027 | 0x1      | 0x1       | 0x1  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0200   | 0x0
3>  04   | 0x000300020000202b | 0x1      | 0x1       | 0x2  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x2         | 0x0300   | 0x0
3>  05   | 0x0000020500002b25 | 0x1      | 0x0       | 0x1  | 0x2      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0002   | 0x0
3>  06   | 0x0003000400002b29 | 0x1      | 0x0       | 0x2  | 0x2      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x4         | 0x0300   | 0x0
3>================end===============
3>=============vrd info=============
3>power domain num: 7
3>power domain[00] id:0 | CORE_DVFS_TA       | PMBus NA | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
3>power domain[01] id:1 | DDR_VDD            | PMBus NA | cap:0x3 | rail:1 | addr:0x20 | def_volt: 765 mV | min_volt: 650 mV | max_volt: 850 mV
3>power domain[02] id:4 | IO_DVDD_NA         | PMBus NA | cap:0x1 | rail:0 | addr:0x2b | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
3>power domain[03] id:2 | CORE_DVFS_TB       | PMBus NB | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
3>power domain[04] id:3 | UNCORE_DVFS        | PMBus NB | cap:0x3 | rail:1 | addr:0x20 | def_volt: 980 mV | min_volt: 750 mV | max_volt:1100 mV
3>power domain[05] id:5 | IO_DVDD_NB         | PMBus NB | cap:0x1 | rail:0 | addr:0x2b | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
3>power domain[06] id:6 | DDR_VDDQ           | PMBus NB | cap:0x1 | rail:1 | addr:0x2b | def_volt:1100 mV | min_volt:1000 mV | max_volt:1200 mV
3>================end===============
3>pmbus[0] init done
3>pmbus[1] init done
3>power domain[0] CORE_DVFS_TA       | NA PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
3>power domain[1] DDR_VDD            | NA PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 765 mV | pmu:MP2882
3>power domain[4] IO_DVDD_NA         | NA PMBus        | rail:0 | addr:0x2b | def_volt: 800 mV | pmu:MP2882
3>power domain[2] CORE_DVFS_TB       | NB PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
3>power domain[3] UNCORE_DVFS        | NB PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 980 mV | pmu:MP2882
3>power domain[5] IO_DVDD_NB         | NB PMBus        | rail:0 | addr:0x2b | def_volt: 800 mV | pmu:MP2882
3>power domain[6] DDR_VDDQ           | NB PMBus        | rail:1 | addr:0x2b | def_volt:1100 mV | pmu:MP2882
3>power domain[0] CORE_DVFS_TA       is transferred to AVSBus mode
3>power domain[1] DDR_VDD            is transferred to AVSBus mode
3>power domain[2] CORE_DVFS_TB       is transferred to AVSBus mode
3>power domain[3] UNCORE_DVFS        is transferred to AVSBus mode
3>avsbus resync success
3>avsbus[0] init done
3>avsbus resync success
3>avsbus[1] init done
3>============volt boot============
3>power domain[0] volt = 1099 mV
3>power domain[1] volt =  765 mV
3>power domain[4] volt =  804 mV
3>power domain[2] volt = 1105 mV
3>power domain[3] volt = 1007 mV
3>power domain[5] volt =  800 mV
3>power domain[6] volt = 1101 mV
3>===============end===============
3>--w&h rd rail:0, 1099, CORE_DVFS_TA
3>--w&h rd rail:1, 765, CORE_DVFS_TA
3>power domain[0] set volt --> 1099 mV success
3>--w&h rd rail:0, 1105, CORE_DVFS_TB
3>--w&h rd rail:1, 1007, CORE_DVFS_TB
3>power domain[2] set volt --> 1105 mV success
3>power domain[3] set volt -->  984 mV success
3>power domain[1] set volt -->  761 mV success
3>power domain[4] set volt -->  804 mV success
3>power domain[5] set volt -->  798 mV success
3>============volt post============
3>power domain[0] volt = 1099 mV
3>power domain[1] volt =  763 mV
3>power domain[4] volt =  804 mV
3>power domain[2] volt = 1105 mV
3>power domain[3] volt =  982 mV
3>power domain[5] volt =  798 mV
3>power domain[6] volt = 1103 mV
3>===============end===============
3>Hboot1 Info RAW Dump: [0x01][0x00][0x00][0x14][0x01][0x00][0x01]
3>PowerSensorSupport[1], Cali[5120], Loss[0]
3>Power Sensor Calibration Value[5120]!
3>the power sensor : manu id = 2peak, die id = TPA626
3>power sensor[0] init success
3>die[0] its[0] init done
3>die[0] its[1] init done
3>die[0] its[2] init done
3>die[0] its[3] init done
3>die[0] its[4] init done
3>die[0] its[5] init done
3>die[0] its[6] init done
3>die[0] its[7] init done
3>die[0] its[8] init done
3>die[0] its[9] init done
3>die[1] its[0] init done
3>die[1] its[1] init done
3>die[1] its[2] init done
3>die[1] its[3] init done
3>die[1] its[4] init done
3>die[1] its[5] init done
3>die[1] its[6] init done
3>die[1] its[7] init done
3>die[1] its[8] init done
3>die[1] its[9] init done
3>Totem[0] Core Boot Vol [1099]mv
3>Totem[0] Core Current Vol [1100]mv
3>Totem[1] Core Boot Vol [1105]mv
3>Totem[1] Core Current Vol [1100]mv
3>NA 1620V190
3>NB 1620V190
3>GetCoreBaseFreq [2900000KHZ]
3>GetCoreTurboFreq [2900000KHZ]
3>GetCustomClusterNum [10]
3>Ipu ACG Training Done!
3>AP Last Time:[0.00.01.545]
3>wait UEFI pll init...
3>done
3>acg trim start
3>core trim freq:2000, avs:0 volt:810mv
3>core trim freq:2000, avs:0 volt:810mv
3>core trim freq:2050, avs:1 volt:810mv
3>core trim freq:2050, avs:1 volt:810mv
3>core trim freq:2100, avs:2 volt:810mv
3>core trim freq:2100, avs:2 volt:810mv
3>core trim freq:2150, avs:3 volt:810mv
3>core trim freq:2150, avs:3 volt:810mv
3>core trim freq:2200, avs:4 volt:810mv
3>core trim freq:2200, avs:4 volt:810mv
3>core trim freq:2250, avs:5 volt:813mv
3>core trim freq:2250, avs:5 volt:815mv
3>core trim freq:2300, avs:6 volt:826mv
3>core trim freq:2300, avs:6 volt:827mv
3>core trim freq:2350, avs:7 volt:838mv
3>core trim freq:2350, avs:7 volt:840mv
3>core trim freq:2400, avs:8 volt:851mv
3>core trim freq:2400, avs:8 volt:853mv
3>core trim freq:2450, avs:9 volt:863mv
3>core trim freq:2450, avs:9 volt:865mv
3>core trim freq:2500, avs:10 volt:876mv
3>core trim freq:2500, avs:10 volt:878mv
3>core trim freq:2550, avs:11 volt:888mv
3>core trim freq:2550, avs:11 volt:891mv
3>core trim freq:2600, avs:12 volt:901mv
3>core trim freq:2600, avs:12 volt:903mv
3>core trim freq:2650, avs:13 volt:913mv
3>core trim freq:2650, avs:13 volt:916mv
3>core trim freq:2700, avs:14 volt:926mv
3>core trim freq:2700, avs:14 volt:929mv
3>core trim freq:2750, avs:15 volt:943mv
3>core trim freq:2750, avs:15 volt:946mv
3>core trim freq:2800, avs:16 volt:961mv
3>core trim freq:2800, avs:16 volt:964mv
3>core trim freq:2850, avs:17 volt:979mv
3>core trim freq:2850, avs:17 volt:982mv
3>core trim freq:2900, avs:18 volt:997mv
3>core trim freq:2900, avs:18 volt:1000mv
3>core trim freq:2950, avs:19 volt:1014mv
3>core trim freq:2950, avs:19 volt:1017mv
3>core trim freq:3000, avs:20 volt:1031mv
3>core trim freq:3000, avs:20 volt:1035mv
3>core trim freq:3050, avs:21 volt:1045mv
3>core trim freq:3050, avs:21 volt:1048mv
3>core trim freq:3100, avs:22 volt:1059mv
3>core trim freq:3100, avs:22 volt:1062mv
3>acg trim end
3>LDO disabled
3>[TracePoint] type[  0] cmd[  2] data[  3]
3>Interrupt 423 register OK
3>Interrupt 430 register OK
3>[TracePoint] type[  0] cmd[  2] data[  4]
3>
3>cpu 0 entering scheduler
3>[TracePoint] type[  0] cmd[  3] data[  1]
3>add your ipu app init here!
3>IpuInterfaceTaskStart Entry ...
3>ipu interface task wait parameters from uefi...
3>thermal soc task enabled
3>AP Last Time:[0.00.44.948]
3>ThermalDimmStart Entry ...
3>wait ddr init done...
3>power task start...
3>[TracePoint] type[  0] cmd[  3] data[  2]
3>ufs task wait parameters from uefi...
3>AmuTaskStart Entry ... 
3>amu task wait parameters from uefi...
3>ThermalSiwStart Entry ...
3>ThermalSiwTask idle...
3>DemtTaskStart Entry ...
3>[TracePoint] type[  0] cmd[  3] data[  3]
3>demt task wait parameters from uefi...
3>HiBoostTaskStart Entry ...
3>HiBoost task enabled
3>Waiting for UEFI parameters...
3>[TracePoint] type[  0] cmd[  3] data[  4]
3>[TracePoint] type[  0] cmd[  3] data[  5]
3>uefi parameters ready!
3>UFSProfile[0]
3>PowerPolicy[2] BenchMarkSelection[0]
3>ipu interface task wait ddr init done from uefi...
3>ufs task parameters from uefi ready
3>uncore domain[0] freq:2900
3>uncore domain[1] freq:2900
3>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
3>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
3>======sioe status======
3>thermal soc task restore underclocking_en=1
3>ppu alert temp div init done
3>TA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
3>TA_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
3>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
3>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
3>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
3>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
3>==========end==========
3>sioe init done
3>ufs task enabled
3>--> UFS profile[0]
3>UEFI parameters ready
3>UncoreMaxFreq Set to [2900 MHZ]
3>get TDP from efuse success, value = 357500mw
3>target power set to [357500]mw, brd:[357500]
3>demt task parameters from uefi ready
0>uefi ddr init finish!
0>ipu interface task wait uefi end done from uefi...
0>ddr init done, start thermal dimm task
0>======dimm status======
0>  chl[0] dimm0 2, dimm1 0
0>  chl[1] dimm0 2, dimm1 0
0>  chl[2] dimm0 2, dimm1 0
0>  chl[3] dimm0 2, dimm1 0
0>  chl[4] dimm0 2, dimm1 0
0>  chl[5] dimm0 2, dimm1 0
0>  chl[6] dimm0 2, dimm1 0
0>  chl[7] dimm0 2, dimm1 0
0>==========end==========
0>chl[0] registered, dimm mask = 0x1
0>chl[1] registered, dimm mask = 0x1
0>chl[2] registered, dimm mask = 0x1
0>chl[3] registered, dimm mask = 0x1
0>chl[4] registered, dimm mask = 0x1
0>chl[5] registered, dimm mask = 0x1
0>chl[6] registered, dimm mask = 0x1
0>chl[7] registered, dimm mask = 0x1
0>=====dimm temp params=====
0>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
0>  is_thermal_thro_en  : 1
0>  is_aref_rate_auto   : 1
0>===========end============
1>uefi ddr init finish!
1>ipu interface task wait uefi end done from uefi...
1>ddr init done, start thermal dimm task
1>======dimm status======
1>  chl[0] dimm0 2, dimm1 0
1>  chl[1] dimm0 2, dimm1 0
1>  chl[2] dimm0 2, dimm1 0
1>  chl[3] dimm0 2, dimm1 0
1>  chl[4] dimm0 2, dimm1 0
1>  chl[5] dimm0 2, dimm1 0
1>  chl[6] dimm0 2, dimm1 0
1>  chl[7] dimm0 2, dimm1 0
2>uefi ddr init finish!
2>ipu interface task wait uefi end done from uefi...
3>uefi ddr init finish!
3>ipu interface task wait uefi end done from uefi...
3>ddr init done, start thermal dimm task
3>======dimm status======
3>  chl[0] dimm0 2, dimm1 0
3>  chl[1] dimm0 2, dimm1 0
3>  chl[2] dimm0 2, dimm1 0
3>  chl[3] dimm0 2, dimm1 0
3>  chl[4] dimm0 2, dimm1 0
3>  chl[5] dimm0 2, dimm1 0
3>  chl[6] dimm0 2, dimm1 0
3>  chl[7] dimm0 2, dimm1 0
3>==========end==========
1>==========end==========
1>chl[0] registered, dimm mask = 0x1
1>chl[1] registered, dimm mask = 0x1
1>chl[2] registered, dimm mask = 0x1
1>chl[3] registered, dimm mask = 0x1
1>chl[4] registered, dimm mask = 0x1
1>chl[5] registered, dimm mask = 0x1
1>chl[6] registered, dimm mask = 0x1
1>chl[7] registered, dimm mask = 0x1
1>=====dimm temp params=====
1>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
1>  is_thermal_thro_en  : 1
1>  is_aref_rate_auto   : 1
1>===========end============
2>ddr init done, start thermal dimm task
2>======dimm status======
2>  chl[0] dimm0 2, dimm1 0
2>  chl[1] dimm0 2, dimm1 0
2>  chl[2] dimm0 2, dimm1 0
2>  chl[3] dimm0 2, dimm1 0
2>  chl[4] dimm0 2, dimm1 0
2>  chl[5] dimm0 2, dimm1 0
2>  chl[6] dimm0 2, dimm1 0
2>  chl[7] dimm0 2, dimm1 0
2>==========end==========
2>chl[0] registered, dimm mask = 0x1
2>chl[1] registered, dimm mask = 0x1
2>chl[2] registered, dimm mask = 0x1
2>chl[3] registered, dimm mask = 0x1
2>chl[4] registered, dimm mask = 0x1
2>chl[5] registered, dimm mask = 0x1
2>chl[6] registered, dimm mask = 0x1
2>chl[7] registered, dimm mask = 0x1
2>=====dimm temp params=====
2>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
2>  is_thermal_thro_en  : 1
2>  is_aref_rate_auto   : 1
2>===========end============
3>chl[0] registered, dimm mask = 0x1
3>chl[1] registered, dimm mask = 0x1
3>chl[2] registered, dimm mask = 0x1
3>chl[3] registered, dimm mask = 0x1
3>chl[4] registered, dimm mask = 0x1
3>chl[5] registered, dimm mask = 0x1
3>chl[6] registered, dimm mask = 0x1
3>chl[7] registered, dimm mask = 0x1
3>=====dimm temp params=====
3>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
3>  is_thermal_thro_en  : 1
3>  is_aref_rate_auto   : 1
3>===========end============
[0.01.24.023]DDR Rreserved for IMU: len = 3e00000
[LOG]head = 0x0, tail = 0x4f35, logSize = 0x4f35
copy registry.json file success
Set component all release version to sram end.
ipcMsgSend success
HsmLogInit Ret 1, Len 4, val 0x32022a06
[0.01.24.073]starting ras Init
nodeId = 0, dieId = 0, isSasExist = 0.
nodeId = 0, dieId = 2, isSasExist = 0.
nodeId = 1, dieId = 0, isSasExist = 0.
nodeId = 1, dieId = 2, isSasExist = 0.
nodeId = 2, dieId = 0, isSasExist = 0.
nodeId = 2, dieId = 2, isSasExist = 0.
nodeId = 3, dieId = 0, isSasExist = 0.
nodeId = 3, dieId = 2, isSasExist = 0.
Mce Table head exist!
RasIntRegister init 452 
RasIntRegister init 453 
RasIntRegister init 64 
RasIntRegister init 65 
RasIntRegister init 465 
RasIntRegister init 466 
RasIntRegister init 86 
RasIntRegister init 87 
RasIntRegister init 478 
RasIntRegister init 479 
RasIntRegister init 108 
RasIntRegister init 109 
RasIntRegister init 491 
RasIntRegister init 492 
RasIntRegister init 130 
RasIntRegister init 131 
RasIntRegister init 504 
RasIntRegister init 505 
RasIntRegister init 152 
RasIntRegister init 153 
RasIntRegister init 517 
RasIntRegister init 518 
RasIntRegister init 174 
RasIntRegister init 175 
RasIntRegister init 530 
RasIntRegister init 531 
RasIntRegister init 196 
RasIntRegister init 197 
RasIntRegister init 543 
RasIntRegister init 544 
RasIntRegister init 218 
RasIntRegister init 219 
RasIntRegister init 76 
RasIntRegister init 98 
RasIntRegister init 120 
RasIntRegister init 142 
RasIntRegister init 164 
RasIntRegister init 186 
RasIntRegister init 208 
RasIntRegister init 230 
[0.01.24.195]starting ras end
3>chl[0] max_temp 26'C, aref_rate 0x5 --> 0x4
3>chl[1] max_temp 26'C, aref_rate 0x5 --> 0x4
3>chl[2] max_temp 26'C, aref_rate 0x5 --> 0x4
3>chl[3] max_temp 26'C, aref_rate 0x5 --> 0x4
3>chl[4] max_temp 26'C, aref_rate 0x5 --> 0x4
3>chl[5] max_temp 26'C, aref_rate 0x5 --> 0x4
3>chl[6] max_temp 26'C, aref_rate 0x5 --> 0x4
3>chl[7] max_temp 26'C, aref_rate 0x5 --> 0x4
0>chl[0] max_temp 26'C, aref_rate 0x5 --> 0x4
0>chl[1] max_temp 26'C, aref_rate 0x5 --> 0x4
0>chl[2] max_temp 26'C, aref_rate 0x5 --> 0x4
0>chl[3] max_temp 26'C, aref_rate 0x5 --> 0x4
0>chl[4] max_temp 26'C, aref_rate 0x5 --> 0x4
0>chl[5] max_temp 26'C, aref_rate 0x5 --> 0x4
0>chl[6] max_temp 26'C, aref_rate 0x5 --> 0x4
0>chl[7] max_temp 26'C, aref_rate 0x5 --> 0x4
1>chl[0] max_temp 26'C, aref_rate 0x5 --> 0x4
1>chl[1] max_temp 26'C, aref_rate 0x5 --> 0x4
1>chl[2] max_temp 26'C, aref_rate 0x5 --> 0x4
1>chl[3] max_temp 26'C, aref_rate 0x5 --> 0x4
1>chl[4] max_temp 26'C, aref_rate 0x5 --> 0x4
1>chl[5] max_temp 26'C, aref_rate 0x5 --> 0x4
1>chl[6] max_temp 26'C, aref_rate 0x5 --> 0x4
1>chl[7] max_temp 26'C, aref_rate 0x5 --> 0x4
2>chl[0] max_temp 27'C, aref_rate 0x5 --> 0x4
2>chl[1] max_temp 27'C, aref_rate 0x5 --> 0x4
2>chl[2] max_temp 27'C, aref_rate 0x5 --> 0x4
2>chl[3] max_temp 27'C, aref_rate 0x5 --> 0x4
2>chl[4] max_temp 27'C, aref_rate 0x5 --> 0x4
2>chl[5] max_temp 27'C, aref_rate 0x5 --> 0x4
2>chl[6] max_temp 27'C, aref_rate 0x5 --> 0x4
2>chl[7] max_temp 27'C, aref_rate 0x5 --> 0x4
[ERR]ipc result error, result 0x28010009
ipcMsgSend fail
Send tee measure to HSM respon:0
get mem silk data length: 192
0: skt = 0 logic = 2 phy = 0 
1: skt = 0 logic = 2 phy = 0 
2: skt = 0 logic = 7 phy = 1 
3: skt = 0 logic = 7 phy = 1 
4: skt = 0 logic = 0 phy = 2 
5: skt = 0 logic = 0 phy = 2 
6: skt = 0 logic = 5 phy = 3 
7: skt = 0 logic = 5 phy = 3 
8: skt = 1 logic = 2 phy = 0 
9: skt = 1 logic = 2 phy = 0 
10: skt = 1 logic = 7 phy = 1 
11: skt = 1 logic = 7 phy = 1 
12: skt = 1 logic = 0 phy = 2 
13: skt = 1 logic = 0 phy = 2 
14: skt = 1 logic = 5 phy = 3 
15: skt = 1 logic = 5 phy = 3 
16: skt = 0 logic = 3 phy = 4 
17: skt = 0 logic = 3 phy = 4 
18: skt = 0 logic = 6 phy = 5 
19: skt = 0 logic = 6 phy = 5 
20: skt = 0 logic = 1 phy = 6 
21: skt = 1 logic = 1 phy = 6 
22: skt = 1 logic = 1 phy = 6 
23: skt = 1 logic = 4 phy = 7 
24: skt = 1 logic = 4 phy = 7 
25: skt = 1 logic = 6 phy = 5 
26: skt = 1 logic = 6 phy = 5 
27: skt = 1 logic = 3 phy = 4 
28: skt = 0 logic = 1 phy = 6 
29: skt = 0 logic = 4 phy = 7 
30: skt = 0 logic = 4 phy = 7 
31: skt = 1 logic = 3 phy = 4 
32: skt = 2 logic = 2 phy = 0 
33: skt = 2 logic = 2 phy = 0 
34: skt = 2 logic = 7 phy = 1 
35: skt = 2 logic = 7 phy = 1 
36: skt = 2 logic = 0 phy = 2 
37: skt = 3 logic = 4 phy = 7 
38: skt = 3 logic = 1 phy = 6 
39: skt = 3 logic = 4 phy = 7 
40: skt = 3 logic = 1 phy = 6 
41: skt = 3 logic = 6 phy = 5 
42: skt = 3 logic = 6 phy = 5 
43: skt = 3 logic = 3 phy = 4 
44: skt = 3 logic = 3 phy = 4 
45: skt = 2 logic = 4 phy = 7 
46: skt = 2 logic = 4 phy = 7 
47: skt = 2 logic = 1 phy = 6 
48: skt = 2 logic = 1 phy = 6 
49: skt = 2 logic = 6 phy = 5 
50: skt = 2 logic = 6 phy = 5 
51: skt = 2 logic = 3 phy = 4 
52: skt = 2 logic = 3 phy = 4 
53: skt = 3 logic = 5 phy = 3 
54: skt = 3 logic = 5 phy = 3 
55: skt = 3 logic = 0 phy = 2 
56: skt = 3 logic = 0 phy = 2 
57: skt = 3 logic = 7 phy = 1 
58: skt = 3 logic = 7 phy = 1 
59: skt = 3 logic = 2 phy = 0 
60: skt = 3 logic = 2 phy = 0 
61: skt = 2 logic = 5 phy = 3 
62: skt = 2 logic = 5 phy = 3 
63: skt = 2 logic = 0 phy = 2 
[0.02.07.902]TF Heartbeat Start
[0.02.12.918]PCIE INIT DONE.
g_mctpQueueCount(48) > tabCnt(42)
slotNum = 0x8
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[0] port:20  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[1] port:22  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[2] port:20  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[3] port:22  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[4] port:20  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[5] port:22  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[6] port:24  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[7] port:26  pcieSlotCtrl.data (after)0x14801c0.

Interrupt 454 register OK
Interrupt 467 register OK
Interrupt 480 register OK
Interrupt 493 register OK
Interrupt 506 register OK
Interrupt 519 register OK
Interrupt 532 register OK
Interrupt 545 register OK
data = 0x0
pmt Init done

Add ep: bdf=a200 eid=9 epCnt=1 eid_alloc=a
Add ep: bdf=c400 eid=a epCnt=1 eid_alloc=b
Add ep: bdf=d000 eid=b epCnt=1 eid_alloc=c
[0.02.13.149]slot[0] port:20 begin to power OFF.
[0.02.13.150]slot[1] port:22 begin to power OFF.
[0.02.13.153]slot[2] port:20 begin to power OFF.
[0.02.13.158]slot[3] port:22 begin to power OFF.
[0.02.13.162]slot[4] port:20 begin to power ON.
[0.02.13.166]slot[5] port:22 begin to power ON.
[0.02.13.171]slot[6] port:24 begin to power ON.
[0.02.13.175]slot[7] port:26 begin to power ON.
Add ep: bdf=300 eid=c epCnt=1 eid_alloc=d
mctp task ok.
[0.03.34.136]BIOS POST END.
Create SetReportPcieMmioToBmc ok.
Start SetReportPcieMmioToBmc ok.
Enter current value process
0>uefi end finish!
0>ipu interface task exit!
0>amu task parameters from uefi ready
1>uefi end finish!
1>ipu interface task exit!
1>amu task parameters from uefi ready
2>uefi end finish!
2>ipu interface task exit!
2>amu task parameters from uefi ready
3>uefi end finish!
3>ipu interface task exit!
3>amu task parameters from uefi ready
0>amu task activated
0>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
1>amu task activated
1>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
2>amu task activated
2>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
3>amu task activated
3>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
[0.08.34.135]IpmiCmdReportPcieMMIO start
[0.08.50.779]IpmiCmdReportPcieMMIO end
pool addr          pool size    used size     free size    max free node size   used node num     free node num      UsageWaterLine
---------------    --------     -------       --------     --------------       -------------      ------------      ------------
0x840908c350       0x22880      0x189d8       0x9c38       0x9550               0xbf               0x3                0x19330        
765, CORE_DVFS_TA
2>power domain[0] set volt --> 1099 mV success
2>--w&h rd rail:0, 1103, CORE_DVFS_TB
2>--w&h rd rail:1, 1003, CORE_DVFS_TB
2>power domain[2] set volt --> 1101 mV success
2>power domain[3] set volt -->  978 mV success
2>power domain[1] set volt -->  763 mV success
2>power domain[4] set volt -->  798 mV success
2>power domain[5] set volt -->  804 mV success
2>============volt post============
2>power domain[0] volt = 1097 mV
2>power domain[1] volt =  763 mV
2>power domain[4] volt =  800 mV
2>power domain[2] volt = 1103 mV
2>power domain[3] volt =  978 mV
2>power domain[5] volt =  802 mV
2>power domain[6] volt = 1103 mV
2>===============end===============
2>Hboot1 Info RAW Dump: [0x91][0x00][0x00][0x14][0x01][0x00][0x01]
2>PowerSensorSupport[1], Cali[5120], Loss[7200]
2>Power Sensor Calibration Value[5120]!
2>the power sensor : manu id = 2peak, die id = TPA626
2>power sensor[0] init success
2>die[0] its[0] init done
2>die[0] its[1] init done
2>die[0] its[2] init done
2>die[0] its[3] init done
2>die[0] its[4] init done
2>die[0] its[5] init done
2>die[0] its[6] init done
2>die[0] its[7] init done
2>die[0] its[8] init done
2>die[0] its[9] init done
2>die[1] its[0] init done
2>die[1] its[1] init done
2>die[1] its[2] init done
2>die[1] its[3] init done
2>die[1] its[4] init done
2>die[1] its[5] init done
2>die[1] its[6] init done
2>die[1] its[7] init done
2>die[1] its[8] init done
2>die[1] its[9] init done
2>Totem[0] Core Boot Vol [1099]mv
2>Totem[0] Core Current Vol [1100]mv
2>Totem[1] Core Boot Vol [1101]mv
2>Totem[1] Core Current Vol [1100]mv
2>NA 1620V190
2>NB 1620V190
2>GetCoreBaseFreq [2900000KHZ]
2>GetCoreTurboFreq [2900000KHZ]
2>GetCustomClusterNum [10]
2>Ipu ACG Training Done!
2>AP Last Time:[0.00.01.547]
2>wait UEFI pll init...
2>done
2>acg trim start
2>core trim freq:2000, avs:0 volt:810mv
2>core trim freq:2000, avs:0 volt:810mv
2>core trim freq:2050, avs:1 volt:810mv
2>core trim freq:2050, avs:1 volt:810mv
2>core trim freq:2100, avs:2 volt:810mv
2>core trim freq:2100, avs:2 volt:810mv
2>core trim freq:2150, avs:3 volt:810mv
2>core trim freq:2150, avs:3 volt:810mv
2>core trim freq:2200, avs:4 volt:810mv
2>core trim freq:2200, avs:4 volt:810mv
2>core trim freq:2250, avs:5 volt:813mv
2>core trim freq:2250, avs:5 volt:814mv
2>core trim freq:2300, avs:6 volt:826mv
2>core trim freq:2300, avs:6 volt:827mv
2>core trim freq:2350, avs:7 volt:838mv
2>core trim freq:2350, avs:7 volt:840mv
2>core trim freq:2400, avs:8 volt:851mv
2>core trim freq:2400, avs:8 volt:852mv
2>core trim freq:2450, avs:9 volt:863mv
2>core trim freq:2450, avs:9 volt:865mv
2>covs:20 volt:1034mv
2>core trim freq:3050, avs:21 volt:1046mv
2>core trim freq:3050, avs:21 volt:1048mv
2>core trim freq:3100, avs:22 volt:1060mv
2>core trim freq:3100, avs:22 volt:1062mv
2>acg trim end
2>LDO disabled
2>[TracePoint] type[  0] cmd[  2] data[  3]
2>Interrupt 423 register OK
2>Interrupt 430 register OK
2>[TracePoint] type[  0] cmd[  2] data[  4]
2>
2>cpu 0 entering scheduler
2>[TracePoint] type[  0] cmd[  3] data[  1]
2>add your ipu app init here!
2>IpuInterfaceTaskStart Entry ...
2>ipu interface task wait parameters from uefi...
2>thermal soc task enabled
2>AP Last Time:[0.00.44.668]
2>ThermalDimmStart Entry ...
2>wait ddr init done...
2>power task start...
2>[TracePoint] type[  0] cmd[  3] data[  2]
2>ufs task wait parameters from uefi...
2>AmuTaskStart Entry ... 
2>amu task wait parameters from uefi...
2>ThermalSiwStart Entry ...
2>ThermalSiwTask idle...
2>DemtTaskStart Entry ...
2>[TracePoint] type[  0] cmd[  3] data[  3]
2>demt task wait parameters from uefi...
2>HiBoostTaskStart Entry ...
2>HiBoost task enabled
2>Waiting for UEFI parameters...
2>[TracePoint] type[  0] cmd[  3] data[  4]
2>[TracePoint] type[  0] cmd[  3] data[  5]
2>uefi parameters ready!
2>UFSProfile[0]
2>PowerPolicy[2] BenchMarkSelection[0]
2>ipu interface task wait ddr init done from uefi...
2>ufs task parameters from uefi ready
2>uncore domain[0] freq:2900
2>uncore domain[1] freq:2900
2>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
2>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
2>======sioe status======
2>thermal soc task restore underclocking_en=1
2>ppu alert temp div init done
2>TA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TA_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
2>TA_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
2>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
2>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
2>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
2>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
2>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
2>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
2>==========end==========
2>sioe init done
2>ufs task enabled
2>--> UFS profile[0]
2>UEFI parameters ready
2>UncoreMaxFreq Set to [2900 MHZ]
2>get TDP from efuse success, value = 357500mw
2>target power set to [357500]mw, brd:[357500]
2>demt task parameters from uefi ready
912] mv
3>Totem Uncore 2700MHZ -> Vol[947] mv
3>Totem Uncore 2900MHZ -> Vol[980] mv
3>Totem Uncore 3000MHZ -> Vol[994] mv
3>Core VF curve:
3>[ 400]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 450]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 500]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 550]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 600]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 650]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 700]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 750]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 800]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 850]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 900]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[ 950]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1000]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1050]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1100]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1150]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1200]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1250]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1300]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1350]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1400]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1450]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1500]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1550]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1600]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1650]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1700]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1750]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1800]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1850]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1900]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[1950]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2000]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2050]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2100]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2150]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2200]MHZ -> Vol TA[ 810]mv TB[ 810]mv
3>[2250]MHZ -> Vol TA[ 813]mv TB[ 815]mv
3>[2300]MHZ -> Vol TA[ 826]mv TB[ 827]mv
3>[2350]MHZ -> Vol TA[ 838]mv TB[ 840]mv
3>[2400]MHZ -> Vol TA[ 851]mv TB[ 853]mv
3>[2450]MHZ -> Vol TA[ 863]mv TB[ 865]mv
3>[2500]MHZ -> Vol TA[ 876]mv TB[ 878]mv
3>[2550]MHZ -> Vol TA[ 888]mv TB[ 891]mv
3>[2600]MHZ -> Vol TA[ 901]mv TB[ 903]mv
3>[2650]MHZ -> Vol TA[ 913]mv TB[ 916]mv
3>[2700]MHZ -> Vol TA[ 926]mv TB[ 929]mv
3>[2750]MHZ -> Vol TA[ 943]mv TB[ 946]mv
3>[2800]MHZ -> Vol TA[ 961]mv TB[ 964]mv
3>[2850]MHZ -> Vol TA[ 979]mv TB[ 982]mv
3>[2900]MHZ -> Vol TA[ 997]mv TB[1000]mv
3>[2950]MHZ -> Vol TA[1014]mv TB[1017]mv
3>[3000]MHZ -> Vol TA[1031]mv TB[1035]mv
3>[3050]MHZ -> Vol TA[1045]mv TB[1048]mv
3>[3100]MHZ -> Vol TA[1059]mv TB[1062]mv
3>Uncore VF curve:
3>Uncore [   0]MHZ -> Vol [ 810]mv
3>Uncore [ 100]MHZ -> Vol [ 810]mv
3>Uncore [ 200]MHZ -> Vol [ 810]mv
3>Uncore [ 300]MHZ -> Vol [ 810]mv
3>Uncore [ 400]MHZ -> Vol [ 810]mv
3>Uncore [ 500]MHZ -> Vol [ 877]mv
3>Uncore [ 600]MHZ -> Vol [ 877]mv
3>Uncore [ 700]MHZ -> Vol [ 877]mv
3>Uncore [ 800]MHZ -> Vol [ 877]mv
3>Uncore [ 900]MHZ -> Vol [ 877]mv
3>Uncore [1000]MHZ -> Vol [ 877]mv
3>Uncore [1100]MHZ -> Vol [ 877]mv
3>Uncore [1200]MHZ -> Vol [ 877]mv
3>Uncore [1300]MHZ -> Vol [ 877]mv
3>Uncore [1400]MHZ -> Vol [ 877]mv
3>Uncore [1500]MHZ -> Vol [ 877]mv
3>Uncore [1600]MHZ -> Vol [ 877]mv
3>Uncore [1700]MHZ -> Vol [ 877]mv
3>Uncore [1800]MHZ -> Vol [ 877]mv
3>Uncore [1900]MHZ -> Vol [ 877]mv
3>Uncore [2000]MHZ -> Vol [ 877]mv
3>Uncore [2100]MHZ -> Vol [ 884]mv
3>Uncore [2200]MHZ -> Vol [ 891]mv
3>Uncore [2300]MHZ -> Vol [ 898]mv
3>Uncore [2400]MHZ -> Vol [ 905]mv
3>Uncore [2500]MHZ -> Vol [ 912]mv
3>Uncore [2600]MHZ -> Vol [ 929]mv
3>Uncore [2700]MHZ -> Vol [ 947]mv
3>Uncore [2800]MHZ -> Vol [ 963]mv
3>Uncore [2900]MHZ -> Vol [ 980]mv
3>Uncore [3000]MHZ -> Vol [ 994]mv
3>[TracePoint] type[  0] cmd[  1] data[  6]
3>[TracePoint] type[  0] cmd[  1] data[  7]
3>
********Hello Huawei LiteOS********

KpxxxxIPU Firmware Version : V32.75.0
LiteOS Kernel Version : 5.7.0
3>Run on ChipVersion[0] Node[3] Die[0]
3>build time : Apr 24 2026 18:00:00

3>**********************************
3>
main core booting up...
3>start set affinity
3>
mpidr = 0x810c0000
3>sram ecc state: 0x0, sram ecc cnt: 0x0
3>[TracePoint] type[  0] cmd[  2] data[  1]
3>[TracePoint] type[  0] cmd[  2] data[  2]
3>LRDXSD_LOCK_OFFSET = 0x0
3>LRDXSD_ERRIMSK_OFFSET = 0x0
3>LRDXSD_DBG_OTIMSK_OFFSET = 0x0
3>LRDXSD_DBG_OT_SET_OFFSET = 0xffffffff
3>LRDXSD_DBG_EN_OFFSET = 0x1
3>======tsensor params======
3>  is_trimmed       : 1
3>  underclocking_en : 1
3>===========end============
3>soc tsensor init done
3>========vrd info from cpld========
3>vrd_id | u64                | pmbus_en | avsbus_en | loop | pmbus_id | pmbus_addr | avs_sw | pmbus_sw | addr_9545 | domain_type | die_mask | reserved
3>  00   | 0x0001000100002017 | 0x1      | 0x1       | 0x1  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0100   | 0x0
3>  01   | 0x000300030000201b | 0x1      | 0x1       | 0x2  | 0x1      | 0x20       | 0x0    | 0x0      | 0x0       | 0x3         | 0x0300   | 0x0
3>  02   | 0x0000010500002b15 | 0x1      | 0x0       | 0x1  | 0x1      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0001   | 0x0
3>  03   | 0x0002000100002027 | 0x1      | 0x1       | 0x1  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x1         | 0x0200   | 0x0
3>  04   | 0x000300020000202b | 0x1      | 0x1       | 0x2  | 0x2      | 0x20       | 0x0    | 0x0      | 0x0       | 0x2         | 0x0300   | 0x0
3>  05   | 0x0000020500002b25 | 0x1      | 0x0       | 0x1  | 0x2      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x5         | 0x0002   | 0x0
3>  06   | 0x0003000400002b29 | 0x1      | 0x0       | 0x2  | 0x2      | 0x2b       | 0x0    | 0x0      | 0x0       | 0x4         | 0x0300   | 0x0
3>================end===============
3>=============vrd info=============
3>power domain num: 7
3>power domain[00] id:0 | CORE_DVFS_TA       | PMBus NA | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
3>power domain[01] id:1 | DDR_VDD            | PMBus NA | cap:0x3 | rail:1 | addr:0x20 | def_volt: 765 mV | min_volt: 650 mV | max_volt: 850 mV
3>power domain[02] id:4 | IO_DVDD_NA         | PMBus NA | cap:0x1 | rail:0 | addr:0x2b | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
3>power domain[03] id:2 | CORE_DVFS_TB       | PMBus NB | cap:0x3 | rail:0 | addr:0x20 | def_volt:1100 mV | min_volt: 750 mV | max_volt:1150 mV
3>power domain[04] id:3 | UNCORE_DVFS        | PMBus NB | cap:0x3 | rail:1 | addr:0x20 | def_volt: 980 mV | min_volt: 750 mV | max_volt:1100 mV
3>power domain[05] id:5 | IO_DVDD_NB         | PMBus NB | cap:0x1 | rail:0 | addr:0x2b | def_volt: 800 mV | min_volt: 700 mV | max_volt: 900 mV
3>power domain[06] id:6 | DDR_VDDQ           | PMBus NB | cap:0x1 | rail:1 | addr:0x2b | def_volt:1100 mV | min_volt:1000 mV | max_volt:1200 mV
3>================end===============
3>pmbus[0] init done
3>pmbus[1] init done
3>power domain[0] CORE_DVFS_TA       | NA PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
3>power domain[1] DDR_VDD            | NA PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 765 mV | pmu:MP2882
3>power domain[4] IO_DVDD_NA         | NA PMBus        | rail:0 | addr:0x2b | def_volt: 800 mV | pmu:MP2882
3>power domain[2] CORE_DVFS_TB       | NB PMBus/AVSBus | rail:0 | addr:0x20 | def_volt:1100 mV | pmu:MP2882
3>power domain[3] UNCORE_DVFS        | NB PMBus/AVSBus | rail:1 | addr:0x20 | def_volt: 980 mV | pmu:MP2882
3>power domain[5] IO_DVDD_NB         | NB PMBus        | rail:0 | addr:0x2b | def_volt: 800 mV | pmu:MP2882
3>power domain[6] DDR_VDDQ           | NB PMBus        | rail:1 | addr:0x2b | def_volt:1100 mV | pmu:MP2882
3>power domain[0] CORE_DVFS_TA       is transferred to AVSBus mode
3>power domain[1] DDR_VDD            is transferred to AVSBus mode
3>power domain[2] CORE_DVFS_TB       is transferred to AVSBus mode
3>power domain[3] UNCORE_DVFS        is transferred to AVSBus mode
3>avsbus resync success
3>avsbus[0] init done
3>avsbus resync success
3>avsbus[1] init done
3>============volt boot============
3>power domain[0] volt = 1099 mV
3>power domain[1] volt =  765 mV
3>power domain[4] volt =  806 mV
3>power domain[2] volt = 1105 mV
3>power domain[3] volt = 1007 mV
3>power domain[5] volt =  800 mV
3>power domain[6] volt = 1099 mV
3>===============end===============
3>--w&h rd rail:0, 1099, CORE_DVFS_TA
3>--w&h rd rail:1, 765, CORE_DVFS_TA
3>power domain[0] set volt --> 1099 mV success
3>--w&h rd rail:0, 1103, CORE_DVFS_TB
3>--w&h rd rail:1, 1007, CORE_DVFS_TB
3>power domain[2] set volt --> 1105 mV success
3>power domain[3] set volt -->  982 mV success
3>power domain[1] set volt -->  763 mV success
3>power domain[4] set volt -->  802 mV success
3>power domain[5] set volt -->  798 mV success
3>============volt post============
3>power domain[0] volt = 1099 mV
3>power domain[1] volt =  763 mV
3>power domain[4] volt =  802 mV
3>power domain[2] volt = 1105 mV
3>power domain[3] volt =  982 mV
3>power domain[5] volt =  798 mV
3>power domain[6] volt = 1101 mV
3>===============end===============
3>Hboot1 Info RAW Dump: [0x01][0x00][0x00][0x14][0x01][0x00][0x01]
3>PowerSensorSupport[1], Cali[5120], Loss[0]
3>Power Sensor Calibration Value[5120]!
3>the power sensor : manu id = 2peak, die id = TPA626
3>power sensor[0] init success
3>die[0] its[0] init done
3>die[0] its[1] init done
3>die[0] its[2] init done
3>die[0] its[3] init done
3>die[0] its[4] init done
3>die[0] its[5] init done
3>die[0] its[6] init done
3>die[0] its[7] init done
3>die[0] its[8] init done
3>die[0] its[9] init done
3>die[1] its[0] init done
3>die[1] its[1] init done
3>die[1] its[2] init done
3>die[1] its[3] init done
3>die[1] its[4] init done
3>die[1] its[5] init done
3>die[1] its[6] init done
3>die[1] its[7] init done
3>die[1] its[8] init done
3>die[1] its[9] init done
3>Totem[0] Core Boot Vol [1099]mv
3>Totem[0] Core Current Vol [1100]mv
3>Totem[1] Core Boot Vol [1105]mv
3>Totem[1] Core Current Vol [1100]mv
3>NA 1620V190
3>NB 1620V190
3>GetCoreBaseFreq [2900000KHZ]
3>GetCoreTurboFreq [2900000KHZ]
3>GetCustomClusterNum [10]
3>Ipu ACG Training Done!
3>AP Last Time:[0.00.01.547]
3>wait UEFI pll init...
3>done
3>acg trim start
3>core trim freq:2000, avs:0 volt:810mv
3>core trim freq:2000, avs:0 volt:810mv
3>core trim freq:2050, avs:1 volt:810mv
3>core trim freq:2050, avs:1 volt:810mv
3>core trim freq:2100, avs:2 volt:810mv
3>core trim freq:2100, avs:2 volt:810mv
3>core trim freq:2150, avs:3 volt:810mv
3>core trim freq:2150, avs:3 volt:810mv
3>core trim freq:2200, avs:4 volt:810mv
3>core trim freq:2200, avs:4 volt:810mv
3>core trim freq:2250, avs:5 volt:813mv
3>core trim freq:2250, avs:5 volt:815mv
3>core trim freq:2300, avs:6 volt:826mv
3>core trim freq:2300, avs:6 volt:827mv
3>core trim freq:2350, avs:7 volt:838mv
3>core trim freq:2350, avs:7 volt:840mv
3>core trim freq:2400, avs:8 volt:851mv
3>core trim freq:2400, avs:8 volt:853mv
3>core trim freq:2450, avs:9 volt:863mv
3>core trim freq:2450, avs:9 volt:865mv
3>core trim freq:2500, avs:10 volt:876mv
3>core trim freq:2500, avs:10 volt:878mv
3>core trim freq:2550, avs:11 volt:888mv
3>core trim freq:2550, avs:11 volt:891mv
3>core trim freq:2600, avs:12 volt:901mv
3>core trim freq:2600, avs:12 volt:903mv
3>core trim freq:2650, avs:13 volt:913mv
3>core trim freq:2650, avs:13 volt:916mv
3>core trim freq:2700, avs:14 volt:926mv
3>core trim freq:2700, avs:14 volt:929mv
3>core trim freq:2750, avs:15 volt:943mv
3>core trim freq:2750, avs:15 volt:946mv
3>core trim freq:2800, avs:16 volt:961mv
3>core trim freq:2800, avs:16 volt:964mv
3>core trim freq:2850, avs:17 volt:979mv
3>core trim freq:2850, avs:17 volt:982mv
3>core trim freq:2900, avs:18 volt:997mv
3>core trim freq:2900, avs:18 volt:1000mv
3>core trim freq:2950, avs:19 volt:1014mv
3>core trim freq:2950, avs:19 volt:1017mv
3>core trim freq:3000, avs:20 volt:1031mv
3>core trim freq:3000, avs:20 volt:1035mv
3>core trim freq:3050, avs:21 volt:1045mv
3>core trim freq:3050, avs:21 volt:1048mv
3>core trim freq:3100, avs:22 volt:1059mv
3>core trim freq:3100, avs:22 volt:1062mv
3>acg trim end
3>LDO disabled
3>[TracePoint] type[  0] cmd[  2] data[  3]
3>Interrupt 423 register OK
3>Interrupt 430 register OK
3>[TracePoint] type[  0] cmd[  2] data[  4]
3>
3>cpu 0 entering scheduler
3>[TracePoint] type[  0] cmd[  3] data[  1]
3>add your ipu app init here!
3>IpuInterfaceTaskStart Entry ...
3>ipu interface task wait parameters from uefi...
3>thermal soc task enabled
3>AP Last Time:[0.00.44.626]
3>ThermalDimmStart Entry ...
3>wait ddr init done...
3>power task start...
3>[TracePoint] type[  0] cmd[  3] data[  2]
3>ufs task wait parameters from uefi...
3>AmuTaskStart Entry ... 
3>amu task wait parameters from uefi...
3>ThermalSiwStart Entry ...
3>ThermalSiwTask idle...
3>DemtTaskStart Entry ...
3>[TracePoint] type[  0] cmd[  3] data[  3]
3>demt task wait parameters from uefi...
3>HiBoostTaskStart Entry ...
3>HiBoost task enabled
3>Waiting for UEFI parameters...
3>[TracePoint] type[  0] cmd[  3] data[  4]
3>[TracePoint] type[  0] cmd[  3] data[  5]
3>uefi parameters ready!
3>UFSProfile[0]
3>PowerPolicy[2] BenchMarkSelection[0]
3>ipu interface task wait ddr init done from uefi...
3>ufs task parameters from uefi ready
3>uncore domain[0] freq:2900
3>uncore domain[1] freq:2900
3>nimbus uncore domain[0] freq_div:4 all_sioe_freq:3000
3>nimbus uncore domain[1] freq_div:4 all_sioe_freq:3000
3>======sioe status======
3>thermal soc task restore underclocking_en=1
3>ppu alert temp div init done
3>TA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TA_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
3>TA_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
3>TB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE2: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE3: ASYNC, QDR, SIO_PLL, is_cdr=0
3>TB_SIOE5: ASYNC, SDR, LOW_PLL, is_cdr=0
3>TB_SIOE6: ASYNC, SDR, LOW_PLL, is_cdr=0
3>NA_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NA_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NA_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
3>NB_SIOE0: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NB_SIOE1: ASYNC, QDR, SIO_PLL, is_cdr=0
3>NB_SIOE2: ASYNC, SDR, LOW_PLL, is_cdr=0
3>==========end==========
3>sioe init done
3>ufs task enabled
3>--> UFS profile[0]
3>UEFI parameters ready
3>UncoreMaxFreq Set to [2900 MHZ]
3>get TDP from efuse success, value = 357500mw
3>target power set to [357500]mw, brd:[357500]
3>demt task parameters from uefi ready
0>uefi ddr init finish!
0>ipu interface task wait uefi end done from uefi...
1>uefi ddr init finish!
1>ipu interface task wait uefi end done from uefi...
2>uefi ddr init finish!
2>ipu interface task wait uefi end done from uefi...
3>uefi ddr init finish!
3>ipu interface task wait uefi end done from uefi...
0>ddr init done, start thermal dimm task
0>======dimm status======
0>  chl[0] dimm0 2, dimm1 0
0>  chl[1] dimm0 2, dimm1 0
0>  chl[2] dimm0 2, dimm1 0
0>  chl[3] dimm0 2, dimm1 0
0>  chl[4] dimm0 2, dimm1 0
0>  chl[5] dimm0 2, dimm1 0
0>  chl[6] dimm0 2, dimm1 0
0>  chl[7] dimm0 2, dimm1 0
0>==========end==========
0>chl[0] registered, dimm mask = 0x1
0>chl[1] registered, dimm mask = 0x1
0>chl[2] registered, dimm mask = 0x1
0>chl[3] registered, dimm mask = 0x1
0>chl[4] registered, dimm mask = 0x1
0>chl[5] registered, dimm mask = 0x1
0>chl[6] registered, dimm mask = 0x1
0>chl[7] registered, dimm mask = 0x1
0>=====dimm temp params=====
0>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
0>  is_thermal_thro_en  : 1
0>  is_aref_rate_auto   : 1
0>===========end============
1>ddr init done, start thermal dimm task
1>======dimm status======
1>  chl[0] dimm0 2, dimm1 0
1>  chl[1] dimm0 2, dimm1 0
1>  chl[2] dimm0 2, dimm1 0
1>  chl[3] dimm0 2, dimm1 0
1>  chl[4] dimm0 2, dimm1 0
1>  chl[5] dimm0 2, dimm1 0
1>  chl[6] dimm0 2, dimm1 0
1>  chl[7] dimm0 2, dimm1 0
1>==========end==========
1>chl[0] registered, dimm mask = 0x1
1>chl[1] registered, dimm mask = 0x1
1>chl[2] registered, dimm mask = 0x1
1>chl[3] registered, dimm mask = 0x1
1>chl[4] registered, dimm mask = 0x1
1>chl[5] registered, dimm mask = 0x1
1>chl[6] registered, dimm mask = 0x1
1>chl[7] registered, dimm mask = 0x1
1>=====dimm temp params=====
1>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
1>  is_thermal_thro_en  : 1
1>  is_aref_rate_auto   : 1
1>===========end============
2>ddr init done, start thermal dimm task
2>======dimm status======
2>  chl[0] dimm0 2, dimm1 0
2>  chl[1] dimm0 2, dimm1 0
2>  chl[2] dimm0 2, dimm1 0
2>  chl[3] dimm0 2, dimm1 0
2>  chl[4] dimm0 2, dimm1 0
2>  chl[5] dimm0 2, dimm1 0
2>  chl[6] dimm0 2, dimm1 0
2>  chl[7] dimm0 2, dimm1 0
2>==========end==========
2>chl[0] registered, dimm mask = 0x1
2>chl[1] registered, dimm mask = 0x1
2>chl[2] registered, dimm mask = 0x1
2>chl[3] registered, dimm mask = 0x1
2>chl[4] registered, dimm mask = 0x1
2>chl[5] registered, dimm mask = 0x1
2>chl[6] registered, dimm mask = 0x1
2>chl[7] registered, dimm mask = 0x1
2>=====dimm temp params=====
2>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
2>  is_thermal_thro_en  : 1
2>  is_aref_rate_auto   : 1
2>===========end============
3>ddr init done, start thermal dimm task
3>======dimm status======
3>  chl[0] dimm0 2, dimm1 0
3>  chl[1] dimm0 2, dimm1 0
3>  chl[2] dimm0 2, dimm1 0
3>  chl[3] dimm0 2, dimm1 0
3>  chl[4] dimm0 2, dimm1 0
3>  chl[5] dimm0 2, dimm1 0
3>  chl[6] dimm0 2, dimm1 0
3>  chl[7] dimm0 2, dimm1 0
3>==========end==========
3>chl[0] registered, dimm mask = 0x1
3>chl[1] registered, dimm mask = 0x1
3>chl[2] registered, dimm mask = 0x1
3>chl[3] registered, dimm mask = 0x1
3>chl[4] registered, dimm mask = 0x1
3>chl[5] registered, dimm mask = 0x1
3>chl[6] registered, dimm mask = 0x1
3>chl[7] registered, dimm mask = 0x1
3>=====dimm temp params=====
3>  temp_threshold      : temp_mid:85,85 | temp_hi:95 | temp_cri:100
3>  is_thermal_thro_en  : 1
3>  is_aref_rate_auto   : 1
3>===========end============
[0.01.24.571]DDR Rreserved for IMU: len = 3e00000
[LOG]head = 0x0, tail = 0x4e48, logSize = 0x4e48
copy registry.json file success
Set component all release version to sram end.
ipcMsgSend success
HsmLogInit Ret 1, Len 4, val 0x32022a06
[0.01.24.613]starting ras Init
nodeId = 0, dieId = 0, isSasExist = 0.
nodeId = 0, dieId = 2, isSasExist = 0.
nodeId = 1, dieId = 0, isSasExist = 0.
nodeId = 1, dieId = 2, isSasExist = 0.
nodeId = 2, dieId = 0, isSasExist = 0.
nodeId = 2, dieId = 2, isSasExist = 0.
nodeId = 3, dieId = 0, isSasExist = 0.
nodeId = 3, dieId = 2, isSasExist = 0.
Mce Table head exist!
RasIntRegister init 452 
RasIntRegister init 453 
RasIntRegister init 64 
RasIntRegister init 65 
RasIntRegister init 465 
RasIntRegister init 466 
RasIntRegister init 86 
RasIntRegister init 87 
RasIntRegister init 478 
RasIntRegister init 479 
RasIntRegister init 108 
RasIntRegister init 109 
RasIntRegister init 491 
RasIntRegister init 492 
RasIntRegister init 130 
RasIntRegister init 131 
RasIntRegister init 504 
RasIntRegister init 505 
RasIntRegister init 152 
RasIntRegister init 153 
RasIntRegister init 517 
RasIntRegister init 518 
RasIntRegister init 174 
RasIntRegister init 175 
RasIntRegister init 530 
RasIntRegister init 531 
RasIntRegister init 196 
RasIntRegister init 197 
RasIntRegister init 543 
RasIntRegister init 544 
RasIntRegister init 218 
RasIntRegister init 219 
RasIntRegister init 76 
RasIntRegister init 98 
RasIntRegister init 120 
RasIntRegister init 142 
RasIntRegister init 164 
RasIntRegister init 186 
RasIntRegister init 208 
RasIntRegister init 230 
[0.01.24.736]starting ras end
0>chl[0] max_temp 29'C, aref_rate 0x5 --> 0x4
0>chl[1] max_temp 29'C, aref_rate 0x5 --> 0x4
0>chl[2] max_temp 29'C, aref_rate 0x5 --> 0x4
0>chl[3] max_temp 29'C, aref_rate 0x5 --> 0x4
0>chl[4] max_temp 29'C, aref_rate 0x5 --> 0x4
0>chl[5] max_temp 29'C, aref_rate 0x5 --> 0x4
0>chl[6] max_temp 29'C, aref_rate 0x5 --> 0x4
0>chl[7] max_temp 29'C, aref_rate 0x5 --> 0x4
1>chl[0] max_temp 28'C, aref_rate 0x5 --> 0x4
1>chl[1] max_temp 28'C, aref_rate 0x5 --> 0x4
1>chl[2] max_temp 28'C, aref_rate 0x5 --> 0x4
1>chl[3] max_temp 28'C, aref_rate 0x5 --> 0x4
1>chl[4] max_temp 28'C, aref_rate 0x5 --> 0x4
1>chl[5] max_temp 28'C, aref_rate 0x5 --> 0x4
1>chl[6] max_temp 28'C, aref_rate 0x5 --> 0x4
1>chl[7] max_temp 28'C, aref_rate 0x5 --> 0x4
2>chl[0] max_temp 29'C, aref_rate 0x5 --> 0x4
2>chl[1] max_temp 29'C, aref_rate 0x5 --> 0x4
2>chl[2] max_temp 29'C, aref_rate 0x5 --> 0x4
2>chl[3] max_temp 29'C, aref_rate 0x5 --> 0x4
2>chl[4] max_temp 29'C, aref_rate 0x5 --> 0x4
2>chl[5] max_temp 29'C, aref_rate 0x5 --> 0x4
2>chl[6] max_temp 29'C, aref_rate 0x5 --> 0x4
2>chl[7] max_temp 29'C, aref_rate 0x5 --> 0x4
3>chl[0] max_temp 28'C, aref_rate 0x5 --> 0x4
3>chl[1] max_temp 28'C, aref_rate 0x5 --> 0x4
3>chl[2] max_temp 28'C, aref_rate 0x5 --> 0x4
3>chl[3] max_temp 28'C, aref_rate 0x5 --> 0x4
3>chl[4] max_temp 28'C, aref_rate 0x5 --> 0x4
3>chl[5] max_temp 28'C, aref_rate 0x5 --> 0x4
3>chl[6] max_temp 28'C, aref_rate 0x5 --> 0x4
3>chl[7] max_temp 28'C, aref_rate 0x5 --> 0x4
[ERR]ipc result error, result 0x28010009
ipcMsgSend fail
Send tee measure to HSM respon:0
get mem silk data length: 192
0: skt = 0 logic = 2 phy = 0 
1: skt = 0 logic = 2 phy = 0 
2: skt = 0 logic = 7 phy = 1 
3: skt = 0 logic = 7 phy = 1 
4: skt = 0 logic = 0 phy = 2 
5: skt = 0 logic = 0 phy = 2 
6: skt = 0 logic = 5 phy = 3 
7: skt = 0 logic = 5 phy = 3 
8: skt = 1 logic = 2 phy = 0 
9: skt = 1 logic = 2 phy = 0 
10: skt = 1 logic = 7 phy = 1 
11: skt = 1 logic = 7 phy = 1 
12: skt = 1 logic = 0 phy = 2 
13: skt = 1 logic = 0 phy = 2 
14: skt = 1 logic = 5 phy = 3 
15: skt = 1 logic = 5 phy = 3 
16: skt = 0 logic = 3 phy = 4 
17: skt = 0 logic = 3 phy = 4 
18: skt = 0 logic = 6 phy = 5 
19: skt = 0 logic = 6 phy = 5 
20: skt = 0 logic = 1 phy = 6 
21: skt = 1 logic = 1 phy = 6 
22: skt = 1 logic = 1 phy = 6 
23: skt = 1 logic = 4 phy = 7 
24: skt = 1 logic = 4 phy = 7 
25: skt = 1 logic = 6 phy = 5 
26: skt = 1 logic = 6 phy = 5 
27: skt = 1 logic = 3 phy = 4 
28: skt = 0 logic = 1 phy = 6 
29: skt = 0 logic = 4 phy = 7 
30: skt = 0 logic = 4 phy = 7 
31: skt = 1 logic = 3 phy = 4 
32: skt = 2 logic = 2 phy = 0 
33: skt = 2 logic = 2 phy = 0 
34: skt = 2 logic = 7 phy = 1 
35: skt = 2 logic = 7 phy = 1 
36: skt = 2 logic = 0 phy = 2 
37: skt = 3 logic = 4 phy = 7 
38: skt = 3 logic = 1 phy = 6 
39: skt = 3 logic = 4 phy = 7 
40: skt = 3 logic = 1 phy = 6 
41: skt = 3 logic = 6 phy = 5 
42: skt = 3 logic = 6 phy = 5 
43: skt = 3 logic = 3 phy = 4 
44: skt = 3 logic = 3 phy = 4 
45: skt = 2 logic = 4 phy = 7 
46: skt = 2 logic = 4 phy = 7 
47: skt = 2 logic = 1 phy = 6 
48: skt = 2 logic = 1 phy = 6 
49: skt = 2 logic = 6 phy = 5 
50: skt = 2 logic = 6 phy = 5 
51: skt = 2 logic = 3 phy = 4 
52: skt = 2 logic = 3 phy = 4 
53: skt = 3 logic = 5 phy = 3 
54: skt = 3 logic = 5 phy = 3 
55: skt = 3 logic = 0 phy = 2 
56: skt = 3 logic = 0 phy = 2 
57: skt = 3 logic = 7 phy = 1 
58: skt = 3 logic = 7 phy = 1 
59: skt = 3 logic = 2 phy = 0 
60: skt = 3 logic = 2 phy = 0 
61: skt = 2 logic = 5 phy = 3 
62: skt = 2 logic = 5 phy = 3 
63: skt = 2 logic = 0 phy = 2 
[0.02.09.413]TF Heartbeat Start
[0.02.14.520]PCIE INIT DONE.
g_mctpQueueCount(48) > tabCnt(42)
slotNum = 0x8
pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[0] port:20  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[1] port:22  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[2] port:20  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 0
present:0, pwr_en:1.
Pcie slot[3] port:22  pcieSlotCtrl.data (after)0x7c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[4] port:20  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[5] port:22  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[6] port:24  pcieSlotCtrl.data (after)0x14801c0.

pcieSlotCtrl.bits.presencd_det_st = 1
present:1, pwr_en:0.
Pcie slot[7] port:26  pcieSlotCtrl.data (after)0x14801c0.

Interrupt 454 register OK
Interrupt 467 register OK
Interrupt 480 register OK
Interrupt 493 register OK
Interrupt 506 register OK
Interrupt 519 register OK
Interrupt 532 register OK
Interrupt 545 register OK
data = 0x0
pmt Init done

Add ep: bdf=a200 eid=9 epCnt=1 eid_alloc=a
Add ep: bdf=c400 eid=a epCnt=1 eid_alloc=b
Add ep: bdf=d000 eid=b epCnt=1 eid_alloc=c
[0.02.14.752]slot[0] port:20 begin to power OFF.
[0.02.14.753]slot[1] port:22 begin to power OFF.
[0.02.14.756]slot[2] port:20 begin to power OFF.
[0.02.14.760]slot[3] port:22 begin to power OFF.
[0.02.14.765]slot[4] port:20 begin to power ON.
[0.02.14.769]slot[5] port:22 begin to power ON.
[0.02.14.773]slot[6] port:24 begin to power ON.
[0.02.14.777]slot[7] port:26 begin to power ON.
Add ep: bdf=300 eid=c epCnt=1 eid_alloc=d
mctp task ok.
[0.03.37.487]BIOS POST END.
Create SetReportPcieMmioToBmc ok.
Start SetReportPcieMmioToBmc ok.
Enter current value process
0>uefi end finish!
0>ipu interface task exit!
0>amu task parameters from uefi ready
1>uefi end finish!
1>ipu interface task exit!
1>amu task parameters from uefi ready
2>uefi end finish!
2>ipu interface task exit!
2>amu task parameters from uefi ready
3>uefi end finish!
3>ipu interface task exit!
3>amu task parameters from uefi ready
0>amu task activated
0>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
1>amu task activated
1>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
2>amu task activated
2>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
3>amu task activated
3>BootCore: Node[0] Totem[3] Cluster[0] Core[0]!
[0.08.37.487]IpmiCmdReportPcieMMIO start
[0.08.54.127]IpmiCmdReportPcieMMIO end
pool addr          pool size    used size     free size    max free node size   used node num     free node num      UsageWaterLine
---------------    --------     -------       --------     --------------       -------------      ------------      ------------
0x840908c350       0x22880      0x189d8       0x9c38       0x9550               0xbf               0x3                0x19330        
