ID      |Generation Time     |Severity    |Event Code  |Status      |Event Description
173     |2026-07-16 05:33:25 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
172     |2026-07-16 03:33:09 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
171     |2026-07-15 10:42:24 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
170     |2026-07-15 10:38:51 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
169     |2026-07-15 10:35:28 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
168     |2026-07-15 10:31:49 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
167     |2026-07-15 10:28:22 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
166     |2026-07-15 10:24:53 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
165     |2026-07-15 10:21:17 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
164     |2026-07-15 10:17:51 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
163     |2026-07-15 10:14:22 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
162     |2026-07-15 10:10:54 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
161     |2026-07-15 10:07:17 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
160     |2026-07-15 10:03:47 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
159     |2026-07-15 10:00:16 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
158     |2026-07-15 09:56:51 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
157     |2026-07-15 09:53:21 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
156     |2026-07-15 09:49:36 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
155     |2026-07-15 09:46:20 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
154     |2026-07-15 09:42:44 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
153     |2026-07-15 09:39:23 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
152     |2026-07-15 09:35:51 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
151     |2026-07-15 09:32:21 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
150     |2026-07-15 09:28:48 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
149     |2026-07-15 09:25:15 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
148     |2026-07-15 09:21:48 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
147     |2026-07-15 09:18:12 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
146     |2026-07-15 09:14:47 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
145     |2026-07-15 09:11:17 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
144     |2026-07-15 09:07:50 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
143     |2026-07-15 09:04:24 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
142     |2026-07-15 09:00:54 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
141     |2026-07-15 08:57:22 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
140     |2026-07-15 08:53:47 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
139     |2026-07-15 08:50:20 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
138     |2026-07-15 08:46:50 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
137     |2026-07-15 08:43:16 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
136     |2026-07-15 08:39:48 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
135     |2026-07-15 08:36:17 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
134     |2026-07-15 08:32:47 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
133     |2026-07-15 08:29:15 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
132     |2026-07-15 08:25:42 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
131     |2026-07-15 08:22:18 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
130     |2026-07-15 08:18:43 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
129     |2026-07-15 08:15:18 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
128     |2026-07-15 08:11:39 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
127     |2026-07-15 08:08:17 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
126     |2026-07-15 08:04:38 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
125     |2026-07-15 08:01:19 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
124     |2026-07-15 07:57:50 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
123     |2026-07-15 07:54:17 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
122     |2026-07-15 07:50:42 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
121     |2026-07-15 07:47:15 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
120     |2026-07-15 07:43:45 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
119     |2026-07-15 07:40:04 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
118     |2026-07-15 07:36:44 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
117     |2026-07-15 07:33:11 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
116     |2026-07-15 07:29:45 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
115     |2026-07-15 07:26:14 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
114     |2026-07-15 07:22:39 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
113     |2026-07-15 07:19:14 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
112     |2026-07-15 07:15:45 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
111     |2026-07-15 07:12:14 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
110     |2026-07-15 07:08:43 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
109     |2026-07-15 07:05:12 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
108     |2026-07-15 07:01:41 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
107     |2026-07-15 06:58:14 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
106     |2026-07-15 06:54:25 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
105     |2026-07-15 06:51:13 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
104     |2026-07-15 06:47:47 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
103     |2026-07-15 06:43:56 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
102     |2026-07-15 06:40:39 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
101     |2026-07-15 06:37:12 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
100     |2026-07-15 06:33:42 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
99      |2026-07-15 06:30:07 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
98      |2026-07-15 06:26:24 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
97      |2026-07-15 06:23:12 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
96      |2026-07-15 06:19:42 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
95      |2026-07-15 06:16:18 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
94      |2026-07-15 06:12:39 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
93      |2026-07-15 06:09:10 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
92      |2026-07-15 06:05:43 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
91      |2026-07-15 06:02:08 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
90      |2026-07-15 05:58:44 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
89      |2026-07-15 05:55:06 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
88      |2026-07-15 05:51:46 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
87      |2026-07-15 05:48:11 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
86      |2026-07-15 05:44:39 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
85      |2026-07-15 05:41:07 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
84      |2026-07-15 05:37:35 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
83      |2026-07-15 05:34:08 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
82      |2026-07-15 05:30:43 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
81      |2026-07-15 05:27:12 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
80      |2026-07-15 05:23:37 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
79      |2026-07-15 05:20:07 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
78      |2026-07-15 05:16:40 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
77      |2026-07-15 05:13:10 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
76      |2026-07-15 05:09:43 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
75      |2026-07-15 05:06:12 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
74      |2026-07-15 05:02:42 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
73      |2026-07-15 04:59:14 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
72      |2026-07-15 04:55:34 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
71      |2026-07-15 04:52:06 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
70      |2026-07-15 04:48:35 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
69      |2026-07-15 04:45:07 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
68      |2026-07-15 04:41:38 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
67      |2026-07-15 04:38:04 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
66      |2026-07-15 04:34:35 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
65      |2026-07-15 04:31:12 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
64      |2026-07-15 04:27:33 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
63      |2026-07-15 04:24:04 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
62      |2026-07-15 04:20:31 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
61      |2026-07-15 04:17:06 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
60      |2026-07-15 04:13:33 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
59      |2026-07-15 04:10:04 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
58      |2026-07-15 04:06:36 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
57      |2026-07-15 04:03:03 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
56      |2026-07-15 03:59:42 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
55      |2026-07-15 03:56:08 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
54      |2026-07-15 03:52:38 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
53      |2026-07-15 03:49:01 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
52      |2026-07-15 03:45:36 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
51      |2026-07-15 03:42:07 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
50      |2026-07-15 03:38:32 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
49      |2026-07-15 03:35:07 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
48      |2026-07-15 03:31:39 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
47      |2026-07-15 03:28:07 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
46      |2026-07-15 03:24:46 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
45      |2026-07-15 03:21:02 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
44      |2026-07-15 03:17:33 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
43      |2026-07-15 03:14:04 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
42      |2026-07-15 03:10:27 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
41      |2026-07-15 03:07:00 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
40      |2026-07-15 03:03:33 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
39      |2026-07-15 03:00:05 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
38      |2026-07-15 02:56:30 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
37      |2026-07-15 02:53:07 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
36      |2026-07-15 02:49:32 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
35      |2026-07-15 02:46:09 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
34      |2026-07-15 02:42:31 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
33      |2026-07-15 02:38:59 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
32      |2026-07-15 02:35:29 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
31      |2026-07-15 02:32:00 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
30      |2026-07-15 02:28:23 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
29      |2026-07-15 02:25:02 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
28      |2026-07-15 02:21:30 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
27      |2026-07-15 02:18:00 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
26      |2026-07-15 02:14:35 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
25      |2026-07-15 02:11:02 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
24      |2026-07-15 02:07:31 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
23      |2026-07-15 02:04:01 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
22      |2026-07-15 02:00:33 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
21      |2026-07-13 06:29:25 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
20      |2026-07-13 03:26:45 |Normal      |0x0800003F  |Asserted    |The PCIe card 6 (SP686C-M-16i 4G) BBU is present.
19      |2026-07-13 03:25:51 |Normal      |0x29000002  |Deasserted  |NIC 2 (SF221Q) Port 1 disconnected.
18      |2026-07-13 03:25:29 |Normal      |0x29000001  |Asserted    |NIC 2 (SF221Q) Port 1 disconnected.
17      |2026-07-13 03:23:48 |Normal      |0x29000002  |Deasserted  |NIC 2 (SF221Q) Port 1 disconnected.
16      |2026-07-13 03:23:37 |Normal      |0x29000001  |Asserted    |NIC 2 (SF221Q) Port 1 disconnected.
15      |2026-07-13 03:23:34 |Normal      |0x2C00000F  |Asserted    |The host was restarted due to unrecognized reason.
14      |2026-07-13 03:07:35 |Normal      |0x0100000F  |Asserted    |DIMM010 installed (SN:80CE0425224246D329).
13      |2026-07-13 03:07:34 |Normal      |0x0100000F  |Asserted    |DIMM020 installed (SN:80CE0425224246D648).
12      |2026-07-13 03:07:34 |Normal      |0x0100000F  |Asserted    |DIMM130 installed (SN:80CE0425224246D300).
11      |2026-07-13 03:07:33 |Normal      |0x0100000F  |Asserted    |DIMM120 installed (SN:80CE0425224246E43C).
10      |2026-07-13 03:07:33 |Normal      |0x0100000F  |Asserted    |DIMM110 installed (SN:80CE0425224246DE3E).
9       |2026-07-13 03:07:33 |Normal      |0x0100000F  |Asserted    |DIMM100 installed (SN:80CE0425224246DE44).
8       |2026-07-13 03:07:33 |Normal      |0x0100000F  |Asserted    |DIMM030 installed (SN:80CE0425224246D342).
7       |2026-07-13 03:07:33 |Normal      |0x01000041  |Asserted    |DIMM000 is replaced from SN(80CE012351059E2C21) to SN(80CE0425224246DF06) (SN:80CE0425224246DF06).
6       |2026-07-13 03:07:31 |Normal      |0x01000041  |Asserted    |DIMM020 is replaced from SN(80CE012351059E2C21) to SN(80CE0425224246D648) (SN:80CE0425224246D648).
5       |2026-07-13 03:07:28 |Normal      |0x0D000015  |Asserted    |The NIC 2 is replaced from SN(102395707213) to SN(W025B0241991) (SN:W025B0241991).
4       |2026-07-13 03:07:27 |Normal      |0x03000043  |Asserted    |PSU 1 is replaced from SN(2102312HGYHVL3027247) to SN(2102312YKRJVRB011135) (SN:2102312YKRJVRB011135, BN:02312YKR).
3       |2026-07-13 03:07:16 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
2       |2026-07-13 03:06:47 |Normal      |0x03000003  |Asserted    |PSU 2 installed.
1       |2026-07-13 03:03:47 |Normal      |0x1A00000F  |Asserted    |openUBMC event records are cleared.
