 Q      ExpBoard1 Q	`  @                       Q$  `c@#o         Watchdog2 Q  -   ` TS200-2280 Q P     BMCCard Q       BMC Q      FanBoard1 Q      PSU1	 Q      PSU2
 Q      NIC 2 (SF221Q) Q      M2TransferCard6 Q      PCIe Riser1
 Q 	     Zijin-DPU Q(  `c@(o ! ! !         Mngmnt Health Q#  `c@o             SYS_Boot Q9  ` p  d        i      1711 Core Temp Q:  a                  EXU1 VCC_12V0_2 Q:  a                  EXU1 VCC_12V0_3 Q8  a                  EXU1 STBY_3V3 Q7  a        d    n  Z    EXU1 VCC_5V0 Q8  	a        d    n  Z    EXU1 STBY_5V0 Q%  
ac@"o a   a         ACPI_State Q6  ah p  d        K      Outlet_Temp Q8  ah                           EXU1 PSU Temp Q9  
ah                           EXU1 NIC1 Temp Q9  ah                           EXU1 NIC2 Temp Q4  a                          FAN_Power Q5  7`hrr  d       +)      Inlet_Temp Q:  a                  EXU1 VCC_12V0_1 Q'  ac@o             Power_Button Q*  ac@o            PwrOk Sig. Drop  Q(  ac@o            PwrOn TimeOut! Q%  ac@o             UID_Button" Q&  ac@	             Power_Fault# Q7  b         ~     *              FAN3_R_Speed$ Q7  b         ~     *              FAN3_F_Speed% Q$  bc@o 4   $         Event_Log& Q(  bc@            Sec. Log Full' Q'  bc@            Op. Log Full( Q3  
`h                              PSU2_VIn) Q*  
`c!o            PS2 Temp Status* Q3  
`h        p                   PSU2_PIn+ Q4  
`h                              PSU2_VOut, Q&     c@	             Power_Fault- Q2  !
`h                              PS2 IIn. Q4  "
`h        p                   PSU2_POut/ Q3  #
`h                              PS2 IOUT0 Q&  $
`co O O O         PSU2_Supply1 Q:  %
`h                             PSU2_Inlet_Temp2 Q4  &
`h                             PSU2_Temp3 Q(  '`c@            Redundant_PSU4 Q6  (ch                             Total_Power5 Q7  )c                             SSD MAX Temp6 Q5  *c                             Disks Temp7 Q(  +cc            PwrCap Status8 Q&  ,  c@	             Power_Fault9 Q6  -ah p  d         i      Riser1_Temp: Q:  .e p  d         }      DPU_FPGA_VRTemp; Q:  /e         d                   DPU_Total_Power< Q9  0e        d                 DPU_CPU_InTemp= Q:  1e        d                  DPU_FPGA_InTemp> Q8  2e p  d         K      DPU_OPT0_Temp? Q;  3e        d                  DPU_FPGA_OutTemp@ Q9  4e p  d         }      DPU_MEM_VRTempA Q:  5e        d                  DPU_CPU_OutTempB Q9  6e p  d         }      DPU_CPU_VRTempC Q'  7ec@o            DPU_PWR_DropD Q6  8e        d                  DPU_M2_TempE Q)  9ec@o @   @         DPU_SOC_StatusF Q9  :e         d                   DPU_DIMM_PowerG Q*  ;ec@o
0
0
0         DPU_PCIE_StatusH Q9  <e         d                   DPU_FPGA_PowerI Q*  =ec@o 0 0 0         DPU_FPGA_StatusJ Q8  >e p  d         d      DPU_FPGA_TempK Q%  ?ec@o            DPU_PWR_OnL Q(  @ec@             DPU_ME_StatusM Q8  Ae        d                  DPU_DIMM_TempN Q'  Bec@o            DPU_P0_C0_D0O Q'  Cec@o            DPU_P0_C1_D0P Q'  D  c@o
0
0
0         PCIe2_StatusQ Q*  Eec@o         DPU_CPU0_StatusR Q8  Feh         d                   DPU_CPU_PowerS Q(  Gec@o         DPU_P0_G0_HotT Q8  He p  d         K      DPU_OPT1_TempU Q7  Ie p  d         d      DPU_CPU_TempV Q7  J`         ~     *              FAN1_F_SpeedW Q7  K`         ~     *              FAN1_R_SpeedX Q4  L*`h p  d        s      NIC2 TempY Q7  Ma         ~     *              FAN2_F_SpeedZ Q7  Na         ~     *              FAN2_R_Speed[ Q&  O2c
o            M2_0_Status\ Q&  P3c
o            M2_1_Status] Q2  Qfh        d                 M2_Temp^ Q4  R
ah                             PSU1_Temp_ Q3  S
ah                              PSU1_VIn` Q*  T
ac!o            PS1 Temp Statusa Q3  U
ah        p t                  PSU1_PInb Q4  V
ah        p N                  PSU1_POutc Q2  W
ah                              PS1 IInd Q4  X
ah                              PSU1_VOute Q&  Y  c@	             Power_Faultf Q3  Z
ah                              PS1 IOUTg Q&  [
aco O O O         PSU1_Supplyh Q:  \
ah                             PSU1_Inlet_Tempi Q7  ]c         ~     *              FAN4_F_Speedj Q7  ^c         ~     *              FAN4_R_Speedk Q*  _ |co            P1_CC_D0_Statusl Q*  ` }co            P1_CD_D0_Statusm Q*  a `co            P0_C0_D0_Statusn Q*  b co            P1_CF_D0_Statuso Q*  c aco            P0_C1_D0_Statusp Q*  d bco            P0_C2_D0_Statusq Q*  e pco            P1_C0_D0_Statusr Q*  f mco            P0_CD_D0_Statuss Q*  g jco            P0_CA_D0_Statust Q*  h qco            P1_C1_D0_Statusu Q*  i yco            P1_C9_D0_Statusv Q*  j zco            P1_CA_D0_Statusw Q*  k kco            P0_CB_D0_Statusx Q*  l xco            P1_C8_D0_Statusy Q*  m vco            P1_C6_D0_Statusz Q*  n tco            P1_C4_D0_Status{ Q*  o nco            P0_CE_D0_Status| Q*  p oco            P0_CF_D0_Status} Q*  q ico            P0_C9_D0_Status~ Q*  r {co            P1_CB_D0_Status Q*  s wco            P1_C7_D0_Status Q*  t uco            P1_C5_D0_Status Q*  u cco            P0_C3_D0_Status Q*  v dco            P0_C4_D0_Status Q*  w eco            P0_C5_D0_Status Q*  x fco            P0_C6_D0_Status Q*  y gco            P0_C7_D0_Status Q*  z hco            P0_C8_D0_Status Q*  { lco            P0_CC_D0_Status Q*  | ~co            P1_CE_D0_Status Q*  } sco            P1_C3_D0_Status Q*  ~ rco            P1_C2_D0_Status Q;  ah p  d          x      CPU2 TDCORE Temp Q;  `h p  d          x      CPU1 0V8_N3 Temp Q:  d       n    z  b    BCU1 3V3_RISER2 Q&  ac@o         CPU2_Status Q;  `       P      :    CPU1 0V9_TD_CORE Q;  ah p  d          x      CPU2 N4AVDD Temp Q;  ah p  d          x      CPU2 0V9_N3 Temp Q;  `       P    n  C    CPU1 0V9_TDTC_UC Q:  
bh                        ((   BCU1 12V0_1 Pwr Q;  ah p  d          x      CPU2 0V9_N4 Temp Q(  dc@            System Notice Q;  `       n      l    CPU1 1V2_N3_AVDD Q;  a       P    c  C    CPU2 0V9_N1_DVDD Q;  ah p  d          x      CPU2 TBTAVQ Temp Q;  ah p  d          x      CPU2 TDTCUC Temp Q;  a       P    n  C    CPU2 0V9_TDTC_UC Q;  a       P    c  D    CPU2 0V9_N3_DVDD Q;  ah p  d          x      CPU2 TCCORE Temp Q9  d       B    H  <    BCU1 VCC_DRMOS Q;  `       x      l    CPU1 1V2_N4_AVDD Q;  ah p  d          x      CPU2 TDTCVD Temp Q5  d                 SYS_12V0_2 Q;  ah p  d          x      CPU2 TDTCVQ Temp Q;  ah p  d          x      CPU2 N3AVDD Temp Q;  a       P      :    CPU2 0V9_TA_CORE Q;  `h p  d          x      CPU1 TACORE Temp Q:  
bh         @              ((   BCU1 12V0_2 Pwr Q4  `rr  d       ni      CPU1_Temp Q7  `h              x      CPU1_VR_Temp Q:  
bh         @              ((   BCU1 12V0_3 Pwr Q9  %` p           _      CPU1_DIMM_Temp Q7  ah              x      CPU2_VR_Temp Q"  dc@)o          P3V_BAT Q:  
bh                        ((   BCU1 12V0_4 Pwr Q;  `       P    c  D    CPU1 0V7_TBTA_VD Q8  
bh                       ((   BCU1 stby Pwr Q;  `       P    c  D    CPU1 0V7_TDTC_VD Q6  dh p           K      NIC OM Temp Q;  `       P    X  H    CPU1 0V8_N1N4_DV Q;  `       P    X  H    CPU1 0V8_N2_DVDD Q;  `       P    c  C    CPU1 0V9_N1_DVDD Q;  `       P    n  C    CPU1 0V9_TBTA_UC Q;  `h p  d          x      CPU1 0V9_N1 Temp Q;  ah p  d          x      CPU2 0V8_N2 Temp Q;  `       P    c  D    CPU1 0V9_N2_DVDD Q;  ah p  d          x      CPU2 N1N4DV Temp Q;  ah p  d          x      CPU2 0V9_N2 Temp Q;  `h p  d          x      CPU1 N3AVDD Temp Q;  ah p  d          x      CPU2 N2AVDD Temp Q;  `h p  d          x      CPU1 N1N4DV Temp Q;  a       P    X  H    CPU2 0V8_N2_DVDD Q9  `h                             CPU1_MEM_Power Q4  `h                             MEM_Power Q;  ah p  d          x      CPU2 N1AVDD Temp Q;  a       n    y  c    CPU2 1V1_TDTC_VQ Q;  `       x      l    CPU1 1V2_N1_AVDD Q'  dc@o             BIOS_Boot_Up Q;  ah p  d          x      CPU2 TBTAUC Temp Q;  `       n    y  c    CPU1 1V1_TDTC_VQ Q;  a       P    n  C    CPU2 0V9_TBTA_UC Q;  a       x      l    CPU2 1V2_N1_AVDD Q;  `       n    y  c    CPU1 1V1_TBTA_VQ Q;  a       P    c  D    CPU2 0V9_N2_DVDD Q;  a       P    c  D    CPU2 0V7_TBTA_VD Q%  dco            Boot Error Q*  dc@+             BMC_Update_Fail Q&  `c@o         CPU1_Status Q;  `       P      :    CPU1 0V9_TA_CORE Q;  a       n      l    CPU2 1V2_N4_AVDD Q;  `       P    c  D    CPU1 0V9_N3_DVDD Q;  a       x      l    CPU2 1V2_N3_AVDD Q;  `h p  d          x      CPU1 TBCORE Temp Q;  `h p  d          x      CPU1 0V9_N2 Temp Q5  d                 SYS_12V0_3 Q;  a       x      l    CPU2 1V2_N2_AVDD Q+  dc@+             BIOS_Update_Fail Q;  a       n    y  c    CPU2 1V1_TBTA_VQ Q$  dc@+o             FW_Update Q;  a       P      :    CPU2 0V9_TD_CORE Q;  `       n      l    CPU1 1V2_N2_AVDD Q;  `       P    X  H    CPU1 0V8_N3_DVDD Q'  dc@o            System Error Q;  a       P      :    CPU2 0V9_TB_CORE Q;  `h p  d          x      CPU1 N1AVDD Temp Q;  ah p  d          x      CPU2 TBTAVD Temp Q4  arr  d       ni      CPU2_Temp Q3  d       n    z  b    SYS_3.3V Q;  `       P      :    CPU1 0V9_TC_CORE Q;  `h p  d          x      CPU1 TDTCVD Temp Q;  `h p  d          x      CPU1 TDTCVQ Temp Q;  a       P    X  H    CPU2 0V8_N1N4_DV Q;  ah p  d          x      CPU2 0V8_N3 Temp Q#  dc@o             BMC_Boot Q9  ah                             CPU2_MEM_Power Q;  a       P    X  H    CPU2 0V8_N3_DVDD Q4  d                             CPU_Power Q6  ah                             CPU2_VR_Pwr Q6  `h                             CPU1_VR_Pwr Q4  `h                         BCU1 Temp Q9  %a p           _      CPU2_DIMM_Temp Q"  dc@o             OS_Boot Q;  a       P    c  D    CPU2 0V7_TDTC_VD Q;  `h p  d          x      CPU1 0V9_N3 Temp Q;  `       P    c  D    CPU1 0V9_N4_DVDD Q;  `h p  d          x      CPU1 TBTAUC Temp Q;  `h p  d          x      CPU1 0V9_N4 Temp Q;  `h p  d          x      CPU1 0V8_N2 Temp Q;  `h p  d          x      CPU1 TBTAVD Temp Q;  `h p  d          x      CPU1 TBTAVQ Temp Q;  `h p  d          x      CPU1 TCCORE Temp Q;  `h p  d          x      CPU1 TDCORE Temp Q;  `h p  d          x      CPU1 TDTCUC Temp Q;  ah p  d          x      CPU2 TBCORE Temp Q;  ah p  d          x      CPU2 TACORE Temp Q'  dco            SYS_Progress Q;  `       P      :    CPU1 0V9_TB_CORE Q;  a       P    c  D    CPU2 0V9_N4_DVDD  Q;  `h p  d          x      CPU1 N4AVDD Temp Q;  `h p  d          x      CPU1 N2AVDD Temp Q5  d                 SYS_12V0_4 Q&  dc@	             Power_Fault Q;  ah p  d          x      CPU2 0V9_N1 Temp Q;  a       P      :    CPU2 0V9_TC_CORE Q(  dc!o            FAN3_R_Status Q(  ec!o            FAN2_R_Status Q(  fc!o            FAN1_R_Status	 Q(  fc!o            FAN1_F_Status
 Q6  h
              *              PUMP1 Speed Q'  ec@
            FAN2_Present Q6 i
              *              PUMP2 Speed
 Q' dc@
            FAN3_Present Q( gc!o            FAN4_R_Status Q4 uh        d                  CLU1 Temp Q' gc@
            FAN4_Present Q' fc@
            FAN1_Present Q( ec!o            FAN2_F_Status Q( dc!o            FAN3_F_Status Q( 	gc!o            FAN4_F_Status Q      CpuBoard1