[20260729114222]2026-07-29 11:42:22,3988,dfx_dump_func,64,*********** DFX DUMP START ***********
[20260729114222]*********** [3] axi dfx dump start ***********
[20260729114222]2026-07-29 11:42:22,3988,hp_subsys_axi_dump,22,hp_subsys a1x2_dbg_ar_err : 0
[20260729114222]2026-07-29 11:42:22,3988,hp_subsys_axi_dump,23,hp_subsys a1x2_dbg_aw_err : 0
[20260729114222]2026-07-29 11:42:22,3988,hp_subsys_axi_dump,24,hp_subsys a1x2_dlock_mst  : 0
[20260729114222]2026-07-29 11:42:22,3988,hp_subsys_axi_dump,25,hp_subsys a1x2_dlock_slv  : 0
[20260729114222]2026-07-29 11:42:22,3988,hp_subsys_axi_dump,28,hp_subsys a3x1_dbg_ar_err : 0
[20260729114222]2026-07-29 11:42:22,3988,hp_subsys_axi_dump,29,hp_subsys a3x1_dbg_aw_err : 0
[20260729114222]2026-07-29 11:42:22,3988,hp_subsys_axi_dump,30,hp_subsys a3x1_dlock_mst  : 0
[20260729114222]2026-07-29 11:42:22,3988,hp_subsys_axi_dump,31,hp_subsys a3x1_dlock_slv  : 0
[20260729114222]2026-07-29 11:42:22,3988,disp_subsys_axi_dump,40,disp dp_pcie_2x2 : 0x16
[20260729114222]2026-07-29 11:42:22,3988,disp_subsys_axi_dump,44,disp dp_pcie_2x2: 0x00000000 0x00000000
[20260729114222]2026-07-29 11:42:22,3988,disp_subsys_axi_dump,48,disp dp_cfg_1x2: 0x00000000 0x00000000
[20260729114222]2026-07-29 11:42:22,3988,disp_subsys_axi_dump,52,disp dp_cfg_1x2: 0x00000000 0x00000000
[20260729114222]2026-07-29 11:42:22,3988,disp_subsys_axi_dump,56,disp dp_gpu_3x1: 0x00000000 0x00000000
[20260729114222]2026-07-29 11:42:22,3988,disp_subsys_axi_dump,60,disp dp_gpu_3x1: 0x00000000 0x00000000
[20260729114222]2026-07-29 11:42:22,3988,disp_subsys_axi_dump,64,disp dp_ddr_3x1: 0x00000000 0x00000000
[20260729114222]2026-07-29 11:42:22,3988,disp_subsys_axi_dump,68,disp dp_ddr_3x1: 0x00000000 0x00000000
[20260729114222]2026-07-29 11:42:22,3988,disp_subsys_axi_dump,72,disp dp_pcie1_1x2: 0x00000000 0x00000000
[20260729114222]2026-07-29 11:42:22,3988,disp_subsys_axi_dump,76,disp dp_pcie1_1x2: 0x00000000 0x00000000
[20260729114222]2026-07-29 11:42:22,3988,disp_subsys_axi_dump,80,disp dp_gpu1_3x1: 0x00000000 0x00000000
[20260729114222]2026-07-29 11:42:22,3988,disp_subsys_axi_dump,84,disp dp_gpu1_3x1: 0x00000000 0x00000000
[20260729114222]2026-07-29 11:42:22,3988,disp_subsys_axi_dump,88,disp matrix_resp_err: 0x00000000 0x00000000
[20260729114222]2026-07-29 11:42:22,3988,disp_subsys_axi_dump,93,disp gpu0_axi_int p0: 0x00000000 0x00000000
[20260729114222]2026-07-29 11:42:22,3988,disp_subsys_axi_dump,95,disp gpu0_axi_int p1: 0x00000000 0x00000000
[20260729114222]2026-07-29 11:42:22,3988,disp_subsys_axi_dump,97,disp gpu0_axi_int p2: 0x00000000 0x00000000
[20260729114222]2026-07-29 11:42:22,3988,disp_subsys_axi_dump,93,disp gpu1_axi_int p0: 0x00000000 0x00000000
[20260729114222]2026-07-29 11:42:22,3988,disp_subsys_axi_dump,95,disp gpu1_axi_int p1: 0x00000000 0x00000000
[20260729114222]2026-07-29 11:42:22,3988,disp_subsys_axi_dump,97,disp gpu1_axi_int p2: 0x00000000 0x00000000
[20260729114222]*********** [3] axi dfx dump end ***********
[20260729114222]*********** [4] scene_mgmt dfx dump start ***********
[20260729114222]host mode: 0, scene mode: 0
[20260729114222]h10_usage: 9, h25_usage: 0
[20260729114222]host0 reseted: 0, host1 reseted: 0
[20260729114222]macro_id: 0x0
[20260729114222]lane_id: 0x0
[20260729114222]init_status: 0x6
[20260729114222]calib_status: 0xf
[20260729114222]top_fsm_done: 0x1
[20260729114222]tx_rate: 0x1
[20260729114222]tx_power_status: 0x2
[20260729114222]tx_phy_mode: 0x1
[20260729114222]tx_fsm_done: 0x1
[20260729114222]tx_eleidle_pin_en: 0x0
[20260729114222]tx_eleidle_status: 0x1
[20260729114222]tx_eleidle: 0x1
[20260729114222]rx_rate: 0x1
[20260729114222]rx_power_status: 0x2
[20260729114222]rx_phy_mode: 0x1
[20260729114222]rx_fsm_done: 0x1
[20260729114222]pll_lock_status: 0x1
[20260729114222]macro_id: 0x1
[20260729114222]lane_id: 0x0
[20260729114222]init_status: 0x6
[20260729114222]calib_status: 0xf
[20260729114222]top_fsm_done: 0x1
[20260729114222]tx_rate: 0x0
[20260729114222]tx_power_status: 0x0
[20260729114222]tx_phy_mode: 0x8
[20260729114222]tx_fsm_done: 0x1
[20260729114222]tx_eleidle_pin_en: 0x0
[20260729114222]tx_eleidle_status: 0x0
[20260729114222]tx_eleidle: 0x0
[20260729114222]rx_rate: 0x0
[20260729114222]rx_power_status: 0x0
[20260729114222]rx_phy_mode: 0x8
[20260729114222]rx_fsm_done: 0x1
[20260729114222]pll_lock_status: 0x1
[20260729114222]macro_id: 0x2
[20260729114222]lane_id: 0x0
[20260729114222]init_status: 0x6
[20260729114222]calib_status: 0xf
[20260729114222]top_fsm_done: 0x1
[20260729114222]tx_rate: 0x0
[20260729114222]tx_power_status: 0x0
[20260729114222]tx_phy_mode: 0x8
[20260729114222]tx_fsm_done: 0x1
[20260729114222]tx_eleidle_pin_en: 0x0
[20260729114222]tx_eleidle_status: 0x0
[20260729114222]tx_eleidle: 0x0
[20260729114222]rx_rate: 0x0
[20260729114222]rx_power_status: 0x0
[20260729114222]rx_phy_mode: 0x8
[20260729114222]rx_fsm_done: 0x1
[20260729114222]pll_lock_status: 0x1
[20260729114222]macro_id: 0x3
[20260729114222]lane_id: 0x0
[20260729114222]init_status: 0x6
[20260729114222]calib_status: 0xf
[20260729114222]top_fsm_done: 0x1
[20260729114222]tx_rate: 0x0
[20260729114222]tx_power_status: 0x0
[20260729114222]tx_phy_mode: 0x8
[20260729114222]tx_fsm_done: 0x1
[20260729114222]tx_eleidle_pin_en: 0x0
[20260729114222]tx_eleidle_status: 0x0
[20260729114222]tx_eleidle: 0x0
[20260729114222]rx_rate: 0x0
[20260729114222]rx_power_status: 0x0
[20260729114222]rx_phy_mode: 0x8
[20260729114222]rx_fsm_done: 0x1
[20260729114222]pll_lock_status: 0x1
[20260729114222]macro_id: 0x4
[20260729114222]lane_id: 0x0
[20260729114222]init_status: 0x6
[20260729114222]calib_status: 0xf
[20260729114222]top_fsm_done: 0x1
[20260729114222]tx_rate: 0x0
[20260729114222]tx_power_status: 0x0
[20260729114222]tx_phy_mode: 0x8
[20260729114222]tx_fsm_done: 0x1
[20260729114222]tx_eleidle_pin_en: 0x0
[20260729114222]tx_eleidle_status: 0x0
[20260729114222]tx_eleidle: 0x0
[20260729114222]rx_rate: 0x0
[20260729114222]rx_power_status: 0x0
[20260729114222]rx_phy_mode: 0x8
[20260729114222]rx_fsm_done: 0x1
[20260729114222]pll_lock_status: 0x1
[20260729114222]macro_id: 0x5
[20260729114222]lane_id: 0x0
[20260729114222]init_status: 0x6
[20260729114222]calib_status: 0xf
[20260729114222]top_fsm_done: 0x1
[20260729114222]tx_rate: 0x0
[20260729114222]tx_power_status: 0x0
[20260729114222]tx_phy_mode: 0x3
[20260729114222]tx_fsm_done: 0x1
[20260729114222]tx_eleidle_pin_en: 0x1
[20260729114222]tx_eleidle_status: 0x1
[20260729114222]tx_eleidle: 0x0
[20260729114222]rx_rate: 0x0
[20260729114222]rx_power_status: 0x0
[20260729114222]rx_phy_mode: 0x3
[20260729114222]rx_fsm_done: 0x1
[20260729114222]pll_lock_status: 0x1
[20260729114222]hilink10_ecc_err_count: 0
[20260729114222]UHUB_LP1X3_CTRL.lp1x3_dbg_aw_err 0x0
[20260729114222]UHUB_LP1X3_CTRL.lp1x3_dlock_mst 0x0
[20260729114222]UHUB_LP1X3_CTRL.lp1x3_dlock_slv 0x0
[20260729114222]UHUB_HOST32_2X1_CTRL.host32_2x1_dbg_ar_err 0x0
[20260729114222]UHUB_HOST32_2X1_CTRL.host32_2x1_dbg_aw_err 0x0
[20260729114222]UHUB_HOST32_2X1_CTRL.host32_2x1_dlock_mst 0x0
[20260729114222]UHUB_HOST32_2X1_CTRL.host32_2x1_dlock_slv 0x0
[20260729114222]UHUB_HOST22_2X1_CTRL.host22_2x1_dbg_ar_err 0x0
[20260729114222]UHUB_HOST22_2X1_CTRL.host22_2x1_dbg_aw_err 0x0
[20260729114222]UHUB_HOST22_2X1_CTRL.host22_2x1_dlock_mst 0x0
[20260729114222]UHUB_HOST22_2X1_CTRL.host22_2x1_dlock_slv 0x0
[20260729114222]UHUB_DEVICE32_2X1_CTRL.device32_2x1_dbg_ar_err 0x0
[20260729114222]UHUB_DEVICE32_2X1_CTRL.device32_2x1_dbg_aw_err 0x0
[20260729114222]UHUB_DEVICE32_2X1_CTRL.device32_2x1_dlock_mst 0x0
[20260729114222]UHUB_DEVICE32_2X1_CTRL.device32_2x1_dlock_slv 0x0
[20260729114222]UHUB_DEVICE22_2X1_CTRL.device22_2x1_dbg_ar_err 0x0
[20260729114222]UHUB_DEVICE22_2X1_CTRL.device22_2x1_dbg_aw_err 0x0
[20260729114222]UHUB_DEVICE22_2X1_CTRL.device22_2x1_dlock_mst 0x0
[20260729114222]UHUB_DEVICE22_2X1_CTRL.device22_2x1_dlock_slv 0x0
[20260729114222]UHUB_TODDR_2X1_CTRL.toddr_2x1_dbg_ar_err 0x0
[20260729114222]UHUB_TODDR_2X1_CTRL.toddr_2x1_dbg_aw_err 0x0
[20260729114222]UHUB_TODDR_2X1_CTRL.toddr_2x1_dlock_mst 0x0
[20260729114222]UHUB_TODDR_2X1_CTRL.toddr_2x1_dlock_slv 0x0
[20260729114222]*********** [4] scene_mgmt dfx dump end ***********
[20260729114222]*********** [5] a5x_subsys dfx dump start ***********
[20260729114222]a5x_subsys sc_ace_1x2_dlock_slave : 0
[20260729114222]a5x_subsys sc_ace_1x2_dlock_master : 0
[20260729114222]a5x_subsys sc_lp_1x2_dlock_slave : 0
[20260729114222]a5x_subsys sc_lp_1x2_dlock_master : 0
[20260729114222]a5x_subsys emptier_bresp_err : 0
[20260729114222]a5x_subsys emptier_rresp_err : 0
[20260729114222]*********** [5] a5x_subsys dfx dump end ***********
[20260729114222]*********** [7] pcie dfx dump start ***********
[20260729114222]FS_CALC_RDY                  : offset(0x03a8) reg_val = 0xffffffff
[20260729114222]SERDES_DFX                   : offset(0x03ac) reg_val = 0xffffffff
[20260729114222]MAC_REG_MAC_INT_STATU        : offset(0x0054) reg_val = 0xffffffff
[20260729114222]MAC_REG_TEST_COUNTER         : offset(0x005c) reg_val = 0xffffffff
[20260729114222]MAC_REG_LINK_INFO            : offset(0x0060) reg_val = 0xffffffff
[20260729114222]MAC_REG_DEBUG_PIPE1          : offset(0x0064) reg_val = 0xffffffff
[20260729114222]MAC_REG_DEBUG_PIPE2          : offset(0x0068) reg_val = 0xffffffff
[20260729114222]MAC_REG_DEBUG_PIPE3          : offset(0x006c) reg_val = 0xffffffff
[20260729114222]MAC_REG_DEBUG_PIPE4          : offset(0x0070) reg_val = 0xffffffff
[20260729114222]MAC_REG_LTSSM_TRACER_OUTPUT_1: offset(0x0084) reg_val = 0xffffffff
[20260729114222]MAC_REG_SYMBOL_UNLOCL_COUNTER: offset(0x008c) reg_val = 0xffffffff
[20260729114222]MAC_REG_PHY_RXDATA_TS        : offset(0x00b4) reg_val = 0xffffffff
[20260729114222]MAC_REG_DEBUG_PIPE6          : offset(0x0244) reg_val = 0xffffffff
[20260729114222]MAC_REG_DEBUG_PIPE8          : offset(0x024c) reg_val = 0xffffffff
[20260729114222]MAC_REG_DEBUG_PIPE9          : offset(0x0250) reg_val = 0xffffffff
[20260729114222]MAC_REG_DEBUG_PIPE10         : offset(0x0254) reg_val = 0xffffffff
[20260729114222]MAC_REG_DEBUG_PIPE11         : offset(0x0258) reg_val = 0xffffffff
[20260729114222]MAC_PCS_RX_ERR_CNT           : offset(0x02bc) reg_val = 0xffffffff
[20260729114222]MAC_LEAVE_L0_INFO            : offset(0x03b4) reg_val = 0xffffffff
[20260729114222]DFX_LCRC_ERR_NUM             : offset(0x0050) reg_val = 0xffffffff
[20260729114222]DFX_DCRC_ERR_NUM             : offset(0x0054) reg_val = 0xffffffff
[20260729114222]DFX_FSM_STATE                : offset(0x0058) reg_val = 0xffffffff
[20260729114222]DFX_RETRY_STATUS             : offset(0x0060) reg_val = 0xffffffff
[20260729114222]DL_INT_STATUS                : offset(0x0088) reg_val = 0xffffffff
[20260729114222]DFX_DLLP_RX_COUNT_NUM        : offset(0x00e0) reg_val = 0xffffffff
[20260729114222]DFX_DLLP_TX_COUNT_NUM        : offset(0x00e4) reg_val = 0xffffffff
[20260729114222]TL_PORT_IDLE_CTRL_STATUS     : offset(0x0028) reg_val = 0xffffffff
[20260729114222]TL_INT_STATUS0               : offset(0x056c) reg_val = 0xffffffff
[20260729114222]TL_INT_STATUS1               : offset(0x0570) reg_val = 0xffffffff
[20260729114222]TL_TX_UR_CNT                 : offset(0x0a0c) reg_val = 0xffffffff
[20260729114222]TL_RX_ERR_CNT                : offset(0x0b2c) reg_val = 0xffffffff
[20260729114222]TL_RX_NULL_CNT               : offset(0x0b30) reg_val = 0xffffffff
[20260729114222]TL_RX_UR_TLP_CNT             : offset(0x0b34) reg_val = 0xffffffff
[20260729114222]TL_RX_TOTAL_CNT              : offset(0x0b38) reg_val = 0xffffffff
[20260729114222]TL_RX_POST_CNT               : offset(0x0b44) reg_val = 0xffffffff
[20260729114222]TL_RX_NONPOST_CNT            : offset(0x0b48) reg_val = 0xffffffff
[20260729114222]TL_RX_CPL_CNT                : offset(0x0b4c) reg_val = 0xffffffff
[20260729114222]TL_RX_LOC_TLP_CNT            : offset(0x0b50) reg_val = 0xffffffff
[20260729114222]TL_RX_ERR_STATUS             : offset(0x0b9c) reg_val = 0xffffffff
[20260729114222]TL_RX_TRACE_CMP_EN           : offset(0x0c10) reg_val = 0xffffffff
[20260729114222]TL_TX_INGRESS_CNT            : offset(0x0008) reg_val = 0xffffffff
[20260729114222]TL_TX_CTRL_EGRESS_CNT        : offset(0x000c) reg_val = 0xffffffff
[20260729114222]TL_TX_CFG_CNT                : offset(0x0098) reg_val = 0xffffffff
[20260729114222]TL_TX_MEM_RD_CNT             : offset(0x009c) reg_val = 0xffffffff
[20260729114222]TL_TX_MEM_WR_CNT             : offset(0x00a0) reg_val = 0xffffffff
[20260729114222]TL_TX_IO_RD_CNT              : offset(0x00a4) reg_val = 0xffffffff
[20260729114222]TL_TX_IO_WR_CNT              : offset(0x00a8) reg_val = 0xffffffff
[20260729114222]TL_TX_MSG_CNT                : offset(0x00ac) reg_val = 0xffffffff
[20260729114222]TL_TX_CPL_CNT                : offset(0x00b0) reg_val = 0xffffffff
[20260729114222]TL_TX_CFG_TX_CNT             : offset(0x00b4) reg_val = 0xffffffff
[20260729114222]TL_TX_GEN_CPL_CNT            : offset(0x00c0) reg_val = 0xffffffff
[20260729114222]IOB_TX_INT_STATUS0           : offset(0x0820) reg_val = 0xffffffff
[20260729114222]IOB_TX_INT_STATUS1           : offset(0x0824) reg_val = 0xffffffff
[20260729114222]IOB_TX_INT_STATUS2           : offset(0x0828) reg_val = 0xffffffff
[20260729114222]IOB_TX_INT_STATUS3           : offset(0x082c) reg_val = 0xffffffff
[20260729114222]DFX_IOB_TX_AXIS_WR_CNT0      : offset(0x2400) reg_val = 0xffffffff
[20260729114222]DFX_IOB_TX_AXIS_WR_CNT1      : offset(0x2404) reg_val = 0xffffffff
[20260729114222]DFX_IOB_TX_AXIS_WR_CNT2      : offset(0x2408) reg_val = 0xffffffff
[20260729114222]DFX_IOB_TX_AXIS_WR_CNT3      : offset(0x240c) reg_val = 0xffffffff
[20260729114222]DFX_IOB_TX_AXIS_RD_CNT0      : offset(0x2440) reg_val = 0xffffffff
[20260729114222]DFX_IOB_TX_AXIS_RD_CNT1      : offset(0x2444) reg_val = 0xffffffff
[20260729114222]DFX_IOB_TX_AXIS_STATUS2      : offset(0x2488) reg_val = 0xffffffff
[20260729114222]DFX_IOB_TX_AXIS_ABNORMAL_CNT0: offset(0x2500) reg_val = 0xffffffff
[20260729114222]DFX_IOB_TX_AXIS_ABNORMAL_CNT1: offset(0x2504) reg_val = 0xffffffff
[20260729114222]DFX_IOB_TX_P_CNT0            : offset(0x2800) reg_val = 0xffffffff
[20260729114222]DFX_IOB_TX_P_CNT1            : offset(0x2804) reg_val = 0xffffffff
[20260729114222]DFX_IOB_TX_P_CNT2            : offset(0x2808) reg_val = 0xffffffff
[20260729114222]DFX_IOB_TX_P_CNT3            : offset(0x280c) reg_val = 0xffffffff
[20260729114222]DFX_IOB_TX_P_CNT4            : offset(0x2810) reg_val = 0xffffffff
[20260729114222]DFX_IOB_TX_NP_CNT0           : offset(0x2880) reg_val = 0xffffffff
[20260729114222]DFX_IOB_TX_NP_CNT1           : offset(0x2884) reg_val = 0xffffffff
[20260729114222]DFX_IOB_TX_NP_CNT2           : offset(0x2888) reg_val = 0xffffffff
[20260729114222]DFX_IOB_TX_CPL_CNT0          : offset(0x2900) reg_val = 0xffffffff
[20260729114222]DFX_IOB_TX_CPL_CNT1          : offset(0x2904) reg_val = 0xffffffff
[20260729114222]DFX_IOB_TX_CPL_CNT2          : offset(0x2908) reg_val = 0xffffffff
[20260729114222]DFX_IOB_TX_STATUS0           : offset(0x2a00) reg_val = 0xffffffff
[20260729114222]IOB_RX_IDLE_STS              : offset(0x10f4) reg_val = 0xffffffff
[20260729114222]DFX_IOB_RX_CNT_RX_REQ        : offset(0x1500) reg_val = 0xffffffff
[20260729114222]DFX_IOB_RX_CNT_LOC_REQ       : offset(0x1504) reg_val = 0xffffffff
[20260729114222]DFX_IOB_RX_CNT_SEND_AM       : offset(0x1510) reg_val = 0xffffffff
[20260729114222]DFX_IOB_RX_CNT_SEND_LOC      : offset(0x1514) reg_val = 0xffffffff
[20260729114222]DFX_IOB_RX_CNT_RESP_RX       : offset(0x1540) reg_val = 0xffffffff
[20260729114222]DFX_IOB_RX_CNT_RESP_LOC      : offset(0x1544) reg_val = 0xffffffff
[20260729114222]IOB_RX_INT_STATUS            : offset(0x1704) reg_val = 0xffffffff
[20260729114222]DFX_IOB_RX_AML_IDLE_STATE    : offset(0x1a00) reg_val = 0xffffffff
[20260729114222]DFX_IOB_RX_AML_WR_CNT_0      : offset(0x1a20) reg_val = 0xffffffff
[20260729114222]DFX_IOB_RX_AML_WR_CNT_1      : offset(0x1a24) reg_val = 0xffffffff
[20260729114222]DFX_IOB_RX_AML_RD_CNT        : offset(0x1a28) reg_val = 0xffffffff
[20260729114222]DFX_IOB_RX_AML_ERR_STS       : offset(0x1a60) reg_val = 0xffffffff
[20260729114222]DFX_IOB_RX_AML_LAST_ADDR_LOW : offset(0x1a64) reg_val = 0xffffffff
[20260729114222]DFX_IOB_RX_AML_LAST_ADDR_HIGH: offset(0x1a68) reg_val = 0xffffffff
[20260729114222]DFX_IOB_RX_AML_WR_ID_STS_0   : offset(0x1a80) reg_val = 0xffffffff
[20260729114222]DFX_IOB_RX_AML_WR_ID_STS_1   : offset(0x1a84) reg_val = 0xffffffff
[20260729114222]DFX_IOB_RX_AML_RD_ID_STS_0   : offset(0x1a90) reg_val = 0xffffffff
[20260729114222]DFX_IOB_RX_AML_RD_ID_STS_1   : offset(0x1a94) reg_val = 0xffffffff
[20260729114222]PCIE_CE_STATUS               : offset(0x0020) reg_val = 0xffffffff
[20260729114222]PCIE_UNF_STATUS              : offset(0x0028) reg_val = 0xffffffff
[20260729114222]PCIE_UF_STATUS               : offset(0x0030) reg_val = 0xffffffff
[20260729114222]PCIE_AP_CE_STATUS            : offset(0x0124) reg_val = 0xffffffff
[20260729114222]PCIE_AP_UNF_STATUS           : offset(0x0128) reg_val = 0xffffffff
[20260729114222]PCIE_AP_UF_STATUS            : offset(0x012c) reg_val = 0xffffffff
[20260729114222]PCIE_CORE_CE_STATUS          : offset(0x0184) reg_val = 0xffffffff
[20260729114222]PCIE_CORE_UNF_STATUS         : offset(0x0188) reg_val = 0xffffffff
[20260729114222]PCIE_CORE_UF_STATUS          : offset(0x018c) reg_val = 0xffffffff
[20260729114222]AP_PORT_IDLE                 : offset(0x0c00) reg_val = 0xffffffff
[20260729114222]AP_IDLE                      : offset(0x0c08) reg_val = 0xffffffff
[20260729114222]M_PCS_RPT_REG                : offset(0x0014) reg_val = 0xffffffff
[20260729114222]SERDES_STATUS_RPT            : offset(0x0018) reg_val = 0xffffffff
[20260729114222]RECV_DET_OR_PWR_CHAGE        : offset(0x0034) reg_val = 0xffffffff
[20260729114222]LANE_INTR_STATUS             : offset(0x004c) reg_val = 0xffffffff
[20260729114222]MSG_BUS_DFX                  : offset(0x0068) reg_val = 0xffffffff
[20260729114222]PHY2MAC_MSG_STATUS           : offset(0x007c) reg_val = 0xffffffff
[20260729114222]PCS_LANE_ITF_STATUS          : offset(0x0830) reg_val = 0xffffffff
[20260729114222]M_PCS_RPT_REG                : offset(0x0014) reg_val = 0xffffffff
[20260729114222]SERDES_STATUS_RPT            : offset(0x0018) reg_val = 0xffffffff
[20260729114222]RECV_DET_OR_PWR_CHAGE        : offset(0x0034) reg_val = 0xffffffff
[20260729114222]LANE_INTR_STATUS             : offset(0x004c) reg_val = 0xffffffff
[20260729114222]MSG_BUS_DFX                  : offset(0x0068) reg_val = 0xffffffff
[20260729114222]PHY2MAC_MSG_STATUS           : offset(0x007c) reg_val = 0xffffffff
[20260729114222]PCS_LANE_ITF_STATUS          : offset(0x0830) reg_val = 0xffffffff
[20260729114222]*********** [7] pcie dfx dump end ***********
[20260729114222]*********** [8] mctp0 dfx dump start ***********
[20260729114222] recv packets: 0x00000000
 send packets: 0x00000000
[20260729114222] all send packets(reg): 0xffffffff
 success send packets(reg): 0xffffffff
[20260729114222] all recv packets(reg): 0xffffffff
 success recv packets(reg): 0xffffffff
[20260729114222] drop for rx buff full(reg): 0xffffffff drop for error(reg): 0xffffffff
 drop for head error: 0x00000000
[20260729114222] drop for rx axi error: 0x00000000
 drop for tx axi error: 0x00000000
[20260729114222] drop for rx buff full: 0x00000000
 drop for rx tlp error: 0x00000000
[20260729114222] drop for alloc buff fail: 0x00000000
 drop for tx len error: 0x00000000
[20260729114222] drop invalid bus id packet fail: 0x00000000
[20260729114222]*********** [8] mctp0 dfx dump end ***********
[20260729114222]*********** [9] mctp1 dfx dump start ***********
[20260729114222] recv packets: 0x00000000
 send packets: 0x00000000
[20260729114222] all send packets(reg): 0xffffffff
 success send packets(reg): 0xffffffff
[20260729114222] all recv packets(reg): 0xffffffff
 success recv packets(reg): 0xffffffff
[20260729114222] drop for rx buff full(reg): 0xffffffff drop for error(reg): 0xffffffff
 drop for head error: 0x00000000
[20260729114222] drop for rx axi error: 0x00000000
 drop for tx axi error: 0x00000000
[20260729114222] drop for rx buff full: 0x00000000
 drop for rx tlp error: 0x00000000
[20260729114222] drop for alloc buff fail: 0x00000000
 drop for tx len error: 0x00000000
[20260729114222] drop invalid bus id packet fail: 0x00000000
[20260729114222]*********** [9] mctp1 dfx dump end ***********
[20260729114222]*********** [10] ipmb dfx dump start ***********
[20260729114222]IPMB[0]-CRD<0>|TMO<0>|DAH<0>|CLH<0>|DAL<0>|CLL<0>|STO<0>|BSY<0>|RNZ<0>|RQI<0>
[20260729114222]IPMB[1]-CRD<0>|TMO<0>|DAH<0>|CLH<0>|DAL<0>|CLL<0>|STO<0>|BSY<0>|RNZ<0>|RQI<0>
[20260729114222]IPMB[2]-CRD<0>|TMO<0>|DAH<0>|CLH<0>|DAL<0>|CLL<0>|STO<0>|BSY<0>|RNZ<0>|RQI<0>
[20260729114222]IPMB[3]-CRD<0>|TMO<0>|DAH<0>|CLH<0>|DAL<0>|CLL<0>|STO<0>|BSY<0>|RNZ<0>|RQI<0>
[20260729114222]IPMB[4]-CRD<0>|TMO<0>|DAH<0>|CLH<0>|DAL<0>|CLL<0>|STO<0>|BSY<0>|RNZ<0>|RQI<0>
[20260729114222]IPMB[5]-CRD<0>|TMO<0>|DAH<0>|CLH<0>|DAL<0>|CLL<0>|STO<0>|BSY<0>|RNZ<0>|RQI<0>
[20260729114222]IPMB[6]-CRD<0>|TMO<0>|DAH<0>|CLH<0>|DAL<0>|CLL<0>|STO<0>|BSY<0>|RNZ<0>|RQI<0>
[20260729114222]IPMB[7]-CRD<0>|TMO<0>|DAH<0>|CLH<0>|DAL<0>|CLL<0>|STO<0>|BSY<0>|RNZ<0>|RQI<0>
[20260729114222]*********** [10] ipmb dfx dump end ***********
[20260729114222]*********** [11] dboot dfx dump start ***********
[20260729114222]CHIP rst ST<0> REG<0x0> CNT<0>|<-1>[0]|<-2>[0]|<-3>[0]|<-4>[0]
[20260729114222]BMC-SEC rst ST<0> REG<0x0> CNT<0>|<-1>[0]|<-2>[0]|<-3>[0]|<-4>[0]
[20260729114222]BMC-UNSEC rst ST<0> REG<0x0> CNT<0>|<-1>[0]|<-2>[0]|<-3>[0]|<-4>[0]
[20260729114222]HOST0 rst ST<0> REG<0x0> CNT<0>|<-1>[0]|<-2>[0]|<-3>[0]|<-4>[0]
[20260729114222]HOST1 rst ST<0> REG<0x0> CNT<0>|<-1>[0]|<-2>[0]|<-3>[0]|<-4>[0]
[20260729114222]PCIE0 rst ST<0> REG<0x0> CNT<0>|<-1>[0]|<-2>[0]|<-3>[0]|<-4>[0]
[20260729114222]PCIE1 rst ST<0> REG<0x0> CNT<0>|<-1>[0]|<-2>[0]|<-3>[0]|<-4>[0]
[20260729114222]PLL_LOCK_ST: offset(0x0040) reg_val = 0x00000007
[20260729114222]*********** [11] dboot dfx dump end ***********
[20260729114222]*********** [12] ddr dfx dump start ***********
[20260729114222]AD_PLL_LOCK              : offset(0x0204) reg_val = 0x00000002
[20260729114222]IECC_INTSTS              : offset(0x0008) reg_val = 0x00000000
[20260729114222]IECC_RINT                : offset(0x0010) reg_val = 0x00000000
[20260729114222]IECC_DFX_ST4             : offset(0x002c) reg_val = 0x011004ce
[20260729114222]IECC_DFX_ST5             : offset(0x0030) reg_val = 0x21b92f23
[20260729114222]IECC_DFX_ST6             : offset(0x0034) reg_val = 0x3f7c01b2
[20260729114222]IECC_DFX_ST7             : offset(0x0038) reg_val = 0xa083b4cd
[20260729114222]IECC_DFX_ST8             : offset(0x003c) reg_val = 0x0000031e
[20260729114222]IECC_DFX_ST9             : offset(0x0040) reg_val = 0x017ad9eb
[20260729114222]IECC_DFX_ST10            : offset(0x0044) reg_val = 0x00002ece
[20260729114222]IECC_DFX_ST11            : offset(0x0048) reg_val = 0x00897eaa
[20260729114222]IECC_DFX_HA_ERR_CNT0     : offset(0x0180) reg_val = 0x00000000
[20260729114222]IECC_DFX_PTR_ERR_CNT1    : offset(0x0184) reg_val = 0x00000000
[20260729114222]*********** [12] ddr dfx dump end ***********
[20260729114222]*********** [13] disp dfx dump start ***********
[20260729114222]*********** [13] disp dfx dump end ***********
[20260729114222]*********** [14] gmac dfx dump start ***********
[20260729114222]gmac 0: offset(0x0008) reg_val = 0x00000001
[20260729114222]gmac 0: offset(0x003c) reg_val = 0x000005f8
[20260729114222]gmac 0: offset(0x0040) reg_val = 0x00000001
[20260729114222]gmac 0: offset(0x0058) reg_val = 0x00040000
[20260729114222]gmac 0: offset(0x00c8) reg_val = 0x00000000
[20260729114222]gmac 0: offset(0x015c) reg_val = 0x00000000
[20260729114222]gmac 0: offset(0x0434) reg_val = 0x00000000
[20260729114222]gmac 0: offset(0x045c) reg_val = 0x007f0000
[20260729114222]gmac 0: offset(0x0694) reg_val = 0x00000000
[20260729114222]gmac 0: offset(0x0698) reg_val = 0x00000000
[20260729114222]gmac 0: offset(0x06a0) reg_val = 0x00000000
[20260729114222]gmac 0: offset(0x06a4) reg_val = 0x00000000
[20260729114222]gmac 1: offset(0x0008) reg_val = 0x00000001
[20260729114222]gmac 1: offset(0x003c) reg_val = 0x000005f8
[20260729114222]gmac 1: offset(0x0040) reg_val = 0x00000001
[20260729114222]gmac 1: offset(0x0058) reg_val = 0x00040000
[20260729114222]gmac 1: offset(0x00c8) reg_val = 0x00000000
[20260729114222]gmac 1: offset(0x015c) reg_val = 0x00000000
[20260729114222]gmac 1: offset(0x0434) reg_val = 0x00000000
[20260729114222]gmac 1: offset(0x045c) reg_val = 0x007f0000
[20260729114222]gmac 1: offset(0x0694) reg_val = 0x00000000
[20260729114222]gmac 1: offset(0x0698) reg_val = 0x00000000
[20260729114222]gmac 1: offset(0x06a0) reg_val = 0x00000000
[20260729114222]gmac 1: offset(0x06a4) reg_val = 0x00000000
[20260729114222]gmac 2: offset(0x0008) reg_val = 0x00000001
[20260729114222]gmac 2: offset(0x003c) reg_val = 0x000005f8
[20260729114222]gmac 2: offset(0x0040) reg_val = 0x00000008
[20260729114222]gmac 2: offset(0x0058) reg_val = 0x00349800
[20260729114222]gmac 2: offset(0x00c8) reg_val = 0x00000000
[20260729114222]gmac 2: offset(0x015c) reg_val = 0x00000000
[20260729114222]gmac 2: offset(0x0434) reg_val = 0x09004000
[20260729114222]gmac 2: offset(0x045c) reg_val = 0x007e0000
[20260729114222]gmac 2: offset(0x0694) reg_val = 0x00000001
[20260729114222]gmac 2: offset(0x0698) reg_val = 0x00000000
[20260729114222]gmac 2: offset(0x06a0) reg_val = 0x00000001
[20260729114222]gmac 2: offset(0x06a4) reg_val = 0x00000000
[20260729114222]gmac 3: offset(0x0008) reg_val = 0x00000001
[20260729114222]gmac 3: offset(0x003c) reg_val = 0x000005f8
[20260729114222]gmac 3: offset(0x0040) reg_val = 0x00000008
[20260729114222]gmac 3: offset(0x0058) reg_val = 0x00340000
[20260729114222]gmac 3: offset(0x00c8) reg_val = 0x00000000
[20260729114222]gmac 3: offset(0x015c) reg_val = 0x00000000
[20260729114222]gmac 3: offset(0x0434) reg_val = 0x00000000
[20260729114222]gmac 3: offset(0x045c) reg_val = 0x007f0000
[20260729114222]gmac 3: offset(0x0694) reg_val = 0x00000001
[20260729114222]gmac 3: offset(0x0698) reg_val = 0x00000000
[20260729114222]gmac 3: offset(0x06a0) reg_val = 0x00000001
[20260729114222]gmac 3: offset(0x06a4) reg_val = 0x00000000
[20260729114222]*********** [14] gmac dfx dump end ***********
[20260729114222]*********** [15] uart_sol dfx dump start ***********
[20260729114222]SOL-0 enable[0]:
[20260729114222]TX_ADD=0x86000000 TX_SIZE=0x400000 RX_ADD=0x86400000 RX_SIZE=0x100000
[20260729114222]TX_NOW=0x85800000 RX_NOW=0x88800000 FIFO_ST=0x00004040 ERR_CNT=0 IRQ=1 RETRY=3
[20260729114222]SOL-1 enable[1]:
[20260729114222]TX_ADD=0x86080000 TX_SIZE=0x400000 RX_ADD=0x86000000 RX_SIZE=0x80000
[20260729114222]TX_NOW=0x8609b37c RX_NOW=0x88800000 FIFO_ST=0x00000a40 ERR_CNT=0 IRQ=0 RETRY=3
[20260729114222]SOL-2 enable[1]:
[20260729114222]TX_ADD=0x86680000 TX_SIZE=0x80000 RX_ADD=0x86480000 RX_SIZE=0x200000
[20260729114222]TX_NOW=0x85800000 RX_NOW=0x88800000 FIFO_ST=0x00004040 ERR_CNT=0 IRQ=0 RETRY=3
[20260729114222]SOL-3 enable[1]:
[20260729114222]TX_ADD=0x86900000 TX_SIZE=0x80000 RX_ADD=0x86700000 RX_SIZE=0x200000
[20260729114222]TX_NOW=0x85800000 RX_NOW=0x88800000 FIFO_ST=0x00004040 ERR_CNT=0 IRQ=0 RETRY=3
[20260729114222]SOL-4 enable[0]:
[20260729114222]TX_ADD=0x8a000000 TX_SIZE=0x800000 RX_ADD=0x8a800000 RX_SIZE=0x200000
[20260729114222]TX_NOW=0x85800000 RX_NOW=0x88800000 FIFO_ST=0x00004040 ERR_CNT=0 IRQ=1 RETRY=3
[20260729114222]SOL-5 enable[0]:
[20260729114222]TX_ADD=0x8aa00000 TX_SIZE=0x400000 RX_ADD=0x8ae00000 RX_SIZE=0x200000
[20260729114222]TX_NOW=0x85800000 RX_NOW=0x88800000 FIFO_ST=0x00004040 ERR_CNT=0 IRQ=1 RETRY=3
[20260729114222]SOL-6 enable[0]:
[20260729114222]TX_ADD=0x8b000000 TX_SIZE=0x200000 RX_ADD=0x8b200000 RX_SIZE=0x400000
[20260729114222]TX_NOW=0x85800000 RX_NOW=0x88800000 FIFO_ST=0x00004040 ERR_CNT=0 IRQ=1 RETRY=3
[20260729114222]SOL-7 enable[0]:
[20260729114222]TX_ADD=0x8b600000 TX_SIZE=0x400000 RX_ADD=0x8ba00000 RX_SIZE=0x100000
[20260729114222]TX_NOW=0x85800000 RX_NOW=0x88800000 FIFO_ST=0x00004040 ERR_CNT=0 IRQ=1 RETRY=3
[20260729114222]SOL-8 enable[0]:
[20260729114222]TX_ADD=0x86000000 TX_SIZE=0x400000 RX_ADD=0x86400000 RX_SIZE=0x100000
[20260729114222]TX_NOW=0x85800000 RX_NOW=0x88800000 FIFO_ST=0x00004040 ERR_CNT=0 IRQ=1 RETRY=3
[20260729114222]SOL-9 enable[0]:
[20260729114222]TX_ADD=0x8b600000 TX_SIZE=0x400000 RX_ADD=0x8ba00000 RX_SIZE=0x100000
[20260729114222]TX_NOW=0x85800000 RX_NOW=0x88800000 FIFO_ST=0x00004040 ERR_CNT=0 IRQ=1 RETRY=3
[20260729114222]*********** [15] uart_sol dfx dump end ***********
[20260729114222]*********** [18] env dfx dump start ***********
[20260729114222]pcie0MiscBar0Size         : 0x17
[20260729114222]pcie0MiscBar2Size         : 0x17
[20260729114222]pcie0MiscBar4Size         : 0x19
[20260729114222]pcie1MiscBar0Size         : 0x17
[20260729114222]pcie1MiscBar2Size         : 0x17
[20260729114222]pcie1MiscBar4Size         : 0x19
[20260729114222]bmcUartPort               : 0x2
[20260729114222]rsvDramSize               : 0x0
[20260729114222]sceneMgmtH10Usage         : 0x9
[20260729114222]sceneMgmtH25Usage         : 0x0
[20260729114222]sceneMgmtGmac2MacAddr_l   : 0xa923ace8
[20260729114222]sceneMgmtGmac2MacAddr_h   : 0xc49
[20260729114222]sceneMgmtGmac3MacAddr_l   : 0xa923ace8
[20260729114222]sceneMgmtGmac3MacAddr_h   : 0xd49
[20260729114222]sceneMgmtGmacPhysAddr     : 0x303
[20260729114222]dfxLastWordIsGpio         : 0x0
[20260729114222]dfxLastWordGpioPin        : 0x7f
[20260729114222]h10Ssc                    : 0x0
[20260729114222]h25Ssc                    : 0x0
[20260729114222]copBootSize               : 0x1000000
[20260729114222]dpLane0TxDeemph           : 0x600
[20260729114222]dpLane1TxDeemph           : 0x600
[20260729114222]rtosMemAddr               : 0x98400000
[20260729114222]a55DdrBwThreshold         : 0xa
[20260729114222]pwmLightCfg               : 0x0
[20260729114222]mmcForceTuning            : 0x0
[20260729114222]cpllHighFreqSel           : 0x0
[20260729114222]cpllFreqConfig            : 0x1
[20260729114222]gmacPhysAddr              : 0xfefefeff
[20260729114222]trfcab                    : 0xffffffff
[20260729114222]trfcpb                    : 0xffffffff
[20260729114222]trpab                     : 0xffffffff
[20260729114222]trppb                     : 0xffffffff
[20260729114222]exmbistBitmap             : 0x0
[20260729114222]marginSwitch              : 0x0
[20260729114222]eyescanSwitch             : 0x0
[20260729114222]eyescanDir                : 0x0
[20260729114222]eyescanPattern            : 0x0
[20260729114222]pcie0PFUsage0             : 0xb9876541
[20260729114222]pcie0PFUsage1             : 0xffffffff
[20260729114222]pcie1PFUsage              : 0xffffffff
[20260729114222]gpuBarType                : 0x0
[20260729114222]caVref                    : 0xffffffff
[20260729114222]caMarginSwitch            : 0x1
[20260729114222]vdac_gc                   : 0xffffffff
[20260729114222]retrainCheck              : 0xffffffff
[20260729114222]mmcTuningDly1             : 0x4
[20260729114222]*********** [18] env dfx dump end ***********
[20260729114222]*********** [19] i3c dfx dump start ***********
[20260729114222]*********** [19] i3c dfx dump end ***********
[20260729114222]*********** [20] emmc dfx dump start ***********
[20260729114222]emmc offset(0x04) reg_val = 0x80200
[20260729114222]emmc offset(0x08) reg_val = 0x0
[20260729114222]emmc offset(0x0c) reg_val = 0xc1a0000
[20260729114222]emmc offset(0x10) reg_val = 0xb00
[20260729114222]emmc offset(0x14) reg_val = 0xffffffff
[20260729114222]emmc offset(0x18) reg_val = 0x329f5903
[20260729114222]emmc offset(0x1c) reg_val = 0xd0ffff
[20260729114222]emmc offset(0x24) reg_val = 0xf1ff0000
[20260729114222]emmc offset(0x28) reg_val = 0xb3c
[20260729114222]emmc offset(0x2c) reg_val = 0x80007
[20260729114222]emmc offset(0x30) reg_val = 0x0
[20260729114222]emmc offset(0x34) reg_val = 0x3fff703f
[20260729114222]emmc offset(0x38) reg_val = 0x2
[20260729114222]emmc offset(0x80) reg_val = 0x8f170100
[20260729114222]emmc offset(0x84) reg_val = 0xd000ff24
[20260729114222]emmc offset(0x90) reg_val = 0x84313e44
[20260729114222]*********** [20] emmc dfx dump end ***********
[20260729114222]*********** [23] btc dfx dump start ***********
[20260729114222]btc_bus_0 busy_status:0
[20260729114222]btc_bus_1 busy_status:0
[20260729114222]btc_bus_2 busy_status:0
[20260729114222]btc_bus_3 busy_status:0
[20260729114222]btc_bus_4 busy_status:0
[20260729114222]btc_bus_5 busy_status:0
[20260729114222]btc_bus_6 busy_status:0
[20260729114222]btc_bus_7 busy_status:0
[20260729114222]btc_bus_8 busy_status:0
[20260729114222]btc_bus_9 busy_status:0
[20260729114222]btc_bus_10 busy_status:0
[20260729114222]btc_bus_11 busy_status:0
[20260729114222]btc_bus_12 busy_status:0
[20260729114222]btc_bus_13 busy_status:0
[20260729114222]btc_bus_14 busy_status:0
[20260729114222]btc_bus_15 busy_status:0
[20260729114222]*********** [23] btc dfx dump end ***********
[20260729114222]2026-07-29 11:42:22,3988,dfx_dump_func,70,*********** DFX DUMP END ***********
[20260729143854]*********** [0] misc_sysctrl dfx dump start ***********
[20260729143854]*********** [0] misc_sysctrl dfx dump end ***********
[20260729143854]*********** [1] usb_subsys dfx dump start ***********
[20260729143854]*********** [1] usb_subsys dfx dump end ***********
[20260729143854]*********** [2] pwm dfx dump start ***********
[20260729143854]*********** [2] pwm dfx dump end ***********
[20260729143854]*********** [3] msg dfx dump start ***********
[20260729143854]*********** [3] msg dfx dump end ***********
[20260729165420]2026-07-29 16:54:20,3933,dfx_dump_func,64,*********** DFX DUMP START ***********
[20260729165420]*********** [3] axi dfx dump start ***********
[20260729165420]2026-07-29 16:54:20,3933,hp_subsys_axi_dump,22,hp_subsys a1x2_dbg_ar_err : 0
[20260729165420]2026-07-29 16:54:20,3933,hp_subsys_axi_dump,23,hp_subsys a1x2_dbg_aw_err : 0
[20260729165420]2026-07-29 16:54:20,3933,hp_subsys_axi_dump,24,hp_subsys a1x2_dlock_mst  : 0
[20260729165420]2026-07-29 16:54:20,3933,hp_subsys_axi_dump,25,hp_subsys a1x2_dlock_slv  : 0
[20260729165420]2026-07-29 16:54:20,3933,hp_subsys_axi_dump,28,hp_subsys a3x1_dbg_ar_err : 0
[20260729165420]2026-07-29 16:54:20,3933,hp_subsys_axi_dump,29,hp_subsys a3x1_dbg_aw_err : 0
[20260729165420]2026-07-29 16:54:20,3933,hp_subsys_axi_dump,30,hp_subsys a3x1_dlock_mst  : 0
[20260729165420]2026-07-29 16:54:20,3933,hp_subsys_axi_dump,31,hp_subsys a3x1_dlock_slv  : 0
[20260729165420]2026-07-29 16:54:20,3933,disp_subsys_axi_dump,40,disp dp_pcie_2x2 : 0x16
[20260729165420]2026-07-29 16:54:20,3933,disp_subsys_axi_dump,44,disp dp_pcie_2x2: 0x00000000 0x00000000
[20260729165420]2026-07-29 16:54:20,3933,disp_subsys_axi_dump,48,disp dp_cfg_1x2: 0x00000000 0x00000000
[20260729165420]2026-07-29 16:54:20,3933,disp_subsys_axi_dump,52,disp dp_cfg_1x2: 0x00000000 0x00000000
[20260729165420]2026-07-29 16:54:20,3933,disp_subsys_axi_dump,56,disp dp_gpu_3x1: 0x00000000 0x00000000
[20260729165420]2026-07-29 16:54:20,3933,disp_subsys_axi_dump,60,disp dp_gpu_3x1: 0x00000000 0x00000000
[20260729165420]2026-07-29 16:54:20,3933,disp_subsys_axi_dump,64,disp dp_ddr_3x1: 0x00000000 0x00000000
[20260729165420]2026-07-29 16:54:20,3933,disp_subsys_axi_dump,68,disp dp_ddr_3x1: 0x00000000 0x00000000
[20260729165420]2026-07-29 16:54:20,3933,disp_subsys_axi_dump,72,disp dp_pcie1_1x2: 0x00000000 0x00000000
[20260729165420]2026-07-29 16:54:20,3933,disp_subsys_axi_dump,76,disp dp_pcie1_1x2: 0x00000000 0x00000000
[20260729165420]2026-07-29 16:54:20,3933,disp_subsys_axi_dump,80,disp dp_gpu1_3x1: 0x00000000 0x00000000
[20260729165420]2026-07-29 16:54:20,3933,disp_subsys_axi_dump,84,disp dp_gpu1_3x1: 0x00000000 0x00000000
[20260729165420]2026-07-29 16:54:20,3933,disp_subsys_axi_dump,88,disp matrix_resp_err: 0x00000000 0x00000000
[20260729165420]2026-07-29 16:54:20,3933,disp_subsys_axi_dump,93,disp gpu0_axi_int p0: 0x00000000 0x00000000
[20260729165420]2026-07-29 16:54:20,3933,disp_subsys_axi_dump,95,disp gpu0_axi_int p1: 0x00000000 0x00000000
[20260729165420]2026-07-29 16:54:20,3933,disp_subsys_axi_dump,97,disp gpu0_axi_int p2: 0x00000000 0x00000000
[20260729165420]2026-07-29 16:54:20,3933,disp_subsys_axi_dump,93,disp gpu1_axi_int p0: 0x00000000 0x00000000
[20260729165420]2026-07-29 16:54:20,3933,disp_subsys_axi_dump,95,disp gpu1_axi_int p1: 0x00000000 0x00000000
[20260729165420]2026-07-29 16:54:20,3933,disp_subsys_axi_dump,97,disp gpu1_axi_int p2: 0x00000000 0x00000000
[20260729165420]*********** [3] axi dfx dump end ***********
[20260729165420]*********** [4] scene_mgmt dfx dump start ***********
[20260729165420]host mode: 0, scene mode: 0
[20260729165420]h10_usage: 9, h25_usage: 0
[20260729165420]host0 reseted: 0, host1 reseted: 0
[20260729165420]macro_id: 0x0
[20260729165420]lane_id: 0x0
[20260729165420]init_status: 0x6
[20260729165420]calib_status: 0xf
[20260729165420]top_fsm_done: 0x1
[20260729165420]tx_rate: 0x1
[20260729165420]tx_power_status: 0x2
[20260729165420]tx_phy_mode: 0x1
[20260729165420]tx_fsm_done: 0x1
[20260729165420]tx_eleidle_pin_en: 0x0
[20260729165420]tx_eleidle_status: 0x1
[20260729165420]tx_eleidle: 0x1
[20260729165420]rx_rate: 0x1
[20260729165420]rx_power_status: 0x2
[20260729165420]rx_phy_mode: 0x1
[20260729165420]rx_fsm_done: 0x1
[20260729165420]pll_lock_status: 0x1
[20260729165420]macro_id: 0x1
[20260729165420]lane_id: 0x0
[20260729165420]init_status: 0x6
[20260729165420]calib_status: 0xf
[20260729165420]top_fsm_done: 0x1
[20260729165420]tx_rate: 0x0
[20260729165420]tx_power_status: 0x0
[20260729165420]tx_phy_mode: 0x8
[20260729165420]tx_fsm_done: 0x1
[20260729165420]tx_eleidle_pin_en: 0x0
[20260729165420]tx_eleidle_status: 0x0
[20260729165420]tx_eleidle: 0x0
[20260729165420]rx_rate: 0x0
[20260729165420]rx_power_status: 0x0
[20260729165420]rx_phy_mode: 0x8
[20260729165420]rx_fsm_done: 0x1
[20260729165420]pll_lock_status: 0x1
[20260729165420]macro_id: 0x2
[20260729165420]lane_id: 0x0
[20260729165420]init_status: 0x6
[20260729165420]calib_status: 0xf
[20260729165420]top_fsm_done: 0x1
[20260729165420]tx_rate: 0x0
[20260729165420]tx_power_status: 0x0
[20260729165420]tx_phy_mode: 0x8
[20260729165420]tx_fsm_done: 0x1
[20260729165420]tx_eleidle_pin_en: 0x0
[20260729165420]tx_eleidle_status: 0x0
[20260729165420]tx_eleidle: 0x0
[20260729165420]rx_rate: 0x0
[20260729165420]rx_power_status: 0x0
[20260729165420]rx_phy_mode: 0x8
[20260729165420]rx_fsm_done: 0x1
[20260729165420]pll_lock_status: 0x1
[20260729165420]macro_id: 0x3
[20260729165420]lane_id: 0x0
[20260729165420]init_status: 0x6
[20260729165420]calib_status: 0xf
[20260729165420]top_fsm_done: 0x1
[20260729165420]tx_rate: 0x0
[20260729165420]tx_power_status: 0x0
[20260729165420]tx_phy_mode: 0x8
[20260729165420]tx_fsm_done: 0x1
[20260729165420]tx_eleidle_pin_en: 0x0
[20260729165420]tx_eleidle_status: 0x0
[20260729165420]tx_eleidle: 0x0
[20260729165420]rx_rate: 0x0
[20260729165420]rx_power_status: 0x0
[20260729165420]rx_phy_mode: 0x8
[20260729165420]rx_fsm_done: 0x1
[20260729165420]pll_lock_status: 0x1
[20260729165420]macro_id: 0x4
[20260729165420]lane_id: 0x0
[20260729165420]init_status: 0x6
[20260729165420]calib_status: 0xf
[20260729165420]top_fsm_done: 0x1
[20260729165420]tx_rate: 0x0
[20260729165420]tx_power_status: 0x0
[20260729165420]tx_phy_mode: 0x8
[20260729165420]tx_fsm_done: 0x1
[20260729165420]tx_eleidle_pin_en: 0x0
[20260729165420]tx_eleidle_status: 0x0
[20260729165420]tx_eleidle: 0x0
[20260729165420]rx_rate: 0x0
[20260729165420]rx_power_status: 0x0
[20260729165420]rx_phy_mode: 0x8
[20260729165420]rx_fsm_done: 0x1
[20260729165420]pll_lock_status: 0x1
[20260729165420]macro_id: 0x5
[20260729165420]lane_id: 0x0
[20260729165420]init_status: 0x6
[20260729165420]calib_status: 0xf
[20260729165420]top_fsm_done: 0x1
[20260729165420]tx_rate: 0x0
[20260729165420]tx_power_status: 0x0
[20260729165420]tx_phy_mode: 0x3
[20260729165420]tx_fsm_done: 0x1
[20260729165420]tx_eleidle_pin_en: 0x1
[20260729165420]tx_eleidle_status: 0x1
[20260729165420]tx_eleidle: 0x0
[20260729165420]rx_rate: 0x0
[20260729165420]rx_power_status: 0x0
[20260729165420]rx_phy_mode: 0x3
[20260729165420]rx_fsm_done: 0x1
[20260729165420]pll_lock_status: 0x1
[20260729165420]hilink10_ecc_err_count: 0
[20260729165420]UHUB_LP1X3_CTRL.lp1x3_dbg_aw_err 0x0
[20260729165420]UHUB_LP1X3_CTRL.lp1x3_dlock_mst 0x0
[20260729165420]UHUB_LP1X3_CTRL.lp1x3_dlock_slv 0x0
[20260729165420]UHUB_HOST32_2X1_CTRL.host32_2x1_dbg_ar_err 0x0
[20260729165420]UHUB_HOST32_2X1_CTRL.host32_2x1_dbg_aw_err 0x0
[20260729165420]UHUB_HOST32_2X1_CTRL.host32_2x1_dlock_mst 0x0
[20260729165420]UHUB_HOST32_2X1_CTRL.host32_2x1_dlock_slv 0x0
[20260729165420]UHUB_HOST22_2X1_CTRL.host22_2x1_dbg_ar_err 0x0
[20260729165420]UHUB_HOST22_2X1_CTRL.host22_2x1_dbg_aw_err 0x0
[20260729165420]UHUB_HOST22_2X1_CTRL.host22_2x1_dlock_mst 0x0
[20260729165420]UHUB_HOST22_2X1_CTRL.host22_2x1_dlock_slv 0x0
[20260729165420]UHUB_DEVICE32_2X1_CTRL.device32_2x1_dbg_ar_err 0x0
[20260729165420]UHUB_DEVICE32_2X1_CTRL.device32_2x1_dbg_aw_err 0x0
[20260729165420]UHUB_DEVICE32_2X1_CTRL.device32_2x1_dlock_mst 0x0
[20260729165420]UHUB_DEVICE32_2X1_CTRL.device32_2x1_dlock_slv 0x0
[20260729165420]UHUB_DEVICE22_2X1_CTRL.device22_2x1_dbg_ar_err 0x0
[20260729165420]UHUB_DEVICE22_2X1_CTRL.device22_2x1_dbg_aw_err 0x0
[20260729165420]UHUB_DEVICE22_2X1_CTRL.device22_2x1_dlock_mst 0x0
[20260729165420]UHUB_DEVICE22_2X1_CTRL.device22_2x1_dlock_slv 0x0
[20260729165420]UHUB_TODDR_2X1_CTRL.toddr_2x1_dbg_ar_err 0x0
[20260729165420]UHUB_TODDR_2X1_CTRL.toddr_2x1_dbg_aw_err 0x0
[20260729165420]UHUB_TODDR_2X1_CTRL.toddr_2x1_dlock_mst 0x0
[20260729165420]UHUB_TODDR_2X1_CTRL.toddr_2x1_dlock_slv 0x0
[20260729165420]*********** [4] scene_mgmt dfx dump end ***********
[20260729165420]*********** [5] a5x_subsys dfx dump start ***********
[20260729165420]a5x_subsys sc_ace_1x2_dlock_slave : 0
[20260729165420]a5x_subsys sc_ace_1x2_dlock_master : 0
[20260729165420]a5x_subsys sc_lp_1x2_dlock_slave : 0
[20260729165420]a5x_subsys sc_lp_1x2_dlock_master : 0
[20260729165420]a5x_subsys emptier_bresp_err : 0
[20260729165420]a5x_subsys emptier_rresp_err : 0
[20260729165420]*********** [5] a5x_subsys dfx dump end ***********
[20260729165420]*********** [7] pcie dfx dump start ***********
[20260729165420]FS_CALC_RDY                  : offset(0x03a8) reg_val = 0xffffffff
[20260729165420]SERDES_DFX                   : offset(0x03ac) reg_val = 0xffffffff
[20260729165420]MAC_REG_MAC_INT_STATU        : offset(0x0054) reg_val = 0xffffffff
[20260729165420]MAC_REG_TEST_COUNTER         : offset(0x005c) reg_val = 0xffffffff
[20260729165420]MAC_REG_LINK_INFO            : offset(0x0060) reg_val = 0xffffffff
[20260729165420]MAC_REG_DEBUG_PIPE1          : offset(0x0064) reg_val = 0xffffffff
[20260729165420]MAC_REG_DEBUG_PIPE2          : offset(0x0068) reg_val = 0xffffffff
[20260729165420]MAC_REG_DEBUG_PIPE3          : offset(0x006c) reg_val = 0xffffffff
[20260729165420]MAC_REG_DEBUG_PIPE4          : offset(0x0070) reg_val = 0xffffffff
[20260729165420]MAC_REG_LTSSM_TRACER_OUTPUT_1: offset(0x0084) reg_val = 0xffffffff
[20260729165420]MAC_REG_SYMBOL_UNLOCL_COUNTER: offset(0x008c) reg_val = 0xffffffff
[20260729165420]MAC_REG_PHY_RXDATA_TS        : offset(0x00b4) reg_val = 0xffffffff
[20260729165420]MAC_REG_DEBUG_PIPE6          : offset(0x0244) reg_val = 0xffffffff
[20260729165420]MAC_REG_DEBUG_PIPE8          : offset(0x024c) reg_val = 0xffffffff
[20260729165420]MAC_REG_DEBUG_PIPE9          : offset(0x0250) reg_val = 0xffffffff
[20260729165420]MAC_REG_DEBUG_PIPE10         : offset(0x0254) reg_val = 0xffffffff
[20260729165420]MAC_REG_DEBUG_PIPE11         : offset(0x0258) reg_val = 0xffffffff
[20260729165420]MAC_PCS_RX_ERR_CNT           : offset(0x02bc) reg_val = 0xffffffff
[20260729165420]MAC_LEAVE_L0_INFO            : offset(0x03b4) reg_val = 0xffffffff
[20260729165420]DFX_LCRC_ERR_NUM             : offset(0x0050) reg_val = 0xffffffff
[20260729165420]DFX_DCRC_ERR_NUM             : offset(0x0054) reg_val = 0xffffffff
[20260729165420]DFX_FSM_STATE                : offset(0x0058) reg_val = 0xffffffff
[20260729165420]DFX_RETRY_STATUS             : offset(0x0060) reg_val = 0xffffffff
[20260729165420]DL_INT_STATUS                : offset(0x0088) reg_val = 0xffffffff
[20260729165420]DFX_DLLP_RX_COUNT_NUM        : offset(0x00e0) reg_val = 0xffffffff
[20260729165420]DFX_DLLP_TX_COUNT_NUM        : offset(0x00e4) reg_val = 0xffffffff
[20260729165420]TL_PORT_IDLE_CTRL_STATUS     : offset(0x0028) reg_val = 0xffffffff
[20260729165420]TL_INT_STATUS0               : offset(0x056c) reg_val = 0xffffffff
[20260729165420]TL_INT_STATUS1               : offset(0x0570) reg_val = 0xffffffff
[20260729165420]TL_TX_UR_CNT                 : offset(0x0a0c) reg_val = 0xffffffff
[20260729165420]TL_RX_ERR_CNT                : offset(0x0b2c) reg_val = 0xffffffff
[20260729165420]TL_RX_NULL_CNT               : offset(0x0b30) reg_val = 0xffffffff
[20260729165420]TL_RX_UR_TLP_CNT             : offset(0x0b34) reg_val = 0xffffffff
[20260729165420]TL_RX_TOTAL_CNT              : offset(0x0b38) reg_val = 0xffffffff
[20260729165420]TL_RX_POST_CNT               : offset(0x0b44) reg_val = 0xffffffff
[20260729165420]TL_RX_NONPOST_CNT            : offset(0x0b48) reg_val = 0xffffffff
[20260729165420]TL_RX_CPL_CNT                : offset(0x0b4c) reg_val = 0xffffffff
[20260729165420]TL_RX_LOC_TLP_CNT            : offset(0x0b50) reg_val = 0xffffffff
[20260729165420]TL_RX_ERR_STATUS             : offset(0x0b9c) reg_val = 0xffffffff
[20260729165420]TL_RX_TRACE_CMP_EN           : offset(0x0c10) reg_val = 0xffffffff
[20260729165420]TL_TX_INGRESS_CNT            : offset(0x0008) reg_val = 0xffffffff
[20260729165420]TL_TX_CTRL_EGRESS_CNT        : offset(0x000c) reg_val = 0xffffffff
[20260729165420]TL_TX_CFG_CNT                : offset(0x0098) reg_val = 0xffffffff
[20260729165420]TL_TX_MEM_RD_CNT             : offset(0x009c) reg_val = 0xffffffff
[20260729165420]TL_TX_MEM_WR_CNT             : offset(0x00a0) reg_val = 0xffffffff
[20260729165420]TL_TX_IO_RD_CNT              : offset(0x00a4) reg_val = 0xffffffff
[20260729165420]TL_TX_IO_WR_CNT              : offset(0x00a8) reg_val = 0xffffffff
[20260729165420]TL_TX_MSG_CNT                : offset(0x00ac) reg_val = 0xffffffff
[20260729165420]TL_TX_CPL_CNT                : offset(0x00b0) reg_val = 0xffffffff
[20260729165420]TL_TX_CFG_TX_CNT             : offset(0x00b4) reg_val = 0xffffffff
[20260729165420]TL_TX_GEN_CPL_CNT            : offset(0x00c0) reg_val = 0xffffffff
[20260729165420]IOB_TX_INT_STATUS0           : offset(0x0820) reg_val = 0xffffffff
[20260729165420]IOB_TX_INT_STATUS1           : offset(0x0824) reg_val = 0xffffffff
[20260729165420]IOB_TX_INT_STATUS2           : offset(0x0828) reg_val = 0xffffffff
[20260729165420]IOB_TX_INT_STATUS3           : offset(0x082c) reg_val = 0xffffffff
[20260729165420]DFX_IOB_TX_AXIS_WR_CNT0      : offset(0x2400) reg_val = 0xffffffff
[20260729165420]DFX_IOB_TX_AXIS_WR_CNT1      : offset(0x2404) reg_val = 0xffffffff
[20260729165420]DFX_IOB_TX_AXIS_WR_CNT2      : offset(0x2408) reg_val = 0xffffffff
[20260729165420]DFX_IOB_TX_AXIS_WR_CNT3      : offset(0x240c) reg_val = 0xffffffff
[20260729165420]DFX_IOB_TX_AXIS_RD_CNT0      : offset(0x2440) reg_val = 0xffffffff
[20260729165420]DFX_IOB_TX_AXIS_RD_CNT1      : offset(0x2444) reg_val = 0xffffffff
[20260729165420]DFX_IOB_TX_AXIS_STATUS2      : offset(0x2488) reg_val = 0xffffffff
[20260729165420]DFX_IOB_TX_AXIS_ABNORMAL_CNT0: offset(0x2500) reg_val = 0xffffffff
[20260729165420]DFX_IOB_TX_AXIS_ABNORMAL_CNT1: offset(0x2504) reg_val = 0xffffffff
[20260729165420]DFX_IOB_TX_P_CNT0            : offset(0x2800) reg_val = 0xffffffff
[20260729165420]DFX_IOB_TX_P_CNT1            : offset(0x2804) reg_val = 0xffffffff
[20260729165420]DFX_IOB_TX_P_CNT2            : offset(0x2808) reg_val = 0xffffffff
[20260729165420]DFX_IOB_TX_P_CNT3            : offset(0x280c) reg_val = 0xffffffff
[20260729165420]DFX_IOB_TX_P_CNT4            : offset(0x2810) reg_val = 0xffffffff
[20260729165420]DFX_IOB_TX_NP_CNT0           : offset(0x2880) reg_val = 0xffffffff
[20260729165420]DFX_IOB_TX_NP_CNT1           : offset(0x2884) reg_val = 0xffffffff
[20260729165420]DFX_IOB_TX_NP_CNT2           : offset(0x2888) reg_val = 0xffffffff
[20260729165420]DFX_IOB_TX_CPL_CNT0          : offset(0x2900) reg_val = 0xffffffff
[20260729165420]DFX_IOB_TX_CPL_CNT1          : offset(0x2904) reg_val = 0xffffffff
[20260729165420]DFX_IOB_TX_CPL_CNT2          : offset(0x2908) reg_val = 0xffffffff
[20260729165420]DFX_IOB_TX_STATUS0           : offset(0x2a00) reg_val = 0xffffffff
[20260729165420]IOB_RX_IDLE_STS              : offset(0x10f4) reg_val = 0xffffffff
[20260729165420]DFX_IOB_RX_CNT_RX_REQ        : offset(0x1500) reg_val = 0xffffffff
[20260729165420]DFX_IOB_RX_CNT_LOC_REQ       : offset(0x1504) reg_val = 0xffffffff
[20260729165420]DFX_IOB_RX_CNT_SEND_AM       : offset(0x1510) reg_val = 0xffffffff
[20260729165420]DFX_IOB_RX_CNT_SEND_LOC      : offset(0x1514) reg_val = 0xffffffff
[20260729165420]DFX_IOB_RX_CNT_RESP_RX       : offset(0x1540) reg_val = 0xffffffff
[20260729165420]DFX_IOB_RX_CNT_RESP_LOC      : offset(0x1544) reg_val = 0xffffffff
[20260729165420]IOB_RX_INT_STATUS            : offset(0x1704) reg_val = 0xffffffff
[20260729165420]DFX_IOB_RX_AML_IDLE_STATE    : offset(0x1a00) reg_val = 0xffffffff
[20260729165420]DFX_IOB_RX_AML_WR_CNT_0      : offset(0x1a20) reg_val = 0xffffffff
[20260729165420]DFX_IOB_RX_AML_WR_CNT_1      : offset(0x1a24) reg_val = 0xffffffff
[20260729165420]DFX_IOB_RX_AML_RD_CNT        : offset(0x1a28) reg_val = 0xffffffff
[20260729165420]DFX_IOB_RX_AML_ERR_STS       : offset(0x1a60) reg_val = 0xffffffff
[20260729165420]DFX_IOB_RX_AML_LAST_ADDR_LOW : offset(0x1a64) reg_val = 0xffffffff
[20260729165420]DFX_IOB_RX_AML_LAST_ADDR_HIGH: offset(0x1a68) reg_val = 0xffffffff
[20260729165420]DFX_IOB_RX_AML_WR_ID_STS_0   : offset(0x1a80) reg_val = 0xffffffff
[20260729165420]DFX_IOB_RX_AML_WR_ID_STS_1   : offset(0x1a84) reg_val = 0xffffffff
[20260729165420]DFX_IOB_RX_AML_RD_ID_STS_0   : offset(0x1a90) reg_val = 0xffffffff
[20260729165420]DFX_IOB_RX_AML_RD_ID_STS_1   : offset(0x1a94) reg_val = 0xffffffff
[20260729165420]PCIE_CE_STATUS               : offset(0x0020) reg_val = 0xffffffff
[20260729165420]PCIE_UNF_STATUS              : offset(0x0028) reg_val = 0xffffffff
[20260729165420]PCIE_UF_STATUS               : offset(0x0030) reg_val = 0xffffffff
[20260729165420]PCIE_AP_CE_STATUS            : offset(0x0124) reg_val = 0xffffffff
[20260729165420]PCIE_AP_UNF_STATUS           : offset(0x0128) reg_val = 0xffffffff
[20260729165420]PCIE_AP_UF_STATUS            : offset(0x012c) reg_val = 0xffffffff
[20260729165420]PCIE_CORE_CE_STATUS          : offset(0x0184) reg_val = 0xffffffff
[20260729165420]PCIE_CORE_UNF_STATUS         : offset(0x0188) reg_val = 0xffffffff
[20260729165420]PCIE_CORE_UF_STATUS          : offset(0x018c) reg_val = 0xffffffff
[20260729165420]AP_PORT_IDLE                 : offset(0x0c00) reg_val = 0xffffffff
[20260729165420]AP_IDLE                      : offset(0x0c08) reg_val = 0xffffffff
[20260729165420]M_PCS_RPT_REG                : offset(0x0014) reg_val = 0xffffffff
[20260729165420]SERDES_STATUS_RPT            : offset(0x0018) reg_val = 0xffffffff
[20260729165420]RECV_DET_OR_PWR_CHAGE        : offset(0x0034) reg_val = 0xffffffff
[20260729165420]LANE_INTR_STATUS             : offset(0x004c) reg_val = 0xffffffff
[20260729165420]MSG_BUS_DFX                  : offset(0x0068) reg_val = 0xffffffff
[20260729165420]PHY2MAC_MSG_STATUS           : offset(0x007c) reg_val = 0xffffffff
[20260729165420]PCS_LANE_ITF_STATUS          : offset(0x0830) reg_val = 0xffffffff
[20260729165420]M_PCS_RPT_REG                : offset(0x0014) reg_val = 0xffffffff
[20260729165420]SERDES_STATUS_RPT            : offset(0x0018) reg_val = 0xffffffff
[20260729165420]RECV_DET_OR_PWR_CHAGE        : offset(0x0034) reg_val = 0xffffffff
[20260729165420]LANE_INTR_STATUS             : offset(0x004c) reg_val = 0xffffffff
[20260729165420]MSG_BUS_DFX                  : offset(0x0068) reg_val = 0xffffffff
[20260729165420]PHY2MAC_MSG_STATUS           : offset(0x007c) reg_val = 0xffffffff
[20260729165420]PCS_LANE_ITF_STATUS          : offset(0x0830) reg_val = 0xffffffff
[20260729165420]*********** [7] pcie dfx dump end ***********
[20260729165420]*********** [8] mctp0 dfx dump start ***********
[20260729165420] recv packets: 0x00000000
 send packets: 0x00000000
[20260729165420] all send packets(reg): 0xffffffff
 success send packets(reg): 0xffffffff
[20260729165420] all recv packets(reg): 0xffffffff
 success recv packets(reg): 0xffffffff
[20260729165420] drop for rx buff full(reg): 0xffffffff drop for error(reg): 0xffffffff
 drop for head error: 0x00000000
[20260729165420] drop for rx axi error: 0x00000000
 drop for tx axi error: 0x00000000
[20260729165420] drop for rx buff full: 0x00000000
 drop for rx tlp error: 0x00000000
[20260729165420] drop for alloc buff fail: 0x00000000
 drop for tx len error: 0x00000000
[20260729165420] drop invalid bus id packet fail: 0x00000000
[20260729165420]*********** [8] mctp0 dfx dump end ***********
[20260729165420]*********** [9] mctp1 dfx dump start ***********
[20260729165420] recv packets: 0x00000000
 send packets: 0x00000000
[20260729165420] all send packets(reg): 0xffffffff
 success send packets(reg): 0xffffffff
[20260729165420] all recv packets(reg): 0xffffffff
 success recv packets(reg): 0xffffffff
[20260729165420] drop for rx buff full(reg): 0xffffffff drop for error(reg): 0xffffffff
 drop for head error: 0x00000000
[20260729165420] drop for rx axi error: 0x00000000
 drop for tx axi error: 0x00000000
[20260729165420] drop for rx buff full: 0x00000000
 drop for rx tlp error: 0x00000000
[20260729165420] drop for alloc buff fail: 0x00000000
 drop for tx len error: 0x00000000
[20260729165420] drop invalid bus id packet fail: 0x00000000
[20260729165420]*********** [9] mctp1 dfx dump end ***********
[20260729165420]*********** [10] ipmb dfx dump start ***********
[20260729165420]IPMB[0]-CRD<0>|TMO<0>|DAH<0>|CLH<0>|DAL<0>|CLL<0>|STO<0>|BSY<0>|RNZ<0>|RQI<0>
[20260729165420]IPMB[1]-CRD<0>|TMO<0>|DAH<0>|CLH<0>|DAL<0>|CLL<0>|STO<0>|BSY<0>|RNZ<0>|RQI<0>
[20260729165420]IPMB[2]-CRD<0>|TMO<0>|DAH<0>|CLH<0>|DAL<0>|CLL<0>|STO<0>|BSY<0>|RNZ<0>|RQI<0>
[20260729165420]IPMB[3]-CRD<0>|TMO<0>|DAH<0>|CLH<0>|DAL<0>|CLL<0>|STO<0>|BSY<0>|RNZ<0>|RQI<0>
[20260729165420]IPMB[4]-CRD<0>|TMO<0>|DAH<0>|CLH<0>|DAL<0>|CLL<0>|STO<0>|BSY<0>|RNZ<0>|RQI<0>
[20260729165420]IPMB[5]-CRD<0>|TMO<0>|DAH<0>|CLH<0>|DAL<0>|CLL<0>|STO<0>|BSY<0>|RNZ<0>|RQI<0>
[20260729165420]IPMB[6]-CRD<0>|TMO<0>|DAH<0>|CLH<7631886592>|DAL<40768>|CLL<0>|STO<953978928>|BSY<26112>|RNZ<0>|RQI<0>
[20260729165420]IPMB[7]-CRD<0>|TMO<0>|DAH<0>|CLH<0>|DAL<0>|CLL<0>|STO<0>|BSY<0>|RNZ<0>|RQI<0>
[20260729165420]*********** [10] ipmb dfx dump end ***********
[20260729165420]*********** [11] dboot dfx dump start ***********
[20260729165420]CHIP rst ST<0> REG<0x0> CNT<0>|<-1>[0]|<-2>[0]|<-3>[0]|<-4>[0]
[20260729165420]BMC-SEC rst ST<0> REG<0x0> CNT<0>|<-1>[0]|<-2>[0]|<-3>[0]|<-4>[0]
[20260729165420]BMC-UNSEC rst ST<0> REG<0x5aa> CNT<5>|<-1>[2]|<-2>[2]|<-3>[2]|<-4>[2]
[20260729165420]HOST0 rst ST<0> REG<0x0> CNT<0>|<-1>[0]|<-2>[0]|<-3>[0]|<-4>[0]
[20260729165420]HOST1 rst ST<0> REG<0x0> CNT<0>|<-1>[0]|<-2>[0]|<-3>[0]|<-4>[0]
[20260729165420]PCIE0 rst ST<0> REG<0x0> CNT<0>|<-1>[0]|<-2>[0]|<-3>[0]|<-4>[0]
[20260729165420]PCIE1 rst ST<0> REG<0x0> CNT<0>|<-1>[0]|<-2>[0]|<-3>[0]|<-4>[0]
[20260729165420]PLL_LOCK_ST: offset(0x0040) reg_val = 0x00000007
[20260729165420]*********** [11] dboot dfx dump end ***********
[20260729165420]*********** [12] ddr dfx dump start ***********
[20260729165420]AD_PLL_LOCK              : offset(0x0204) reg_val = 0x00000002
[20260729165420]IECC_INTSTS              : offset(0x0008) reg_val = 0x00000000
[20260729165420]IECC_RINT                : offset(0x0010) reg_val = 0x00000000
[20260729165420]IECC_DFX_ST4             : offset(0x002c) reg_val = 0x011004ce
[20260729165420]IECC_DFX_ST5             : offset(0x0030) reg_val = 0x21b92f23
[20260729165420]IECC_DFX_ST6             : offset(0x0034) reg_val = 0x3f7c01b2
[20260729165420]IECC_DFX_ST7             : offset(0x0038) reg_val = 0xa083b4cd
[20260729165420]IECC_DFX_ST8             : offset(0x003c) reg_val = 0x0000031e
[20260729165420]IECC_DFX_ST9             : offset(0x0040) reg_val = 0x017ad9eb
[20260729165420]IECC_DFX_ST10            : offset(0x0044) reg_val = 0x00002ece
[20260729165420]IECC_DFX_ST11            : offset(0x0048) reg_val = 0x00897eaa
[20260729165420]IECC_DFX_HA_ERR_CNT0     : offset(0x0180) reg_val = 0x00000000
[20260729165420]IECC_DFX_PTR_ERR_CNT1    : offset(0x0184) reg_val = 0x00000000
[20260729165420]*********** [12] ddr dfx dump end ***********
[20260729165420]*********** [13] disp dfx dump start ***********
[20260729165420]*********** [13] disp dfx dump end ***********
[20260729165420]*********** [14] gmac dfx dump start ***********
[20260729165420]gmac 0: offset(0x0008) reg_val = 0x00000001
[20260729165420]gmac 0: offset(0x003c) reg_val = 0x000005f8
[20260729165420]gmac 0: offset(0x0040) reg_val = 0x00000001
[20260729165420]gmac 0: offset(0x0058) reg_val = 0x00040000
[20260729165420]gmac 0: offset(0x00c8) reg_val = 0x00000000
[20260729165420]gmac 0: offset(0x015c) reg_val = 0x00000000
[20260729165420]gmac 0: offset(0x0434) reg_val = 0x00000000
[20260729165420]gmac 0: offset(0x045c) reg_val = 0x007f0000
[20260729165420]gmac 0: offset(0x0694) reg_val = 0x00000000
[20260729165420]gmac 0: offset(0x0698) reg_val = 0x00000000
[20260729165420]gmac 0: offset(0x06a0) reg_val = 0x00000000
[20260729165420]gmac 0: offset(0x06a4) reg_val = 0x00000000
[20260729165420]gmac 1: offset(0x0008) reg_val = 0x00000001
[20260729165420]gmac 1: offset(0x003c) reg_val = 0x000005f8
[20260729165420]gmac 1: offset(0x0040) reg_val = 0x00000001
[20260729165420]gmac 1: offset(0x0058) reg_val = 0x00040000
[20260729165420]gmac 1: offset(0x00c8) reg_val = 0x00000000
[20260729165420]gmac 1: offset(0x015c) reg_val = 0x00000000
[20260729165420]gmac 1: offset(0x0434) reg_val = 0x00000000
[20260729165420]gmac 1: offset(0x045c) reg_val = 0x007f0000
[20260729165420]gmac 1: offset(0x0694) reg_val = 0x00000000
[20260729165420]gmac 1: offset(0x0698) reg_val = 0x00000000
[20260729165420]gmac 1: offset(0x06a0) reg_val = 0x00000000
[20260729165420]gmac 1: offset(0x06a4) reg_val = 0x00000000
[20260729165420]gmac 2: offset(0x0008) reg_val = 0x00000001
[20260729165420]gmac 2: offset(0x003c) reg_val = 0x000005f8
[20260729165420]gmac 2: offset(0x0040) reg_val = 0x00000008
[20260729165420]gmac 2: offset(0x0058) reg_val = 0x00349800
[20260729165420]gmac 2: offset(0x00c8) reg_val = 0x00000000
[20260729165420]gmac 2: offset(0x015c) reg_val = 0x00000000
[20260729165420]gmac 2: offset(0x0434) reg_val = 0x09004000
[20260729165420]gmac 2: offset(0x045c) reg_val = 0x007e0000
[20260729165420]gmac 2: offset(0x0694) reg_val = 0x00000001
[20260729165420]gmac 2: offset(0x0698) reg_val = 0x00000000
[20260729165420]gmac 2: offset(0x06a0) reg_val = 0x00000001
[20260729165420]gmac 2: offset(0x06a4) reg_val = 0x00000000
[20260729165420]gmac 3: offset(0x0008) reg_val = 0x00000001
[20260729165420]gmac 3: offset(0x003c) reg_val = 0x000005f8
[20260729165420]gmac 3: offset(0x0040) reg_val = 0x00000008
[20260729165420]gmac 3: offset(0x0058) reg_val = 0x00340000
[20260729165420]gmac 3: offset(0x00c8) reg_val = 0x00000000
[20260729165420]gmac 3: offset(0x015c) reg_val = 0x00000000
[20260729165420]gmac 3: offset(0x0434) reg_val = 0x00000000
[20260729165420]gmac 3: offset(0x045c) reg_val = 0x007f0000
[20260729165420]gmac 3: offset(0x0694) reg_val = 0x00000001
[20260729165420]gmac 3: offset(0x0698) reg_val = 0x00000000
[20260729165420]gmac 3: offset(0x06a0) reg_val = 0x00000001
[20260729165420]gmac 3: offset(0x06a4) reg_val = 0x00000000
[20260729165420]*********** [14] gmac dfx dump end ***********
[20260729165420]*********** [15] uart_sol dfx dump start ***********
[20260729165420]SOL-0 enable[0]:
[20260729165420]TX_ADD=0x86000000 TX_SIZE=0x400000 RX_ADD=0x86400000 RX_SIZE=0x100000
[20260729165420]TX_NOW=0x85800000 RX_NOW=0x88800000 FIFO_ST=0x00004040 ERR_CNT=0 IRQ=1 RETRY=3
[20260729165420]SOL-1 enable[1]:
[20260729165420]TX_ADD=0x86080000 TX_SIZE=0x400000 RX_ADD=0x86000000 RX_SIZE=0x80000
[20260729165420]TX_NOW=0x8608533c RX_NOW=0x88800000 FIFO_ST=0x00001940 ERR_CNT=0 IRQ=1 RETRY=3
[20260729165420]SOL-2 enable[1]:
[20260729165420]TX_ADD=0x86680000 TX_SIZE=0x80000 RX_ADD=0x86480000 RX_SIZE=0x200000
[20260729165420]TX_NOW=0x85800000 RX_NOW=0x88800000 FIFO_ST=0x00004040 ERR_CNT=0 IRQ=1 RETRY=3
[20260729165420]SOL-3 enable[1]:
[20260729165420]TX_ADD=0x86900000 TX_SIZE=0x80000 RX_ADD=0x86700000 RX_SIZE=0x200000
[20260729165420]TX_NOW=0x85800000 RX_NOW=0x88800000 FIFO_ST=0x00004040 ERR_CNT=0 IRQ=1 RETRY=3
[20260729165420]SOL-4 enable[0]:
[20260729165420]TX_ADD=0x8a000000 TX_SIZE=0x800000 RX_ADD=0x8a800000 RX_SIZE=0x200000
[20260729165420]TX_NOW=0x85800000 RX_NOW=0x88800000 FIFO_ST=0x00004040 ERR_CNT=0 IRQ=1 RETRY=3
[20260729165420]SOL-5 enable[0]:
[20260729165420]TX_ADD=0x8aa00000 TX_SIZE=0x400000 RX_ADD=0x8ae00000 RX_SIZE=0x200000
[20260729165420]TX_NOW=0x85800000 RX_NOW=0x88800000 FIFO_ST=0x00004040 ERR_CNT=0 IRQ=1 RETRY=3
[20260729165420]SOL-6 enable[0]:
[20260729165420]TX_ADD=0x8b000000 TX_SIZE=0x200000 RX_ADD=0x8b200000 RX_SIZE=0x400000
[20260729165420]TX_NOW=0x85800000 RX_NOW=0x88800000 FIFO_ST=0x00004040 ERR_CNT=0 IRQ=1 RETRY=3
[20260729165420]SOL-7 enable[0]:
[20260729165420]TX_ADD=0x8b600000 TX_SIZE=0x400000 RX_ADD=0x8ba00000 RX_SIZE=0x100000
[20260729165420]TX_NOW=0x85800000 RX_NOW=0x88800000 FIFO_ST=0x00004040 ERR_CNT=0 IRQ=1 RETRY=3
[20260729165420]SOL-8 enable[0]:
[20260729165420]TX_ADD=0x86000000 TX_SIZE=0x400000 RX_ADD=0x86400000 RX_SIZE=0x100000
[20260729165420]TX_NOW=0x85800000 RX_NOW=0x88800000 FIFO_ST=0x00004040 ERR_CNT=0 IRQ=1 RETRY=3
[20260729165420]SOL-9 enable[0]:
[20260729165420]TX_ADD=0x8b600000 TX_SIZE=0x400000 RX_ADD=0x8ba00000 RX_SIZE=0x100000
[20260729165420]TX_NOW=0x85800000 RX_NOW=0x88800000 FIFO_ST=0x00004040 ERR_CNT=0 IRQ=1 RETRY=3
[20260729165420]*********** [15] uart_sol dfx dump end ***********
[20260729165420]*********** [18] env dfx dump start ***********
[20260729165420]pcie0MiscBar0Size         : 0x17
[20260729165420]pcie0MiscBar2Size         : 0x17
[20260729165420]pcie0MiscBar4Size         : 0x19
[20260729165420]pcie1MiscBar0Size         : 0x17
[20260729165420]pcie1MiscBar2Size         : 0x17
[20260729165420]pcie1MiscBar4Size         : 0x19
[20260729165420]bmcUartPort               : 0x2
[20260729165420]rsvDramSize               : 0x0
[20260729165420]sceneMgmtH10Usage         : 0x9
[20260729165420]sceneMgmtH25Usage         : 0x0
[20260729165420]sceneMgmtGmac2MacAddr_l   : 0xa923ace8
[20260729165420]sceneMgmtGmac2MacAddr_h   : 0xc49
[20260729165420]sceneMgmtGmac3MacAddr_l   : 0xa923ace8
[20260729165420]sceneMgmtGmac3MacAddr_h   : 0xd49
[20260729165420]sceneMgmtGmacPhysAddr     : 0x303
[20260729165420]dfxLastWordIsGpio         : 0x0
[20260729165420]dfxLastWordGpioPin        : 0x7f
[20260729165420]h10Ssc                    : 0x0
[20260729165420]h25Ssc                    : 0x0
[20260729165420]copBootSize               : 0x1000000
[20260729165420]dpLane0TxDeemph           : 0x600
[20260729165420]dpLane1TxDeemph           : 0x600
[20260729165420]rtosMemAddr               : 0x98400000
[20260729165420]a55DdrBwThreshold         : 0xa
[20260729165420]pwmLightCfg               : 0x0
[20260729165420]mmcForceTuning            : 0x0
[20260729165420]cpllHighFreqSel           : 0x0
[20260729165420]cpllFreqConfig            : 0x1
[20260729165420]gmacPhysAddr              : 0xfefefeff
[20260729165420]trfcab                    : 0xffffffff
[20260729165420]trfcpb                    : 0xffffffff
[20260729165420]trpab                     : 0xffffffff
[20260729165420]trppb                     : 0xffffffff
[20260729165420]exmbistBitmap             : 0x0
[20260729165420]marginSwitch              : 0x0
[20260729165420]eyescanSwitch             : 0x0
[20260729165420]eyescanDir                : 0x0
[20260729165420]eyescanPattern            : 0x0
[20260729165420]pcie0PFUsage0             : 0xb9876541
[20260729165420]pcie0PFUsage1             : 0xffffffff
[20260729165420]pcie1PFUsage              : 0xffffffff
[20260729165420]gpuBarType                : 0x0
[20260729165420]caVref                    : 0xffffffff
[20260729165420]caMarginSwitch            : 0x1
[20260729165420]vdac_gc                   : 0xffffffff
[20260729165420]retrainCheck              : 0xffffffff
[20260729165420]mmcTuningDly1             : 0x4
[20260729165420]*********** [18] env dfx dump end ***********
[20260729165420]*********** [19] i3c dfx dump start ***********
[20260729165420]*********** [19] i3c dfx dump end ***********
[20260729165420]*********** [20] emmc dfx dump start ***********
[20260729165420]emmc offset(0x04) reg_val = 0x20200
[20260729165420]emmc offset(0x08) reg_val = 0x10000
[20260729165420]emmc offset(0x0c) reg_val = 0xd1a0000
[20260729165420]emmc offset(0x10) reg_val = 0x900
[20260729165420]emmc offset(0x14) reg_val = 0xffffffff
[20260729165420]emmc offset(0x18) reg_val = 0x329f5903
[20260729165420]emmc offset(0x1c) reg_val = 0xd0ffff
[20260729165420]emmc offset(0x24) reg_val = 0xf1ff0000
[20260729165420]emmc offset(0x28) reg_val = 0xb3c
[20260729165420]emmc offset(0x2c) reg_val = 0x80007
[20260729165420]emmc offset(0x30) reg_val = 0x0
[20260729165420]emmc offset(0x34) reg_val = 0x3fff703f
[20260729165420]emmc offset(0x38) reg_val = 0x2
[20260729165420]emmc offset(0x80) reg_val = 0x8f170100
[20260729165420]emmc offset(0x84) reg_val = 0xd000ff24
[20260729165420]emmc offset(0x90) reg_val = 0x84313e44
[20260729165420]*********** [20] emmc dfx dump end ***********
[20260729165420]*********** [23] btc dfx dump start ***********
[20260729165420]btc_bus_0 busy_status:0
[20260729165420]btc_bus_1 busy_status:0
[20260729165420]btc_bus_2 busy_status:0
[20260729165420]btc_bus_3 busy_status:0
[20260729165420]btc_bus_4 busy_status:0
[20260729165420]btc_bus_5 busy_status:0
[20260729165420]btc_bus_6 busy_status:0
[20260729165420]btc_bus_7 busy_status:0
[20260729165420]btc_bus_8 busy_status:0
[20260729165420]btc_bus_9 busy_status:0
[20260729165420]btc_bus_10 busy_status:0
[20260729165420]btc_bus_11 busy_status:0
[20260729165420]btc_bus_12 busy_status:0
[20260729165420]btc_bus_13 busy_status:0
[20260729165420]btc_bus_14 busy_status:0
[20260729165420]btc_bus_15 busy_status:0
[20260729165420]*********** [23] btc dfx dump end ***********
[20260729165420]2026-07-29 16:54:20,3933,dfx_dump_func,70,*********** DFX DUMP END ***********
