DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
[IMU][DEBUG]:  Offset 0xfc0000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
registry filesize:0x31cb

[IMU][DEBUG]:  Offset 0xfd8000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x[IMU][ERROR]:  The response code is0
[IMU][DEBUG]:  CS is abnormal 0xd6.
 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
version:
Welcome to the IMU Firmware!
IMU Firmware version 6.65.0
LiteOS version 5.0.0
[IMU][ERROR]:  IMU reset 0
[2.248]IMU System Timer setup OK!
[2.251][IMU] lbc Config Done.
[2.256]CpuType: 0
[2.256]IsHi1620S: 0
BoardType: 0xffffffff
[2.261]base: 0x90b00000
GetV167Flag = 0x0
SFC Initialization Start...
[GetDeviceId]:[384L]SFC Cs 0 detected ID[0x1860c8]!
[GetDeviceId]:[384L]SFC Cs 1 detected ID[0x0]!
[IMU][ERROR]:  [CollectSpiFlash]:[411] Don't support the flash, Cs[1] ID[0x0]!!
System supported 1 Flash.
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1811] Spi Cs 0
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1823] Before config value 0x80800300
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1831] After config value 0x80800300
SFC Initialization Done
It is NS boot!!!
boot from L2!!!
[2.307]reboot time:0
[CheckAllTrainingStatus]:[1495L] Idx0 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx1 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx2 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx3 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx4 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx5 HllcIdx0 read: 30000f 
[CheingStatus]:[1495L] Idx2 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx3 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx4 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx5 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx6 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx7 HllcIdx0 read: 30000f 
when compile IMU, have to use parameter 'bit', 1024[2.356][CheckAllTrainingStatus]Chip:0
[CheckAllTrainingStatus]:[1495L] Idx0 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx1 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx2 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx3 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx4 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx5 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx6 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx7 HllcIdx0 read: 30000f 
when compile IMU, have to use parameter 'bit', 2048[2.407][CheckAllTrainingStatus]Chip:1
[2.411]ChipNum: 2
TotemNum: 4
NimbusNum: 2
[0]1.
[1]3.
[2]5.
[3]7.
[IMU][DEBUG]:  Back sram data...
Socket=2
dieId=0x1
EfuseBase=0x98380000
efuse=0x0
DieId=1
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x3
EfuseBase=0x90380000
efuse=0x0
DieId=3
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x5
EfuseBase=0x4098380000
efuse=0x0
DieId=5
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x7
EfuseBase=0x4090380000
efuse=0x0
DieId=7
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
[IMU][DEBUG]:  Restore sram data...
osAppInit
recvSerdesCfg[0][0]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][1]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][2]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][3]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][4]serdesMode = 3, bandWidth = 4, GenSpeed = 2, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][5]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][6]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[7] bandWidth is X16!
recvSerdesCfg[0][7]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[8] bandWidth is X16!
recvSerdesCfg[0][8]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][9]serdesMode = 1, bandWidth = 3, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[10] bandWidth is X16!
recvSerdesCfg[0][10]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][0]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][1]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][2]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][3]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][4]serdesMode = 1, bandWidth = 3, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][5]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][6]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[7] bandWidth is X16!
recvSerdesCfg[1][7]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[8] bandWidth is X16!
recvSerdesCfg[1][8]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][9]serdesMode = 4, bandWidth = 4, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[10] bandWidth is X16!
recvSerdesCfg[1][10]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
SerdesDataStruct size = 7
[TianChiGetNicTypeFromCpld][241L] ExecuteCPLDSmcCmd:5
[SetTianChiNicType] Nic 0 Type: 0x0
[TianChiGetNicTypeFromCpld][241L] ExecuteCPLDSmcCmd:5
[SetTianChiNicType] Nic 1 Type: 0x0
[3.511]Normal version.
[InterruptRegister]:[395L]id = 65
[SIWInterruptInit]:[151L]id:65, init done!
[InterruptRegister]:[395L]id = 67
[InterruptRegister]:[395L]id = 69
[IpmbInterruptInit]:[262L]id:69
[InterruptRegister]:[395L]id = 71
[Scmi0InterruptInit]:[25L]id:71, init done!
[InterruptRegister]:[395L]id = 72
[Scmi1InterruptInit]:[38L]id:72, init done!
[InterruptRegister]:[395L]id = 76
[InterruptRegister]:[395L]id = 78
[TotemResetInit]:[70L]id:78, init done!
[InterruptRegister]:[395L]id = 83
[InterruptRegister]:[395L]id = 275
[InterruptRegister]:[395L]id = 299
[InterruptRegister]:[395L]id = 116
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x0 Clear done
[InterruptRegister]:[395L]id = 117
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x0 Clear done
[InterruptRegister]:[395L]id = 134
[InterruptRegister]:[395L]id = 96
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x8000000 Clear done
[InterruptRegister]:[395L]id = 97
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x8000000 Clear done
[InterruptRegister]:[395L]id = 114
[InterruptRegister]:[395L]id = 256
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt0RasIntClear]:[259L]nimbusBase 0x0 clear done
[InterruptRegister]:[395L]id = 257
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt1RasIntClear]:[529L]nimbusBase 0x0 Clear done
[InterruptRegister]:[395L]id = 258
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt2RasIntClear]:[638L]nimbusBase 0x0 Clear done
[InterruptRegister]:[395L]id = 259
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusHacRasIntClear]:[311L]NimbusHacRasIntClear done
[InterruptRegister]:[395L]id = 260
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusNicRasIntClear]:[466L]nimbusBase 0x0 Clear done
[InterruptRegister]:[395L]id = 261
[NimbusPCIeRasIntClear]:[662L]NimbusBase 0x0 Clear Start...
[NimbusPCIeRasIntClear]:[673L]NimbusBase 0x0 Clear done!
[InterruptRegister]:[395L]id = 156
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 157
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 174
[InterruptRegister]:[395L]id = 136
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x4008000000 Clear done
[InterruptRegister]:[395L]id = 137
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x4008000000 Clear done
[InterruptRegister]:[395L]id = 154
[InterruptRegister]:[395L]id = 280
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt0RasIntClear]:[259L]nimbusBase 0x4000000000 clear done
[InterruptRegister]:[395L]id = 281
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt1RasIntClear]:[529L]nimbusBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 282
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt2RasIntClear]:[638L]nimbusBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 283
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusHacRasIntClear]:[311L]NimbusHacRasIntClear done
[InterruptRegister]:[395L]id = 284
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusNicRasIntClear]:[466L]nimbusBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 285
[NimbusPCIeRasIntClear]:[662L]NimbusBase 0x4000000000 Clear Start...
[NimbusPCIeRasIntClear]:[673L]NimbusBase 0x4000000000 Clear done!
Cer Initialization start...
[IMU][DEBUG]:  CER_CFG_BD_ENDIAN_ADDR is 0x3
[IMU][DEBUG]:  OUT STANDING is 0x4040
[IMU][DEBUG]:  OUT STANDING after set is 0x140
Cer Initialization done.
[IMU] I2C Initialization start...
[IMU] I2cDealNimbusException secket:0
[IMU] Set I2C4 ----> IPMB mode(default), Set I2C5 ----> I2C mode Success.
[IMU][DEBUG]:  Start init I2C on Address: [0x210050000].
[IMU][DEBUG]:  I2C on Address: [0x210050000] init Succed.
[IMU] Set I2C5 to NORMAL mode.
[IMU] I2C Initialization done!
[IMU] Scmi channels Initialization done!
SIW Initialization Starting...

Enable SIW Debug interface ...
[IMU][DEBUG]:  ES.IMU.SIW.006 SC_SIW_STAT register value is 0x8000.
SIW bypass disabled.
SIW Initialization Done.

[IMU] MiscConfig Start.
[IMU][DEBUG]:  DDRC_CFG_STADAT before config 0x0.
[IMU][DEBUG]:  DDRC_CFG_STADAT after config 0x40000000.
[IMU] Misc Config Done.
[IMU] Gpio MUX Config Done.
[IMU] N_CATERR Gpio MUX Config Done.
[IMU][DEBUG]:  CPU_cluster 0x5a00 is 0xff, hotreset is 0x0
TotemPll0InitCs nodeId:3
TotemPll0InitCs nodeId:1
SllcSetBand isHigh:1
SpiTpmRead ret: 0x0, detect = 0x0
SpiTpmRead ret: 0x0, didVid = 0x0
[IMU][ERROR]:  TPM is not detected
[IMU][ERROR]:  Tpm init err, 0x1
[IMU][DEBUG]:  Offset 0x800000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
 IMU compilation script 
IMU start to measure sec.
[IMU][ERROR]:  Unsupported trusted module
TPM Measure UEFI SEC fail, 0x1
[IMU][DEBUG]:  Offset 0x400000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
[IMU][DEBUG]:  Offset 0x90000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
It's not secure boot
TotemPll0DeInitCs nodeId:1
TotemPll0DeInitCs nodeId:3
SllcSetBand isHigh:0
base: 0x98200000
Ap is booting up, status: 0xee
[IMU][DEBUG]:  Offset 0x890000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
IMU start to measure Fvmain_compact and TF.
[IMU][ERROR]:  Unsupported trusted module
TPM Measure Uefi and TF fail, 0x1
IMU start to measure certificate and HD.
[IMU][ERROR]:  Unsupported trusted module
TPM Measure Certificate and HD fail, 0x1
[SetSkipTrainingFlag]21007f024:1620a5a2
[IMU] Watchdog Initialization done!
cpu 0 entering scheduler
[IMU] Chip: 0 Totem-B Fabric sub T-sensor setup ok!
[IMU] Chip: 0 Totem-B Sys sub T-sensor setup ok!
[IMU] Chip: 0 Totem-A Fabric sub T-sensor setup ok!
[IMU] Chip: 0 Totem-A Sys T-sensor setup ok!
[IMU] Chip: 0 Nimbus T-sensor setup ok!
IPMB initialization Start...
IPMB module clock set done.
IPMB Rx FIFO clear empty.
IPMB initialization Done.
[GetInitSendNumber]:[2142]semaphore create init number = 0!
cfg=110005 g_mctpCount=4
mctp_dev[0] enable=1 mode=1
mctp_dev[1] enable=0 mode=0
mctp_dev[2] enable=1 mode=1
mctp_dev[3] enable=0 mode=0
mctp_loop_task Create Success
HardWare Send IPMI Errorr regValue = 0x8 !!!!
Send process recive sto !!!!

[extInt0Init]:[65L]

[extInt0Init]:[69L]
Core Number: 0x40
Enable scmi int done
mctp loop task start.
Ras Handle task start.
[IpmiMsgGetManufactureid][135]Gotted ManufactureId:db 07 00
pwr cap[0]: 0, 63
pwr cap[1]: f, 27
SetupCfg  :
EnFdmSupport:            0x1
DdrRefreshRate:          0x0
PowerESaving:            0x0
HotPlug:                 0x1
ProcessorFlexibleRatio:  0x1a
CoreIsolateOnlineFlag:   0x0
EnRasSupport:            0x1
AdvanceDeviceCorrection: 0x0
PatrolScrubDuration:     0x18
X8MisCorrEn:             0x0
PowerOnTime:             0xa
DimmTime:                0xa
PageIsolation:           0x0
Mem2BitErrCorrEn:        0x1
pwr cap[2]: 1, 3
[24.858]Real time now:  2026/04/29, 19:58:23
[24.860]InitialCntTime = 24
[24.978][IMU] System DDR Init Done!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x56 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x56 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x56 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x56 DRAM Width failed
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntInit done
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntInit done
[NimbusMgmt0IntInit]:[233L]NimbusMgmt0IntInit done
[NimbusMgmt1IntInit]:[499L]
[NimbusMgmt2IntInit]:[626L]NimbusMgmt2IntInit done
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntInit done
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntIniCppcShareMem: 0x44000000
t done
[NimbusMgmt0IntInit]:[233L]NimbusMgmt0IntInit done
[NimbusMgmt1IntInit]:[499L]
[NimbusMgmt2IntInit]:[626L]NimbusMgmt2IntInit done
[IMU][DEBUG]:  Offset 0x400000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
[IMU][DEBUG]:  Offset 0xfc0000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
registry filesize:0x31cb

[IMU][DEBUG]:  Offset 0xfd8000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[I[IMU][ERROR]:  The resMU][DEBUG]:  CS is 0x0
ponse code is abnormal 
[IMU][DEBUG]:  [SfcCmd0xd6.
Read][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
version:
Welcome to the IMU Firmware!
IMU Firmware version 6.65.0
LiteOS version 5.0.0
[IMU][ERROR]:  IMU reset 0
[2.248]IMU System Timer setup OK!
[2.251][IMU] lbc Config Done.
[2.256]CpuType: 0
[2.256]IsHi1620S: 0
BoardType: 0xffffffff
[2.261]base: 0x90b00000
GetV167Flag = 0x0
SFC Initialization Start...
[GetDeviceId]:[384L]SFC Cs 0 detected ID[0x1860c8]!
[GetDeviceId]:[384L]SFC Cs 1 detected ID[0x0]!
[IMU][ERROR]:  [CollectSpiFlash]:[411] Don't support the flash, Cs[1] ID[0x0]!!
System supported 1 Flash.
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1811] Spi Cs 0
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1823] Before config value 0x80800300
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1831] After config value 0x80800300
SFC Initialization Done
It is NS boot!!!
boot from L2!!!
[2.307]reboot time:0
[CheckAllTrainingStatus]:[1495L] Idx0 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx1 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx2 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx3 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx4 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx5 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx6 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx7 HllcIdx0 read: 30000f 
when compile IMU, have to use parameter 'bit', 1024[2.356][CheckAllTrainingStatus]Chip:0
[CheckAllTrainingStatus]:[1495L] Idx0 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx1 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx2 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx3 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx4 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx5 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx6 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx7 HllcIdx0 read: 30000f 
when compile IMU, have to use parameter 'bit', 2048[2.407][CheckAllTrainingStatus]Chip:1
[2.411]ChipNum: 2
TotemNum: 4
NimbusNum: 2
[0]1.
[1]3.
[2]5.
[3]7.
[IMU][DEBUG]:  Back sram data...
Socket=2
dieId=0x1
EfuseBase=0x98380000
efuse=0x0
DieId=1
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x3
EfuseBase=0x90380000
efuse=0x0
DieId=3
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x5
EfuseBase=0x4098380000
efuse=0x0
DieId=5
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x7
EfuseBase=0x4090380000
efuse=0x0
DieId=7
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
[IMU][DEBUG]:  Restore sram data...
osAppInit
recvSerdesCfg[0][0]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][1]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][2]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][3]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][4]serdesMode = 3, bandWidth = 4, GenSpeed = 2, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][5]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][6]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[7] bandWidth is X16!
recvSerdesCfg[0][7]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[8] bandWidth is X16!
recvSerdesCfg[0][8]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][9]serdesMode = 1, bandWidth = 3, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[10] bandWidth is X16!
recvSerdesCfg[0][10]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][0]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][1]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][2]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][3]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][4]serdesMode = 1, bandWidth = 3, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][5]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][6]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[7] bandWidth is X16!
recvSerdesCfg[1][7]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[8] bandWidth is X16!
recvSerdesCfg[1][8]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][9]serdesMode = 4, bandWidth = 4, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[10] bandWidth is X16!
recvSerdesCfg[1][10]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
SerdesDataStruct size = 7
[TianChiGetNicTypeFromCpld][241L] ExecuteCPLDSmcCmd:5
[SetTianChiNicType] Nic 0 Type: 0x0
[TianChiGetNicTypeFromCpld][241L] ExecuteCPLDSmcCmd:5
[SetTianChiNicType] Nic 1 Type: 0x0
[3.511]Normal version.
[InterruptRegister]:[395L]id = 65
[SIWInterruptInit]:[151L]id:65, init done!
[InterruptRegister]:[395L]id = 67
[InterruptRegister]:[395L]id = 69
[IpmbInterruptInit]:[262L]id:69
[InterruptRegister]:[395L]id = 71
[Scmi0InterruptInit]:[25L]id:71, init done!
[InterruptRegister]:[395L]id = 72
[Scmi1InterruptInit]:[38L]id:72, init done!
[InterruptRegister]:[395L]id = 76
[InterruptRegister]:[395L]id = 78
[TotemResetInit]:[70L]id:78, init done!
[InterruptRegister]:[395L]id = 83
[InterruptRegister]:[395L]id = 275
[InterruptRegister]:[395L]id = 299
[InterruptRegister]:[395L]id = 116
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x0 Clear done
[InterruptRegister]:[395L]id = 117
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x0 Clear done
[InterruptRegister]:[395L]id = 134
[InterruptRegister]:[395L]id = 96
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x8000000 Clear done
[InterruptRegister]:[395L]id = 97
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x8000000 Clear done
[InterruptRegister]:[395L]id = 114
[InterruptRegister]:[395L]id = 256
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt0RasIntClear]:[259L]nimbusBase 0x0 clear done
[InterruptRegister]:[395L]id = 257
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt1RasIntClear]:[529L]nimbusBase 0x0 Clear done
[InterruptRegister]:[395L]id = 258
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt2RasIntClear]:[638L]nimbusBase 0x0 Clear done
[InterruptRegister]:[395L]id = 259
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusHacRasIntClear]:[311L]NimbusHacRasIntClear done
[InterruptRegister]:[395L]id = 260
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusNicRasIntClear]:[466L]nimbusBase 0x0 Clear done
[InterruptRegister]:[395L]id = 261
[NimbusPCIeRasIntClear]:[662L]NimbusBase 0x0 Clear Start...
[NimbusPCIeRasIntClear]:[673L]NimbusBase 0x0 Clear done!
[InterruptRegister]:[395L]id = 156
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 157
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 174
[InterruptRegister]:[395L]id = 136
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x4008000000 Clear done
[InterruptRegister]:[395L]id = 137
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x4008000000 Clear done
[InterruptRegister]:[395L]id = 154
[InterruptRegister]:[395L]id = 280
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt0RasIntClear]:[259L]nimbusBase 0x4000000000 clear done
[InterruptRegister]:[395L]id = 281
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt1RasIntClear]:[529L]nimbusBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 282
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt2RasIntClear]:[638L]nimbusBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 283
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusHacRasIntClear]:[311L]NimbusHacRasIntClear done
[InterruptRegister]:[395L]id = 284
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusNicRasIntClear]:[466L]nimbusBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 285
[NimbusPCIeRasIntClear]:[662L]NimbusBase 0x4000000000 Clear Start...
[NimbusPCIeRasIntClear]:[673L]NimbusBase 0x4000000000 Clear done!
Cer Initialization start...
[IMU][DEBUG]:  CER_CFG_BD_ENDIAN_ADDR is 0x3
[IMU][DEBUG]:  OUT STANDING is 0x4040
[IMU][DEBUG]:  OUT STANDING after set is 0x140
Cer Initialization done.
[IMU] I2C Initialization start...
[IMU] I2cDealNimbusException secket:0
[IMU] Set I2C4 ----> IPMB mode(default), Set I2C5 ----> I2C mode Success.
[IMU][DEBUG]:  Start init I2C on Address: [0x210050000].
[IMU][DEBUG]:  I2C on Address: [0x210050000] init Succed.
[IMU] Set I2C5 to NORMAL mode.
[IMU] I2C Initialization done!
[IMU] Scmi channels Initialization done!
SIW Initialization Starting...

Enable SIW Debug interface ...
[IMU][DEBUG]:  ES.IMU.SIW.006 SC_SIW_STAT register value is 0x8000.
SIW bypass disabled.
SIW Initialization Done.

[IMU] MiscConfig Start.
[IMU][DEBUG]:  DDRC_CFG_STADAT before config 0x0.
[IMU][DEBUG]:  DDRC_CFG_STADAT after config 0x40000000.
[IMU] Misc Config Done.
[IMU] Gpio MUX Config Done.
[IMU] N_CATERR Gpio MUX Config Done.
[IMU][DEBUG]:  CPU_cluster 0x5a00 is 0xff, hotreset is 0x0
TotemPll0InitCs nodeId:3
TotemPll0InitCs nodeId:1
SllcSetBand isHigh:1
SpiTpmRead ret: 0x0, detect = 0x0
SpiTpmRead ret: 0x0, didVid = 0x0
[IMU][ERROR]:  TPM is not detected
[IMU][ERROR]:  Tpm init err, 0x1
[IMU][DEBUG]:  Offset 0x800000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
 IMU compilation script 
IMU start to measure sec.
[IMU][ERROR]:  Unsupported trusted module
TPM Measure UEFI SEC fail, 0x1
[IMU][DEBUG]:  Offset 0x400000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
[IMU][DEBUG]:  Offset 0x90000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
It's not secure boot
TotemPll0DeInitCs nodeId:1
TotemPll0DeInitCs nodeId:3
SllcSetBand isHigh:0
base: 0x98200000
Ap is booting up, status: 0xee
[IMU][DEBUG]:  Offset 0x890000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
IMU start to measure Fvmain_compact and TF.
[IMU][ERROR]:  Unsupported trusted module
TPM Measure Uefi and TF fail, 0x1
IMU start to measure certificate and HD.
[IMU][ERROR]:  Unsupported trusted module
TPM Measure Certificate and HD fail, 0x1
[SetSkipTrainingFlag]21007f024:1620a5a2
[IMU] Watchdog Initialization done!
cpu 0 entering scheduler
[IMU] Chip: 0 Totem-B Fabric sub T-sensor setup ok!
[IMU] Chip: 0 Totem-B Sys sub T-sensor setup ok!
[IMU] Chip: 0 Totem-A Fabric sub T-sensor setup ok!
[IMU] Chip: 0 Totem-A Sys T-sensor setup ok!
[IMU] Chip: 0 Nimbus T-sensor setup ok!
IPMB initialization Start...
IPMB module clock set done.
IPMB Rx FIFO clear empty.
IPMB initialization Done.
[GetInitSendNumber]:[2142]semaphore create init number = 0!
cfg=110005 g_mctpCount=4
mctp_dev[0] enable=1 mode=1
mctp_dev[1] enable=0 mode=0
mctp_dev[2] enable=1 mode=1
mctp_dev[3] enable=0 mode=0
mctp_loop_task Create Success
HardWare Send IPMI Errorr regValue = 0x8 !!!!
Send process recive sto !!!!

[extInt0Init]:[65L]

[extInt0Init]:[69L]
Core Number: 0x40
Enable scmi int done
mctp loop task start.
Ras Handle task start.
[IpmiMsgGetManufactureid][135]Gotted ManufactureId:db 07 00
pwr cap[0]: 0, 63
pwr cap[1]: f, 27
SetupCfg  :
EnFdmSupport:            0x1
DdrRefreshRate:          0x0
PowerESaving:            0x0
HotPlug:                 0x1
ProcessorFlexibleRatio:  0x1a
CoreIsolateOnlineFlag:   0x0
EnRasSupport:            0x1
AdvanceDeviceCorrection: 0x0
PatrolScrubDuration:     0x18
X8MisCorrEn:             0x0
PowerOnTime:             0xa
DimmTime:                0xa
PageIsolation:           0x0
Mem2BitErrCorrEn:        0x1
pwr cap[2]: 1, 3
[24.825]Real time now:  2026/04/29, 20:03:29
[24.827]InitialCntTime = 24
[24.939][IMU] System DDR Init Done!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x56 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x56 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x56 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x56 DRAM Width failed
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntInit done
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntInit done
[NimbusMgmt0IntInit]:[233L]NimbusMgmt0IntInit done
[NimbusMgmt1IntInit]:[499L]
[NimbusMgmt2IntInit]:[626L]NimbusMgmt2IntInit done
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntInit done
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntInit done
[NimbusMgmt0IntInit]:[233L]NimbusMgmt0IntInit done
[NimbusMgmt1IntInit]:[499L]
[NimbusMgmt2IntInit]:[626L]NimbusMgmt2IntInit done
[IMU][DEBUG]:  Offset 0x400000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
CppcShareMem: 0x44000000
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
[IMU][DEBUG]:  Offset 0xfc0000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
registry filesize:0x31cb

[IMU][DEBUG]:  Offset 0xfd8000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0[IMU][ERROR]
[IMU][DEBUG]:  [SfcCm:  The response code isdRead][1580] Start Cs=[ abnormal 0xd6.
0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
version:
Welcome to the IMU Firmware!
IMU Firmware version 6.65.0
LiteOS version 5.0.0
[IMU][ERROR]:  IMU reset 0
[2.248]IMU System Timer setup OK!
[2.251][IMU] lbc Config Done.
[2.256]CpuType: 0
[2.256]IsHi1620S: 0
BoardType: 0xffffffff
[2.261]base: 0x90b00000
GetV167Flag = 0x0
SFC Initialization Start...
[GetDeviceId]:[384L]SFC Cs 0 detected ID[0x1860c8]!
[GetDeviceId]:[384L]SFC Cs 1 detected ID[0x0]!
[IMU][ERROR]:  [CollectSpiFlash]:[411] Don't support the flash, Cs[1] ID[0x0]!!
System supported 1 Flash.
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1811] Spi Cs 0
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1823] Before config value 0x80800300
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1831] After config value 0x80800300
SFC Initialization Done
It is NS boot!!!
boot from L2!!!
[2.307]reboot time:0
[CheckAllTrainingStatus]:[1495L] Idx0 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx1 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx2 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx3 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx4 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx5 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx6 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx7 HllcIdx0 read: 30000f 
when compile IMU, have to use parameter 'bit', 1024[2.356][CheckAllTrainingStatus]Chip:0
[CheckAllTrainingStatus]:[1495L] Idx0 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx1 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx2 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx3 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx4 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx5 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx6 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx7 HllcIdx0 read: 30000f 
when compile IMU, have to use parameter 'bit', 2048[2.407][CheckAllTrainingStatus]Chip:1
[2.411]ChipNum: 2
TotemNum: 4
NimbusNum: 2
[0]1.
[1]3.
[2]5.
[3]7.
[IMU][DEBUG]:  Back sram data...
Socket=2
dieId=0x1
EfuseBase=0x98380000
efuse=0x0
DieId=1
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x3
EfuseBase=0x90380000
efuse=0x0
DieId=3
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x5
EfuseBase=0x4098380000
efuse=0x0
DieId=5
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x7
EfuseBase=0x4090380000
efuse=0x0
DieId=7
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
[IMU][DEBUG]:  Restore sram data...
osAppInit
recvSerdesCfg[0][0]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][1]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][2]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][3]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][4]serdesMode = 3, bandWidth = 4, GenSpeed = 2, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][5]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][6]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[7] bandWidth is X16!
recvSerdesCfg[0][7]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[8] bandWidth is X16!
recvSerdesCfg[0][8]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][9]serdesMode = 1, bandWidth = 3, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[10] bandWidth is X16!
recvSerdesCfg[0][10]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][0]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][1]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][2]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][3]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][4]serdesMode = 1, bandWidth = 3, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][5]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][6]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[7] bandWidth is X16!
recvSerdesCfg[1][7]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[8] bandWidth is X16!
recvSerdesCfg[1][8]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][9]serdesMode = 4, bandWidth = 4, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[10] bandWidth is X16!
recvSerdesCfg[1][10]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
SerdesDataStruct size = 7
[TianChiGetNicTypeFromCpld][241L] ExecuteCPLDSmcCmd:5
[SetTianChiNicType] Nic 0 Type: 0x0
[TianChiGetNicTypeFromCpld][241L] ExecuteCPLDSmcCmd:5
[SetTianChiNicType] Nic 1 Type: 0x0
[3.510]Normal version.
[InterruptRegister]:[395L]id = 65
[SIWInterruptInit]:[151L]id:65, init done!
[InterruptRegister]:[395L]id = 67
[InterruptRegister]:[395L]id = 69
[IpmbInterruptInit]:[262L]id:69
[InterruptRegister]:[395L]id = 71
[Scmi0InterruptInit]:[25L]id:71, init done!
[InterruptRegister]:[395L]id = 72
[Scmi1InterruptInit]:[38L]id:72, init done!
[InterruptRegister]:[395L]id = 76
[InterruptRegister]:[395L]id = 78
[TotemResetInit]:[70L]id:78, init done!
[InterruptRegister]:[395L]id = 83
[InterruptRegister]:[395L]id = 275
[InterruptRegister]:[395L]id = 299
[InterruptRegister]:[395L]id = 116
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x0 Clear done
[InterruptRegister]:[395L]id = 117
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x0 Clear done
[InterruptRegister]:[395L]id = 134
[InterruptRegister]:[395L]id = 96
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x8000000 Clear done
[InterruptRegister]:[395L]id = 97
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x8000000 Clear done
[InterruptRegister]:[395L]id = 114
[InterruptRegister]:[395L]id = 256
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt0RasIntClear]:[259L]nimbusBase 0x0 clear done
[InterruptRegister]:[395L]id = 257
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt1RasIntClear]:[529L]nimbusBase 0x0 Clear done
[InterruptRegister]:[395L]id = 258
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt2RasIntClear]:[638L]nimbusBase 0x0 Clear done
[InterruptRegister]:[395L]id = 259
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusHacRasIntClear]:[311L]NimbusHacRasIntClear done
[InterruptRegister]:[395L]id = 260
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusNicRasIntClear]:[466L]nimbusBase 0x0 Clear done
[InterruptRegister]:[395L]id = 261
[NimbusPCIeRasIntClear]:[662L]NimbusBase 0x0 Clear Start...
[NimbusPCIeRasIntClear]:[673L]NimbusBase 0x0 Clear done!
[InterruptRegister]:[395L]id = 156
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 157
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 174
[InterruptRegister]:[395L]id = 136
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x4008000000 Clear done
[InterruptRegister]:[395L]id = 137
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x4008000000 Clear done
[InterruptRegister]:[395L]id = 154
[InterruptRegister]:[395L]id = 280
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt0RasIntClear]:[259L]nimbusBase 0x4000000000 clear done
[InterruptRegister]:[395L]id = 281
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt1RasIntClear]:[529L]nimbusBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 282
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt2RasIntClear]:[638L]nimbusBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 283
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusHacRasIntClear]:[311L]NimbusHacRasIntClear done
[InterruptRegister]:[395L]id = 284
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusNicRasIntClear]:[466L]nimbusBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 285
[NimbusPCIeRasIntClear]:[662L]NimbusBase 0x4000000000 Clear Start...
[NimbusPCIeRasIntClear]:[673L]NimbusBase 0x4000000000 Clear done!
Cer Initialization start...
[IMU][DEBUG]:  CER_CFG_BD_ENDIAN_ADDR is 0x3
[IMU][DEBUG]:  OUT STANDING is 0x4040
[IMU][DEBUG]:  OUT STANDING after set is 0x140
Cer Initialization done.
[IMU] I2C Initialization start...
[IMU] I2cDealNimbusException secket:0
[IMU] Set I2C4 ----> IPMB mode(default), Set I2C5 ----> I2C mode Success.
[IMU][DEBUG]:  Start init I2C on Address: [0x210050000].
[IMU][DEBUG]:  I2C on Address: [0x210050000] init Succed.
[IMU] Set I2C5 to NORMAL mode.
[IMU] I2C Initialization done!
[IMU] Scmi channels Initialization done!
SIW Initialization Starting...

Enable SIW Debug interface ...
[IMU][DEBUG]:  ES.IMU.SIW.006 SC_SIW_STAT register value is 0x8000.
SIW bypass disabled.
SIW Initialization Done.

[IMU] MiscConfig Start.
[IMU][DEBUG]:  DDRC_CFG_STADAT before config 0x0.
[IMU][DEBUG]:  DDRC_CFG_STADAT after config 0x40000000.
[IMU] Misc Config Done.
[IMU] Gpio MUX Config Done.
[IMU] N_CATERR Gpio MUX Config Done.
[IMU][DEBUG]:  CPU_cluster 0x5a00 is 0xff, hotreset is 0x0
TotemPll0InitCs nodeId:3
TotemPll0InitCs nodeId:1
SllcSetBand isHigh:1
SpiTpmRead ret: 0x0, detect = 0x0
SpiTpmRead ret: 0x0, didVid = 0x0
[IMU][ERROR]:  TPM is not detected
[IMU][ERROR]:  Tpm init err, 0x1
[IMU][DEBUG]:  Offset 0x800000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
 IMU compilation script 
IMU start to measure sec.
[IMU][ERROR]:  Unsupported trusted module
TPM Measure UEFI SEC fail, 0x1
[IMU][DEBUG]:  Offset 0x400000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
[IMU][DEBUG]:  Offset 0x90000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
It's not secure boot
TotemPll0DeInitCs nodeId:1
TotemPll0DeInitCs nodeId:3
SllcSetBand isHigh:0
base: 0x98200000
Ap is booting up, status: 0xee
[IMU][DEBUG]:  Offset 0x890000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
IMU start to measure Fvmain_compact and TF.
[IMU][ERROR]:  Unsupported trusted module
TPM Measure Uefi and TF fail, 0x1
IMU start to measure certificate and HD.
[IMU][ERROR]:  Unsupported trusted module
TPM Measure Certificate and HD fail, 0x1
[SetSkipTrainingFlag]21007f024:1620a5a2
[IMU] Watchdog Initialization done!
cpu 0 entering scheduler
[IMU] Chip: 0 Totem-B Fabric sub T-sensor setup ok!
[IMU] Chip: 0 Totem-B Sys sub T-sensor setup ok!
[IMU] Chip: 0 Totem-A Fabric sub T-sensor setup ok!
[IMU] Chip: 0 Totem-A Sys T-sensor setup ok!
[IMU] Chip: 0 Nimbus T-sensor setup ok!
IPMB initialization Start...
IPMB module clock set done.
IPMB Rx FIFO clear empty.
IPMB initialization Done.
[GetInitSendNumber]:[2142]semaphore create init number = 0!
cfg=110005 g_mctpCount=4
mctp_dev[0] enable=1 mode=1
mctp_dev[1] enable=0 mode=0
mctp_dev[2] enable=1 mode=1
mctp_dev[3] enable=0 mode=0
mctp_loop_task Create Success
HardWare Send IPMI Errorr regValue = 0x8 !!!!
Send process recive sto !!!!

[extInt0Init]:[65L]

[extInt0Init]:[69L]
Core Number: 0x40
Enable scmi int done
mctp loop task start.
Ras Handle task start.
[IpmiMsgGetManufactureid][135]Gotted ManufactureId:db 07 00
pwr cap[0]: 0, 63
pwr cap[1]: f, 27
SetupCfg  :
EnFdmSupport:            0x1
DdrRefreshRate:          0x0
PowerESaving:            0x0
HotPlug:                 0x1
ProcessorFlexibleRatio:  0x1a
CoreIsolateOnlineFlag:   0x0
EnRasSupport:            0x1
AdvanceDeviceCorrection: 0x0
PatrolScrubDuration:     0x18
X8MisCorrEn:             0x0
PowerOnTime:             0xa
DimmTime:                0xa
PageIsolation:           0x0
Mem2BitErrCorrEn:        0x1
pwr cap[2]: 1, 3
[24.866]Real time now:  2026/04/29, 20:08:41
[24.868]InitialCntTime = 24
[24.985][IMU] System DDR Init Done!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x56 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x56 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x56 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x56 DRAM Width failed
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntInit done
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntInit done
[NimbusMgmt0IntInit]:[233L]NimbusMgmt0IntInit done
[NimbusMgmt1IntInit]:[499L]
[NimbusMgmt2IntInit]:[626L]NimbusMgmt2IntInit done
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntInit done
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntInit done
[NimbusMgmt0IntInit]:[233L]NimbusMgmt0IntInit done
[NimbusMgmt1IntInit]:[499L]
[NimbusMgmt2IntInit]:[626L]NimbusMgmt2IntInit done
[IMU][DEBUG]:  Offset 0x400000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
CppcShareMem: 0x44000000
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
[IMU][DEBUG]:  Offset 0xfc0000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
registry filesize:0x31cb

[IMU][DEBUG]:  Offset 0xfd8000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEB[IMU][ERROR]:UG]:  CS is 0x0
[IMU][  The response code is DEBUG]:  [SfcCmdRead][1abnormal 0xd6.
580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
version:
Welcome to the IMU Firmware!
IMU Firmware version 6.65.0
LiteOS version 5.0.0
[IMU][ERROR]:  IMU reset 0
[2.248]IMU System Timer setup OK!
[2.251][IMU] lbc Config Done.
[2.256]CpuType: 0
[2.256]IsHi1620S: 0
BoardType: 0xffffffff
[2.261]base: 0x90b00000
GetV167Flag = 0x0
SFC Initialization Start...
[GetDeviceId]:[384L]SFC Cs 0 detected ID[0x1860c8]!
[GetDeviceId]:[384L]SFC Cs 1 detected ID[0x0]!
[IMU][ERROR]:  [CollectSpiFlash]:[411] Don't support the flash, Cs[1] ID[0x0]!!
System supported 1 Flash.
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1811] Spi Cs 0
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1823] Before config value 0x80800300
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1831] After config value 0x80800300
SFC Initialization Done
It is NS boot!!!
boot from L2!!!
[2.307]reboot time:0
[CheckAllTrainingStatus]:[1495L] Idx0 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx1 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx2 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx3 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx4 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx5 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx6 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx7 HllcIdx0 read: 30000f 
when compile IMU, have to use parameter 'bit', 1024[2.356][CheckAllTrainingStatus]Chip:0
[CheckAllTrainingStatus]:[1495L] Idx0 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx1 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx2 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx3 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx4 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx5 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx6 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx7 HllcIdx0 read: 30000f 
when compile IMU, have to use parameter 'bit', 2048[2.407][CheckAllTrainingStatus]Chip:1
[2.411]ChipNum: 2
TotemNum: 4
NimbusNum: 2
[0]1.
[1]3.
[2]5.
[3]7.
[IMU][DEBUG]:  Back sram data...
Socket=2
dieId=0x1
EfuseBase=0x98380000
efuse=0x0
DieId=1
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x3
EfuseBase=0x90380000
efuse=0x0
DieId=3
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x5
EfuseBase=0x4098380000
efuse=0x0
DieId=5
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x7
EfuseBase=0x4090380000
efuse=0x0
DieId=7
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
[IMU][DEBUG]:  Restore sram data...
osAppInit
recvSerdesCfg[0][0]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][1]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][2]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][3]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][4]serdesMode = 3, bandWidth = 4, GenSpeed = 2, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][5]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][6]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[7] bandWidth is X16!
recvSerdesCfg[0][7]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[8] bandWidth is X16!
recvSerdesCfg[0][8]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][9]serdesMode = 1, bandWidth = 3, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[10] bandWidth is X16!
recvSerdesCfg[0][10]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][0]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][1]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][2]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][3]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][4]serdesMode = 1, bandWidth = 3, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][5]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][6]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[7] bandWidth is X16!
recvSerdesCfg[1][7]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[8] bandWidth is X16!
recvSerdesCfg[1][8]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][9]serdesMode = 4, bandWidth = 4, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[10] bandWidth is X16!
recvSerdesCfg[1][10]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
SerdesDataStruct size = 7
[TianChiGetNicTypeFromCpld][241L] ExecuteCPLDSmcCmd:5
[SetTianChiNicType] Nic 0 Type: 0x0
[TianChiGetNicTypeFromCpld][241L] ExecuteCPLDSmcCmd:5
[SetTianChiNicType] Nic 1 Type: 0x0
[3.510]Normal version.
[InterruptRegister]:[395L]id = 65
[SIWInterruptInit]:[151L]id:65, init done!
[InterruptRegister]:[395L]id = 67
[InterruptRegister]:[395L]id = 69
[IpmbInterruptInit]:[262L]id:69
[InterruptRegister]:[395L]id = 71
[Scmi0InterruptInit]:[25L]id:71, init done!
[InterruptRegister]:[395L]id = 72
[Scmi1InterruptInit]:[38L]id:72, init done!
[InterruptRegister]:[395L]id = 76
[InterruptRegister]:[395L]id = 78
[TotemResetInit]:[70L]id:78, init done!
[InterruptRegister]:[395L]id = 83
[InterruptRegister]:[395L]id = 275
[InterruptRegister]:[395L]id = 299
[InterruptRegister]:[395L]id = 116
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x0 Clear done
[InterruptRegister]:[395L]id = 117
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x0 Clear done
[InterruptRegister]:[395L]id = 134
[InterruptRegister]:[395L]id = 96
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x8000000 Clear done
[InterruptRegister]:[395L]id = 97
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x8000000 Clear done
[InterruptRegister]:[395L]id = 114
[InterruptRegister]:[395L]id = 256
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt0RasIntClear]:[259L]nimbusBase 0x0 clear done
[InterruptRegister]:[395L]id = 257
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt1RasIntClear]:[529L]nimbusBase 0x0 Clear done
[InterruptRegister]:[395L]id = 258
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt2RasIntClear]:[638L]nimbusBase 0x0 Clear done
[InterruptRegister]:[395L]id = 259
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusHacRasIntClear]:[311L]NimbusHacRasIntClear done
[InterruptRegister]:[395L]id = 260
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusNicRasIntClear]:[466L]nimbusBase 0x0 Clear done
[InterruptRegister]:[395L]id = 261
[NimbusPCIeRasIntClear]:[662L]NimbusBase 0x0 Clear Start...
[NimbusPCIeRasIntClear]:[673L]NimbusBase 0x0 Clear done!
[InterruptRegister]:[395L]id = 156
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 157
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 174
[InterruptRegister]:[395L]id = 136
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x4008000000 Clear done
[InterruptRegister]:[395L]id = 137
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x4008000000 Clear done
[InterruptRegister]:[395L]id = 154
[InterruptRegister]:[395L]id = 280
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt0RasIntClear]:[259L]nimbusBase 0x4000000000 clear done
[InterruptRegister]:[395L]id = 281
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt1RasIntClear]:[529L]nimbusBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 282
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt2RasIntClear]:[638L]nimbusBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 283
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusHacRasIntClear]:[311L]NimbusHacRasIntClear done
[InterruptRegister]:[395L]id = 284
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusNicRasIntClear]:[466L]nimbusBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 285
[NimbusPCIeRasIntClear]:[662L]NimbusBase 0x4000000000 Clear Start...
[NimbusPCIeRasIntClear]:[673L]NimbusBase 0x4000000000 Clear done!
Cer Initialization start...
[IMU][DEBUG]:  CER_CFG_BD_ENDIAN_ADDR is 0x3
[IMU][DEBUG]:  OUT STANDING is 0x4040
[IMU][DEBUG]:  OUT STANDING after set is 0x140
Cer Initialization done.
[IMU] I2C Initialization start...
[IMU] I2cDealNimbusException secket:0
[IMU] Set I2C4 ----> IPMB mode(default), Set I2C5 ----> I2C mode Success.
[IMU][DEBUG]:  Start init I2C on Address: [0x210050000].
[IMU][DEBUG]:  I2C on Address: [0x210050000] init Succed.
[IMU] Set I2C5 to NORMAL mode.
[IMU] I2C Initialization done!
[IMU] Scmi channels Initialization done!
SIW Initialization Starting...

Enable SIW Debug interface ...
[IMU][DEBUG]:  ES.IMU.SIW.006 SC_SIW_STAT register value is 0x8000.
SIW bypass disabled.
SIW Initialization Done.

[IMU] MiscConfig Start.
[IMU][DEBUG]:  DDRC_CFG_STADAT before config 0x0.
[IMU][DEBUG]:  DDRC_CFG_STADAT after config 0x40000000.
[IMU] Misc Config Done.
[IMU] Gpio MUX Config Done.
[IMU] N_CATERR Gpio MUX Config Done.
[IMU][DEBUG]:  CPU_cluster 0x5a00 is 0xff, hotreset is 0x0
TotemPll0InitCs nodeId:3
TotemPll0InitCs nodeId:1
SllcSetBand isHigh:1
SpiTpmRead ret: 0x0, detect = 0x0
SpiTpmRead ret: 0x0, didVid = 0x0
[IMU][ERROR]:  TPM is not detected
[IMU][ERROR]:  Tpm init err, 0x1
[IMU][DEBUG]:  Offset 0x800000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
 IMU compilation script 
IMU start to measure sec.
[IMU][ERROR]:  Unsupported trusted module
TPM Measure UEFI SEC fail, 0x1
[IMU][DEBUG]:  Offset 0x400000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
[IMU][DEBUG]:  Offset 0x90000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
It's not secure boot
TotemPll0DeInitCs nodeId:1
TotemPll0DeInitCs nodeId:3
SllcSetBand isHigh:0
base: 0x98200000
Ap is booting up, status: 0xee
[IMU][DEBUG]:  Offset 0x890000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
IMU start to measure Fvmain_compact and TF.
[IMU][ERROR]:  Unsupported trusted module
TPM Measure Uefi and TF fail, 0x1
IMU start to measure certificate and HD.
[IMU][ERROR]:  Unsupported trusted module
TPM Measure Certificate and HD fail, 0x1
[SetSkipTrainingFlag]21007f024:1620a5a2
[IMU] Watchdog Initialization done!
cpu 0 entering scheduler
[IMU] Chip: 0 Totem-B Fabric sub T-sensor setup ok!
[IMU] Chip: 0 Totem-B Sys sub T-sensor setup ok!
[IMU] Chip: 0 Totem-A Fabric sub T-sensor setup ok!
[IMU] Chip: 0 Totem-A Sys T-sensor setup ok!
[IMU] Chip: 0 Nimbus T-sensor setup ok!
IPMB initialization Start...
IPMB module clock set done.
IPMB Rx FIFO clear empty.
IPMB initialization Done.
[GetInitSendNumber]:[2142]semaphore create init number = 0!
cfg=110005 g_mctpCount=4
mctp_dev[0] enable=1 mode=1
mctp_dev[1] enable=0 mode=0
mctp_dev[2] enable=1 mode=1
mctp_dev[3] enable=0 mode=0
mctp_loop_task Create Success
HardWare Send IPMI Errorr regValue = 0x8 !!!!
Send process recive sto !!!!

[extInt0Init]:[65L]

[extInt0Init]:[69L]
Core Number: 0x40
Enable scmi int done
mctp loop task start.
Ras Handle task start.
[IpmiMsgGetManufactureid][135]Gotted ManufactureId:db 07 00
pwr cap[0]: 0, 63
pwr cap[1]: f, 27
SetupCfg  :
EnFdmSupport:            0x1
DdrRefreshRate:          0x0
PowerESaving:            0x0
HotPlug:                 0x1
ProcessorFlexibleRatio:  0x1a
CoreIsolateOnlineFlag:   0x0
EnRasSupport:            0x1
AdvanceDeviceCorrection: 0x0
PatrolScrubDuration:     0x18
X8MisCorrEn:             0x0
PowerOnTime:             0xa
DimmTime:                0xa
PageIsolation:           0x0
Mem2BitErrCorrEn:        0x1
pwr cap[2]: 1, 3
[24.876]Real time now:  2026/04/29, 20:13:50
[24.877]InitialCntTime = 24
[24.990][IMU] System DDR Init Done!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x56 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x56 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x56 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x56 DRAM Width failed
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntInit done
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntInit done
[NimbusMgmt0IntInit]:[233L]NimbusMgmt0IntInit done
[NimbusMgmt1IntInit]:[499L]
[NimbusMgmt2IntInit]:[626L]NimbusMgmt2IntInit done
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntInit done
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntInit done
[NimbusMgmt0IntInit]:[233L]NimbusMgmt0IntInit done
[NimbusMgmt1IntInit]:[499L]
[NimbusMgmt2IntInit]:[626L]NimbusMgmt2IntInit done
[IMU][DEBUG]:  Offset 0x400000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
CppcShareMem: 0x44000000
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
[IMU][DEBUG]:  Offset 0xfc0000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
registry filesize:0x31cb

[IMU][DEBUG]:  Offset 0xfd8000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
version:[IMU][ERROR]:  The response code is abnormal 0xd6.

Welcome to the IMU Firmware!
IMU Firmware version 6.65.0
LiteOS version 5.0.0
[IMU][ERROR]:  IMU reset 0
[2.248]IMU System Timer setup OK!
[2.251][IMU] lbc Config Done.
[2.256]CpuType: 0
[2.256]IsHi1620S: 0
BoardType: 0xffffffff
[2.261]base: 0x90b00000
GetV167Flag = 0x0
SFC Initialization Start...
[GetDeviceId]:[384L]SFC Cs 0 detected ID[0x1860c8]!
[GetDeviceId]:[384L]SFC Cs 1 detected ID[0x0]!
[IMU][ERROR]:  [CollectSpiFlash]:[411] Don't support the flash, Cs[1] ID[0x0]!!
System supported 1 Flash.
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1811] Spi Cs 0
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1823] Before config value 0x80800300
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1831] After config value 0x80800300
SFC Initialization Done
It is NS boot!!!
boot from L2!!!
[2.307]reboot time:0
[CheckAllTrainingStatus]:[1495L] Idx0 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx1 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx2 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx3 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx4 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx5 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx6 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx7 HllcIdx0 read: 30000f 
when compile IMU, have to use parameter 'bit', 1024[2.356][CheckAllTrainingStatus]Chip:0
[CheckAllTrainingStatus]:[1495L] Idx0 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx1 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx2 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx3 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx4 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx5 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx6 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx7 HllcIdx0 read: 30000f 
when compile IMU, have to use parameter 'bit', 2048[2.407][CheckAllTrainingStatus]Chip:1
[2.411]ChipNum: 2
TotemNum: 4
NimbusNum: 2
[0]1.
[1]3.
[2]5.
[3]7.
[IMU][DEBUG]:  Back sram data...
Socket=2
dieId=0x1
EfuseBase=0x98380000
efuse=0x0
DieId=1
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x3
EfuseBase=0x90380000
efuse=0x0
DieId=3
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x5
EfuseBase=0x4098380000
efuse=0x0
DieId=5
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x7
EfuseBase=0x4090380000
efuse=0x0
DieId=7
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
[IMU][DEBUG]:  Restore sram data...
osAppInit
recvSerdesCfg[0][0]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][1]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][2]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][3]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][4]serdesMode = 3, bandWidth = 4, GenSpeed = 2, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][5]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][6]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[7] bandWidth is X16!
recvSerdesCfg[0][7]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[8] bandWidth is X16!
recvSerdesCfg[0][8]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][9]serdesMode = 1, bandWidth = 3, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[10] bandWidth is X16!
recvSerdesCfg[0][10]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][0]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][1]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][2]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][3]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][4]serdesMode = 1, bandWidth = 3, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][5]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][6]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[7] bandWidth is X16!
recvSerdesCfg[1][7]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[8] bandWidth is X16!
recvSerdesCfg[1][8]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][9]serdesMode = 4, bandWidth = 4, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[10] bandWidth is X16!
recvSerdesCfg[1][10]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
SerdesDataStruct size = 7
[TianChiGetNicTypeFromCpld][241L] ExecuteCPLDSmcCmd:5
[SetTianChiNicType] Nic 0 Type: 0x0
[TianChiGetNicTypeFromCpld][241L] ExecuteCPLDSmcCmd:5
[SetTianChiNicType] Nic 1 Type: 0x0
[3.511]Normal version.
[InterruptRegister]:[395L]id = 65
[SIWInterruptInit]:[151L]id:65, init done!
[InterruptRegister]:[395L]id = 67
[InterruptRegister]:[395L]id = 69
[IpmbInterruptInit]:[262L]id:69
[InterruptRegister]:[395L]id = 71
[Scmi0InterruptInit]:[25L]id:71, init done!
[InterruptRegister]:[395L]id = 72
[Scmi1InterruptInit]:[38L]id:72, init done!
[InterruptRegister]:[395L]id = 76
[InterruptRegister]:[395L]id = 78
[TotemResetInit]:[70L]id:78, init done!
[InterruptRegister]:[395L]id = 83
[InterruptRegister]:[395L]id = 275
[InterruptRegister]:[395L]id = 299
[InterruptRegister]:[395L]id = 116
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x0 Clear done
[InterruptRegister]:[395L]id = 117
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x0 Clear done
[InterruptRegister]:[395L]id = 134
[InterruptRegister]:[395L]id = 96
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x8000000 Clear done
[InterruptRegister]:[395L]id = 97
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x8000000 Clear done
[InterruptRegister]:[395L]id = 114
[InterruptRegister]:[395L]id = 256
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt0RasIntClear]:[259L]nimbusBase 0x0 clear done
[InterruptRegister]:[395L]id = 257
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt1RasIntClear]:[529L]nimbusBase 0x0 Clear done
[InterruptRegister]:[395L]id = 258
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt2RasIntClear]:[638L]nimbusBase 0x0 Clear done
[InterruptRegister]:[395L]id = 259
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusHacRasIntClear]:[311L]NimbusHacRasIntClear done
[InterruptRegister]:[395L]id = 260
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusNicRasIntClear]:[466L]nimbusBase 0x0 Clear done
[InterruptRegister]:[395L]id = 261
[NimbusPCIeRasIntClear]:[662L]NimbusBase 0x0 Clear Start...
[NimbusPCIeRasIntClear]:[673L]NimbusBase 0x0 Clear done!
[InterruptRegister]:[395L]id = 156
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 157
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 174
[InterruptRegister]:[395L]id = 136
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x4008000000 Clear done
[InterruptRegister]:[395L]id = 137
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x4008000000 Clear done
[InterruptRegister]:[395L]id = 154
[InterruptRegister]:[395L]id = 280
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt0RasIntClear]:[259L]nimbusBase 0x4000000000 clear done
[InterruptRegister]:[395L]id = 281
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt1RasIntClear]:[529L]nimbusBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 282
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt2RasIntClear]:[638L]nimbusBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 283
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusHacRasIntClear]:[311L]NimbusHacRasIntClear done
[InterruptRegister]:[395L]id = 284
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusNicRasIntClear]:[466L]nimbusBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 285
[NimbusPCIeRasIntClear]:[662L]NimbusBase 0x4000000000 Clear Start...
[NimbusPCIeRasIntClear]:[673L]NimbusBase 0x4000000000 Clear done!
Cer Initialization start...
[IMU][DEBUG]:  CER_CFG_BD_ENDIAN_ADDR is 0x3
[IMU][DEBUG]:  OUT STANDING is 0x4040
[IMU][DEBUG]:  OUT STANDING after set is 0x140
Cer Initialization done.
[IMU] I2C Initialization start...
[IMU] I2cDealNimbusException secket:0
[IMU] Set I2C4 ----> IPMB mode(default), Set I2C5 ----> I2C mode Success.
[IMU][DEBUG]:  Start init I2C on Address: [0x210050000].
[IMU][DEBUG]:  I2C on Address: [0x210050000] init Succed.
[IMU] Set I2C5 to NORMAL mode.
[IMU] I2C Initialization done!
[IMU] Scmi channels Initialization done!
SIW Initialization Starting...

Enable SIW Debug interface ...
[IMU][DEBUG]:  ES.IMU.SIW.006 SC_SIW_STAT register value is 0x8000.
SIW bypass disabled.
SIW Initialization Done.

[IMU] MiscConfig Start.
[IMU][DEBUG]:  DDRC_CFG_STADAT before config 0x0.
[IMU][DEBUG]:  DDRC_CFG_STADAT after config 0x40000000.
[IMU] Misc Config Done.
[IMU] Gpio MUX Config Done.
[IMU] N_CATERR Gpio MUX Config Done.
[IMU][DEBUG]:  CPU_cluster 0x5a00 is 0xff, hotreset is 0x0
TotemPll0InitCs nodeId:3
TotemPll0InitCs nodeId:1
SllcSetBand isHigh:1
SpiTpmRead ret: 0x0, detect = 0x0
SpiTpmRead ret: 0x0, didVid = 0x0
[IMU][ERROR]:  TPM is not detected
[IMU][ERROR]:  Tpm init err, 0x1
[IMU][DEBUG]:  Offset 0x800000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
 IMU compilation script 
IMU start to measure sec.
[IMU][ERROR]:  Unsupported trusted module
TPM Measure UEFI SEC fail, 0x1
[IMU][DEBUG]:  Offset 0x400000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
[IMU][DEBUG]:  Offset 0x90000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
It's not secure boot
TotemPll0DeInitCs nodeId:1
TotemPll0DeInitCs nodeId:3
SllcSetBand isHigh:0
base: 0x98200000
Ap is booting up, status: 0xee
[IMU][DEBUG]:  Offset 0x890000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
IMU start to measure Fvmain_compact and TF.
[IMU][ERROR]:  Unsupported trusted module
TPM Measure Uefi and TF fail, 0x1
IMU start to measure certificate and HD.
[IMU][ERROR]:  Unsupported trusted module
TPM Measure Certificate and HD fail, 0x1
[SetSkipTrainingFlag]21007f024:1620a5a2
[IMU] Watchdog Initialization done!
cpu 0 entering scheduler
[IMU] Chip: 0 Totem-B Fabric sub T-sensor setup ok!
[IMU] Chip: 0 Totem-B Sys sub T-sensor setup ok!
[IMU] Chip: 0 Totem-A Fabric sub T-sensor setup ok!
[IMU] Chip: 0 Totem-A Sys T-sensor setup ok!
[IMU] Chip: 0 Nimbus T-sensor setup ok!
IPMB initialization Start...
IPMB module clock set done.
IPMB Rx FIFO clear empty.
IPMB initialization Done.
[GetInitSendNumber]:[2142]semaphore create init number = 0!
cfg=110005 g_mctpCount=4
mctp_dev[0] enable=1 mode=1
mctp_dev[1] enable=0 mode=0
mctp_dev[2] enable=1 mode=1
mctp_dev[3] enable=0 mode=0
mctp_loop_task Create Success
HardWare Send IPMI Errorr regValue = 0x8 !!!!
Send process recive sto !!!!

[extInt0Init]:[65L]

[extInt0Init]:[69L]
Core Number: 0x40
Enable scmi int done
mctp loop task start.
Ras Handle task start.
[IpmiMsgGetManufactureid][135]Gotted ManufactureId:db 07 00
pwr cap[0]: 0, 63
pwr cap[1]: f, 27
SetupCfg  :
EnFdmSupport:            0x1
DdrRefreshRate:          0x0
PowerESaving:            0x0
HotPlug:                 0x1
ProcessorFlexibleRatio:  0x1a
CoreIsolateOnlineFlag:   0x0
EnRasSupport:            0x1
AdvanceDeviceCorrection: 0x0
PatrolScrubDuration:     0x18
X8MisCorrEn:             0x0
PowerOnTime:             0xa
DimmTime:                0xa
PageIsolation:           0x0
Mem2BitErrCorrEn:        0x1
pwr cap[2]: 1, 3
[24.986]Real time now:  2026/04/29, 20:19:10
[24.987]InitialCntTime = 24
[25.099][IMU] System DDR Init Done!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[284L]I2C operation abort, there is no ack returned!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x56 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x56 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[284L]I2C operation abort, there is no ack returned!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x56 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x56 DRAM Width failed
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntInit done
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntInit done
[NimbusMgmt0IntInit]:[233L]NimbusMgmt0IntInit done
[NimbusMgmt1IntInit]:[499L]
[NimbusMgmt2IntInit]:[626L]NimbusMgmt2IntInit done
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntInit done
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntInit done
[NimbusMgmt0IntInit]:[233L]NimbusMgmt0IntInit done
[NimbusMgmt1IntInit]:[499L]
[NimbusMgmt2IntInit]:[626L]NimbusMgmt2IntInit done
[IMU][DEBUG]:  Offset 0x400000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
[IMU][DEBUG]:  Offset 0xfc0000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
registry filesize:0x31cb

[IMU][DEBUG]:  Offset 0xfd8000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
version:[IMU][ERROR]:  The response code is abnormal 0xd6.

Welcome to the IMU Firmware!
IMU Firmware version 6.65.0
LiteOS version 5.0.0
[IMU][ERROR]:  IMU reset 0
[2.248]IMU System Timer setup OK!
[2.251][IMU] lbc Config Done.
[2.256]CpuType: 0
[2.256]IsHi1620S: 0
BoardType: 0xffffffff
[2.261]base: 0x90b00000
GetV167Flag = 0x0
SFC Initialization Start...
[GetDeviceId]:[384L]SFC Cs 0 detected ID[0x1860c8]!
[GetDeviceId]:[384L]SFC Cs 1 detected ID[0x0]!
[IMU][ERROR]:  [CollectSpiFlash]:[411] Don't support the flash, Cs[1] ID[0x0]!!
System supported 1 Flash.
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1811] Spi Cs 0
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1823] Before config value 0x80800300
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1831] After config value 0x80800300
SFC Initialization Done
It is NS boot!!!
boot from L2!!!
[2.307]reboot time:0
[CheckAllTrainingStatus]:[1495L] Idx0 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx1 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx2 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx3 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx4 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx5 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx6 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx7 HllcIdx0 read: 30000f 
when compile IMU, have to use parameter 'bit', 1024[2.356][CheckAllTrainingStatus]Chip:0
[CheckAllTrainingStatus]:[1495L] Idx0 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx1 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx2 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx3 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx4 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx5 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx6 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx7 HllcIdx0 read: 30000f 
when compile IMU, have to use parameter 'bit', 2048[2.407][CheckAllTrainingStatus]Chip:1
[2.411]ChipNum: 2
TotemNum: 4
NimbusNum: 2
[0]1.
[1]3.
[2]5.
[3]7.
[IMU][DEBUG]:  Back sram data...
Socket=2
dieId=0x1
EfuseBase=0x98380000
efuse=0x0
DieId=1
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x3
EfuseBase=0x90380000
efuse=0x0
DieId=3
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x5
EfuseBase=0x4098380000
efuse=0x0
DieId=5
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x7
EfuseBase=0x4090380000
efuse=0x0
DieId=7
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
[IMU][DEBUG]:  Restore sram data...
osAppInit
recvSerdesCfg[0][0]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][1]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][2]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][3]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][4]serdesMode = 3, bandWidth = 4, GenSpeed = 2, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][5]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][6]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[7] bandWidth is X16!
recvSerdesCfg[0][7]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[8] bandWidth is X16!
recvSerdesCfg[0][8]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][9]serdesMode = 1, bandWidth = 3, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[10] bandWidth is X16!
recvSerdesCfg[0][10]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][0]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][1]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][2]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][3]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][4]serdesMode = 1, bandWidth = 3, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][5]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][6]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[7] bandWidth is X16!
recvSerdesCfg[1][7]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[8] bandWidth is X16!
recvSerdesCfg[1][8]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][9]serdesMode = 4, bandWidth = 4, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[10] bandWidth is X16!
recvSerdesCfg[1][10]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
SerdesDataStruct size = 7
[TianChiGetNicTypeFromCpld][241L] ExecuteCPLDSmcCmd:5
[SetTianChiNicType] Nic 0 Type: 0x0
[TianChiGetNicTypeFromCpld][241L] ExecuteCPLDSmcCmd:5
[SetTianChiNicType] Nic 1 Type: 0x0
[3.510]Normal version.
[InterruptRegister]:[395L]id = 65
[SIWInterruptInit]:[151L]id:65, init done!
[InterruptRegister]:[395L]id = 67
[InterruptRegister]:[395L]id = 69
[IpmbInterruptInit]:[262L]id:69
[InterruptRegister]:[395L]id = 71
[Scmi0InterruptInit]:[25L]id:71, init done!
[InterruptRegister]:[395L]id = 72
[Scmi1InterruptInit]:[38L]id:72, init done!
[InterruptRegister]:[395L]id = 76
[InterruptRegister]:[395L]id = 78
[TotemResetInit]:[70L]id:78, init done!
[InterruptRegister]:[395L]id = 83
[InterruptRegister]:[395L]id = 275
[InterruptRegister]:[395L]id = 299
[InterruptRegister]:[395L]id = 116
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x0 Clear done
[InterruptRegister]:[395L]id = 117
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x0 Clear done
[InterruptRegister]:[395L]id = 134
[InterruptRegister]:[395L]id = 96
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x8000000 Clear done
[InterruptRegister]:[395L]id = 97
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x8000000 Clear done
[InterruptRegister]:[395L]id = 114
[InterruptRegister]:[395L]id = 256
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt0RasIntClear]:[259L]nimbusBase 0x0 clear done
[InterruptRegister]:[395L]id = 257
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt1RasIntClear]:[529L]nimbusBase 0x0 Clear done
[InterruptRegister]:[395L]id = 258
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt2RasIntClear]:[638L]nimbusBase 0x0 Clear done
[InterruptRegister]:[395L]id = 259
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusHacRasIntClear]:[311L]NimbusHacRasIntClear done
[InterruptRegister]:[395L]id = 260
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusNicRasIntClear]:[466L]nimbusBase 0x0 Clear done
[InterruptRegister]:[395L]id = 261
[NimbusPCIeRasIntClear]:[662L]NimbusBase 0x0 Clear Start...
[NimbusPCIeRasIntClear]:[673L]NimbusBase 0x0 Clear done!
[InterruptRegister]:[395L]id = 156
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 157
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 174
[InterruptRegister]:[395L]id = 136
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x4008000000 Clear done
[InterruptRegister]:[395L]id = 137
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x4008000000 Clear done
[InterruptRegister]:[395L]id = 154
[InterruptRegister]:[395L]id = 280
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt0RasIntClear]:[259L]nimbusBase 0x4000000000 clear done
[InterruptRegister]:[395L]id = 281
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt1RasIntClear]:[529L]nimbusBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 282
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt2RasIntClear]:[638L]nimbusBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 283
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusHacRasIntClear]:[311L]NimbusHacRasIntClear done
[InterruptRegister]:[395L]id = 284
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusNicRasIntClear]:[466L]nimbusBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 285
[NimbusPCIeRasIntClear]:[662L]NimbusBase 0x4000000000 Clear Start...
[NimbusPCIeRasIntClear]:[673L]NimbusBase 0x4000000000 Clear done!
Cer Initialization start...
[IMU][DEBUG]:  CER_CFG_BD_ENDIAN_ADDR is 0x3
[IMU][DEBUG]:  OUT STANDING is 0x4040
[IMU][DEBUG]:  OUT STANDING after set is 0x140
Cer Initialization done.
[IMU] I2C Initialization start...
[IMU] I2cDealNimbusException secket:0
[IMU] Set I2C4 ----> IPMB mode(default), Set I2C5 ----> I2C mode Success.
[IMU][DEBUG]:  Start init I2C on Address: [0x210050000].
[IMU][DEBUG]:  I2C on Address: [0x210050000] init Succed.
[IMU] Set I2C5 to NORMAL mode.
[IMU] I2C Initialization done!
[IMU] Scmi channels Initialization done!
SIW Initialization Starting...

Enable SIW Debug interface ...
[IMU][DEBUG]:  ES.IMU.SIW.006 SC_SIW_STAT register value is 0x8000.
SIW bypass disabled.
SIW Initialization Done.

[IMU] MiscConfig Start.
[IMU][DEBUG]:  DDRC_CFG_STADAT before config 0x0.
[IMU][DEBUG]:  DDRC_CFG_STADAT after config 0x40000000.
[IMU] Misc Config Done.
[IMU] Gpio MUX Config Done.
[IMU] N_CATERR Gpio MUX Config Done.
[IMU][DEBUG]:  CPU_cluster 0x5a00 is 0xff, hotreset is 0x0
TotemPll0InitCs nodeId:3
TotemPll0InitCs nodeId:1
SllcSetBand isHigh:1
SpiTpmRead ret: 0x0, detect = 0x0
SpiTpmRead ret: 0x0, didVid = 0x0
[IMU][ERROR]:  TPM is not detected
[IMU][ERROR]:  Tpm init err, 0x1
[IMU][DEBUG]:  Offset 0x800000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
 IMU compilation script 
IMU start to measure sec.
[IMU][ERROR]:  Unsupported trusted module
TPM Measure UEFI SEC fail, 0x1
[IMU][DEBUG]:  Offset 0x400000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
[IMU][DEBUG]:  Offset 0x90000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
It's not secure boot
TotemPll0DeInitCs nodeId:1
TotemPll0DeInitCs nodeId:3
SllcSetBand isHigh:0
base: 0x98200000
Ap is booting up, status: 0xee
[IMU][DEBUG]:  Offset 0x890000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
IMU start to measure Fvmain_compact and TF.
[IMU][ERROR]:  Unsupported trusted module
TPM Measure Uefi and TF fail, 0x1
IMU start to measure certificate and HD.
[IMU][ERROR]:  Unsupported trusted module
TPM Measure Certificate and HD fail, 0x1
[SetSkipTrainingFlag]21007f024:1620a5a2
[IMU] Watchdog Initialization done!
cpu 0 entering scheduler
[IMU] Chip: 0 Totem-B Fabr
Welcome to the IMU Firmware!
IMU Firmware version 6.65.0
LiteOS version 5.0.0
[IMU][ERROR]:  IMU reset 0
[2.248]IMU System Timer setup OK!
[2.251][IMU] lbc Config Done.
[2.256]CpuType: 0
[2.256]IsHi1620S: 0
BoardType: 0xffffffff
[2.261]base: 0x90b00000
GetV167Flag = 0x0
SFC Initialization Start...
[GetDeviceId]:[384L]SFC Cs 0 detected ID[0x1860c8]!
[GetDeviceId]:[384L]SFC Cs 1 detected ID[0x0]!
[IMU][ERROR]:  [CollectSpiFlash]:[411] Don't support the flash, Cs[1] ID[0x0]!!
System supported 1 Flash.
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1811] Spi Cs 0
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1823] Before config value 0x80800300
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1831] After config value 0x80800300
SFC Initialization Done
It is NS boot!!!
boot from L2!!!
[2.307]reboot time:0
[CheckAllTrainingStatus]:[1495L] Idx0 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx1 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx2 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx3 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx4 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx5 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx6 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx7 HllcIdx0 read: 30000f 
when compile IMU, have to use parameter 'bit', 1024[2.356][CheckAllTrainingStatus]Chip:0
[CheckAllTrainingStatus]:[1495L] Idx0 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx1 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx2 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx3 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx4 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx5 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx6 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx7 HllcIdx0 read: 30000f 
when compile IMU, have to use parameter 'bit', 2048[2.407][CheckAllTrainingStatus]Chip:1
[2.411]ChipNum: 2
TotemNum: 4
NimbusNum: 2
[0]1.
[1]3.
[2]5.
[3]7.
[IMU][DEBUG]:  Back sram data...
Socket=2
dieId=0x1
EfuseBase=0x98380000
efuse=0x0
DieId=1
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x3
EfuseBase=0x90380000
efuse=0x0
DieId=3
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x5
EfuseBase=0x4098380000
efuse=0x0
DieId=5
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x7
EfuseBase=0x4090380000
efuse=0x0
DieId=7
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
[IMU][DEBUG]:  Restore sram data...
osAppInit
recvSerdesCfg[0][0]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][1]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][2]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][3]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][4]serdesMode = 3, bandWidth = 4, GenSpeed = 2, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][5]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][6]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[7] bandWidth is X16!
recvSerdesCfg[0][7]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[8] bandWidth is X16!
recvSerdesCfg[0][8]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][9]serdesMode = 1, bandWidth = 3, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[10] bandWidth is X16!
recvSerdesCfg[0][10]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][0]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][1]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][2]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][3]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][4]serdesMode = 1, bandWidth = 3, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][5]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][6]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[7] bandWidth is X16!
recvSerdesCfg[1][7]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[8] bandWidth is X16!
recvSerdesCfg[1][8]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][9]serdesMode = 4, bandWidth = 4, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[10] bandWidth is X16!
recvSerdesCfg[1][10]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
SerdesDataStruct size = 7
[TianChiGetNicTypeFromCpld][241L] ExecuteCPLDSmcCmd:5
[SetTianChiNicType] Nic 0 Type: 0x0
[TianChiGetNicTypeFromCpld][241L] ExecuteCPLDSmcCmd:5
[SetTianChiNicType] Nic 1 Type: 0x0
[3.511]Normal version.
[InterruptRegister]:[395L]id = 65
[SIWInterruptInit]:[151L]id:65, init done!
[InterruptRegister]:[395L]id = 67
[InterruptRegister]:[395L]id = 69
[IpmbInterruptInit]:[262L]id:69
[InterruptRegister]:[395L]id = 71
[Scmi0InterruptInit]:[25L]id:71, init done!
[InterruptRegister]:[395L]id = 72
[Scmi1InterruptInit]:[38L]id:72, init done!
[InterruptRegister]:[395L]id = 76
[InterruptRegister]:[395L]id = 78
[TotemResetInit]:[70L]id:78, init done!
[InterruptRegister]:[395L]id = 83
[InterruptRegister]:[395L]id = 275
[InterruptRegister]:[395L]id = 299
[InterruptRegister]:[395L]id = 116
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x0 Clear done
[InterruptRegister]:[395L]id = 117
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x0 Clear done
[InterruptRegister]:[395L]id = 134
[InterruptRegister]:[395L]id = 96
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x8000000 Clear done
[InterruptRegister]:[395L]id = 97
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x8000000 Clear done
[InterruptRegister]:[395L]id = 114
[InterruptRegister]:[395L]id = 256
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt0RasIntClear]:[259L]nimbusBase 0x0 clear done
[InterruptRegister]:[395L]id = 257
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt1RasIntClear]:[529L]nimbusBase 0x0 Clear done
[InterruptRegister]:[395L]id = 258
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt2RasIntClear]:[638L]nimbusBase 0x0 Clear done
[InterruptRegister]:[395L]id = 259
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusHacRasIntClear]:[311L]NimbusHacRasIntClear done
[InterruptRegister]:[395L]id = 260
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusNicRasIntClear]:[466L]nimbusBase 0x0 Clear done
[InterruptRegister]:[395L]id = 261
[NimbusPCIeRasIntClear]:[662L]NimbusBase 0x0 Clear Start...
[NimbusPCIeRasIntClear]:[673L]NimbusBase 0x0 Clear done!
[InterruptRegister]:[395L]id = 156
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 157
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 174
[InterruptRegister]:[395L]id = 136
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x4008000000 Clear done
[InterruptRegister]:[395L]id = 137
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x4008000000 Clear done
[InterruptRegister]:[395L]id = 154
[InterruptRegister]:[395L]id = 280
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt0RasIntClear]:[259L]nimbusBase 0x4000000000 clear done
[InterruptRegister]:[395L]id = 281
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt1RasIntClear]:[529L]nimbusBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 282
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt2RasIntClear]:[638L]nimbusBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 283
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusHacRasIntClear]:[311L]NimbusHacRasIntClear done
[InterruptRegister]:[395L]id = 284
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusNicRasIntClear]:[466L]nimbusBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 285
[NimbusPCIeRasIntClear]:[662L]NimbusBase 0x4000000000 Clear Start...
[NimbusPCIeRasIntClear]:[673L]NimbusBase 0x4000000000 Clear done!
Cer Initialization start...
[IMU][DEBUG]:  CER_CFG_BD_ENDIAN_ADDR is 0x3
[IMU][DEBUG]:  OUT STANDING is 0x4040
[IMU][DEBUG]:  OUT STANDING after set is 0x140
Cer Initialization done.
[IMU] I2C Initialization start...
[IMU] I2cDealNimbusException secket:0
[IMU] Set I2C4 ----> IPMB mode(default), Set I2C5 ----> I2C mode Success.
[IMU][DEBUG]:  Start init I2C on Address: [0x210050000].
[IMU][DEBUG]:  I2C on Address: [0x210050000] init Succed.
[IMU] Set I2C5 to NORMAL mode.
[IMU] I2C Initialization done!
[IMU] Scmi channels Initialization done!
SIW Initialization Starting...

Enable SIW Debug interface ...
[IMU][DEBUG]:  ES.IMU.SIW.006 SC_SIW_STAT register value is 0x8000.
SIW bypass disabled.
SIW Initialization Done.

[IMU] MiscConfig Start.
[IMU][DEBUG]:  DDRC_CFG_STADAT before config 0x0.
[IMU][DEBUG]:  DDRC_CFG_STADAT after config 0x40000000.
[IMU] Misc Config Done.
[IMU] Gpio MUX Config Done.
[IMU] N_CATERR Gpio MUX Config Done.
[IMU][DEBUG]:  CPU_cluster 0x5a00 is 0xff, hotreset is 0x0
TotemPll0InitCs nodeId:3
TotemPll0InitCs nodeId:1
SllcSetBand isHigh:1
SpiTpmRead ret: 0x0, detect = 0x0
SpiTpmRead ret: 0x0, didVid = 0x0
[IMU][ERROR]:  TPM is not detected
[IMU][ERROR]:  Tpm init err, 0x1
[IMU][DEBUG]:  Offset 0x800000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
 IMU compilation script 
IMU start to measure sec.
[IMU][ERROR]:  Unsupported trusted module
TPM Measure UEFI SEC fail, 0x1
[IMU][DEBUG]:  Offset 0x400000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
[IMU][DEBUG]:  Offset 0x90000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
It's not secure boot
TotemPll0DeInitCs nodeId:1
TotemPll0DeInitCs nodeId:3
SllcSetBand isHigh:0
base: 0x98200000
Ap is booting up, status: 0xee
[IMU][DEBUG]:  Offset 0x890000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
IMU start to measure Fvmain_compact and TF.
[IMU][ERROR]:  Unsupported trusted module
TPM Measure Uefi and TF fail, 0x1
IMU start to measure certificate and HD.
[IMU][ERROR]:  Unsupported trusted module
TPM Measure Certificate and HD fail, 0x1
[SetSkipTrainingFlag]21007f024:1620a5a2
[IMU] Watchdog Initialization done!
cpu 0 entering scheduler
[IMU] Chip: 0 Totem-B Fabric sub T-sensor setup ok!
[IMU] Chip: 0 Totem-B Sys sub T-sensor setup ok!
[IMU] Chip: 0 Totem-A Fabric sub T-sensor setup ok!
[IMU] Chip: 0 Totem-A Sys T-sensor setup ok!
[IMU] Chip: 0 Nimbus T-sensor setup ok!
IPMB initialization Start...
IPMB module clock set done.
IPMB Rx FIFO clear empty.
IPMB initialization Done.
[GetInitSendNumber]:[2142]semaphore create init number = 0!
cfg=110005 g_mctpCount=4
mctp_dev[0] enable=1 mode=1
mctp_dev[1] enable=0 mode=0
mctp_dev[2] enable=1 mode=1
mctp_dev[3] enable=0 mode=0
mctp_loop_task Create Success
HardWare Send IPMI Errorr regValue = 0x8 !!!!
Send process recive sto !!!!

[extInt0Init]:[65L]

[extInt0Init]:[69L]
Core Number: 0x40
Enable scmi int done
mctp loop task start.
Ras Handle task start.
[IpmiMsgGetManufactureid][135]Gotted ManufactureId:db 07 00
pwr cap[0]: 0, 63
pwr cap[1]: f, 27
SetupCfg  :
EnFdmSupport:            0x1
DdrRefreshRate:          0x0
PowerESaving:            0x0
HotPlug:                 0x1
ProcessorFlexibleRatio:  0x1a
CoreIsolateOnlineFlag:   0x0
EnRasSupport:            0x1
AdvanceDeviceCorrection: 0x0
PatrolScrubDuration:     0x18
X8MisCorrEn:             0x0
PowerOnTime:             0xa
DimmTime:                0xa
PageIsolation:           0x0
Mem2BitErrCorrEn:        0x1
pwr cap[2]: 1, 3
[24.903]Real time now:  2026/04/29, 20:29:28
[24.904]InitialCntTime = 24
[25.022][IMU] System DDR Init Done!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x56 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x56 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x56 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x56 DRAM Width failed
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntInit done
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntInit done
[NimbusMgmt0IntInit]:[233L]NimbusMgmt0IntInit done
[NimbusMgmt1IntInit]:[499L]
[NimbusMgmt2IntInit]:[626L]NimbusMgmt2IntInit done
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntInit done
[TotemRasIntCppcShareMem: 0x44000000
Init]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntInit done
[NimbusMgmt0IntInit]:[233L]NimbusMgmt0IntInit done
[NimbusMgmt1IntInit]:[499L]
[NimbusMgmt2IntInit]:[626L]NimbusMgmt2IntInit done
[IMU][DEBUG]:  Offset 0x400000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
[IMU][DEBUG]:  Offset 0xfc0000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
registry filesize:0x31cb

[IMU][DEBUG]:  Offset 0xfd8000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[I[IMUMU][DEBUG]:  CS is 0x0
][ERROR]:  The response
[IMU][DEBUG]:  [SfcCmd code is abnormal 0xd6.Read][1580] Start Cs=[0
]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
version:
Welcome to the IMU Firmware!
IMU Firmware version 6.65.0
LiteOS version 5.0.0
[IMU][ERROR]:  IMU reset 0
[2.248]IMU System Timer setup OK!
[2.251][IMU] lbc Config Done.
[2.256]CpuType: 0
[2.256]IsHi1620S: 0
BoardType: 0xffffffff
[2.261]base: 0x90b00000
GetV167Flag = 0x0
SFC Initialization Start...
[GetDeviceId]:[384L]SFC Cs 0 detected ID[0x1860c8]!
[GetDeviceId]:[384L]SFC Cs 1 detected ID[0x0]!
[IMU][ERROR]:  [CollectSpiFlash]:[411] Don't support the flash,
[2.261]base: 0x90b00000
GetV167Flag = 0x0
SFC Initialization Start...
[GetDeviceId]:[384L]SFC Cs 0 detected ID[0x1860c8]!
[GetDeviceId]:[384L]SFC Cs 1 detected ID[0x0]!
[IMU][ERROR]:  [CollectSpiFlash]:[411] Don't support the flash, Cs[1] ID[0x0]!!
System supported 1 Flash.
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1811] Spi Cs 0
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1823] Before config value 0x80800300
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1831] After config value 0x80800300
SFC Initialization Done
It is NS boot!!!
boot from L2!!!
[2.307]reboot time:0
[CheckAllTrainingStatus]:[1495L] Idx0 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx1 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx2 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx3 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx4 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx5 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx6 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx7 HllcIdx0 read: 30000f 
when compile IMU, have to use parameter 'bit', 1024[2.356][CheckAllTrainingStatus]Chip:0
[CheckAllTrainingStatus]:[1495L] Idx0 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx1 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx2 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx3 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx4 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx5 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx6 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx7 HllcIdx0 read: 30000f 
when compile IMU, have to use parameter 'bit', 2048[2.407][CheckAllTrainingStatus]Chip:1
[2.411]ChipNum: 2
TotemNum: 4
NimbusNum: 2
[0]1.
[1]3.
[2]5.
[3]7.
[IMU][DEBUG]:  Back sram data...
Socket=2
dieId=0x1
EfuseBase=0x98380000
efuse=0x0
DieId=1
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x3
EfuseBase=0x90380000
efuse=0x0
DieId=3
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x5
EfuseBase=0x4098380000
efuse=0x0
DieId=5
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x7
EfuseBase=0x4090380000
efuse=0x0
DieId=7
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
[IMU][DEBUG]:  Restore sram data...
osAppInit
recvSerdesCfg[0][0]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][1]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][2]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][3]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][4]serdesMode = 3, bandWidth = 4, GenSpeed = 2, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][5]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][6]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[7] bandWidth is X16!
recvSerdesCfg[0][7]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[8] bandWidth is X16!
recvSerdesCfg[0][8]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][9]serdesMode = 1, bandWidth = 3, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[10] bandWidth is X16!
recvSerdesCfg[0][10]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][0]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][1]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][2]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][3]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][4]serdesMode = 1, bandWidth = 3, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][5]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][6]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[7] bandWidth is X16!
recvSerdesCfg[1][7]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[8] bandWidth is X16!
recvSerdesCfg[1][8]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][9]serdesMode = 4, bandWidth = 4, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[10] bandWidth is X16!
recvSerdesCfg[1][10]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
SerdesDataStruct size = 7
[TianChiGetNicTypeFromCpld][241L] ExecuteCPLDSmcCmd:5
[SetTianChiNicType] Nic 0 Type: 0x0
[TianChiGetNicTypeFromCpld][241L] ExecuteCPLDSmcCmd:5
[SetTianChiNicType] Nic 1 Type: 0x0
[3.510]Normal version.
[InterruptRegister]:[395L]id = 65
[SIWInterruptInit]:[151L]id:65, init done!
[InterruptRegister]:[395L]id = 67
[InterruptRegister]:[395L]id = 69
[IpmbInterruptInit]:[262L]id:69
[InterruptRegister]:[395L]id = 71
[Scmi0InterruptInit]:[25L]id:71, init done!
[InterruptRegister]:[395L]id = 72
[Scmi1InterruptInit]:[38L]id:72, init done!
[InterruptRegister]:[395L]id = 76
[InterruptRegister]:[395L]id = 78
[TotemResetInit]:[70L]id:78, init done!
[InterruptRegister]:[395L]id = 83
[InterruptRegister]:[395L]id = 275
[InterruptRegister]:[395L]id = 299
[InterruptRegister]:[395L]id = 116
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x0 Clear done
[InterruptRegister]:[395L]id = 117
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x0 Clear done
[InterruptRegister]:[395L]id = 134
[InterruptRegister]:[395L]id = 96
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x8000000 Clear done
[InterruptRegister]:[395L]id = 97
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x8000000 Clear done
[InterruptRegister]:[395L]id = 114
[InterruptRegister]:[395L]id = 256
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt0RasIntClear]:[259L]nimbusBase 0x0 clear done
[InterruptRegister]:[395L]id = 257
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt1RasIntClear]:[529L]nimbusBase 0x0 Clear done
[InterruptRegister]:[395L]id = 258
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt2RasIntClear]:[638L]nimbusBase 0x0 Clear done
[InterruptRegister]:[395L]id = 259
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusHacRasIntClear]:[311L]NimbusHacRasIntClear done
[InterruptRegister]:[395L]id = 260
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusNicRasIntClear]:[466L]nimbusBase 0x0 Clear done
[InterruptRegister]:[395L]id = 261
[NimbusPCIeRasIntClear]:[662L]NimbusBase 0x0 Clear Start...
[NimbusPCIeRasIntClear]:[673L]NimbusBase 0x0 Clear done!
[InterruptRegister]:[395L]id = 156
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 157
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 174
[InterruptRegister]:[395L]id = 136
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x4008000000 Clear done
[InterruptRegister]:[395L]id = 137
TYPE0: 0
TYPE1: 0
TYPE2: 
Welcome to the IMU Firmware!
IMU Firmware version 6.65.0
LiteOS version 5.0.0
[IMU][ERROR]:  IMU reset 0
[2.248]IMU System Timer setup OK!
[2.251][IMU] lbc Config Done.
[2.256]CpuType: 0
[2.256]IsHi1620S: 0
BoardType: 0xffffffff
[2.261]base: 0x90b00000
GetV167Flag = 0x0
SFC Initialization Start...
[GetDeviceId]:[384L]SFC Cs 0 detected ID[0x1860c8]!
[GetDeviceId]:[384L]SFC Cs 1 detected ID[0x0]!
[IMU][ERROR]:  [CollectSpiFlash]:[411] Don't support the flash, Cs[1] ID[0x0]!!
System supported 1 Flash.
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1811] Spi Cs 0
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1823] Before config value 0x80800300
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1831] After config value 0x80800300
SFC Initialization Done
It is NS boot!!!
boot from L2!!!
[2.307]reboot time:0
[CheckAllTrainingStatus]:[1495L] Idx0 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx1 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx2 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx3 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx4 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx5 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx6 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx7 HllcIdx0 read: 30000f 
when compile IMU, have to use parameter 'bit', 1024[2.356][CheckAllTrainingStatus]Chip:0
[CheckAllTrainingStatus]:[1495L] Idx0 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx1 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx2 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx3 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx4 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx5 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx6 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx7 HllcIdx0 read: 30000f 
when compile IMU, have to use parameter 'bit', 2048[2.407][CheckAllTrainingStatus]Chip:1
[2.411]ChipNum: 2
TotemNum: 4
NimbusNum: 2
[0]1.
[1]3.
[2]5.
[3]7.
[IMU][DEBUG]:  Back sram data...
Socket=2
dieId=0x1
EfuseBase=0x98380000
efuse=0x0
DieId=1
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x3
EfuseBase=0x90380000
efuse=0x0
DieId=3
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x5
EfuseBase=0x4098380000
efuse=0x0
DieId=5
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x7
EfuseBase=0x4090380000
efuse=0x0
DieId=7
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
[IMU][DEBUG]:  Restore sram data...
osAppInit
recvSerdesCfg[0][0]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][1]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][2]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][3]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][4]serdesMode = 3, bandWidth = 4, GenSpeed = 2, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][5]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][6]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[7] bandWidth is X16!
recvSerdesCfg[0][7]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[8] bandWidth is X16!
recvSerdesCfg[0][8]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][9]serdesMode = 1, bandWidth = 3, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[10] bandWidth is X16!
recvSerdesCfg[0][10]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][0]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][1]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][2]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][3]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][4]serdesMode = 1, bandWidth = 3, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][5]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][6]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[7] bandWidth is X16!
recvSerdesCfg[1][7]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[8] bandWidth is X16!
recvSerdesCfg[1][8]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][9]serdesMode = 4, bandWidth = 4, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[10] bandWidth is X16!
recvSerdesCfg[1][10]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
SerdesDataStruct size = 7
[TianChiGetNicTypeFromCpld][241L] ExecuteCPLDSmcCmd:5
[SetTianChiNicType] Nic 0 Type: 0x0
[TianChiGetNicTypeFromCpld][241L] ExecuteCPLDSmcCmd:5
[SetTianChiNicType] Nic 1 Type: 0x0
[3.510]Normal version.
[InterruptRegister]:[395L]id = 65
[SIWInterruptInit]:[151L]id:65, init done!
[InterruptRegister]:[395L]id = 67
[InterruptRegister]:[395L]id = 69
[IpmbInterruptInit]:[262L]id:69
[InterruptRegister]:[395L]id = 71
[Scmi0InterruptInit]:[25L]id:71, init done!
[InterruptRegister]:[395L]id = 72
[Scmi1InterruptInit]:[38L]id:72, init done!
[InterruptRegister]:[395L]id = 76
[InterruptRegister]:[395L]id = 78
[TotemResetInit]:[70L]id:78, init done!
[InterruptRegister]:[395L]id = 83
[InterruptRegister]:[395L]id = 275
[InterruptRegister]:[395L]id = 299
[InterruptRegister]:[395L]id = 116
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x0 Clear done
[InterruptRegister]:[395L]id = 117
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x0 Clear done
[InterruptRegister]:[395L]id = 134
[InterruptRegister]:[395L]id = 96
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x8000000 Clear done
[InterruptRegister]:[395L]id = 97
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x8000000 Clear done
[InterruptRegister]:[395L]id = 114
[InterruptRegister]:[395L]id = 256
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt0RasIntClear]:[259L]nimbusBase 0x0 clear done
[InterruptRegister]:[395L]id = 257
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt1RasIntClear]:[529L]nimbusBase 0x0 Clear done
[InterruptRegister]:[395L]id = 258
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt2RasIntClear]:[638L]nimbusBase 0x0 Clear done
[InterruptRegister]:[395L]id = 259
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusHacRasIntClear]:[311L]NimbusHacRasIntClear done
[InterruptRegister]:[395L]id = 260
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusNicRasIntClear]:[466L]nimbusBase 0x0 Clear done
[InterruptRegister]:[395L]id = 261
[NimbusPCIeRasIntClear]:[662L]NimbusBase 0x0 Clear Start...
[NimbusPCIeRasIntClear]:[673L]NimbusBase 0x0 Clear done!
[InterruptRegister]:[395L]id = 156
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 157
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 174
[InterruptRegister]:[395L]id = 136
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x4008000000 Clear done
[InterruptRegister]:[395L]id = 137
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x4008000000 Clear done
[InterruptRegister]:[395L]id = 154
[InterruptRegister]:[395L]id = 280
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt0RasIntClear]:[259L]nimbusBase 0x4000000000 clear done
[InterruptRegister]:[395L]id = 281
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt1RasIntClear]:[529L]nimbusBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 282
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt2RasIntClear]:[638L]nimbusBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 283
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusHacRasIntClear]:[311L]NimbusHacRasIntClear done
[InterruptRegister]:[395L]id = 284
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusNicRasIntClear]:[466L]nimbusBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 285
[NimbusPCIeRasIntClear]:[662L]NimbusBase 0x4000000000 Clear Start...
[NimbusPCIeRasIntClear]:[673L]NimbusBase 0x4000000000 Clear done!
Cer Initialization start...
[IMU][DEBUG]:  CER_CFG_BD_ENDIAN_ADDR is 0x3
[IMU][DEBUG]:  OUT STANDING is 0x4040
[IMU][DEBUG]:  OUT STANDING after set is 0x140
Cer Initialization done.
[IMU] I2C Initialization start...
[IMU] I2cDealNimbusException secket:0
[IMU] Set I2C4 ----> IPMB mode(default), Set I2C5 ----> I2C mode Success.
[IMU][DEBUG]:  Start init I2C on Address: [0x210050000].
[IMU][DEBUG]:  I2C on Address: [0x210050000] init Succed.
[IMU] Set I2C5 to NORMAL mode.
[IMU] I2C Initialization done!
[IMU] Scmi channels Initialization done!
SIW Initialization Starting...

Enable SIW Debug interface ...
[IMU][DEBUG]:  ES.IMU.SIW.006 SC_SIW_STAT register value is 0x8000.
SIW bypass disabled.
SIW Initialization Done.

[IMU] MiscConfig Start.
[IMU][DEBUG]:  DDRC_CFG_STADAT before config 0x0.
[IMU][DEBUG]:  DDRC_CFG_STADAT after config 0x40000000.
[IMU] Misc Config Done.
[IMU] Gpio MUX Config Done.
[IMU] N_CATERR Gpio MUX Config Done.
[IMU][DEBUG]:  CPU_cluster 0x5a00 is 0xff, hotreset is 0x0
TotemPll0InitCs nodeId:3
TotemPll0InitCs nodeId:1
SllcSetBand isHigh:1
SpiTpmRead ret: 0x0, detect = 0x0
SpiTpmRead ret: 0x0, didVid = 0x0
[IMU][ERROR]:  TPM is not detected
[IMU][ERROR]:  Tpm init err, 0x1
[IMU][DEBUG]:  Offset 0x800000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
 IMU compilation script 
IMU start to measure sec.
[IMU][ERROR]:  Unsupported trusted module
TPM Measure UEFI SEC fail, 0x1
[IMU][DEBUG]:  Offset 0x400000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
[IMU][DEBUG]:  Offset 0x90000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
It's not secure boot
TotemPll0DeInitCs nodeId:1
TotemPll0DeInitCs nodeId:3
SllcSetBand isHigh:0
base: 0x98200000
Ap is booting up, status: 0xee
[IMU][DEBUG]:  Offset 0x890000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
IMU start to measure Fvmain_compact and TF.
[IMU][ERROR]:  Unsupported trusted module
TPM Measure Uefi and TF fail, 0x1
IMU start to measure certificate and HD.
[IMU][ERROR]:  Unsupported trusted module
TPM Measure Certificate and HD fail, 0x1
[SetSkipTrainingFlag]21007f024:1620a5a2
[IMU] Watchdog Initialization done!
cpu 0 entering scheduler
[IMU] Chip: 0 Totem-B Fabric sub T-sensor setup ok!
[IMU] Chip: 0 Totem-B Sys sub T-sensor setup ok!
[IMU] Chip: 0 Totem-A Fabric sub T-sensor setup ok!
[IMU] Chip: 0 Totem-A Sys T-sensor setup ok!
[IMU] Chip: 0 Nimbus T-sensor setup ok!
IPMB initialization Start...
IPMB module clock set done.
IPMB Rx FIFO clear empty.
IPMB initialization Done.
[GetInitSendNumber]:[2142]semaphore create init number = 0!
cfg=110005 g_mctpCount=4
mctp_dev[0] enable=1 mode=1
mctp_dev[1] enable=0 mode=0
mctp_dev[2] enable=1 mode=1
mctp_dev[3] enable=0 mode=0
mctp_loop_task Create Success
HardWare Send IPMI Errorr regValue = 0x8 !!!!
Send process recive sto !!!!

[extInt0Init]:[65L]

[extInt0Init]:[69L]
Core Number: 0x40
Enable scmi int done
mctp loop task start.
Ras Handle task start.
[IpmiMsgGetManufactureid][135]Gotted ManufactureId:db 07 00
pwr cap[0]: 0, 63
pwr cap[1]: f, 27
SetupCfg  :
EnFdmSupport:            0x1
DdrRefreshRate:          0x0
PowerESaving:            0x0
HotPlug:                 0x1
ProcessorFlexibleRatio:  0x1a
CoreIsolateOnlineFlag:   0x0
EnRasSupport:            0x1
AdvanceDeviceCorrection: 0x0
PatrolScrubDuration:     0x18
X8MisCorrEn:             0x0
PowerOnTime:             0xa
DimmTime:                0xa
PageIsolation:           0x0
Mem2BitErrCorrEn:        0x1
pwr cap[2]: 1, 3
[24.945]Real time now:  2026/04/29, 20:40:06
[24.946]InitialCntTime = 24
[25.065][IMU] System DDR Init Done!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x56 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x56 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x56 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x56 DRAM Width failed
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntInit done
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntInit done
[NimbusMgmt0IntInit]:[233L]NimbusMgmt0IntInit done
[NimbusMgmt1IntInit]:[499L]
[NimbusMgmt2IntInit]:[626L]NimbusMgmt2IntInit done
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntInit done
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntInit done
[NimbusMgmt0IntInit]:[233L]NimbusMgmt0IntInit done
[NimbusMgmt1IntInit]:[499L]
[NimbusMgmt2IntInit]:[626L]NimbusMgmt2IntInit done
[IMU][DEBUG]:  Offset 0x400000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUCppcShareMem: 0x44000000
G]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
[IMU][DEBUG]:  Offset 0xfc0000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
registry filesize:0x31cb

[IMU][DEBUG]:  Offset 0xfd8000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS i[IMU][ERs 0x0
[IMU][DEBUG]:  [SROR]:  The response codfcCmdRead][1580] Start e is abnormal 0xd6.
Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
version:
Welcome to the IMU Firmware!
IMU Firmware version 6.65.0
LiteOS version 5.0.0
[IMU][ERROR]:  IMU reset 0
[2.248]IMU System Timer setup OK!
[2.251][IMU] lbc Config Done.
[2.256]CpuType: 0
[2.256]IsHi1620S: 0
BoardType: 0xffffffff
[2.261]base: 0x90b00000
GetV167Flag = 0x0
SFC Initialization Start...
[GetDeviceId]:[384L]SFC Cs 0 detected ID[0x1860c8]!
[GetDeviceId]:[384L]SFC Cs 1 detected ID[0x0]!
[IMU][ERROR]:  [CollectSpiFlash]:[411] Don't support the flash, Cs[1] ID[0x0]!!
System supported 1 Flash.
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1811] Spi Cs 0
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1823] Before config value 0x80800300
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1831] After config value 0x80800300
SFC Initialization Done
It is NS boot!!!
boot from L2!!!
[2.307]reboot time:0
[CheckAllTrainingStatus]:[1495L] Idx0 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx1 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx2 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx3 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx4 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx5 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx6 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx7 HllcIdx0 read: 30000f 
when compile IMU, have to use parameter 'bit', 1024[2.356][CheckAllTrainingStatus]Chip:0
[CheckAllTrainingStatus]:[1495L] Idx0 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx1 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx2 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx3 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx4 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx5 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx6 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx7 HllcIdx0 read: 30000f 
when compile IMU, have to use parameter 'bit', 2048[2.407][CheckAllTrainingStatus]Chip:1
[2.411]ChipNum: 2
TotemNum: 4
NimbusNum: 2
[0]1.
[1]3.
[2]5.
[3]7.
[IMU][DEBUG]:  Back sram data...
Socket=2
dieId=0x1
EfuseBase=0x98380000
efuse=0x0
DieId=1
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x3
EfuseBase=0x90380000
efuse=0x0
DieId=3
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x5
EfuseBase=0x4098380000
efuse=0x0
DieId=5
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x7
EfuseBase=0x4090380000
efuse=0x0
DieId=7
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
[IMU][DEBUG]:  Restore sram data...
osAppInit
recvSerdesCfg[0][0]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][1]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][2]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][3]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][4]serdesMode = 3, bandWidth = 4, GenSpeed = 2, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][5]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][6]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[7] bandWidth is X16!
recvSerdesCfg[0][7]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[8] bandWidth is X16!
recvSerdesCfg[0][8]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][9]serdesMode = 1, bandWidth = 3, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[10] bandWidth is X16!
recvSerdesCfg[0][10]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][0]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][1]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][2]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][3]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][4]serdesMode = 1, bandWidth = 3, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][5]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][6]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[7] bandWidth is X16!
recvSerdesCfg[1][7]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[8] bandWidth is X16!
recvSerdesCfg[1][8]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][9]serdesMode = 4, bandWidth = 4, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[10] bandWidth is X16!
recvSerdesCfg[1][10]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
SerdesDataStruct size = 7
[TianChiGetNicTypeFromCpld][241L] ExecuteCPLDSmcCmd:5
[SetTianChiNicType] Nic 0 Type: 0x0
[TianChiGetNicTypeFromCpld][241L] ExecuteCPLDSmcCmd:5
[SetTianChiNicType] Nic 1 Type: 0x0
[3.510]Normal version.
[InterruptRegister]:[395L]id = 65
[SIWInterruptInit]:[151L]id:65, init done!
[InterruptRegister]:[395L]id = 67
[InterruptRegister]:[395L]id = 69
[IpmbInterruptInit]:[262L]id:69
[InterruptRegister]:[395L]id = 71
[Scmi0InterruptInit]:[25L]id:71, init done!
[InterruptRegister]:[395L]id = 72
[Scmi1InterruptInit]:[38L]id:72, init done!
[InterruptRegister]:[395L]id = 76
[InterruptRegister]:[395L]id = 78
[TotemResetInit]:[70L]id:78, init done!
[InterruptRegister]:[395L]id = 83
[InterruptRegister]:[395L]id = 275
[InterruptRegister]:[395L]id = 299
[InterruptRegister]:[395L]id = 116
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x0 Clear done
[InterruptRegister]:[395L]id = 117
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x0 Clear done
[InterruptRegister]:[395L]id = 134
[InterruptRegister]:[395L]id = 96
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x8000000 Clear done
[InterruptRegister]:[395L]id = 97
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x8000000 Clear done
[InterruptRegister]:[395L]id = 114
[InterruptRegister]:[395L]id = 256
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt0RasIntClear]:[259L]nimbusBase 0x0 clear done
[InterruptRegister]:[395L]id = 257
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt1RasIntClear]:[529L]nimbusBase 0x0 Clear done
[InterruptRegister]:[395L]id = 258
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt2RasIntClear]:[638L]nimbusBase 0x0 Clear done
[InterruptRegister]:[395L]id = 259
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusHacRasIntClear]:[311L]NimbusHacRasIntClear done
[InterruptRegister]:[395L]id = 260
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusNicRasIntClear]:[466L]nimbusBase 0x0 Clear done
[InterruptRegister]:[395L]id = 261
[NimbusPCIeRasIntClear]:[662L]NimbusBase 0x0 Clear Start...
[NimbusPCIeRasIntClear]:[673L]NimbusBase 0x0 Clear done!
[InterruptRegister]:[395L]id = 156
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 157
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 174
[InterruptRegister]:[395L]id = 136
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x4008000000 Clear done
[InterruptRegister]:[395L]id = 137
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x4008000000 Clear done
[InterruptRegister]:[395L]id = 154
[InterruptRegister]:[395L]id = 280
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt0RasIntClear]:[259L]nimbusBase 0x4000000000 clear done
[InterruptRegister]:[395L]id = 281
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt1RasIntClear]:[529L]nimbusBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 282
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt2RasIntClear]:[638L]nimbusBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 283
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusHacRasIntClear]:[311L]NimbusHacRasIntClear done
[InterruptRegister]:[395L]id = 284
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusNicRasIntClear]:[466L]nimbusBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 285
[NimbusPCIeRasIntClear]:[662L]NimbusBase 0x4000000000 Clear Start...
[NimbusPCIeRasIntClear]:[673L]NimbusBase 0x4000000000 Clear done!
Cer Initialization start...
[IMU][DEBUG]:  CER_CFG_BD_ENDIAN_ADDR is 0x3
[IMU][DEBUG]:  OUT STANDING is 0x4040
[IMU][DEBUG]:  OUT STANDING after set is 0x140
Cer Initialization done.
[IMU] I2C Initialization start...
[IMU] I2cDealNimbusException secket:0
[IMU] Set I2C4 ----> IPMB mode(default), Set I2C5 ----> I2C mode Success.
[IMU][DEBUG]:  Start init I2C on Address: [0x210050000].
[IMU][DEBUG]:  I2C on Address: [0x210050000] init Succed.
[IMU] Set I2C5 to NORMAL mode.
[IMU] I2C Initialization done!
[IMU] Scmi channels Initialization done!
SIW Initialization Starting...

Enable SIW Debug interface ...
[IMU][DEBUG]:  ES.IMU.SIW.006 SC_SIW_STAT register value is 0x8000.
SIW bypass disabled.
SIW Initialization Done.

[IMU] MiscConfig Start.
[IMU][DEBUG]:  DDRC_CFG_STADAT before config 0x0.
[IMU][DEBUG]:  DDRC_CFG_STADAT after config 0x40000000.
[IMU] Misc Config Done.
[IMU] Gpio MUX Config Done.
[IMU] N_CATERR Gpio MUX Config Done.
[IMU][DEBUG]:  CPU_cluster 0x5a00 is 0xff, hotreset is 0x0
TotemPll0InitCs nodeId:3
TotemPll0InitCs nodeId:1
SllcSetBand isHigh:1
SpiTpmRead ret: 0x0, detect = 0x0
SpiTpmRead ret: 0x0, didVid = 0x0
[IMU][ERROR]:  TPM is not detected
[IMU][ERROR]:  Tpm init err, 0x1
[IMU][DEBUG]:  Offset 0x800000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
 IMU compilation script 
IMU start to measure sec.
[IMU][ERROR]:  Unsupported trusted module
TPM Measure UEFI SEC fail, 0x1
[IMU][DEBUG]:  Offset 0x400000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
[IMU][DEBUG]:  Offset 0x90000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
It's not secure boot
TotemPll0DeInitCs nodeId:1
TotemPll0DeInitCs nodeId:3
SllcSetBand isHigh:0
base: 0x98200000
Ap is booting up, status: 0xee
[IMU][DEBUG]:  Offset 0x890000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
IMU start to measure Fvmain_compact and TF.
[IMU][ERROR]:  Unsupported trusted module
TPM Measure Uefi and TF fail, 0x1
IMU start to measure certificate and HD.
[IMU][ERROR]:  Unsupported trusted module
TPM Measure Certificate and HD fail, 0x1
[SetSkipTrainingFlag]21007f024:1620a5a2
[IMU] Watchdog Initialization done!
cpu 0 entering scheduler
[IMU] Chip: 0 Totem-B Fabric sub T-sensor setup ok!
[IMU] Chip: 0 Totem-B Sys sub T-sensor setup ok!
[IMU] Chip: 0 Totem-A Fabric sub T-sensor setup ok!
[IMU] Chip: 0 Totem-A Sys T-sensor setup ok!
[IMU] Chip: 0 Nimbus T-sensor setup ok!
IPMB initialization Start...
IPMB module clock set done.
IPMB Rx FIFO clear empty.
IPMB initialization Done.
[GetInitSendNumber]:[2142]semaphore create init number = 0!
cfg=110005 g_mctpCount=4
mctp_dev[0] enable=1 mode=1
mctp_dev[1] enable=0 mode=0
mctp_dev[2] enable=1 mode=1
mctp_dev[3] enable=0 mode=0
mctp_loop_task Create Success
HardWare Send IPMI Errorr regValue = 0x8 !!!!
Send process recive sto !!!!

[extInt0Init]:[65L]

[extInt0Init]:[69L]
Core Number: 0x40
Enable scmi int done
mctp loop task start.
Ras Handle task start.
[IpmiMsgGetManufactureid][135]Gotted ManufactureId:db 07 00
pwr cap[0]: 0, 63
pwr cap[1]: f, 27
SetupCfg  :
EnFdmSupport:            0x1
DdrRefreshRate:          0x0
PowerESaving:            0x0
HotPlug:                 0x1
ProcessorFlexibleRatio:  0x1a
CoreIsolateOnlineFlag:   0x0
EnRasSupport:            0x1
AdvanceDeviceCorrection: 0x0
PatrolScrubDuration:     0x18
X8MisCorrEn:             0x0
PowerOnTime:             0xa
DimmTime:                0xa
PageIsolation:           0x0
Mem2BitErrCorrEn:        0x1
pwr cap[2]: 1, 3
[24.866]Real time now:  2026/04/29, 20:45:15
[24.868]InitialCntTime = 24
[24.986][IMU] System DDR Init Done!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!

Welcome to the IMU Firmware!
IMU Firmware version 6.65.0
LiteOS version 5.0.0
[IMU][ERROR]:  IMU reset 0
[2.248]IMU System Timer setup OK!
[2.251][IMU] lbc Config Done.
[2.256]CpuType: 0
[2.256]IsHi1620S: 0
BoardType: 0xffffffff
[2.261]base: 0x90b00000
GetV167Flag = 0x0
SFC Initialization Start...
[GetDeviceId]:[384L]SFC Cs 0 detected ID[0x1860c8]!
[GetDeviceId]:[384L]SFC Cs 1 detected ID[0x0]!
[IMU][ERROR]:  [CollectSpiFlash]:[411] Don't support the flash, Cs[1] ID[0x0]!!
System supported 1 Flash.
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1811] Spi Cs 0
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1823] Before config value 0x80800300
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1831] After config value 0x80800300
SFC Initialization Done
It is NS boot!!!
boot from L2!!!
[2.307]reboot time:0
[CheckAllTrainingStatus]:[1495L] Idx0 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx1 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx2 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx3 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx4 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx5 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx6 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx7 HllcIdx0 read: 30000f 
when compile IMU, have to use parameter 'bit', 1024[2.356][CheckAllTrainingStatus]Chip:0
[CheckAllTrainingStatus]:[1495L] Idx0 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx1 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx2 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx3 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx4 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx5 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx6 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx7 HllcIdx0 read: 30000f 
when compile IMU, have to use parameter 'bit', 2048[2.407][CheckAllTrainingStatus]Chip:1
[2.411]ChipNum: 2
TotemNum: 4
NimbusNum: 2
[0]1.
[1]3.
[2]5.
[3]7.
[IMU][DEBUG]:  Back sram data...
Socket=2
dieId=0x1
EfuseBase=0x98380000
efuse=0x0
DieId=1
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x3
EfuseBase=0x90380000
efuse=0x0
DieId=3
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x5
EfuseBase=0x4098380000
efuse=0x0
DieId=5
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x7
EfuseBase=0x4090380000
efuse=0x0
DieId=7
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
[IMU][DEBUG]:  Restore sram data...
osAppInit
recvSerdesCfg[0][0]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][1]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][2]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][3]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][4]serdesMode = 3, bandWidth = 4, GenSpeed = 2, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][5]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][6]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[7] bandWidth is X16!
recvSerdesCfg[0][7]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[8] bandWidth is X16!
recvSerdesCfg[0][8]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][9]serdesMode = 1, bandWidth = 3, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[10] bandWidth is X16!
recvSerdesCfg[0][10]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][0]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][1]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][2]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][3]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][4]serdesMode = 1, bandWidth = 3, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][5]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][6]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[7] bandWidth is X16!
recvSerdesCfg[1][7]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[8] bandWidth is X16!
recvSerdesCfg[1][8]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][9]serdesMode = 4, bandWidth = 4, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[10] bandWidth is X16!
recvSerdesCfg[1][10]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
SerdesDataStruct size = 7
[TianChiGetNicTypeFromCpld][241L] ExecuteCPLDSmcCmd:5
[SetTianChiNicType] Nic 0 Type: 0x0
[TianChiGetNicTypeFromCpld][241L] ExecuteCPLDSmcCmd:5
[SetTianChiNicType] Nic 1 Type: 0x0
[3.511]Normal version.
[InterruptRegister]:[395L]id = 65
[SIWInterruptInit]:[151L]id:65, init done!
[InterruptRegister]:[395L]id = 67
[InterruptRegister]:[395L]id = 69
[IpmbInterruptInit]:[262L]id:69
[InterruptRegister]:[395L]id = 71
[Scmi0InterruptInit]:[25L]id:71, init done!
[InterruptRegister]:[395L]id = 72
[Scmi1InterruptInit]:[38L]id:72, init done!
[InterruptRegister]:[395L]id = 76
[InterruptRegister]:[395L]id = 78
[TotemResetInit]:[70L]id:78, init done!
[InterruptRegister]:[395L]id = 83
[InterruptRegister]:[395L]id = 275
[InterruptRegister]:[395L]id = 299
[InterruptRegister]:[395L]id = 116
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x0 Clear done
[InterruptRegister]:[395L]id = 117
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x0 Clear done
[InterruptRegister]:[395L]id = 134
[InterruptRegister]:[395L]id = 96
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x8000000 Clear done
[InterruptRegister]:[395L]id = 97
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x8000000 Clear done
[InterruptRegister]:[395L]id = 114
[InterruptRegister]:[395L]id = 256
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt0RasIntClear]:[259L]nimbusBase 0x0 clear done
[InterruptRegister]:[395L]id = 257
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt1RasIntClear]:[529L]nimbusBase 0x0 Clear done
[InterruptRegister]:[395L]id = 258
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt2RasIntClear]:[638L]nimbusBase 0x0 Clear done
[InterruptRegister]:[395L]id = 259
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusHacRasIntClear]:[311L]NimbusHacRasIntClear done
[InterruptRegister]:[395L]id = 260
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusNicRasIntClear]:[466L]nimbusBase 0x0 Clear done
[InterruptRegister]:[395L]id = 261
[NimbusPCIeRasIntClear]:[662L]NimbusBase 0x0 Clear Start...
[NimbusPCIeRasIntClear]:[673L]NimbusBase 0x0 Clear done!
[InterruptRegister]:[395L]id = 156
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 157
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 174
[InterruptRegister]:[395L]id = 136
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x4008000000 Clear done
[InterruptRegister]:[395L]id = 137
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x4008000000 Clear done
[InterruptRegister]:[395L]id = 154
[InterruptRegister]:[395L]id = 280
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt0RasIntClear]:[259L]nimbusBase 0x4000000000 clear done
[InterruptRegister]:[395L]id = 281
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt1RasIntClear]:[529L]nimbusBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 282
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt2RasIntClear]:[638L]nimbusBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 283
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusHacRasIntClear]:[311L]NimbusHacRasIntClear done
[InterruptRegister]:[395L]id = 284
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusNicRasIntClear]:[466L]nimbusBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 285
[NimbusPCIeRasIntClear]:[662L]NimbusBase 0x4000000000 Clear Start...
[NimbusPCIeRasIntClear]:[673L]NimbusBase 0x4000000000 Clear done!
Cer Initialization start...
[IMU][DEBUG]:  CER_CFG_BD_ENDIAN_ADDR is 0x3
[IMU][DEBUG]:  OUT STANDING is 0x4040
[IMU][DEBUG]:  OUT STANDING after set is 0x140
Cer Initialization done.
[IMU] I2C Initialization start...
[IMU] I2cDealNimbusException secket:0
[IMU] Set I2C4 ----> IPMB mode(default), Set I2C5 ----> I2C mode Success.
[IMU][DEBUG]:  Start init I2C on Address: [0x210050000].
[IMU][DEBUG]:  I2C on Address: [0x210050000] init Succed.
[IMU] Set I2C5 to NORMAL mode.
[IMU] I2C Initialization done!
[IMU] Scmi channels Initialization done!
SIW Initialization Starting...

Enable SIW Debug interface ...
[IMU][DEBUG]:  ES.IMU.SIW.006 SC_SIW_STAT register value is 0x8000.
SIW bypass disabled.
SIW Initialization Done.

[IMU] MiscConfig Start.
[IMU][DEBUG]:  DDRC_CFG_STADAT before config 0x0.
[IMU][DEBUG]:  DDRC_CFG_STADAT after config 0x40000000.
[IMU] Misc Config Done.
[IMU] Gpio MUX Config Done.
[IMU] N_CATERR Gpio MUX Config Done.
[IMU][DEBUG]:  CPU_cluster 0x5a00 is 0xff, hotreset is 0x0
TotemPll0InitCs nodeId:3
TotemPll0InitCs nodeId:1
SllcSetBand isHigh:1
SpiTpmRead ret: 0x0, detect = 0x0
SpiTpmRead ret: 0x0, didVid = 0x0
[IMU][ERROR]:  TPM is not detected
[IMU][ERROR]:  Tpm init err, 0x1
[IMU][DEBUG]:  Offset 0x800000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
 IMU compilation script 
IMU start to measure sec.
[IMU][ERROR]:  Unsupported trusted module
TPM Measure UEFI SEC fail, 0x1
[IMU][DEBUG]:  Offset 0x400000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
[IMU][DEBUG]:  Offset 0x90000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
It's not secure boot
TotemPll0DeInitCs nodeId:1
TotemPll0DeInitCs nodeId:3
SllcSetBand isHigh:0
base: 0x98200000
Ap is booting up, status: 0xee
[IMU][DEBUG]:  Offset 0x890000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
IMU start to measure Fvmain_compact and TF.
[IMU][ERROR]:  Unsupported trusted module
TPM Measure Uefi and TF fail, 0x1
IMU start to measure certificate and HD.
[IMU][ERROR]:  Unsupported trusted module
TPM Measure Certificate and HD fail, 0x1
[SetSkipTrainingFlag]21007f024:1620a5a2
[IMU] Watchdog Initialization done!
cpu 0 entering scheduler
[IMU] Chip: 0 Totem-B Fabric sub T-sensor setup ok!
[IMU] Chip: 0 Totem-B Sys sub T-sensor setup ok!
[IMU] Chip: 0 Totem-A Fabric sub T-sensor setup ok!
[IMU] Chip: 0 Totem-A Sys T-sensor setup ok!
[IMU] Chip: 0 Nimbus T-sensor setup ok!
IPMB initialization Start...
IPMB module clock set done.
IPMB Rx FIFO clear empty.
IPMB initialization Done.
[GetInitSendNumber]:[2142]semaphore create init number = 0!
cfg=110005 g_mctpCount=4
mctp_dev[0] enable=1 mode=1
mctp_dev[1] enable=0 mode=0
mctp_dev[2] enable=1 mode=1
mctp_dev[3] enable=0 mode=0
mctp_loop_task Create Success
HardWare Send IPMI Errorr regValue = 0x8 !!!!
Send process recive sto !!!!

[extInt0Init]:[65L]

[extInt0Init]:[69L]
Core Number: 0x40
Enable scmi int done
mctp loop task start.
Ras Handle task start.
[IpmiMsgGetManufactureid][135]Gotted ManufactureId:db 07 00
pwr cap[0]: 0, 63
pwr cap[1]: f, 27
SetupCfg  :
EnFdmSupport:            0x1
DdrRefreshRate:          0x0
PowerESaving:            0x0
HotPlug:                 0x1
ProcessorFlexibleRatio:  0x1a
CoreIsolateOnlineFlag:   0x0
EnRasSupport:            0x1
AdvanceDeviceCorrection: 0x0
PatrolScrubDuration:     0x18
X8MisCorrEn:             0x0
PowerOnTime:             0xa
DimmTime:                0xa
PageIsolation:           0x0
Mem2BitErrCorrEn:        0x1
pwr cap[2]: 1, 3
[25.299]Real time now:  2026/04/29, 20:50:45
[25.300]InitialCntTime = 25
[25.412][IMU] System DDR Init Done!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[284L]I2C operation abort, there is no ack returned!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x56 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x56 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x56 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x56 DRAM Width failed
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntInit done
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntInit done
[NimbusMgmt0IntInit]:[233L]NimbusMgmt0IntInit done
[NimbusMgmt1IntInit]:[499L]
[NimbusMgmt2IntInit]:[626L]NimbusMgmt2IntInit done
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntInit done
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntInit done
[NimbusMgmt0IntInit]:[233L]NimbusMgmt0IntInit done
[NimbusMgmt1IntInit]:[499L]
[NimbusMgmt2IntInit]:[626L]NimbusMgmt2IntInit done
[IMU][DEBUG]:  Offset 0x400000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
CppcShareMem: 0x44000000
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
[IMU][DEBUG]:  Offset 0xfc0000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
registry filesize:0x31cb

[IMU][DEBUG]:  Offset 0xfd8000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]: [IMU][ERROR]:  The r FlashIndex is 0x0
[IMesponse code is abnormaU][DEBUG]:  CS is 0x0
l 0xd6.
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
version:
Welcome to the IMU Firmware!
IMU Firmware version 6.65.0
LiteOS version 5.0.0
[IMU][ERROR]:  IMU reset 0
[2.248]IMU System Timer setup OK!
[2.251][IMU] lbc Config Done.
[2.256]CpuType: 0
[2.256]IsHi1620S: 0
BoardType: 0xffffffff
[2.261]base: 0x90b00000
GetV167Flag = 0x0
SFC Initialization Start...
[GetDeviceId]:[384L]SFC Cs 0 detected ID[0x1860c8]!
[GetDeviceId]:[384L]SFC Cs 1 detected ID[0x0]!
[IMU][ERROR]:  [CollectSpiFlash]:[411] Don't support the flash, Cs[1] ID[0x0]!!
System supported 1 Flash.
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1811] Spi Cs 0
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1823] Before config value 0x80800300
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1831] After config value 0x80800300
SFC Initialization Done
It is NS boot!!!
boot from L2!!!
[2.307]reboot time:0
[CheckAllTrainingStatus]:[1495L] Idx0 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx1 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx2 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx3 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx4 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx5 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx6 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx7 HllcIdx0 read: 30000f 
when compile IMU, have to use parameter 'bit', 1024[2.356][CheckAllTrainingStatus]Chip:0
[CheckAllTrainingStatus]:[1495L] Idx0 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx1 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx2 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx3 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx4 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx5 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx6 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx7 HllcIdx0 read: 30000f 
when compile IMU, have to use parameter 'bit', 2048[2.407][CheckAllTrainingStatus]Chip:1
[2.411]ChipNum: 2
TotemNum: 4
NimbusNum: 2
[0]1.
[1]3.
[2]5.
[3]7.
[IMU][DEBUG]:  Back sram data...
Socket=2
dieId=0x1
EfuseBase=0x98380000
efuse=0x0
DieId=1
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x3
EfuseBase=0x90380000
efuse=0x0
DieId=3
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x5
EfuseBase=0x4098380000
efuse=0x0
DieId=5
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x7
EfuseBase=0x4090380000
efuse=0x0
DieId=7
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
[IMU][DEBUG]:  Restore sram data...
osAppInit
recvSerdesCfg[0][0]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][1]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][2]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][3]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][4]serdesMode = 3, bandWidth = 4, GenSpeed = 2, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][5]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][6]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[7] bandWidth is X16!
recvSerdesCfg[0][7]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[8] bandWidth is X16!
recvSerdesCfg[0][8]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][9]serdesMode = 1, bandWidth = 3, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[10] bandWidth is X16!
recvSerdesCfg[0][10]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][0]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][1]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][2]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][3]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][4]serdesMode = 1, bandWidth = 3, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][5]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][6]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[7] bandWidth is X16!
recvSerdesCfg[1][7]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[8] bandWidth is X16!
recvSerdesCfg[1][8]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][9]serdesMode = 4, bandWidth = 4, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[10] bandWidth is X16!
recvSerdesCfg[1][10]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
SerdesDataStruct size = 7
[TianChiGetNicTypeFromCpld][241L] ExecuteCPLDSmcCmd:5
[SetTianChiNicType] Nic 0 Type: 0x0
[TianChiGetNicTypeFromCpld][241L] ExecuteCPLDSmcCmd:5
[SetTianChiNicType] Nic 1 Type: 0x0
[3.511]Normal version.
[InterruptRegister]:[395L]id = 65
[SIWInterruptInit]:[151L]id:65, init done!
[InterruptRegister]:[395L]id = 67
[InterruptRegister]:[395L]id = 69
[IpmbInterruptInit]:[262L]id:69
[InterruptRegister]:[395L]id = 71
[Scmi0InterruptInit]:[25L]id:71, init done!
[InterruptRegister]:[395L]id = 72
[Scmi1InterruptInit]:[38L]id:72, init done!
[InterruptRegister]:[395L]id = 76
[InterruptRegister]:[395L]id = 78
[TotemResetInit]:[70L]id:78, init done!
[InterruptRegister]:[395L]id = 83
[InterruptRegister]:[395L]id = 275
[InterruptRegister]:[395L]id = 299
[InterruptRegister]:[395L]id = 116
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x0 Clear done
[InterruptRegister]:[395L]id = 117
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x0 Clear done
[InterruptRegister]:[395L]id = 134
[InterruptRegister]:[395L]id = 96
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x8000000 Clear done
[InterruptRegister]:[395L]id = 97
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x8000000 Clear done
[InterruptRegister]:[395L]id = 114
[InterruptRegister]:[395L]id = 256
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt0RasIntClear]:[259L]nimbusBase 0x0 clear done
[InterruptRegister]:[395L]id = 257
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt1RasIntClear]:[529L]nimbusBase 0x0 Clear done
[InterruptRegister]:[395L]id = 258
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt2RasIntClear]:[638L]nimbusBase 0x0 Clear done
[InterruptRegister]:[395L]id = 259
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusHacRasIntClear]:[311L]NimbusHacRasIntClear done
[InterruptRegister]:[395L]id = 260
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusNicRasIntClear]:[466L]nimbusBase 0x0 Clear done
[InterruptRegister]:[395L]id = 261
[NimbusPCIeRasIntClear]:[662L]NimbusBase 0x0 Clear Start...
[NimbusPCIeRasIntClear]:[673L]NimbusBase 0x0 Clear done!
[InterruptRegister]:[395L]id = 156
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 157
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 174
[InterruptRegister]:[395L]id = 136
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x4008000000 Clear done
[InterruptRegister]:[395L]id = 137
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x4008000000 Clear done
[InterruptRegister]:[395L]id = 154
[InterruptRegister]:[395L]id = 280
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt0RasIntClear]:[259L]nimbusBase 0x4000000000 clear done
[InterruptRegister]:[395L]id = 281
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt1RasIntClear]:[529L]nimbusBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 282
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt2RasIntClear]:[638L]nimbusBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 283
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusHacRasIntClear]:[311L]NimbusHacRasIntClear done
[InterruptRegister]:[395L]id = 284
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusNicRasIntClear]:[466L]nimbusBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 285
[NimbusPCIeRasIntClear]:[662L]NimbusBase 0x4000000000 Clear Start...
[NimbusPCIeRasIntClear]:[673L]NimbusBase 0x4000000000 Clear done!
Cer Initialization start...
[IMU][DEBUG]:  CER_CFG_BD_ENDIAN_ADDR is 0x3
[IMU][DEBUG]:  OUT STANDING is 0x4040
[IMU][DEBUG]:  OUT STANDING after set is 0x140
Cer Initialization done.
[IMU] I2C Initialization start...
[IMU] I2cDealNimbusException secket:0
[IMU] Set I2C4 ----> IPMB mode(default), Set I2C5 ----> I2C mode Success.
[IMU][DEBUG]:  Start init I2C on Address: [0x210050000].
[IMU][DEBUG]:  I2C on Address: [0x210050000] init Succed.
[IMU] Set I2C5 to NORMAL mode.
[IMU] I2C Initialization done!
[IMU] Scmi channels Initialization done!
SIW Initialization Starting...

Enable SIW Debug interface ...
[IMU][DEBUG]:  ES.IMU.SIW.006 SC_SIW_STAT register value is 0x8000.
SIW bypass disabled.
SIW Initialization Done.

[IMU] MiscConfig Start.
[IMU][DEBUG]:  DDRC_CFG_STADAT before config 0x0.
[IMU][DEBUG]:  DDRC_CFG_STADAT after config 0x40000000.
[IMU] Misc Config Done.
[IMU] Gpio MUX Config Done.
[IMU] N_CATERR Gpio MUX Config Done.
[IMU][DEBUG]:  CPU_cluster 0x5a00 is 0xff, hotreset is 0x0
TotemPll0InitCs nodeId:3
TotemPll0InitCs nodeId:1
SllcSetBand isHigh:1
SpiTpmRead ret: 0x0, detect = 0x0
SpiTpmRead ret: 0x0, didVid = 0x0
[IMU][ERROR]:  TPM is not detected
[IMU][ERROR]:  Tpm init err, 0x1
[IMU][DEBUG]:  Offset 0x800000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
 IMU compilation script 
IMU start to measure sec.
[IMU][ERROR]:  Unsupported trusted module
TPM Measure UEFI SEC fail, 0x1
[IMU][DEBUG]:  Offset 0x400000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
[IMU][DEBUG]:  Offset 0x90000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
It's not secure boot
TotemPll0DeInitCs nodeId:1
TotemPll0DeInitCs nodeId:3
SllcSetBand isHigh:0
base: 0x98200000
Ap is booting up, status: 0xee
[IMU][DEBUG]:  Offset 0x890000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
IMU start to measure Fvmain_compact and TF.
[IMU][ERROR]:  Unsupported trusted module
TPM Measure Uefi and TF fail, 0x1
IMU start to measure certificate and HD.
[IMU][ERROR]:  Unsupported trusted module
TPM Measure Certificate and HD fail, 0x1
[SetSkipTrainingFlag]21007f024:1620a5a2
[IMU] Watchdog Initialization done!
cpu 0 entering scheduler
[IMU] Chip: 0 Totem-B Fabric sub T-sensor setup ok!
[IMU] Chip: 0 Totem-B Sys sub T-sensor setup ok!
[IMU] Chip: 0 Totem-A Fabric sub T-sensor setup ok!
[IMU] Chip: 0 Totem-A Sys T-sensor setup ok!
[IMU] Chip: 0 Nimbus T-sensor setup ok!
IPMB initialization Start...
IPMB module clock set done.
IPMB Rx FIFO clear empty.
IPMB initialization Done.
[GetInitSendNumber]:[2142]semaphore create init number = 0!
cfg=110005 g_mctpCount=4
mctp_dev[0] enable=1 mode=1
mctp_dev[1] enable=0 mode=0
mctp_dev[2] enable=1 mode=1
mctp_dev[3] enable=0 mode=0
mctp_loop_task Create Success
HardWare Send IPMI Errorr regValue = 0x8 !!!!
Send process recive sto !!!!

[extInt0Init]:[65L]

[extInt0Init]:[69L]
Core Number: 0x40
Enable scmi int done
mctp loop task start.
Ras Handle task start.
[IpmiMsgGetManufactureid][135]Gotted ManufactureId:db 07 00
pwr cap[0]: 0, 63
pwr cap[1]: f, 27
SetupCfg  :
EnFdmSupport:            0x1
DdrRefreshRate:          0x0
PowerESaving:            0x0
HotPlug:                 0x1
ProcessorFlexibleRatio:  0x1a
CoreIsolateOnlineFlag:   0x0
EnRasSupport:            0x1
AdvanceDeviceCorrection: 0x0
PatrolScrubDuration:     0x18
X8MisCorrEn:             0x0
PowerOnTime:             0xa
DimmTime:                0xa
PageIsolation:           0x0
Mem2BitErrCorrEn:        0x1
pwr cap[2]: 1, 3
[24.905]Real time now:  2026/04/29, 20:55:51
[24.906]InitialCntTime = 24
[25.024][IMU] System DDR Init Done!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[284L]I2C operation abort, there is no ack returned!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x56 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x56 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x56 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x56 DRAM Width failed
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntInit done
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntInit done
[NimbusMgmt0IntInit]:[233L]NimbusMgmt0IntInit done
[NimbusMgmt1IntInit]:[499L]
[NimbusMgmt2IntInit]:[626L]NimbusMgmt2IntInit done
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntInit done
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntInit done
[NimbusMgmt0IntInit]:[233L]NimbusMgmt0IntInit done
[NimbusMgmt1IntInit]:[499L]
[NimbusMgmt2IntInit]:[626L]NimbusMgmt2IntInit done
[IMU][DEBUG]:  Offset 0x400000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
CppcShareMem: 0x44000000
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
[IMU][DEBUG]:  Offset 0xfc0000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
registry filesize:0x31cb

[IMU][DEBUG]:  Offset 0xfd8000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x[IMU][ERROR]:  The respo0
[IMU][DEBUG]:  [SfcCnse code is abnormal 0xmdRead][1580] Start Cs=d6.
[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
version:
[IMU] Chip: 1 Totem-B Fabric sub T-sensor setup ok!
[IMU] Chip: 1 Totem-B Sys sub T-sensor setup ok!
[IMU] Chip: 1 Totem-A Fabric sub T-sensor setup ok!
[IMU] Chip: 1 Totem-A Sys T-sensor setup ok!
[IMU] Chip: 1 Nimbus T-sensor setup ok!
[IMU] Thermal Event Initialization done!
[NicRstInterruptInit]:[84L] NicRstInterruptInit done

chip[0]MaxFreq = 2600
chip[1]MaxFreq = 2600
BinZ Flag = 0x0.
 IMU]PreviousLogPos:0; PreviousLogSize:0; Currrent
Welcome to the IMU Firmware!
IMU Firmware version 6.65.0
LiteOS version 5.0.0
[IMU][ERROR]:  IMU reset 0
[2.248]IMU System Timer setup OK!
[2.251][IMU] lbc Config Done.
[2.256]CpuType: 0
[2.256]IsHi1620S: 0
BoardType: 0xffffffff
[2.261]base: 0x90b00000
GetV167Flag = 0x0
SFC Initialization Start...
[GetDeviceId]:[384L]SFC Cs 0 detected ID[0x1860c8]!
[GetDeviceId]:[384L]SFC Cs 1 detected ID[0x0]!
[IMU][ERROR]:  [CollectSpiFlash]:[411] Don't support the flash, Cs[1] ID[0x0]!!
System supported 1 Flash.
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1811] Spi Cs 0
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1823] Before config value 0x80800300
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1831] After config value 0x80800300
SFC Initialization Done
It is NS boot!!!
boot from L2!!!
[2.307]reboot time:0
[CheckAllTrainingStatus]:[1495L] Idx0 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx1 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx2 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx3 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx4 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx5 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx6 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx7 HllcIdx0 read: 30000f 
when compile IMU, have to use parameter 'bit', 1024[2.356][CheckAllTrainingStatus]Chip:0
[CheckAllTrainingStatus]:[1495L] Idx0 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx1 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx2 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx3 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx4 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx5 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx6 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx7 HllcIdx0 read: 30000f 
when compile IMU, have to use parameter 'bit', 2048[2.407][CheckAllTrainingStatus]Chip:1
[2.411]ChipNum: 2
TotemNum: 4
NimbusNum: 2
[0]1.
[1]3.
[2]5.
[3]7.
[IMU][DEBUG]:  Back sram data...
Socket=2
dieId=0x1
EfuseBase=0x98380000
efuse=0x0
DieId=1
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x3
EfuseBase=0x90380000
efuse=0x0
DieId=3
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x5
EfuseBase=0x4098380000
efuse=0x0
DieId=5
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x7
EfuseBase=0x4090380000
efuse=0x0
DieId=7
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
[IMU][DEBUG]:  Restore sram data...
osAppInit
recvSerdesCfg[0][0]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][1]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][2]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][3]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][4]serdesMode = 3, bandWidth = 4, GenSpeed = 2, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][5]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][6]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[7] bandWidth is X16!
recvSerdesCfg[0][7]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[8] bandWidth is X16!
recvSerdesCfg[0][8]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][9]serdesMode = 1, bandWidth = 3, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[10] bandWidth is X16!
recvSerdesCfg[0][10]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][0]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][1]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][2]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][3]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][4]serdesMode = 1, bandWidth = 3, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][5]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][6]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[7] bandWidth is X16!
recvSerdesCfg[1][7]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[8] bandWidth is X16!
recvSerdesCfg[1][8]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][9]serdesMode = 4, bandWidth = 4, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[10] bandWidth is X16!
recvSerdesCfg[1][10]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
SerdesDataStruct size = 7
[TianChiGetNicTypeFromCpld][241L] ExecuteCPLDSmcCmd:5
[SetTianChiNicType] Nic 0 Type: 0x0
[TianChiGetNicTypeFromCpld][241L] ExecuteCPLDSmcCmd:5
[SetTianChiNicType] Nic 1 Type: 0x0
[3.511]Normal version.
[InterruptRegister]:[395L]id = 65
[SIWInterruptInit]:[151L]id:65, init done!
[InterruptRegister]:[395L]id = 67
[InterruptRegister]:[395L]id = 69
[IpmbInterruptInit]:[262L]id:69
[InterruptRegister]:[395L]id = 71
[Scmi0InterruptInit]:[25L]id:71, init done!
[InterruptRegister]:[395L]id = 72
[Scmi1InterruptInit]:[38L]id:72, init done!
[InterruptRegister]:[395L]id = 76
[InterruptRegister]:[395L]id = 78
[TotemResetInit]:[70L]id:78, init done!
[InterruptRegister]:[395L]id = 83
[InterruptRegister]:[395L]id = 275
[InterruptRegister]:[395L]id = 299
[InterruptRegister]:[395L]id = 116
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x0 Clear done
[InterruptRegister]:[395L]id = 117
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x0 Clear done
[InterruptRegister]:[395L]id = 134
[InterruptRegister]:[395L]id = 96
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x8000000 Clear done
[InterruptRegister]:[395L]id = 97
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x8000000 Clear done
[InterruptRegister]:[395L]id = 114
[InterruptRegister]:[395L]id = 256
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt0RasIntClear]:[259L]nimbusBase 0x0 clear done
[InterruptRegister]:[395L]id = 257
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt1RasIntClear]:[529L]nimbusBase 0x0 Clear done
[InterruptRegister]:[395L]id = 258
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt2RasIntClear]:[638L]nimbusBase 0x0 Clear done
[InterruptRegister]:[395L]id = 259
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusHacRasIntClear]:[311L]NimbusHacRasIntClear done
[InterruptRegister]:[395L]id = 260
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusNicRasIntClear]:[466L]nimbusBase 0x0 Clear done
[InterruptRegister]:[395L]id = 261
[NimbusPCIeRasIntClear]:[662L]NimbusBase 0x0 Clear Start...
[NimbusPCIeRasIntClear]:[673L]NimbusBase 0x0 Clear done!
[InterruptRegister]:[395L]id = 156
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 157
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 174
[InterruptRegister]:[395L]id = 136
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x4008000000 Clear done
[InterruptRegister]:[395L]id = 137
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x4008000000 Clear done
[InterruptRegister]:[395L]id = 154
[InterruptRegister]:[395L]id = 280
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt0RasIntClear]:[259L]nimbusBase 0x4000000000 clear done
[InterruptRegister]:[395L]id = 281
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt1RasIntClear]:[529L]nimbusBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 282
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt2RasIntClear]:[638L]nimbusBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 283
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusHacRasIntClear]:[311L]NimbusHacRasIntClear done
[InterruptRegister]:[395L]id = 284
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusNicRasIntClear]:[466L]nimbusBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 285
[NimbusPCIeRasIntClear]:[662L]NimbusBase 0x4000000000 Clear Start...
[NimbusPCIeRasIntClear]:[673L]NimbusBase 0x4000000000 Clear done!
Cer Initialization start...
[IMU][DEBUG]:  CER_CFG_BD_ENDIAN_ADDR is 0x3
[IMU][DEBUG]:  OUT STANDING is 0x4040
[IMU][DEBUG]:  OUT STANDING after set is 0x140
Cer Initialization done.
[IMU] I2C Initialization start...
[IMU] I2cDealNimbusException secket:0
[IMU] Set I2C4 ----> IPMB mode(default), Set I2C5 ----> I2C mode Success.
[IMU][DEBUG]:  Start init I2C on Address: [0x210050000].
[IMU][DEBUG]:  I2C on Address: [0x210050000] init Succed.
[IMU] Set I2C5 to NORMAL mode.
[IMU] I2C Initialization done!
[IMU] Scmi channels Initialization done!
SIW Initialization Starting...

Enable SIW Debug interface ...
[IMU][DEBUG]:  ES.IMU.SIW.006 SC_SIW_STAT register value is 0x8000.
SIW bypass disabled.
SIW Initialization Done.

[IMU] MiscConfig Start.
[IMU][DEBUG]:  DDRC_CFG_STADAT before config 0x0.
[IMU][DEBUG]:  DDRC_CFG_STADAT after config 0x40000000.
[IMU] Misc Config Done.
[IMU] Gpio MUX Config Done.
[IMU] N_CATERR Gpio MUX Config Done.
[IMU][DEBUG]:  CPU_cluster 0x5a00 is 0xff, hotreset is 0x0
TotemPll0InitCs nodeId:3
TotemPll0InitCs nodeId:1
SllcSetBand isHigh:1
SpiTpmRead ret: 0x0, detect = 0x0
SpiTpmRead ret: 0x0, didVid = 0x0
[IMU][ERROR]:  TPM is not detected
[IMU][ERROR]:  Tpm init err, 0x1
[IMU][DEBUG]:  Offset 0x800000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
 IMU compilation script 
IMU start to measure sec.
[IMU][ERROR]:  Unsupported trusted module
TPM Measure UEFI SEC fail, 0x1
[IMU][DEBUG]:  Offset 0x400000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
[IMU][DEBUG]:  Offset 0x90000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
It's not secure boot
TotemPll0DeInitCs nodeId:1
TotemPll0DeInitCs nodeId:3
SllcSetBand isHigh:0
base: 0x98200000
Ap is booting up, status: 0xee
[IMU][DEBUG]:  Offset 0x890000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
IMU start to measure Fvmain_compact and TF.
[IMU][ERROR]:  Unsupported trusted module
TPM Measure Uefi and TF fail, 0x1
IMU start to measure certificate and HD.
[IMU][ERROR]:  Unsupported trusted module
TPM Measure Certificate and HD fail, 0x1
[SetSkipTrainingFlag]21007f024:1620a5a2
[IMU] Watchdog Initialization done!
cpu 0 entering scheduler
[IMU] Chip: 0 Totem-B Fabric sub T-sensor setup ok!
[IMU] Chip: 0 Totem-B Sys sub T-sensor setup ok!
[IMU] Chip: 0 Totem-A Fabric sub T-sensor setup ok!
[IMU] Chip: 0 Totem-A Sys T-sensor setup ok!
[IMU] Chip: 0 Nimbus T-sensor setup ok!
IPMB initialization Start...
IPMB module clock set done.
IPMB Rx FIFO clear empty.
IPMB initialization Done.
[GetInitSendNumber]:[2142]semaphore create init number = 0!
cfg=110005 g_mctpCount=4
mctp_dev[0] enable=1 mode=1
mctp_dev[1] enable=0 mode=0
mctp_dev[2] enable=1 mode=1
mctp_dev[3] enable=0 mode=0
mctp_loop_task Create Success
HardWare Send IPMI Errorr regValue = 0x8 !!!!
Send process recive sto !!!!

[extInt0Init]:[65L]

[extInt0Init]:[69L]
Core Number: 0x40
Enable scmi int done
mctp loop task start.
Ras Handle task start.
[IpmiMsgGetManufactureid][135]Gotted ManufactureId:db 07 00
pwr cap[0]: 0, 63
pwr cap[1]: f, 27
SetupCfg  :
EnFdmSupport:            0x1
DdrRefreshRate:          0x0
PowerESaving:            0x0
HotPlug:                 0x1
ProcessorFlexibleRatio:  0x1a
CoreIsolateOnlineFlag:   0x0
EnRasSupport:            0x1
AdvanceDeviceCorrection: 0x0
PatrolScrubDuration:     0x18
X8MisCorrEn:             0x0
PowerOnTime:             0xa
DimmTime:                0xa
PageIsolation:           0x0
Mem2BitErrCorrEn:        0x1
pwr cap[2]: 1, 3
[24.920]Real time now:  2026/04/29, 21:01:03
[24.921]InitialCntTime = 24
[25.040][IMU] System DDR Init Done!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x56 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x56 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x56 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x56 DRAM Width failed
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntInit done
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntInit done
[NimbusMgmt0IntInit]:[233L]NimbusMgmt0IntInit done
[NimbusMgmt1IntInit]:[499L]
[NimbusMgmt2IntInit]:[626L]NimbusMgmt2IntICppcShareMem: 0x44000000
nit done
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntInit done
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntInit done
[NimbusMgmt0IntInit]:[233L]NimbusMgmt0IntInit done
[NimbusMgmt1IntInit]:[499L]
[NimbusMgmt2IntInit]:[626L]NimbusMgmt2IntInit done
[IMU][DEBUG]:  Offset 0x400000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
[IMU][DEBUG]:  Offset 0xfc0000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
registry filesize:0x31cb

[IMU][DEBUG]:  Offset 0xfd8000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU[IMU][ERROR]:  Th][DEBUG]:  FlashIndex ie response code is abnos 0x0
[IMU][DEBUG]:  Crmal 0xd6.
S is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
version:
Welcome to the IMU Firmware!
IMU Firmware version 6.65.0
LiteOS version 5.0.0
[IMU][ERROR]:  IMU reset 0
[2.248]IMU System Timer setup OK!
[2.251][IMU] lbc Config Done.
[2.256]CpuType: 0
[2.256]IsHi1620S: 0
BoardType: 0xffffffff
[2.261]base: 0x90b00000
GetV167Flag = 0x0
SFC Initialization Start...
[GetDeviceId]:[384L]SFC Cs 0 detected ID[0x1860c8]!
[GetDeviceId]:[384L]SFC Cs 1 detected ID[0x0]!
[IMU][ERROR]:  [CollectSpiFlash]:[411] Don't support the flash, Cs[1] ID[0x0]!!
System supported 1 Flash.
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1811] Spi Cs 0
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1823] Before config value 0x80800300
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1831] After config value 0x80800300
SFC Initialization Done
It is NS boot!!!
boot from L2!!!
[2.307]reboot time:0
[CheckAllTrainingStatus]:[1495L] Idx0 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx1 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx2 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx3 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx4 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx5 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx6 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx7 HllcIdx0 read: 30000f 
when compile IMU, have to use parameter 'bit', 1024[2.356][CheckAllTrainingStatus]Chip:0
[CheckAllTrainingStatus]:[1495L] Idx0 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx1 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx2 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx3 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx4 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx5 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx6 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx7 HllcIdx0 read: 30000f 
when compile IMU, have to use parameter 'bit', 2048[2.407][CheckAllTrainingStatus]Chip:1
[2.411]ChipNum: 2
TotemNum: 4
NimbusNum: 2
[0]1.
[1]3.
[2]5.
[3]7.
[IMU][DEBUG]:  Back sram data...
Socket=2
dieId=0x1
EfuseBase=0x98380000
efuse=0x0
DieId=1
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x3
EfuseBase=0x90380000
efuse=0x0
DieId=3
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x5
EfuseBase=0x4098380000
efuse=0x0
DieId=5
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x7
EfuseBase=0x4090380000
efuse=0x0
DieId=7
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
[IMU][DEBUG]:  Restore sram data...
osAppInit
recvSerdesCfg[0][0]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][1]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][2]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][3]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][4]serdesMode = 3, bandWidth = 4, GenSpeed = 2, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][5]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][6]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[7] bandWidth is X16!
recvSerdesCfg[0][7]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[8] bandWidth is X16!
recvSerdesCfg[0][8]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][9]serdesMode = 1, bandWidth = 3, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[10] bandWidth is X16!
recvSerdesCfg[0][10]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][0]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][1]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][2]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][3]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][4]serdesMode = 1, bandWidth = 3, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][5]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][6]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[7] bandWidth is X16!
recvSerdesCfg[1][7]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[8] bandWidth is X16!
recvSerdesCfg[1][8]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][9]serdesMode = 4, bandWidth = 4, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[10] bandWidth is X16!
recvSerdesCfg[1][10]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
SerdesDataStruct size = 7
[TianChiGetNicTypeFromCpld][241L] ExecuteCPLDSmcCmd:5
[SetTianChiNicType] Nic 0 Type: 0x0
[TianChiGetNicTypeFromCpld][241L] ExecuteCPLDSmcCmd:5
[SetTianChiNicType] Nic 1 Type: 0x0
[3.511]Normal version.
[InterruptRegister]:[395L]id = 65
[SIWInterruptInit]:[151L]id:65, init done!
[InterruptRegister]:[395L]id = 67
[InterruptRegister]:[395L]id = 69
[IpmbInterruptInit]:[262L]id:69
[InterruptRegister]:[395L]id = 71
[Scmi0InterruptInit]:[25L]id:71, init done!
[InterruptRegister]:[395L]id = 72
[Scmi1InterruptInit]:[38L]id:72, init done!
[InterruptRegister]:[395L]id = 76
[InterruptRegister]:[395L]id = 78
[TotemResetInit]:[70L]id:78, init done!
[InterruptRegister]:[395L]id = 83
[InterruptRegister]:[395L]id = 275
[InterruptRegister]:[395L]id = 299
[InterruptRegister]:[395L]id = 116
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x0 Clear done
[InterruptRegister]:[395L]id = 117
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x0 Clear done
[InterruptRegister]:[395L]id = 134
[InterruptRegister]:[395L]id = 96
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x8000000 Clear done
[InterruptRegister]:[395L]id = 97
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x8000000 Clear done
[InterruptRegister]:[395L]id = 114
[InterruptRegister]:[395L]id = 256
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt0RasIntClear]:[259L]nimbusBase 0x0 clear done
[InterruptRegister]:[395L]id = 257
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt1RasIntClear]:[529L]nimbusBase 0x0 Clear done
[InterruptRegister]:[395L]id = 258
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt2RasIntClear]:[638L]nimbusBase 0x0 Clear done
[InterruptRegister]:[395L]id = 259
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusHacRasIntClear]:[311L]NimbusHacRasIntClear done
[InterruptRegister]:[395L]id = 260
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusNicRasIntClear]:[466L]nimbusBase 0x0 Clear done
[InterruptRegister]:[395L]id = 261
[NimbusPCIeRasIntClear]:[662L]NimbusBase 0x0 Clear Start...
[NimbusPCIeRasIntClear]:[673L]NimbusBase 0x0 Clear done!
[InterruptRegister]:[395L]id = 156
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 157
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 174
[InterruptRegister]:[395L]id = 136
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x4008000000 Clear done
[InterruptRegister]:[395L]id = 137
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x4008000000 Clear done
[InterruptRegister]:[395L]id = 154
[InterruptRegister]:[395L]id = 280
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt0RasIntClear]:[259L]nimbusBase 0x4000000000 clear done
[InterruptRegister]:[395L]id = 281
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt1RasIntClear]:[529L]nimbusBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 282
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt2RasIntClear]:[638L]nimbusBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 283
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusHacRasIntClear]:[311L]NimbusHacRasIntClear done
[InterruptRegister]:[395L]id = 284
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusNicRasIntClear]:[466L]nimbusBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 285
[NimbusPCIeRasIntClear]:[662L]NimbusBase 0x4000000000 Clear Start...
[NimbusPCIeRasIntClear]:[673L]NimbusBase 0x4000000000 Clear done!
Cer Initialization start...
[IMU][DEBUG]:  CER_CFG_BD_ENDIAN_ADDR is 0x3
[IMU][DEBUG]:  OUT STANDING is 0x4040
[IMU][DEBUG]:  OUT STANDING after set is 0x140
Cer Initialization done.
[IMU] I2C Initialization start...
[IMU] I2cDealNimbusException secket:0
[IMU] Set I2C4 ----> IPMB mode(default), Set I2C5 ----> I2C mode Success.
[IMU][DEBUG]:  Start init I2C on Address: [0x210050000].
[IMU][DEBUG]:  I2C on Address: [0x210050000] init Succed.
[IMU] Set I2C5 to NORMAL mode.
[IMU] I2C Initialization done!
[IMU] Scmi channels Initialization done!
SIW Initialization Starting...

Enable SIW Debug interface ...
[IMU][DEBUG]:  ES.IMU.SIW.006 SC_SIW_STAT register value is 0x8000.
SIW bypass disabled.
SIW Initialization Done.

[IMU] MiscConfig Start.
[IMU][DEBUG]:  DDRC_CFG_STADAT before config 0x0.
[IMU][DEBUG]:  DDRC_CFG_STADAT after config 0x40000000.
[IMU] Misc Config Done.
[IMU] Gpio MUX Config Done.
[IMU] N_CATERR Gpio MUX Config Done.
[IMU][DEBUG]:  CPU_cluster 0x5a00 is 0xff, hotreset is 0x0
TotemPll0InitCs nodeId:3
TotemPll0InitCs nodeId:1
SllcSetBand isHigh:1
SpiTpmRead ret: 0x0, detect = 0x0
SpiTpmRead ret: 0x0, didVid = 0x0
[IMU][ERROR]:  TPM is not detected
[IMU][ERROR]:  Tpm init err, 0x1
[IMU][DEBUG]:  Offset 0x800000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
 IMU compilation script 
IMU start to measure sec.
[IMU][ERROR]:  Unsupported trusted module
TPM Measure UEFI SEC fail, 0x1
[IMU][DEBUG]:  Offset 0x400000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
[IMU][DEBUG]:  Offset 0x90000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
It's not secure boot
TotemPll0DeInitCs nodeId:1
TotemPll0DeInitCs nodeId:3
SllcSetBand isHigh:0
base: 0x98200000
Ap is booting up, status: 0xee
[IMU][DEBUG]:  Offset 0x890000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
IMU start to measure Fvmain_compact and TF.
[IMU][ERROR]:  Unsupported trusted module
TPM Measure Uefi and TF fail, 0x1
IMU start to measure certificate and HD.
[IMU][ERROR]:  Unsupported trusted module
TPM Measure Certificate and HD fail, 0x1
[SetSkipTrainingFlag]21007f024:1620a5a2
[IMU] Watchdog Initialization done!
cpu 0 entering scheduler
[IMU] Chip: 0 Totem-B Fabric sub T-sensor setup ok!
[IMU] Chip: 0 Totem-B Sys sub T-sensor setup ok!
[IMU] Chip: 0 Totem-A Fabric sub T-sensor setup ok!
[IMU] Chip: 0 Totem-A Sys T-sensor setup ok!
[IMU] Chip: 0 Nimbus T-sensor setup ok!
IPMB initialization Start...
IPMB module clock set done.
IPMB Rx FIFO clear empty.
IPMB initialization Done.
[GetInitSendNumber]:[2142]semaphore create init number = 0!
cfg=110005 g_mctpCount=4
mctp_dev[0] enable=1 mode=1
mctp_dev[1] enable=0 mode=0
mctp_dev[2] enable=1 mode=1
mctp_dev[3] enable=0 mode=0
mctp_loop_task Create Success
HardWare Send IPMI Errorr regValue = 0x8 !!!!
Send process recive sto !!!!

[extInt0Init]:[65L]

[extInt0Init]:[69L]
Core Number: 0x40
Enable scmi int done
mctp loop task start.
Ras Handle task start.
[IpmiMsgGetManufactureid][135]Gotted ManufactureId:db 07 00
pwr cap[0]: 0, 63
SetupCfg  :
EnFdmSupport:            0x1
DdrRefreshRate:          0x0
PowerESaving:            0x0
HotPlug:                 0x1
ProcessorFlexibleRatio:  0x1a
CoreIsolateOnlineFlag:   0x0
EnRasSupport:            0x1
AdvanceDeviceCorrection: 0x0
PatrolScrubDuration:     0x18
X8MisCorrEn:             0x0
PowerOnTime:             0xa
DimmTime:                0xa
PageIsolation:           0x0
Mem2BitErrCorrEn:        0x1
pwr cap[1]: f, 27
pwr cap[2]: 1, 3
[24.904]Real time now:  2026/04/29, 21:06:13
[24.905]InitialCntTime = 24
[25.024][IMU] System DDR Init Done!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x56 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x56 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x56 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  SCppcShareMem: 0x44000000
ocket 1 I2c port 0 read addr 0x56 DRAM Width failed
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntInit done
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntInit done
[NimbusMgmt0IntInit]:[233L]NimbusMgmt0IntInit done
[NimbusMgmt1IntInit]:[499L]
[NimbusMgmt2IntInit]:[626L]NimbusMgmt2IntInit done
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntInit done
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntInit done
[NimbusMgmt0IntInit]:[233L]NimbusMgmt0IntInit done
[NimbusMgmt1IntInit]:[499L]
[NimbusMgmt2IntInit]:[626L]NimbusMgmt2IntInit done
[IMU][DEBUG]:  Offset 0x400000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
[IMU][DEBUG]:  Offset 0xfc0000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
registry filesize:0x31cb

[IMU][DEBUG]:  Offset 0xfd8000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[I[IMU][ERROR]:  The respoMU][DEBUG]:  FlashIndexnse code is abnormal 0x is 0x0
[IMU][DEBUG]: d6.
 CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
version:
Welcome to the IMU Firmware!
IMU Firmware version 6.65.0
LiteOS version 5.0.0
[IMU][ERROR]:  IMU reset 0
[2.248]IMU System Timer setup OK!
[2.251][IMU] lbc Config Done.
[2.256]CpuType: 0
[2.256]IsHi1620S: 0
BoardType: 0xffffffff
[2.261]base: 0x90b00000
GetV167Flag = 0x0
SFC Initialization Start...
[GetDeviceId]:[384L]SFC Cs 0 detected ID[0x1860c8]!
[GetDeviceId]:[384L]SFC Cs 1 detected ID[0x0]!
[IMU][ERROR]:  [CollectSpiFlash]:[411] Don't support the flash, Cs[1] ID[0x0]!!
System supported 1 Flash.
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1811] Spi Cs 0
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1823] Before config value 0x80800300
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1831] After config value 0x80800300
SFC Initialization Done
It is NS boot!!!
boot from L2!!!
[2.307]reboot time:0
[CheckAllTrainingStatus]:[1495L] Idx0 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx1 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx2 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx3 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx4 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx5 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx6 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx7 HllcIdx0 read: 30000f 
when compile IMU, have to use parameter 'bit', 1024[2.356][CheckAllTrainingStatus]Chip:0
[CheckAllTrainingStatus]:[1495L] Idx0 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx1 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx2 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx3 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx4 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx5 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx6 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx7 HllcIdx0 read: 30000f 
when compile IMU, have to use parameter 'bit', 2048[2.407][CheckAllTrainingStatus]Chip:1
[2.411]ChipNum: 2
TotemNum: 4
NimbusNum: 2
[0]1.
[1]3.
[2]5.
[3]7.
[IMU][DEBUG]:  Back sram data...
Socket=2
dieId=0x1
EfuseBase=0x98380000
efuse=0x0
DieId=1
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x3
EfuseBase=0x90380000
efuse=0x0
DieId=3
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x5
EfuseBase=0x4098380000
efuse=0x0
DieId=5
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x7
EfuseBase=0x4090380000
efuse=0x0
DieId=7
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
[IMU][DEBUG]:  Restore sram data...
osAppInit
recvSerdesCfg[0][0]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][1]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][2]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][3]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][4]serdesMode = 3, bandWidth = 4, GenSpeed = 2, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][5]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][6]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[7] bandWidth is X16!
recvSerdesCfg[0][7]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[8] bandWidth is X16!
recvSerdesCfg[0][8]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][9]serdesMode = 1, bandWidth = 3, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[10] bandWidth is X16!
recvSerdesCfg[0][10]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][0]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][1]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][2]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][3]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][4]serdesMode = 1, bandWidth = 3, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][5]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][6]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[7] bandWidth is X16!
recvSerdesCfg[1][7]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[8] bandWidth is X16!
recvSerdesCfg[1][8]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][9]serdesMode = 4, bandWidth = 4, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[10] bandWidth is X16!
recvSerdesCfg[1][10]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
SerdesDataStruct size = 7
[TianChiGetNicTypeFromCpld][241L] ExecuteCPLDSmcCmd:5
[SetTianChiNicType] Nic 0 Type: 0x0
[TianChiGetNicTypeFromCpld][241L] ExecuteCPLDSmcCmd:5
[SetTianChiNicType] Nic 1 Type: 0x0
[3.510]Normal version.
[InterruptRegister]:[395L]id = 65
[SIWInterruptInit]:[151L]id:65, init done!
[InterruptRegister]:[395L]id = 67
[InterruptRegister]:[395L]id = 69
[IpmbInterruptInit]:[262L]id:69
[InterruptRegister]:[395L]id = 71
[Scmi0InterruptInit]:[25L]id:71, init done!
[InterruptRegister]:[395L]id = 72
[Scmi1InterruptInit]:[38L]id:72, init done!
[InterruptRegister]:[395L]id = 76
[InterruptRegister]:[395L]id = 78
[TotemResetInit]:[70L]id:78, init done!
[InterruptRegister]:[395L]id = 83
[InterruptRegister]:[395L]id = 275
[InterruptRegister]:[395L]id = 299
[InterruptRegister]:[395L]id = 116
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x0 Clear done
[InterruptRegister]:[395L]id = 117
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x0 Clear done
[InterruptRegister]:[395L]id = 134
[InterruptRegister]:[395L]id = 96
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x8000000 Clear done
[InterruptRegister]:[395L]id = 97
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x8000000 Clear done
[InterruptRegister]:[395L]id = 114
[InterruptRegister]:[395L]id = 256
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt0RasIntClear]:[259L]nimbusBase 0x0 clear done
[InterruptRegister]:[395L]id = 257
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt1RasIntClear]:[529L]nimbusBase 0x0 Clear done
[InterruptRegister]:[395L]id = 258
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt2RasIntClear]:[638L]nimbusBase 0x0 Clear done
[InterruptRegister]:[395L]id = 259
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusHacRasIntClear]:[311L]NimbusHacRasIntClear done
[InterruptRegister]:[395L]id = 260
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusNicRasIntClear]:[466L]nimbusBase 0x0 Clear done
[InterruptRegister]:[395L]id = 261
[NimbusPCIeRasIntClear]:[662L]NimbusBase 0x0 Clear Start...
[NimbusPCIeRasIntClear]:[673L]NimbusBase 0x0 Clear done!
[InterruptRegister]:[395L]id = 156
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 157
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 174
[InterruptRegister]:[395L]id = 136
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x4008000000 Clear done
[InterruptRegister]:[395L]id = 137
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x4008000000 Clear done
[InterruptRegister]:[395L]id = 154
[InterruptRegister]:[395L]id = 280
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt0RasIntClear]:[259L]nimbusBase 0x4000000000 clear done
[InterruptRegister]:[395L]id = 281
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt1RasIntClear]:[529L]nimbusBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 282
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt2RasIntClear]:[638L]nimbusBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 283
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusHacRasIntClear]:[311L]NimbusHacRasIntClear done
[InterruptRegister]:[395L]id = 284
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusNicRasIntClear]:[466L]nimbusBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 285
[NimbusPCIeRasIntClear]:[662L]NimbusBase 0x4000000000 Clear Start...
[NimbusPCIeRasIntClear]:[673L]NimbusBase 0x4000000000 Clear done!
Cer Initialization start...
[IMU][DEBUG]:  CER_CFG_BD_ENDIAN_ADDR is 0x3
[IMU][DEBUG]:  OUT STANDING is 0x4040
[IMU][DEBUG]:  OUT STANDING after set is 0x140
Cer Initialization done.
[IMU] I2C Initialization start...
[IMU] I2cDealNimbusException secket:0
[IMU] Set I2C4 ----> IPMB mode(default), Set I2C5 ----> I2C mode Success.
[IMU][DEBUG]:  Start init I2C on Address: [0x210050000].
[IMU][DEBUG]:  I2C on Address: [0x210050000] init Succed.
[IMU] Set I2C5 to NORMAL mode.
[IMU] I2C Initialization done!
[IMU] Scmi channels Initialization done!
SIW Initialization Starting...

Enable SIW Debug interface ...
[IMU][DEBUG]:  ES.IMU.SIW.006 SC_SIW_STAT register value is 0x8000.
SIW bypass disabled.
SIW Initialization Done.

[IMU] MiscConfig Start.
[IMU][DEBUG]:  DDRC_CFG_STADAT before config 0x0.
[IMU][DEBUG]:  DDRC_CFG_STADAT after config 0x40000000.
[IMU] Misc Config Done.
[IMU] Gpio MUX Config Done.
[IMU] N_CATERR Gpio MUX Config Done.
[IMU][DEBUG]:  CPU_cluster 0x5a00 is 0xff, hotreset is 0x0
TotemPll0InitCs nodeId:3
TotemPll0InitCs nodeId:1
SllcSetBand isHigh:1
SpiTpmRead ret: 0x0, detect = 0x0
SpiTpmRead ret: 0x0, didVid = 0x0
[IMU][ERROR]:  TPM is not detected
[IMU][ERROR]:  Tpm init err, 0x1
[IMU][DEBUG]:  Offset 0x800000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
 IMU compilation script 
IMU start to measure sec.
[IMU][ERROR]:  Unsupported trusted module
TPM Measure UEFI SEC fail, 0x1
[IMU][DEBUG]:  Offset 0x400000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
[IMU][DEBUG]:  Offset 0x90000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
It's not secure boot
TotemPll0DeInitCs nodeId:1
TotemPll0DeInitCs nodeId:3
SllcSetBand isHigh:0
base: 0x98200000
Ap is booting up, status: 0xee
[IMU][DEBUG]:  Offset 0x890000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
IMU start to measure Fvmain_compact and TF.
[IMU][ERROR]:  Unsupported trusted module
TPM Measure Uefi and TF fail, 0x1
IMU start to measure certificate and HD.
[IMU][ERROR]:  Unsupported trusted module
TPM Measure Certificate and HD fail, 0x1
[SetSkipTrainingFlag]21007f024:1620a5a2
[IMU] Watchdog Initialization done!
cpu 0 entering scheduler
[IMU] Chip: 0 Totem-B Fabric sub T-sensor setup ok!
[IMU] Chip: 0 Totem-B Sys sub T-sensor setup ok!
[IMU] Chip: 0 Totem-A Fabric sub T-sensor setup ok!
[IMU] Chip: 0 Totem-A Sys T-sensor setup ok!
[IMU] Chip: 0 Nimbus T-sensor setup ok!
IPMB initialization Start...
IPMB module clock set done.
IPMB Rx FIFO clear empty.
IPMB initialization Done.
[GetInitSendNumber]:[2142]semaphore create init number = 0!
cfg=110005 g_mctpCount=4
mctp_dev[0] enable=1 mode=1
mctp_dev[1] enable=0 mode=0
mctp_dev[2] enable=1 mode=1
mctp_dev[3] enable=0 mode=0
mctp_loop_task Create Success
HardWare Send IPMI Errorr regValue = 0x8 !!!!
Send process recive sto !!!!

[extInt0Init]:[65L]

[extInt0Init]:[69L]
Core Number: 0x40
Enable scmi int done
mctp loop task start.
Ras Handle task start.
[IpmiMsgGetManufactureid][135]Gotted ManufactureId:db 07 00
pwr cap[0]: 0, 63
pwr cap[1]: f, 27
SetupCfg  :
EnFdmSupport:            0x1
DdrRefreshRate:          0x0
PowerESaving:            0x0
HotPlug:                 0x1
ProcessorFlexibleRatio:  0x1a
CoreIsolateOnlineFlag:   0x0
EnRasSupport:            0x1
AdvanceDeviceCorrection: 0x0
PatrolScrubDuration:     0x18
X8MisCorrEn:             0x0
PowerOnTime:             0xa
DimmTime:                0xa
PageIsolation:           0x0
Mem2BitErrCorrEn:        0x1
pwr cap[2]: 1, 3
[24.831]Real time now:  2026/04/29, 21:11:22
[24.832]InitialCntTime = 24
[24.950][IMU] System DDR Init Done!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x56 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x56 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x56 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x56 DRAM Width failed
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntInit done
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntInit done
[NimbusMgmt0IntInit]:[233L]NimbusMgmt0IntInit done
[NimbusMgmt1IntInit]:[499L]
[NimbusMgmt2IntInit]:[626L]NimbusMgmt2IntInit done
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemCppcShareMem: 0x44000000
ScclIntInit]:[323L]TotemScclIntInit done
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntInit done
[NimbusMgmt0IntInit]:[233L]NimbusMgmt0IntInit done
[NimbusMgmt1IntInit]:[499L]
[NimbusMgmt2IntInit]:[626L]NimbusMgmt2IntInit done
[IMU][DEBUG]:  Offset 0x400000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
[IMU][DEBUG]:  Offset 0xfc0000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
registry filesize:0x31cb

[IMU][DEBUG]:  Offset 0xfd8000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0[IMU][ERROR]:  The 
[IMU][DEBUG]:  CS is response code is abnorm0x0
[IMU][DEBUG]:  [Sfal 0xd6.
cCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
version:
Welcome to the IMU Firmware!
IMU Firmware version 6.65.0
LiteOS version 5.0.0
[IMU][ERROR]:  IMU reset 0
[2.248]IMU System Timer setup OK!
[2.251][IMU] lbc Config Done.
[2.256]CpuType: 0
[2.256]IsHi1620S: 0
BoardType: 0xffffffff
[2.261]base: 0x90b00000
GetV167Flag = 0x0
SFC Initialization Start...
[GetDeviceId]:[384L]SFC Cs 0 detected ID[0x1860c8]!
[GetDeviceId]:[384L]SFC Cs 1 detected ID[0x0]!
[IMU][ERROR]:  [CollectSpiFlash]:[411] Don't support the flash, Cs[1] ID[0x0]!!
System supported 1 Flash.
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1811] Spi Cs 0
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1823] Before config value 0x80800300
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1831] After config value 0x80800300
SFC Initialization Done
It is NS boot!!!
boot from L2!!!
[2.307]reboot time:0
[CheckAllTrainingStatus]:[1495L] Idx0 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx1 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx2 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx3 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx4 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx5 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx6 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx7 HllcIdx0 read: 30000f 
when compile IMU, have to use parameter 'bit', 1024[2.356][CheckAllTrainingStatus]Chip:0
[CheckAllTrainingStatus]:[1495L] Idx0 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx1 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx2 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx3 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx4 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx5 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx6 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx7 HllcIdx0 read: 30000f 
when compile IMU, have to use parameter 'bit', 2048[2.407][CheckAllTrainingStatus]Chip:1
[2.411]ChipNum: 2
TotemNum: 4
NimbusNum: 2
[0]1.
[1]3.
[2]5.
[3]7.
[IMU][DEBUG]:  Back sram data...
Socket=2
dieId=0x1
EfuseBase=0x98380000
efuse=0x0
DieId=1
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x3
EfuseBase=0x90380000
efuse=0x0
DieId=3
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x5
EfuseBase=0x4098380000
efuse=0x0
DieId=5
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x7
EfuseBase=0x4090380000
efuse=0x0
DieId=7
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
[IMU][DEBUG]:  Restore sram data...
osAppInit
recvSerdesCfg[0][0]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][1]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][2]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][3]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][4]serdesMode = 3, bandWidth = 4, GenSpeed = 2, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][5]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][6]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[7] bandWidth is X16!
recvSerdesCfg[0][7]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[8] bandWidth is X16!
recvSerdesCfg[0][8]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][9]serdesMode = 1, bandWidth = 3, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[10] bandWidth is X16!
recvSerdesCfg[0][10]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][0]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][1]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][2]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][3]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][4]serdesMode = 1, bandWidth = 3, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][5]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][6]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[7] bandWidth is X16!
recvSerdesCfg[1][7]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[8] bandWidth is X16!
recvSerdesCfg[1][8]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][9]serdesMode = 4, bandWidth = 4, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[10] bandWidth is X16!
recvSerdesCfg[1][10]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
SerdesDataStruct size = 7
[TianChiGetNicTypeFromCpld][241L] ExecuteCPLDSmcCmd:5
[SetTianChiNicType] Nic 0 Type: 0x0
[TianChiGetNicTypeFromCpld][241L] ExecuteCPLDSmcCmd:5
[SetTianChiNicType] Nic 1 Type: 0x0
[3.510]Normal version.
[InterruptRegister]:[395L]id = 65
[SIWInterruptInit]:[151L]id:65, init done!
[InterruptRegister]:[395L]id = 67
[InterruptRegister]:[395L]id = 69
[IpmbInterruptInit]:[262L]id:69
[InterruptRegister]:[395L]id = 71
[Scmi0InterruptInit]:[25L]id:71, init done!
[InterruptRegister]:[395L]id = 72
[Scmi1InterruptInit]:[38L]id:72, init done!
[InterruptRegister]:[395L]id = 76
[InterruptRegister]:[395L]id = 78
[TotemResetInit]:[70L]id:78, init done!
[InterruptRegister]:[395L]id = 83
[InterruptRegister]:[395L]id = 275
[InterruptRegister]:[395L]id = 299
[InterruptRegister]:[395L]id = 116
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x0 Clear done
[InterruptRegister]:[395L]i
Welcome to the IMU Firmware!
IMU Firmware version 6.65.0
LiteOS version 5.0.0
[IMU][ERROR]:  IMU reset 0
[2.248]IMU System Timer setup OK!
[2.251][IMU] lbc Config Done.
[2.256]CpuType: 0
[2.256]IsHi1620S: 0
BoardType: 0xffffffff
[2.261]base: 0x90b00000
GetV167Flag = 0x0
SFC Initialization Start...
[GetDeviceId]:[384L]SFC Cs 0 detected ID[0x1860c8]!
[GetDeviceId]:[384L]SFC Cs 1 detected ID[0x0]!
[IMU][ERROR]:  [CollectSpiFlash]:[411] Don't support the flash, Cs[1] ID[0x0]!!
System supported 1 Flash.
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1811] Spi Cs 0
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1823] Before config value 0x80800300
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1831] After config value 0x80800300
SFC Initialization Done
It is NS boot!!!
boot from L2!!!
[2.307]reboot time:0
[CheckAllTrainingStatus]:[1495L] Idx0 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx1 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx2 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx3 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx4 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx5 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx6 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx7 HllcIdx0 read: 30000f 
when compile IMU, have to use parameter 'bit', 1024[2.356][CheckAllTrainingStatus]Chip:0
[CheckAllTrainingStatus]:[1495L] Idx0 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx1 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx2 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx3 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx4 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx5 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx6 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx7 HllcIdx0 read: 30000f 
when compile IMU, have to use parameter 'bit', 2048[2.407][CheckAllTrainingStatus]Chip:1
[2.411]ChipNum: 2
TotemNum: 4
NimbusNum: 2
[0]1.
[1]3.
[2]5.
[3]7.
[IMU][DEBUG]:  Back sram data...
Socket=2
dieId=0x1
EfuseBase=0x98380000
efuse=0x0
DieId=1
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x3
EfuseBase=0x90380000
efuse=0x0
DieId=3
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x5
EfuseBase=0x4098380000
efuse=0x0
DieId=5
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x7
EfuseBase=0x4090380000
efuse=0x0
DieId=7
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
[IMU][DEBUG]:  Restore sram data...
osAppInit
recvSerdesCfg[0][0]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 
Welcome to the IMU Firmware!
IMU Firmware version 6.65.0
LiteOS version 5.0.0
[IMU][ERROR]:  IMU reset 0
[2.248]IMU System Timer setup OK!
[2.251][IMU] lbc Config Done.
[2.256]CpuType: 0
[2.256]IsHi1620S: 0
BoardType: 0xffffffff
[2.261]base: 0x90b00000
GetV167Flag = 0x0
SFC Initialization Start...
[GetDeviceId]:[384L]SFC Cs 0 detected ID[0x1860c8]!
[GetDeviceId]:[384L]SFC Cs 1 detected ID[0x0]!
[IMU][ERROR]:  [CollectSpiFlash]:[411] Don't support the flash, Cs[1] ID[0x0]!!
System supported 1 Flash.
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1811] Spi Cs 0
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1823] Before config value 0x80800300
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1831] After config value 0x80800300
SFC Initialization Done
It is NS boot!!!
boot from L2!!!
[2.307]reboot time:0
[CheckAllTrainingStatus]:[1495L] Idx0 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx1 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx2 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx3 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx4 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx5 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx6 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx7 HllcIdx0 read: 30000f 
when compile IMU, have to use parameter 'bit', 1024[2.356][CheckAllTrainingStatus]Chip:0
[CheckAllTrainingStatus]:[1495L] Idx0 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx1 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx2 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx3 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx4 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx5 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx6 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx7 HllcIdx0 read: 30000f 
when compile IMU, have to use parameter 'bit', 2048[2.407][CheckAllTrainingStatus]Chip:1
[2.411]ChipNum: 2
TotemNum: 4
NimbusNum: 2
[0]1.
[1]3.
[2]5.
[3]7.
[IMU][DEBUG]:  Back sram data...
Socket=2
dieId=0x1
EfuseBase=0x98380000
efuse=0x0
DieId=1
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x3
EfuseBase=0x90380000
efuse=0x0
DieId=3
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x5
EfuseBase=0x4098380000
efuse=0x0
DieId=5
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x7
EfuseBase=0x4090380000
efuse=0x0
DieId=7
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
[IMU][DEBUG]:  Restore sram data...
osAppInit
recvSerdesCfg[0][0]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][1]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][2]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][3]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][4]serdesMode = 3, bandWidth = 4, GenSpeed = 2, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][5]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][6]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[7] bandWidth is X16!
recvSerdesCfg[0][7]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[8] bandWidth is X16!
recvSerdesCfg[0][8]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][9]serdesMode = 1, bandWidth = 3, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[10] bandWidth is X16!
recvSerdesCfg[0][10]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][0]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][1]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][2]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][3]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][4]serdesMode = 1, bandWidth = 3, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][5]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][6]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[7] bandWidth is X16!
recvSerdesCfg[1][7]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[8] bandWidth is X16!
recvSerdesCfg[1][8]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][9]serdesMode = 4, bandWidth = 4, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[10] bandWidth is X16!
recvSerdesCfg[1][10]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
SerdesDataStruct size = 7
[TianChiGetNicTypeFromCpld][241L] ExecuteCPLDSmcCmd:5
[SetTianChiNicType] Nic 0 Type: 0x0
[TianChiGetNicTypeFromCpld][241L] ExecuteCPLDSmcCmd:5
[SetTianChiNicType] Nic 1 Type: 0x0
[3.511]Normal version.
[InterruptRegister]:[395L]id = 65
[SIWInterruptInit]:[151L]id:65, init done!
[InterruptRegister]:[395L]id = 67
[InterruptRegister]:[395L]id = 69
[IpmbInterruptInit]:[262L]id:69
[InterruptRegister]:[395L]id = 71
[Scmi0InterruptInit]:[25L]id:71, init done!
[InterruptRegister]:[395L]id = 72
[Scmi1InterruptInit]:[38L]id:72, init done!
[InterruptRegister]:[395L]id = 76
[InterruptRegister]:[395L]id = 78
[TotemResetInit]:[70L]id:78, init done!
[InterruptRegister]:[395L]id = 83
[InterruptRegister]:[395L]id = 275
[InterruptRegister]:[395L]id = 299
[InterruptRegister]:[395L]id = 116
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x0 Clear done
[InterruptRegister]:[395L]id = 117
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x0 Clear done
[InterruptRegister]:[395L]id = 134
[InterruptRegister]:[395L]id = 96
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x8000000 Clear done
[InterruptRegister]:[395L]id = 97
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x8000000 Clear done
[InterruptRegister]:[395L]id = 114
[InterruptRegister]:[395L]id = 256
TYPE0: 0
TYPE1: 0
TYPE2:
Welcome to the IMU Firmware!
IMU Firmware version 6.65.0
LiteOS version 5.0.0
[IMU][ERROR]:  IMU reset 0
[2.248]IMU System Timer setup OK!
[2.251][IMU] lbc Config Done.
[2.256]CpuType: 0
[2.256]IsHi1620S: 0
BoardType: 0xffffffff
[2.261]base: 0x90b00000
GetV167Flag = 0x0
SFC Initialization Start...
[GetDeviceId]:[384L]SFC Cs 0 detected ID[0x1860c8]!
[GetDeviceId]:[384L]SFC Cs 1 detected ID[0x0]!
[IMU][ERROR]:  [CollectSpiFlash]:[411] Don't support the flash, Cs[1] ID[0x0]!!
System supported 1 Flash.
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1811] Spi Cs 0
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1823] Before config value 0x80800300
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1831] After config value 0x80800300
SFC Initialization Done
It is NS boot!!!
boot from L2!!!
[2.307]reboot time:0
[CheckAllTrainingStatus]:[1495L] Idx0 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx1 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx2 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx3 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx4 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx5 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx6 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx7 HllcIdx0 read: 30000f 
when compile IMU, have to use parameter 'bit', 1024[2.356][CheckAllTrainingStatus]Chip:0
[CheckAllTrainingStatus]:[1495L] Idx0 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx1 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx2 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx3 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx4 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx5 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx6 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx7 HllcIdx0 read: 30000f 
when compile IMU, have to use parameter 'bit', 2048[2.407][CheckAllTrainingStatus]Chip:1
[2.411]ChipNum: 2
TotemNum: 4
NimbusNum: 2
[0]1.
[1]3.
[2]5.
[3]7.
[IMU][DEBUG]:  Back sram data...
Socket=2
dieId=0x1
EfuseBase=0x98380000
efuse=0x0
DieId=1
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x3
EfuseBase=0x90380000
efuse=0x0
DieId=3
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x5
EfuseBase=0x4098380000
efuse=0x0
DieId=5
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x7
EfuseBase=0x4090380000
efuse=0x0
DieId=7
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
[IMU][DEBUG]:  Restore sram data...
osAppInit
recvSerdesCfg[0][0]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][1]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][2]serdesMode = 6, bandWi
Welcome to the IMU Firmware!
IMU Firmware version 6.65.0
LiteOS version 5.0.0
[IMU][ERROR]:  IMU reset 0
[2.248]IMU System Timer setup OK!
[2.251][IMU] lbc Config Done.
[2.256]CpuType: 0
[2.256]IsHi1620S: 0
BoardType: 0xffffffff
[2.261]base: 0x90b00000
GetV167Flag = 0x0
SFC Initialization Start...
[GetDeviceId]:[384L]SFC Cs 0 detected ID[0x1860c8]!
[GetDeviceId]:[384L]SFC Cs 1 detected ID[0x0]!
[IMU][ERROR]:  [CollectSpiFlash]:[411] Don't support the flash, Cs[1] ID[0x0]!!
System supported 1 Flash.
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1811] Spi Cs 0
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1823] Before config value 0x80800300
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1831] After config value 0x80800300
SFC Initialization Done
It is NS boot!!!
boot from L2!!!
[2.307]reboot time:0
[CheckAllTrainingStatus]:[1495L] Idx0 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx1 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx2 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx3 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx4 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx5 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx6 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx7 HllcIdx0 read: 30000f 
when compile IMU, have to use parameter 'bit', 1024[2.356][CheckAllTrainingStatus]Chip:0
[CheckAllTrainingStatus]:[1495L] Idx0 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx1 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx2 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx3 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx4 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx5 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx6 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx7 HllcIdx0 read: 30000f 
when compile IMU, have to use parameter 'bit', 2048[2.407][CheckAllTrainingStatus]Chip:1
[2.411]ChipNum: 2
TotemNum: 4
NimbusNum: 2
[0]1.
[1]3.
[2]5.
[3]7.
[IMU][DEBUG]:  Back sram data...
Socket=2
dieId=0x1
EfuseBase=0x98380000
efuse=0x0
DieId=1
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x3
EfuseBase=0x90380000
efuse=0x0
DieId=3
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x5
EfuseBase=0x4098380000
efuse=0x0
DieId=5
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x7
EfuseBase=0x4090380000
efuse=0x0
DieId=7
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
[IMU][DEBUG]:  Restore sram data...
osAppInit
recvSerdesCfg[0][0]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][1]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][2]serdesMode = 6, bandWi
Welcome to the IMU Firmware!
IMU Firmware version 6.65.0
LiteOS version 5.0.0
[IMU][ERROR]:  IMU reset 0
[2.248]IMU System Timer setup OK!
[2.251][IMU] lbc Config Done.
[2.256]CpuType: 0
[2.256]IsHi1620S: 0
BoardType: 0xffffffff
[2.261]base: 0x90b00000
GetV167Flag = 0x0
SFC Initialization Start...
[GetDeviceId]:[384L]SFC Cs 0 detected ID[0x1860c8]!
[GetDeviceId]:[384L]SFC Cs 1 detected ID[0x0]!
[IMU][ERROR]:  [CollectSpiFlash]:[411] Don't support the flash, Cs[1] ID[0x0]!!
System supported 1 Flash.
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1811] Spi Cs 0
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1823] Before config value 0x80800300
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1831] After config value 0x80800300
SFC Initialization Done
It is NS boot!!!
boot from L2!!!
[2.307]reboot time:0
[CheckAllTrainingStatus]:[1495L] Idx0 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx1 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx2 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx3 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx4 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx5 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx6 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx7 HllcIdx0 read: 30000f 
when compile IMU, have to use parameter 'bit', 1024[2.356][CheckAllTrainingStatus]Chip:0
[CheckAllTrainingStatus]:[1495L] Idx0 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx1 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx2 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx3 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx4 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx5 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx6 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx7 HllcIdx0 read: 30000f 
when compile IMU, have to use parameter 'bit', 2048[2.407][CheckAllTrainingStatus]Chip:1
[2.411]ChipNum: 2
TotemNum: 4
NimbusNum: 2
[0]1.
[1]3.
[2]5.
[3]7.
[IMU][DEBUG]:  Back sram data...
Socket=2
dieId=0x1
EfuseBase=0x98380000
efuse=0x0
DieId=1
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x3
EfuseBase=0x90380000
efuse=0x0
DieId=3
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x5
EfuseBase=0x4098380000
efuse=0x0
DieId=5
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x7
EfuseBase=0x4090380000
efuse=0x0
DieId=7
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
[IMU][DEBUG]:  Restore sram data...
osAppInit
recvSerdesCfg[0][0]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][1]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][2]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][3]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][4]serdesMode = 3, bandWidth = 4, GenSpeed = 2, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][5]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][6]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[7] bandWidth is X16!
recvSerdesCfg[0][7]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[8] bandWidth is X16!
recvSerdesCfg[0][8]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][9]serdesMode = 1, bandWidth = 3, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[10] bandWidth is X16!
recvSerdesCfg[0][10]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][0]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][1]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][2]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][3]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][4]serdesMode = 1, bandWidth = 3, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][5]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][6]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[7] bandWidth is X16!
recvSerdesCfg[1][7]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[8] bandWidth is X16!
recvSerdesCfg[1][8]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][9]serdesMode = 4, bandWidth = 4, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[10] bandWidth is X16!
recvSerdesCfg[1][10]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
SerdesDataStruct size = 7
[TianChiGetNicTypeFromCpld][241L] ExecuteCPLDSmcCmd:5
[SetTianChiNicType] Nic 0 Type: 0x0
[TianChiGetNicTypeFromCpld][241L] ExecuteCPLDSmcCmd:5
[SetTianChiNicType] Nic 1 Type: 0x0
[3.510]Normal version.
[InterruptRegister]:[395L]id = 65
[SIWInterruptInit]:[151L]id:65, init done!
[InterruptRegister]:[395L]id = 67
[InterruptRegister]:[395L]id = 69
[IpmbInterruptInit]:[262L]id:69
[InterruptRegister]:[395L]id = 71
[Scmi0InterruptInit]:[25L]id:71, init done!
[InterruptRegister]:[395L]id = 72
[Scmi1InterruptInit]:[38L]id:72, init done!
[InterruptRegister]:[395L]id = 76
[InterruptRegister]:[395L]id = 78
[TotemResetInit]:[70L]id:78, init done!
[InterruptReg
Welcome to the IMU Firmware!
IMU Firmware version 6.65.0
LiteOS version 5.0.0
[IMU][ERROR]:  IMU reset 0
[2.248]IMU System Timer setup OK!
[2.251][IMU] lbc Config Done.
[2.256]CpuType: 0
[2.256]IsHi1620S: 0
BoardType: 0xffffffff
[2.261]base: 0x90b00000
GetV167Flag = 0x0
SFC Initialization Start...
[GetDeviceId]:[384L]SFC Cs 0 detected ID[0x1860c8]!
[GetDeviceId]:[384L]SFC Cs 1 detected ID[0x0]!
[IMU][ERROR]:  [CollectSpiFlash]:[411] Don't support the flash, Cs[1] ID[0x0]!!
System supported 1 Flash.
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1811] Spi Cs 0
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1823] Before config value 0x80800300
[IMU][DEBUG]:  [SfcConfigInterfaceMode][1831] After config value 0x80800300
SFC Initialization Done
It is NS boot!!!
boot from L2!!!
[2.307]reboot time:0
[CheckAllTrainingStatus]:[1495L] Idx0 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx1 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx2 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx3 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx4 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx5 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx6 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx7 HllcIdx0 read: 30000f 
when compile IMU, have to use parameter 'bit', 1024[2.356][CheckAllTrainingStatus]Chip:0
[CheckAllTrainingStatus]:[1495L] Idx0 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx1 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx2 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx3 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx4 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx5 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx6 HllcIdx0 read: 30000f 
[CheckAllTrainingStatus]:[1495L] Idx7 HllcIdx0 read: 30000f 
when compile IMU, have to use parameter 'bit', 2048[2.407][CheckAllTrainingStatus]Chip:1
[2.411]ChipNum: 2
TotemNum: 4
NimbusNum: 2
[0]1.
[1]3.
[2]5.
[3]7.
[IMU][DEBUG]:  Back sram data...
Socket=2
dieId=0x1
EfuseBase=0x98380000
efuse=0x0
DieId=1
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x3
EfuseBase=0x90380000
efuse=0x0
DieId=3
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x5
EfuseBase=0x4098380000
efuse=0x0
DieId=5
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
dieId=0x7
EfuseBase=0x4090380000
efuse=0x0
DieId=7
L3d0 left Mbist
L3d0 right Mbist
L3d0 other mbist


L3d1 left Mbist
L3d1 right Mbist
L3d1 other mbist


L3d2 left Mbist
L3d2 right Mbist
L3d2 other mbist


L3d3 left Mbist
L3d3 right Mbist
L3d3 other mbist


L3T0  Mbist
L3T1  Mbist
L3T2  Mbist
L3T3  Mbist
L3T4  Mbist
L3T5  Mbist
L3T6  Mbist
L3T7  Mbist
[IMU][DEBUG]:  Restore sram data...
osAppInit
recvSerdesCfg[0][0]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][1]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][2]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][3]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][4]serdesMode = 3, bandWidth = 4, GenSpeed = 2, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][5]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][6]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[7] bandWidth is X16!
recvSerdesCfg[0][7]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[8] bandWidth is X16!
recvSerdesCfg[0][8]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[0][9]serdesMode = 1, bandWidth = 3, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[0]hilink[10] bandWidth is X16!
recvSerdesCfg[0][10]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][0]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][1]serdesMode = 2, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][2]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][3]serdesMode = 6, bandWidth = 3, GenSpeed = 0, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][4]serdesMode = 1, bandWidth = 3, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][5]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][6]serdesMode = 1, bandWidth = 2, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[7] bandWidth is X16!
recvSerdesCfg[1][7]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[8] bandWidth is X16!
recvSerdesCfg[1][8]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
recvSerdesCfg[1][9]serdesMode = 4, bandWidth = 4, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
CPLD set socket[1]hilink[10] bandWidth is X16!
recvSerdesCfg[1][10]serdesMode = 1, bandWidth = 1, GenSpeed = 4, hotPlugEnable = 0,               laneInversion = 0, RXPNInversion = 0, TXPNInversion = 0!
SerdesDataStruct size = 7
[TianChiGetNicTypeFromCpld][241L] ExecuteCPLDSmcCmd:5
[SetTianChiNicType] Nic 0 Type: 0x0
[TianChiGetNicTypeFromCpld][241L] ExecuteCPLDSmcCmd:5
[SetTianChiNicType] Nic 1 Type: 0x0
[3.511]Normal version.
[InterruptRegister]:[395L]id = 65
[SIWInterruptInit]:[151L]id:65, init done!
[InterruptRegister]:[395L]id = 67
[InterruptRegister]:[395L]id = 69
[IpmbInterruptInit]:[262L]id:69
[InterruptRegister]:[395L]id = 71
[Scmi0InterruptInit]:[25L]id:71, init done!
[InterruptRegister]:[395L]id = 72
[Scmi1InterruptInit]:[38L]id:72, init done!
[InterruptRegister]:[395L]id = 76
[InterruptRegister]:[395L]id = 78
[TotemResetInit]:[70L]id:78, init done!
[InterruptRegister]:[395L]id = 83
[InterruptRegister]:[395L]id = 275
[InterruptRegister]:[395L]id = 299
[InterruptRegister]:[395L]id = 116
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x0 Clear done
[InterruptRegister]:[395L]id = 117
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x0 Clear done
[InterruptRegister]:[395L]id = 134
[InterruptRegister]:[395L]id = 96
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x8000000 Clear done
[InterruptRegister]:[395L]id = 97
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x8000000 Clear done
[InterruptRegister]:[395L]id = 114
[InterruptRegister]:[395L]id = 256
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt0RasIntClear]:[259L]nimbusBase 0x0 clear done
[InterruptRegister]:[395L]id = 257
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt1RasIntClear]:[529L]nimbusBase 0x0 Clear done
[InterruptRegister]:[395L]id = 258
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt2RasIntClear]:[638L]nimbusBase 0x0 Clear done
[InterruptRegister]:[395L]id = 259
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusHacRasIntClear]:[311L]NimbusHacRasIntClear done
[InterruptRegister]:[395L]id = 260
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusNicRasIntClear]:[466L]nimbusBase 0x0 Clear done
[InterruptRegister]:[395L]id = 261
[NimbusPCIeRasIntClear]:[662L]NimbusBase 0x0 Clear Start...
[NimbusPCIeRasIntClear]:[673L]NimbusBase 0x0 Clear done!
[InterruptRegister]:[395L]id = 156
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 157
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 174
[InterruptRegister]:[395L]id = 136
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemRasIntClear]:[246L]TotemBase 0x4008000000 Clear done
[InterruptRegister]:[395L]id = 137
TYPE0: 0
TYPE1: 0
TYPE2: 0
[TotemScclRasIntClear]:[340L]TotemBase 0x4008000000 Clear done
[InterruptRegister]:[395L]id = 154
[InterruptRegister]:[395L]id = 280
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt0RasIntClear]:[259L]nimbusBase 0x4000000000 clear done
[InterruptRegister]:[395L]id = 281
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt1RasIntClear]:[529L]nimbusBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 282
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusMgmt2RasIntClear]:[638L]nimbusBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 283
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusHacRasIntClear]:[311L]NimbusHacRasIntClear done
[InterruptRegister]:[395L]id = 284
TYPE0: 0
TYPE1: 0
TYPE2: 0
[NimbusNicRasIntClear]:[466L]nimbusBase 0x4000000000 Clear done
[InterruptRegister]:[395L]id = 285
[NimbusPCIeRasIntClear]:[662L]NimbusBase 0x4000000000 Clear Start...
[NimbusPCIeRasIntClear]:[673L]NimbusBase 0x4000000000 Clear done!
Cer Initialization start...
[IMU][DEBUG]:  CER_CFG_BD_ENDIAN_ADDR is 0x3
[IMU][DEBUG]:  OUT STANDING is 0x4040
[IMU][DEBUG]:  OUT STANDING after set is 0x140
Cer Initialization done.
[IMU] I2C Initialization start...
[IMU] I2cDealNimbusException secket:0
[IMU] Set I2C4 ----> IPMB mode(default), Set I2C5 ----> I2C mode Success.
[IMU][DEBUG]:  Start init I2C on Address: [0x210050000].
[IMU][DEBUG]:  I2C on Address: [0x210050000] init Succed.
[IMU] Set I2C5 to NORMAL mode.
[IMU] I2C Initialization done!
[IMU] Scmi channels Initialization done!
SIW Initialization Starting...

Enable SIW Debug interface ...
[IMU][DEBUG]:  ES.IMU.SIW.006 SC_SIW_STAT register value is 0x8000.
SIW bypass disabled.
SIW Initialization Done.

[IMU] MiscConfig Start.
[IMU][DEBUG]:  DDRC_CFG_STADAT before config 0x0.
[IMU][DEBUG]:  DDRC_CFG_STADAT after config 0x40000000.
[IMU] Misc Config Done.
[IMU] Gpio MUX Config Done.
[IMU] N_CATERR Gpio MUX Config Done.
[IMU][DEBUG]:  CPU_cluster 0x5a00 is 0xff, hotreset is 0x0
TotemPll0InitCs nodeId:3
TotemPll0InitCs nodeId:1
SllcSetBand isHigh:1
SpiTpmRead ret: 0x0, detect = 0x0
SpiTpmRead ret: 0x0, didVid = 0x0
[IMU][ERROR]:  TPM is not detected
[IMU][ERROR]:  Tpm init err, 0x1
[IMU][DEBUG]:  Offset 0x800000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
 IMU compilation script 
IMU start to measure sec.
[IMU][ERROR]:  Unsupported trusted module
TPM Measure UEFI SEC fail, 0x1
[IMU][DEBUG]:  Offset 0x400000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
[IMU][DEBUG]:  Offset 0x90000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
It's not secure boot
TotemPll0DeInitCs nodeId:1
TotemPll0DeInitCs nodeId:3
SllcSetBand isHigh:0
base: 0x98200000
Ap is booting up, status: 0xee
[IMU][DEBUG]:  Offset 0x890000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
IMU start to measure Fvmain_compact and TF.
[IMU][ERROR]:  Unsupported trusted module
TPM Measure Uefi and TF fail, 0x1
IMU start to measure certificate and HD.
[IMU][ERROR]:  Unsupported trusted module
TPM Measure Certificate and HD fail, 0x1
[SetSkipTrainingFlag]21007f024:1620a5a2
[IMU] Watchdog Initialization done!
cpu 0 entering scheduler
[IMU] Chip: 0 Totem-B Fabric sub T-sensor setup ok!
[IMU] Chip: 0 Totem-B Sys sub T-sensor setup ok!
[IMU] Chip: 0 Totem-A Fabric sub T-sensor setup ok!
[IMU] Chip: 0 Totem-A Sys T-sensor setup ok!
[IMU] Chip: 0 Nimbus T-sensor setup ok!
IPMB initialization Start...
IPMB module clock set done.
IPMB Rx FIFO clear empty.
IPMB initialization Done.
[GetInitSendNumber]:[2142]semaphore create init number = 0!
cfg=110005 g_mctpCount=4
mctp_dev[0] enable=1 mode=1
mctp_dev[1] enable=0 mode=0
mctp_dev[2] enable=1 mode=1
mctp_dev[3] enable=0 mode=0
mctp_loop_task Create Success
HardWare Send IPMI Errorr regValue = 0x8 !!!!
Send process recive sto !!!!

[extInt0Init]:[65L]

[extInt0Init]:[69L]
Core Number: 0x40
Enable scmi int done
mctp loop task start.
Ras Handle task start.
[IpmiMsgGetManufactureid][135]Gotted ManufactureId:db 07 00
pwr cap[0]: 0, 63
pwr cap[1]: f, 27
SetupCfg  :
EnFdmSupport:            0x1
DdrRefreshRate:          0x0
PowerESaving:            0x0
HotPlug:                 0x1
ProcessorFlexibleRatio:  0x1a
CoreIsolateOnlineFlag:   0x0
EnRasSupport:            0x1
AdvanceDeviceCorrection: 0x0
PatrolScrubDuration:     0x18
X8MisCorrEn:             0x0
PowerOnTime:             0xa
DimmTime:                0xa
PageIsolation:           0x0
Mem2BitErrCorrEn:        0x1
pwr cap[2]: 1, 3
[24.938]Real time now:  2026/04/30, 01:03:06
[24.939]InitialCntTime = 24
[25.051][IMU] System DDR Init Done!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 1 read addr 0x56 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 0 I2c port 0 read addr 0x56 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x54 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x50 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 1 read addr 0x56 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x52 DRAM Width failed
[IMU][ERROR]:  [CheckI2cTimeOut]:[302L]I2C Read fail, read back buffer empty, time out!
[IMU][ERROR]:  Socket 1 I2c port 0 read addr 0x56 DRAM Width failed
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntInit done
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntInit done
[NimbusMgmt0IntInit]:[233L]NimbusMgmt0IntInit done
[NimbusMgmt1IntInit]:[499L]
[NimbusMgmt2IntInit]:[626L]NimbusMgmt2IntInit done
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntInit done
[TotemRasIntInit]:[229L]TotemRasIntInit done
[TotemScclIntInit]:[323L]TotemScclIntInit done
[NimbusMgmt0IntInit]:[233L]NimbusMgmt0IntInit done
[NimbusMgmt1IntInit]:[499L]
[NimbusMgmt2IntInit]:[626L]NimbusMgmt2IntInit done
[IMU][DEBUG]:  Offset 0x400000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
CppcShareMem: 0x44000000
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
[IMU][DEBUG]:  Offset 0xfc0000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
registry filesize:0x31cb

[IMU][DEBUG]:  Offset 0xfd8000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:[IMU][ERROR]:  Th  CS is 0x0
[IMU][DEBUe response code is abnoG]:  [SfcCmdRead][1580]rmal 0xd6.
 Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
version:
[IMU] Chip: 1 Totem-B Fabric sub T-sensor setup ok!
[IMU] Chip: 1 Totem-B Sys sub T-sensor setup ok!
[IMU] Chip: 1 Totem-A Fabric sub T-sensor setup ok!
[IMU] Chip: 1 Totem-A Sys T-sensor setup ok!
[IMU] Chip: 1 Nimbus T-sensor setup ok!
[IMU] Thermal Event Initialization done!
[NicRstInterruptInit]:[84L] NicRstInterruptInit done

chip[0]MaxFreq = 2600
chip[1]MaxFreq = 2600
BinZ Flag = 0x0.
[IMU]PreviousLogPos:0; PreviousLogSize:0; CurrrentLogSize:26608, CurrrentLogPos:0, Add:26608
[get_avs_loadline][864L]chip_version is V110/V111!
Socket[0] get hpm_C=0x41.
Socket[0] inital_avs_vmin = 822.
Socket[0] guardband = 70
Socket[0] res_margin = 0
Socket[0] res_margin_3G = 0
Socket[0] average_iddq = 13191
Socket[0] imax = 113.
Socket[0] vol_loadline = 96
Socket[0] power_avs_vmin = 895
chip_version is V110/V111!
----------------------------------------------------------------
g_avsLoadingInfo.message[0].Power_load_inital_vol_1 = 0xe3
g_avsLoadingInfo.message[0].Power_load_inital_vol_h = 0x3
g_avsLoadingInfo.message[0].loadline_R = 85
----------------------------------------------------------------
Socket[0] loadline_R is 85 .
Socket[0] Power_load_inital_vol low is 0xe3 mv.
Socket[0] Power_load_inital_vol high is 0x3 mv.
chip_version is V110/V111!
Socket[1] get hpm_C=0x41.
Socket[1] inital_avs_vmin = 757.
Socket[1] guardband = 70
Socket[1] res_margin = 0
Socket[1] res_margin_3G = 0
Socket[1] average_iddq = 29645
Socket[1] imax = 118.
Socket[1] vol_loadline = 100
Socket[1] power_avs_vmin = 830
chip_version is V110/V111!
----------------------------------------------------------------
g_avsLoadingInfo.message[1].Power_load_inital_vol_1 = 0xa2
g_avsLoadingInfo.message[1].Power_load_inital_vol_h = 0x3
g_avsLoadingInfo.message[1].loadline_R = 85
----------------------------------------------------------------
Socket[1] loadline_R is 85 .
Socket[1] Power_load_inital_vol low is 0xa2 mv.
Socket[1] Power_load_inital_vol high is 0x3 mv.
 crc_val is 163 .
[NoCommitEnable]:[107L]NOCOMMITInit done
m7 queue init done
ApeiTable: 0x2f384018
chip_id:1, M7 Version:1.21.0.1
barStoreAddr:0x45608020, barStoreCount:0x2c
HotPlug Open

Pcie Hotplug init task done, with 0 port(s).
[130.135]BIOS post end
Lock flash Done
set sram secure done
Here to send update current value info
g_currVal:{"RefreshRate":0,"PdEn":0,"PdPrd":256,"Demt":0,"Funnel":1,"PsFunnel":1,"UnitTime":1,"CETh":6000,"PSEn":1,"Mem2BitErrCorrEn":0}
wait 5 mins to update pciemmio..
Init mctp[0] done.
Init mctp[2] done.
rx[0] units=1
Add ep: bdf=1c00 eid=9 ep_cnt=1 eid_alloc=a
rx[0] units=2
core[32]pmu init done
core[33]pmu init done
core[34]pmu init done
core[35]pmu init done
core[36]pmu init done
core[37]pmu init done
core[38]pmu init done
core[39]pmu init done
core[40]pmu init done
core[41]pmu init done
core[42]pmu init done
core[43]pmu init done
core[44]pmu init done
core[45]pmu init done
core[46]pmu init done
core[47]pmu init done
core[48]pmu init done
core[49]pmu init done
core[50]pmu init done
core[51]pmu init done
core[52]pmu init done
core[53]pmu init done
core[54]pmu init done
core[55]pmu init done
core[56]pmu init done
core[57]pmu init done
core[58]pmu init done
core[59]pmu init done
core[60]pmu init done
core[61]pmu init done
core[62]pmu init done
core[63]pmu init done
core[0]pmu init done
core[1]pmu init done
core[2]pmu init done
core[3]pmu init done
core[4]pmu init done
core[5]pmu init done
core[6]pmu init done
core[7]pmu init done
core[8]pmu init done
core[9]pmu init done
core[10]pmu init done
core[11]pmu init done
core[12]pmu init done
core[13]pmu init done
core[14]pmu init done
core[15]pmu init done
core[16]pmu init done
core[17]pmu init done
core[18]pmu init done
core[19]pmu init done
core[20]pmu init done
core[21]pmu init done
core[22]pmu init done
core[23]pmu init done
core[24]pmu init done
core[25]pmu init done
core[26]pmu init done
core[27]pmu init done
core[28]pmu init done
core[29]pmu init done
core[30]pmu init done
core[31]pmu init done
core[96]pmu init done
core[97]pmu init done
core[98]pmu init done
core[99]pmu init done
core[100]pmu init done
core[101]pmu init done
core[102]pmu init done
core[103]pmu init done
core[104]pmu init done
core[105]pmu init done
core[106]pmu init done
core[107]pmu init done
core[108]pmu init done
core[109]pmu init done
core[110]pmu init done
core[111]pmu init done
core[112]pmu init done
core[113]pmu init done
core[114]pmu init done
core[115]pmu init done
core[116]pmu init done
core[117]pmu init done
core[118]pmu init done
core[119]pmu init done
core[120]pmu init done
core[121]pmu init done
core[122]pmu init done
core[123]pmu init done
core[124]pmu init done
core[125]pmu init done
core[126]pmu init done
core[127]pmu init done
core[64]pmu init done
core[65]pmu init done
core[66]pmu init done
core[67]pmu init done
core[68]pmu init done
core[69]pmu init done
core[70]pmu init done
core[71]pmu init done
core[72]pmu init done
core[73]pmu init done
core[74]pmu init done
core[75]pmu init done
core[76]pmu init done
core[77]pmu init done
core[78]pmu init done
core[79]pmu init done
core[80]pmu init done
core[81]pmu init done
core[82]pmu init done
core[83]pmu init done
core[84]pmu init done
core[85]pmu init done
core[86]pmu init done
core[87]pmu init done
core[88]pmu init done
core[89]pmu init done
core[90]pmu init done
core[91]pmu init done
core[92]pmu init done
core[93]pmu init done
core[94]pmu init done
core[95]pmu init done
[IMU] g_runtimeVersio->impVerStr=1.21.0.1!
the M7 Versions are updated:0x2
g_runtimeVersion->imuVerStr=6.65.0!
the IMU Versions are updated:0x3
[IMU][DEBUG]:  Offset 0xfd8000 flash_size is 0x1000000
[IMU][DEBUG]:  SPI Flash id is 0x1860c8
[IMU][DEBUG]:  FlashIndex is 0x0
[IMU][DEBUG]:  CS is 0x0
[IMU][DEBUG]:  [SfcCmdRead][1580] Start Cs=[0]!
[IMU][DEBUG]:  [SfcCmdRead][1602] end!
version:
[IMU][ERROR]:  !!!the Component Versions are not same:0x0!!!
gCompponentVersionSize: 275
{"PatchVersion":"","ComponentInfo":[    {"BitMap":0,"Name":"IMU","Version":"6.65.0","Attribute":["Hotfix"]},    {"BitMap":1,"Name":"IMP","Version":"1.21.0.1","Attribute":["Hotfix","BusinessInterrupted"]},    {"BitMap":7,"Name":"Extensible BIOS","Version":"","Attribute":[]}]}
sendDataLen: 200
sendDataLen: 75
sendDataLen: 200
sendDataLen: 75
mctp task ok.
[ipmb_write]:[241L]Wait Ack TimeOut !!!!
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][E[ipmb_write]:[241L]Wait Ack TimeOut !!!!
RROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ER[ipmb_write]:[241L]Wait Ack TimeOut !!!!
ROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERR[ipmb_write]:[241L]Wait Ack TimeOut !!!!
OR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [I[ipmb_write]:[241L]Wait Ack TimeOut !!!!
pmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
[IMU][ERROR]:  [IpmiCmdReportPcieMMIO] ExecuteIpmiCmd : 0x1
update pciemmio completed!
[ipmb_write]:[241L]Wait Ack TimeOut !!!!
[ipmb_write]:[241L]Wait Ack TimeOut !!!!
[ipmb_write]:[241L]Wait Ack TimeOut !!!!
[ipmb_write]:[241L]Wait Ack TimeOut !!!!
[ipmb_write]:[241L]Wait Ack TimeOut !!!!
[ipmb_write]:[241L]Wait Ack TimeOut !!!!
