 Q	    @                       Q$  `c@#o         Watchdog2 Q  -      TS200-2280 Q P     BMCCard Q       BMC Q      ExpBoard1 Q      ExpBoard6 Q      PeuBoard1	 Q      ExpBoard2
 Q      ExpBoard5 Q 
     ExpBoard4 Q      ExpBoard3
 Q      FanBoard2 Q 	     PSU7 Q !     PCIe Riser2 Q       PCIe Riser1 Q "     PCIe Riser3 Q      PSU8 Q      DiskBP1 Q      PSU9 Q      PSU10 Q 
     PSU5 Q      PSU4 Q      PSU6 Q      PSU1 Q      PSU3 Q      PSU2 Q      FanBoard3 Q      NpuBoard1 Q      NpuBoard5 Q      NpuBoard8  Q $     Zijin-DPU! Q      NpuBoard4" Q      NpuBoard7# Q      NpuBoard3$ Q      NpuBoard2% Q      NpuBoard6& Q      FanBoard1' Q$  `c@+o            FW_Update( Q(  `c@(o ! ! !         Mngmnt Health) Q#  `c@o             SYS_Boot* Q9  ` p  d        i      1711 Core Temp+ Q/   hco            BCU1_P1_C0_D0_Status, Q/   sco            BCU1_P0_C5_D1_Status- Q/   ico            BCU1_P1_C0_D1_Status. Q/  	 jco            BCU1_P1_C1_D0_Status/ Q/  
 uco            BCU1_P0_C6_D1_Status0 Q/   xco            BCU1_P1_C4_D0_Status1 Q/   yco            BCU1_P1_C4_D1_Status2 Q/  
 kco            BCU1_P1_C1_D1_Status3 Q/   lco            BCU1_P1_C2_D0_Status4 Q/   gco            BCU1_P0_C3_D1_Status5 Q/   aco            BCU1_P0_C0_D1_Status6 Q/   `co            BCU1_P0_C0_D0_Status7 Q/   bco            BCU1_P0_C1_D0_Status8 Q/   cco            BCU1_P0_C1_D1_Status9 Q/   dco            BCU1_P0_C2_D0_Status: Q/   co            BCU1_P1_C7_D1_Status; Q/   mco            BCU1_P1_C2_D1_Status< Q/   eco            BCU1_P0_C2_D1_Status= Q/   rco            BCU1_P0_C5_D0_Status> Q/   ~co            BCU1_P1_C7_D0_Status? Q/   qco            BCU1_P0_C4_D1_Status@ Q/   tco            BCU1_P0_C6_D0_StatusA Q/   nco            BCU1_P1_C3_D0_StatusB Q/   wco            BCU1_P0_C7_D1_StatusC Q/   fco            BCU1_P0_C3_D0_StatusD Q/   }co            BCU1_P1_C6_D1_StatusE Q/    pco            BCU1_P0_C4_D0_StatusF Q/  ! oco            BCU1_P1_C3_D1_StatusG Q/  " vco            BCU1_P0_C7_D0_StatusH Q/  # |co            BCU1_P1_C6_D0_StatusI Q/  $ {co            BCU1_P1_C5_D1_StatusJ Q/  % zco            BCU1_P1_C5_D0_StatusK Q$  &ac@o 4   $         Event_LogL Q'  'ac@            Op. Log FullM Q(  (ac@            Sec. Log FullN Q6  )`h   d        U      Riser1_TempO Q7  **`h            i      Swi CDR TempP Q6  +ah   d        U      Riser3_TempQ Q&  ,
`co O O O         PSU7_SupplyR Q:  -
`h                             PSU7_Inlet_TempS Q4  .
`h                   n        PSU7_TempT Q3  /
`h                             PSU7_PInU Q3  0
ah                             PSU9_PInV Q&  1
aco O O O         PSU9_SupplyW Q:  2
ah                             PSU9_Inlet_TempX Q4  3
ah                             PSU9_TempY Q7  4`h p  d    (    v        NB3 LM75B_TEZ Q:  5`                              NB3 NPU1 Chip_V[ Q9  6a p  d    (    i      NB3 NPU2 AI_Tj\ Q:  7a p  d    (    i      NB3 NPU2 HBM_Tj] Q&  8`c
o            NPU3 Health^ Q:  9a p  d    (    i      NB3 NPU2 Nim_Tj_ Q:  :` p  d    (    i      NB3 NPU1 HBM_Tj` Q7  ;` p  d    (    v        NB3 LM75A_TEa Q:  <` p  d    (    i      NB3 NPU1 Nim_Tjb Q5  =`        p                  NPU3 Powerc Q:  >a                              NB3 NPU2 Chip_Vd Q9  ?` p  d    (    i      NB3 NPU1 AI_Tje Q9  @a p  d    (    v      NB3 NPU VRD_Tjf Q;  A7`hrr  d        __      IOB Retimer Tempg Q5  B7`h2  d        .*      Inlet_Temph Q8  Cch   d         i      Swi Chip Tempi Q9  Dc             F        SSD_F_Max_Tempj Q%  Ecc@"o A   A         ACPI_Statek Q6  Fch         H                    Total_Powerl Q:  Gc             F        NVMe_F_Max_Tempm Q%  Hcc@o A   A         UID_Buttonn Q7  Ich   d         q      Swi VRM Tempo Q(  J  c@            PSU_Redundantp Q(  Kcc@o            PwrOn TimeOutq Q'  Lcc@o             Power_Buttonr Q7  Mch   d         i      Swi VDM Temps Q*  Ncc@o            PwrOk Sig. Dropt Q;  Och   d         F      Swi Optical Tempu Q7  Pch   d         i      Swi SOC Tempv Q6  Qbh   d        U      Riser2_Tempw Q:  R
bh                             PSU8_Inlet_Tempx Q4  S
bh                             PSU8_Tempy Q3  T
bh                             PSU8_PInz Q&  U
bco O O O         PSU8_Supply{ Q:  Vdh                           EXU5 Inlet Temp| Q6  We
              *              PUMP4 Speed} Q:  Xdh                           EXU4 Inlet Temp~ Q6  Yd
              *              PUMP3 Speed Q'  Z
cco O O O         PSU10_Supply Q;  [
ch                             PSU10_Inlet_Temp Q5  \
ch                             PSU10_Temp Q4  ]
ch                             PSU10_PIn Q:  ^c                              NB7 NPU1 Chip_V Q9  _c p  d    (    i      NB7 NPU1 AI_Tj Q&  `cc
o            NPU7 Health Q:  ab p  d    (    i      NB7 NPU2 Nim_Tj Q9  bb p  d    (    i      NB7 NPU2 AI_Tj Q:  cb                              NB7 NPU2 Chip_V Q:  db p  d    (    i      NB7 NPU2 HBM_Tj Q7  eah p  d    (    v        NB7 LM75B_TE Q7  fa p  d    (    v        NB7 LM75A_TE Q9  gb p  d    (    v      NB7 NPU VRD_Tj Q:  hc p  d    (    i      NB7 NPU1 Nim_Tj Q5  ic        p                  NPU7 Power Q:  jc p  d    (    i      NB7 NPU1 HBM_Tj Q4  k
dh                             PSU5_Temp Q3  l
dh                             PSU5_PIn Q3  m
dh                              PSU5_Iin Q4  n
dh                             PSU5_POut Q:  o
dh                             PSU5_Inlet_Temp Q3  p
dh                              PSU5_Vin Q4  q
dh                              PSU5_VOut Q4  r
dh                              PSU5_IOut Q&  s
dco O O O         PSU5_Supply Q+  t
dc!o            PSU5_Temp_Status Q9  u79hrr    d                PEU Inlet Temp Q:  v78hrr    d                PEU Outlet Temp Q4  w
eh                             PSU3_Temp Q3  x
eh                             PSU3_PIn Q3  y
eh                              PSU3_Iin Q4  z
eh                             PSU3_POut Q:  {
eh                             PSU3_Inlet_Temp Q3  |
eh                              PSU3_Vin Q4  }
eh                              PSU3_VOut Q4  ~
eh                              PSU3_IOut Q&  
eco O O O         PSU3_Supply Q+  
ec!o            PSU3_Temp_Status Q:  
fh                           BCU1 12V0_4 Pwr Q:  e                 BCU1_SYS_12V0_1 Q4  e
z88  d      id_      CPU0_Temp Q#  ec@o             BMC_Boot Q4  d
z88  d      id_      CPU1_Temp Q9  dh                             CPU1_MEM_Power Q9  %a
z88         id_      CPU1_DIMM_Temp Q:  d       P    X  H    CPU1 0V8_NBDVDD Q+  ec@	             BCU1_Power_Fault Q:  e                 BCU1_SYS_12V0_2 Q:  e                 BCU1_SYS_12V0_3 Q2  e       n    n  C    P3V_BAT Q)  ec@o            BCU1 Sys Error Q:  e       n    z  b    BCU1 3V3_RISER2 Q6  d       P      :    CPU1_TBCORE Q:  
fh                        ((   BCU1 12V0_2 Pwr Q:  
fh                        ((   BCU1 12V0_3 Pwr Q6  e       B    H  <    BCU1_SYS_5V Q:  d       P    n  C    CPU1 0V9_UNCORE Q8  d       n    y  c    CPU1 1V1_VDDQ Q+  dc@o          BCU1_Cpu1_Status Q8  e       n    z  b    BCU1_SYS_3.3V Q+  ec@o          BCU1_Cpu0_Status Q4  bh                         BCU1 Temp Q'  ec@o             BIOS_Boot_Up Q;  eh                             BCU1_CPU0_VR_Pwr Q9  eh                             CPU0_MEM_Power Q9 we                             BCU1_CPU_Power Q9  bh                             BCU1_MEM_Power Q6  e       P      :    CPU0_TACORE Q:  e       P    X  H    CPU0 0V8_NADVDD Q:  e       P    X  H    CPU0 0V8_NBDVDD Q8  e       n    y  c    CPU0 1V1_VDDQ Q8  d       R    T  E    CPU1 0V75_VDD Q;  eh p  d          x      CPU0 TACORE Temp Q8  eh p  d          x      CPU0 VDD Temp Q;  eh p  d          x      CPU0 TBCORE Temp Q;  eh p  d          x      CPU0 UNCORE Temp Q;  eh p  d          x      CPU0 NADVDD Temp Q;  eh p  d          x      CPU0 NBDVDD Temp Q9  eh p  d          x      CPU0 VDDQ Temp Q7  eh              x      CPU0_VR_Temp Q;  dh p  d          x      CPU1 TACORE Temp Q8  dh p  d          x      CPU1 VDD Temp Q;  dh p  d          x      CPU1 TBCORE Temp Q;  dh p  d          x      CPU1 UNCORE Temp Q;  dh p  d          x      CPU1 NADVDD Temp Q'  eco            SYS_Progress Q;  dh p  d          x      CPU1 NBDVDD Temp Q9  dh p  d          x      CPU1 VDDQ Temp Q7  dh              x      CPU1_VR_Temp Q*  ec@            BCU1 Sys Notice Q:  d       P    X  H    CPU1 0V8_NADVDD Q6  d       P      :    CPU1_TACORE Q;  dh                             BCU1_CPU1_VR_Pwr Q8  e       R    T  E    CPU0 0V75_VDD Q+  ec@)o          BCU1 RTC Battery Q*  eco            BCU1 Boot Error Q"  ec@o             OS_Boot Q:  e       P    n  C    CPU0 0V9_UNCORE Q6  e       P      :    CPU0_TBCORE Q9  %`
z88         id_      CPU0_DIMM_Temp Q7  ch p  d    (    v        NB2 LM75B_TE Q:  f p  d    (    i      NB2 NPU2 Nim_Tj Q&  gc
o            NPU2 Health Q:  f                              NB2 NPU2 Chip_V Q5  g        p V                 NPU2 Power Q:  g p  d    (    i      NB2 NPU1 HBM_Tj Q9  f p  d    (    v      NB2 NPU VRD_Tj Q:  g p  d    (    i      NB2 NPU1 Nim_Tj Q9  f p  d    (    i      NB2 NPU2 AI_Tj Q:  f p  d    (    i      NB2 NPU2 HBM_Tj Q:  g                              NB2 NPU1 Chip_V Q7  c p  d    (    v        NB2 LM75A_TE Q9  g p  d    (    i      NB2 NPU1 AI_Tj Q7  f         K     *              FAN7_R_Speed Q7  f         K     *              FAN7_F_Speed Q:  h p  d    (    i      NB4 NPU2 Nim_Tj Q9  i p  d    (    i      NB4 NPU1 AI_Tj Q:  i p  d    (    i      NB4 NPU1 HBM_Tj Q:  i                              NB4 NPU1 Chip_V Q:  h                              NB4 NPU2 Chip_V Q:  h p  d    (    i      NB4 NPU2 HBM_Tj Q:  i p  d    (    i      NB4 NPU1 Nim_Tj Q7  d p  d    (    v        NB4 LM75A_TE Q7  dh p  d    (    v        NB4 LM75B_TE Q9  h p  d    (    i      NB4 NPU2 AI_Tj Q5  i        p V                 NPU4 Power Q&  ic
o            NPU4 Health Q9  h p  d    (    v      NB4 NPU VRD_Tj  Q9  e p  d         }      DPU_MEM_VRTemp Q*  ec@o         DPU_CPU0_Status Q6  e        d                  DPU_M2_Temp Q8  eh         d                   DPU_CPU_Power Q:  e p  d         }      DPU_FPGA_VRTemp Q:  e        d                  DPU_FPGA_InTemp Q:  e         d                   DPU_Total_Power Q8  e p  d         K      DPU_OPT0_Temp Q9  e         d                   DPU_DIMM_Power	 Q8  e p  d         K      DPU_OPT1_Temp
 Q)  ec@o @   @         DPU_SOC_Status Q7  e p  d         d      DPU_CPU_Temp Q*  ec@o 0 0 0         DPU_FPGA_Status
 Q8  e        d                  DPU_DIMM_Temp Q'  ec@o            DPU_P0_C0_D0 Q8  e p  d         K      DPU_OPT3_Temp Q8  e p  d         d      DPU_FPGA_Temp Q'  ec@o            DPU_P0_C1_D0 Q:  e        d                  DPU_CPU_OutTemp Q*  ec@o
0
0
0         DPU_PCIE_Status Q(  ec@o         DPU_P0_G0_Hot Q'  ec@o            DPU_PWR_Drop Q9  e p  d         }      DPU_CPU_VRTemp Q%  ec@o            DPU_PWR_On Q9  e        d                 DPU_CPU_InTemp Q8  e p  d         K      DPU_OPT2_Temp Q9  e         d                   DPU_FPGA_Power Q(  ec@             DPU_ME_Status Q;  e        d                  DPU_FPGA_OutTemp Q4  
gh                             PSU1_POut Q:  
gh                             PSU1_Inlet_Temp Q3  
gh                              PSU1_Vin  Q4  
gh                              PSU1_VOut! Q4  
gh                              PSU1_IOut" Q&  
gco O O O         PSU1_Supply# Q+  
gc!o            PSU1_Temp_Status$ Q4  
gh                             PSU1_Temp% Q3 
gh                             PSU1_PIn& Q3 
gh                              PSU1_Iin' Q: fh                           EXU3 Inlet Temp( Q #     SP686C-M-16i 4G) Q6 g
              *              PUMP1 Speed* Q6 h
              *              PUMP2 Speed+ Q: fh                           EXU2 Inlet Temp, Q5 ch p  d        i      RAID2_Temp- Q) cc)o            PCIe2 Card BBU. Q9 	ch p  d        _      RAID2 DDR Temp/ Q4 
f p  d        i      NIC1_Temp0 Q'   c@o
0
0
0         PCIe1_Status1 Q9 f p           K      NIC1_Opt1_Temp2 Q9 
f p           K      NIC1_Opt2_Temp3 Q/  co            BCU2_P1_C2_D1_Status4 Q/  co            BCU2_P0_C4_D1_Status5 Q/  co            BCU2_P1_C0_D0_Status6 Q/  co            BCU2_P1_C0_D1_Status7 Q/  co            BCU2_P1_C1_D0_Status8 Q/  co            BCU2_P0_C0_D1_Status9 Q/  co            BCU2_P0_C7_D1_Status: Q/  co            BCU2_P0_C7_D0_Status; Q/  co            BCU2_P1_C5_D0_Status< Q/  co            BCU2_P0_C1_D0_Status= Q/  co            BCU2_P0_C1_D1_Status> Q/  co            BCU2_P0_C2_D0_Status? Q/  co            BCU2_P1_C4_D0_Status@ Q/  co            BCU2_P1_C4_D1_StatusA Q/  co            BCU2_P0_C2_D1_StatusB Q/  co            BCU2_P1_C5_D1_StatusC Q/  co            BCU2_P1_C6_D0_StatusD Q/  co            BCU2_P1_C6_D1_StatusE Q/   co            BCU2_P0_C3_D0_StatusF Q/ ! co            BCU2_P1_C7_D0_StatusG Q/ " co            BCU2_P1_C7_D1_StatusH Q/ # co            BCU2_P1_C2_D0_StatusI Q/ $ co            BCU2_P1_C3_D1_StatusJ Q/ % co            BCU2_P0_C4_D0_StatusK Q/ & co            BCU2_P1_C3_D0_StatusL Q/ ' co            BCU2_P0_C3_D1_StatusM Q/ ( co            BCU2_P0_C6_D0_StatusN Q/ ) co            BCU2_P0_C0_D0_StatusO Q/ * co            BCU2_P0_C5_D0_StatusP Q/ + co            BCU2_P0_C5_D1_StatusQ Q/ , co            BCU2_P0_C6_D1_StatusR Q/ - co            BCU2_P1_C1_D1_StatusS Q4 .
hh                             PSU2_TempT Q3 /
hh                             PSU2_PInU Q3 0
hh                              PSU2_IinV Q4 1
hh                             PSU2_POutW Q: 2
hh                             PSU2_Inlet_TempX Q3 3
hh                              PSU2_VinY Q4 4
hh                              PSU2_VOutZ Q4 5
hh                              PSU2_IOut[ Q& 6
hco O O O         PSU2_Supply\ Q+ 7
hc!o            PSU2_Temp_Status] Q: 8uh                             FanBoard2 Power^ Q( 9ac@
            FAN7_Presence_ Q5 :uh                             FAN6_Power` Q5 ;uh                             FAN7_Powera Q( <bc@
            FAN8_Presenceb Q5 =uh                             FAN9_Powerc Q& >ac            FAN7_Statusd Q( ?cc@
            FAN9_Presencee Q& @bc            FAN8_Statusf Q) Aic@
            FAN10_Presenceg Q( B`c@
            FAN6_Presenceh Q' Cic            FAN10_Statusi Q6 Duh                             FAN10_Powerj Q5 Euh                             FAN8_Powerk Q4 Fuh        d                  CLU2 Templ Q& G`c            FAN6_Statusm Q& Hcc            FAN9_Statusn Q( Ijc@
            FAN2_Presenceo Q& Jnc            FAN5_Statusp Q& Kjc            FAN2_Statusq Q( Lkc@
            FAN1_Presencer Q( Mnc@
            FAN5_Presences Q& Nkc            FAN1_Statust Q5 Ovh                             FAN1_Poweru Q5 Pvh                             FAN2_Powerv Q5 Qvh                             FAN3_Powerw Q( Rlc@
            FAN3_Presencex Q5 Svh                             FAN4_Powery Q& Tlc            FAN3_Statusz Q& Umc            FAN4_Status{ Q: Vvh                             FanBoard1 Power| Q4 Wvh        d                  CLU1 Temp} Q( Xmc@
            FAN4_Presence~ Q5 Yvh                             FAN5_Power Q3 Z
ih                              PSU4_Iin Q4 [
ih                             PSU4_POut Q: \
ih                             PSU4_Inlet_Temp Q3 ]
ih                              PSU4_Vin Q4 ^
ih                              PSU4_VOut Q4 _
ih                              PSU4_IOut Q& `
ico O O O         PSU4_Supply Q+ a
ic!o            PSU4_Temp_Status Q4 b
ih                             PSU4_Temp Q3 c
ih                             PSU4_PIn Q* dgc@            BCU2 Sys Notice Q) egc@o            BCU2 Sys Error Q; fjh p  d          x      CPU2 TBCORE Temp Q8 gjh p  d          x      CPU2 VDD Temp Q* hgco            BCU2 Boot Error Q9 ikh                             CPU3_MEM_Power Q9 jjh                             CPU2_MEM_Power Q9 kjh p  d          x      CPU2 VDDQ Temp Q9 leh                             BCU2_MEM_Power Q; mjh p  d          x      CPU2 UNCORE Temp Q: nj       P    X  H    CPU2 0V8_NBDVDD Q8 okh p  d          x      CPU3 VDD Temp Q; pkh p  d          x      CPU3 TBCORE Temp Q; qkh p  d          x      CPU3 NADVDD Temp Q: rj       P    X  H    CPU2 0V8_NADVDD Q+ sgc@	             BCU2_Power_Fault Q: t
jh                           BCU2 12V0_4 Pwr Q; ukh                             BCU2_CPU1_VR_Pwr Q; vjh                             BCU2_CPU0_VR_Pwr Q9  g                             BCU2_CPU_Power Q: xk       P    X  H    CPU3 0V8_NADVDD Q6 yk       P      :    CPU3_TACORE Q: zk       P    n  C    CPU3 0V9_UNCORE Q6 {k       P      :    CPU3_TBCORE Q+ |kc@o          BCU2_Cpu1_Status Q; }jh p  d          x      CPU2 NBDVDD Temp Q+ ~gc@)o          BCU2 RTC Battery Q: g                 BCU2_SYS_12V0_1 Q9 %b
z88         id_      CPU2_DIMM_Temp Q9 %c
z88         id_      CPU3_DIMM_Temp Q: 
jh                        ((   BCU2 12V0_2 Pwr Q: 
jh                        ((   BCU2 12V0_3 Pwr Q6 j       P      :    CPU2_TACORE Q6 j       P      :    CPU2_TBCORE Q: j       P    n  C    CPU2 0V9_UNCORE Q: k       P    X  H    CPU3 0V8_NBDVDD Q8 k       n    y  c    CPU3 1V1_VDDQ Q; jh p  d          x      CPU2 TACORE Temp Q; kh p  d          x      CPU3 TACORE Temp Q8 k       R    T  E    CPU3 0V75_VDD Q6 g       B    H  <    BCU2_SYS_5V Q+ jc@o          BCU2_Cpu0_Status Q7 jh              x      CPU2_VR_Temp Q8 g       n    z  b    BCU2_SYS_3.3V Q; jh p  d          x      CPU2 NADVDD Temp Q8 j       R    T  E    CPU2 0V75_VDD Q4 j
z88  d      id_      CPU2_Temp Q4 k
z88  d      id_      CPU3_Temp Q9 kh p  d          x      CPU3 VDDQ Temp Q: g                 BCU2_SYS_12V0_2 Q8 j       n    y  c    CPU2 1V1_VDDQ Q: g                 BCU2_SYS_12V0_3 Q: g       n    z  b    BCU2 3V3_RISER2 Q4 eh                         BCU2 Temp Q; kh p  d          x      CPU3 UNCORE Temp Q; kh p  d          x      CPU3 NBDVDD Temp Q7 kh              x      CPU3_VR_Temp Q7 o         K     *              FAN9_R_Speed Q7 o         K     *              FAN9_F_Speed Q8 p         K     *              FAN15_R_Speed Q8 p         K     *              FAN15_F_Speed Q7 q         K     *              FAN2_F_Speed Q7 q         K     *              FAN2_R_Speed Q7 r         K     *              FAN4_R_Speed Q7 r         K     *              FAN4_F_Speed Q7 s         K     *              FAN1_R_Speed Q7 s         K     *              FAN1_F_Speed Q8 t         K     *              FAN11_R_Speed Q8 t         K     *              FAN11_F_Speed Q7 u         K     *              FAN5_R_Speed Q7 u         K     *              FAN5_F_Speed Q8 v         K     *              FAN13_R_Speed Q8 v         K     *              FAN13_F_Speed Q8 w         K     *              FAN14_R_Speed Q8 w         K     *              FAN14_F_Speed Q7 x         K     *              FAN6_F_Speed Q7 x         K     *              FAN6_R_Speed Q8 y         K     *              FAN10_F_Speed Q8 y         K     *              FAN10_R_Speed Q8 z         K     *              FAN12_R_Speed Q8 z         K     *              FAN12_F_Speed Q7 {         K     *              FAN3_R_Speed Q7 {         K     *              FAN3_F_Speed Q' `c
o            DISK0_Status Q' dc
o            DISK4_Status Q' ac
o            DISK1_Status Q' ec
o            DISK5_Status Q' hc
o            DISK8_Status Q' gc
o            NVME7_Status Q9 ph        d                 NVMe_F_BP_Temp Q' fc
o            NVME6_Status Q' bc
o            DISK2_Status Q' ic
o            DISK9_Status Q' cc
o            DISK3_Status Q9 jhrr  d       UT      SSD Disk3 Temp Q7 |         K     *              FAN8_R_Speed Q7 |         K     *              FAN8_F_Speed Q& mc
o            NPU6 Health Q: l                              NB6 NPU2 Chip_V Q: m p  d    (    i      NB6 NPU1 HBM_Tj Q5 m        p V                 NPU6 Power Q9 m p  d    (    i      NB6 NPU1 AI_Tj Q9 l p  d    (    v      NB6 NPU VRD_Tj Q: m p  d    (    i      NB6 NPU1 Nim_Tj Q9 l p  d    (    i      NB6 NPU2 AI_Tj Q: l p  d    (    i      NB6 NPU2 HBM_Tj Q: m                              NB6 NPU1 Chip_V Q7 f p  d    (    v        NB6 LM75A_TE Q: l p  d    (    i      NB6 NPU2 Nim_Tj Q7 fh p  d    (    v        NB6 LM75B_TE Q: o p  d    (    i      NB1 NPU1 HBM_Tj Q7 gh p  d    (    v        NB1 LM75B_TE Q: n p  d    (    i      NB1 NPU2 Nim_Tj Q7 g p  d    (    v        NB1 LM75A_TE Q: o                              NB1 NPU1 Chip_V Q: n p  d    (    i      NB1 NPU2 HBM_Tj Q9 n p  d    (    i      NB1 NPU2 AI_Tj Q: o p  d    (    i      NB1 NPU1 Nim_Tj Q9 n p  d    (    v      NB1 NPU VRD_Tj  Q9 o p  d    (    i      NB1 NPU1 AI_Tj Q& oc
o            NPU1 Health Q5 o        p                  NPU1 Power Q: n                              NB1 NPU2 Chip_V Q9 khrr  d       UT      SSD Disk2 Temp Q4 
kh                             PSU6_Temp Q3 
kh                             PSU6_PIn Q3 
kh                              PSU6_Iin Q4 
kh                             PSU6_POut	 Q: 
kh                             PSU6_Inlet_Temp
 Q+ 
kc!o            PSU6_Temp_Status Q& 
kco O O O         PSU6_Supply Q4 
kh                              PSU6_IOut
 Q4 
kh                              PSU6_VOut Q3 
kh                              PSU6_Vin Q: q p  d    (    i      NB8 NPU1 HBM_Tj Q7 hh p  d    (    v        NB8 LM75B_TE Q: p p  d    (    i      NB8 NPU2 Nim_Tj Q5 q        p V                 NPU8 Power Q7 h p  d    (    v        NB8 LM75A_TE Q: p                              NB8 NPU2 Chip_V Q& qc
o            NPU8 Health Q9 q p  d    (    i      NB8 NPU1 AI_Tj Q9 p p  d    (    v      NB8 NPU VRD_Tj Q: q p  d    (    i      NB8 NPU1 Nim_Tj Q9 p p  d    (    i      NB8 NPU2 AI_Tj Q: p p  d    (    i      NB8 NPU2 HBM_Tj Q: q                              NB8 NPU1 Chip_V Q4 wh        d                  CLU3 Temp Q' c            FAN14_Status Q6 wh                             FAN11_Power Q) }c@
            FAN11_Presence  Q) ~c@
            FAN13_Presence! Q) c@
            FAN15_Presence" Q: wh                             FanBoard3 Power# Q6 wh                             FAN13_Power$ Q) c@
            FAN14_Presence% Q6 wh                             FAN14_Power& Q' ~c            FAN13_Status' Q6 wh                             FAN15_Power( Q6 wh                             FAN12_Power) Q) c@
            FAN12_Presence* Q' }c            FAN11_Status+ Q' c            FAN12_Status, Q' c            FAN15_Status- Q: 	s p  d    (    i      NB5 NPU1 HBM_Tj. Q7 
ih p  d    (    v        NB5 LM75B_TE/ Q9 s p  d    (    i      NB5 NPU1 AI_Tj0 Q9 r p  d    (    v      NB5 NPU VRD_Tj1 Q7 
i p  d    (    v        NB5 LM75A_TE2 Q: s                              NB5 NPU1 Chip_V3 Q5 s        p                  NPU5 Power4 Q: s p  d    (    i      NB5 NPU1 Nim_Tj5 Q9 r p  d    (    i      NB5 NPU2 AI_Tj6 Q: r p  d    (    i      NB5 NPU2 HBM_Tj7 Q: r p  d    (    i      NB5 NPU2 Nim_Tj8 Q& sc
o            NPU5 Health9 Q: r                              NB5 NPU2 Chip_V Q      CpuBoard1 Q      CpuBoard2