ID      |Generation Time     |Severity    |Event Code  |Status      |Event Description
218     |2026-05-14 09:11:23 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
217     |2026-05-14 09:10:50 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
216     |2026-05-14 08:52:15 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
215     |2026-05-14 08:51:49 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
214     |2026-05-13 18:16:44 |Major       |0x29000013  |Asserted    |Abnormal Rx signal of optical module is detected on Port 2 on NIC 2 (SF223D-H).
213     |2026-05-13 18:16:43 |Major       |0x29000013  |Asserted    |Abnormal Rx signal of optical module is detected on Port 1 on NIC 2 (SF223D-H).
212     |2026-05-13 18:15:33 |Normal      |0x1A00006F  |Asserted    |The BMC is reset, with the cause code of 0x2.
211     |2026-05-13 18:15:27 |Normal      |0x1A000021  |Asserted    |BMC is reset and started.
210     |2026-05-13 16:54:24 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
209     |2026-05-13 16:54:21 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
208     |2026-05-13 13:07:14 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
207     |2026-05-13 13:07:13 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
206     |2026-05-12 17:23:23 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
205     |2026-05-12 17:22:51 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
204     |2026-05-12 17:00:53 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
203     |2026-05-12 17:00:52 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
202     |2026-05-12 16:11:57 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
201     |2026-05-12 16:11:24 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
200     |2026-05-12 15:18:34 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
199     |2026-05-12 15:18:33 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
198     |2026-05-12 13:10:17 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
197     |2026-05-12 13:10:00 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
196     |2026-05-12 10:46:00 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
195     |2026-05-12 10:45:59 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
194     |2026-05-12 10:32:14 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
193     |2026-05-12 10:31:17 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
192     |2026-05-12 10:04:10 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
191     |2026-05-12 10:03:12 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
190     |2026-05-12 09:51:41 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
189     |2026-05-12 09:51:41 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
188     |2026-05-12 08:40:38 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
187     |2026-05-12 08:39:59 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
186     |2026-05-11 17:58:07 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
185     |2026-05-11 17:58:06 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
184     |2026-05-11 17:53:06 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
183     |2026-05-11 17:53:05 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
182     |2026-05-11 14:11:39 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x1.
181     |2026-05-11 14:11:07 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
180     |2026-05-11 10:44:14 |Normal      |0x2C000011  |Asserted    |The host was restarted by command.
179     |2026-05-11 10:32:54 |Normal      |0x2C000009  |Asserted    |ACPI is in the working state.
178     |2026-05-11 10:32:53 |Normal      |0x2C000011  |Asserted    |The host was restarted by command.
177     |2026-05-11 10:32:17 |Normal      |0x2C00000B  |Asserted    |ACPI is in the soft-off state.
176     |2026-05-11 10:22:30 |Normal      |0x2C000011  |Asserted    |The host was restarted by command.
175     |2026-05-11 10:07:49 |Normal      |0x2C000011  |Asserted    |The host was restarted by command.
174     |2026-05-11 10:07:48 |Normal      |0x2C000009  |Asserted    |ACPI is in the working state.
173     |2026-05-11 10:06:06 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
172     |2026-05-11 10:05:46 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
171     |2026-05-09 19:36:52 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
170     |2026-05-09 19:36:14 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
169     |2026-05-09 14:08:43 |Minor       |0x08000007  |Asserted    |Failed to obtain electronic label data of the PCIe card 255 (SP680).
168     |2026-05-09 14:07:04 |Minor       |0x08000008  |Deasserted  |Failed to obtain electronic label data of the PCIe card 1 (SP680).
167     |2026-05-09 14:05:29 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
166     |2026-05-09 14:05:27 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
165     |2026-05-09 11:11:24 |Minor       |0x08000007  |Asserted    |Failed to obtain electronic label data of the PCIe card 1 (SP680).
164     |2026-05-09 11:04:31 |Normal      |0x1A00006F  |Asserted    |The BMC is reset, with the cause code of 0x2.
163     |2026-05-09 11:04:28 |Normal      |0x1A000021  |Asserted    |BMC is reset and started.
162     |1970-01-03 06:36:41 |Minor       |0x08000007  |Asserted    |Failed to obtain electronic label data of the PCIe card 2 (SP680).
161     |1970-01-02 23:38:29 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
160     |1970-01-02 23:38:29 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
159     |1970-01-02 07:16:03 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
158     |1970-01-02 07:15:45 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
157     |1970-01-02 05:40:09 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
156     |1970-01-02 05:39:42 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
155     |1970-01-02 04:39:02 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
154     |1970-01-02 04:38:58 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
153     |1970-01-02 02:46:35 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
152     |1970-01-02 02:46:32 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
151     |1970-01-02 01:46:13 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
150     |1970-01-02 01:46:12 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
149     |1970-01-02 00:33:34 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
148     |1970-01-02 00:33:33 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
147     |1970-01-01 23:41:59 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
146     |1970-01-01 23:41:30 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
145     |1970-01-01 10:02:34 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
144     |1970-01-01 10:02:33 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
143     |1970-01-01 09:07:02 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
142     |1970-01-01 09:06:58 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
141     |1970-01-01 00:04:31 |Major       |0x0300001F  |Asserted    |Server power failure occurred at 1970-01-01 00:01:30 UTC, The power has been already restored.
140     |1970-01-01 00:02:44 |Critical    |0x0300000D  |Asserted    |The AC/DC input of PSU 1 is lost or out-of-range (SN:2102314KMUW0QB009279, BN:02314KMU).
139     |1970-01-01 00:02:43 |Normal      |0x1A00000D  |Asserted    |openUBMC is restarted after AC power supply is restored.
138     |1970-01-01 00:02:19 |Minor       |0x1A000049  |Asserted    |Insecure protocol RMCP is enabled in the system.
137     |1970-01-03 23:46:18 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
136     |1970-01-03 23:45:55 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
135     |1970-01-03 22:22:21 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
134     |1970-01-03 22:22:00 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
133     |1970-01-03 20:59:55 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
132     |1970-01-03 20:59:34 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
131     |1970-01-03 20:31:20 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
130     |1970-01-03 20:30:57 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
129     |1970-01-02 22:26:06 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
128     |1970-01-02 22:25:43 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
127     |1970-01-01 18:00:26 |Minor       |0x08000007  |Asserted    |Failed to obtain electronic label data of the PCIe card 255 (SP680).
126     |1970-01-01 17:34:22 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
125     |1970-01-01 17:34:03 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
124     |1970-01-01 03:06:49 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
123     |1970-01-01 03:06:47 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
122     |1970-01-01 02:25:14 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
121     |1970-01-01 02:25:12 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
120     |1970-01-01 02:06:15 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
119     |1970-01-01 02:05:32 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
118     |1970-01-01 01:21:19 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
117     |1970-01-01 01:20:33 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
116     |1970-01-01 00:22:15 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
115     |1970-01-01 00:21:54 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
114     |1970-01-01 00:17:43 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
113     |1970-01-01 00:17:37 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
112     |1970-01-01 00:04:31 |Major       |0x0300001F  |Asserted    |Server power failure occurred at 1970-01-01 00:01:31 UTC, The power has been already restored.
111     |1970-01-01 00:02:19 |Critical    |0x0300000D  |Asserted    |The AC/DC input of PSU 1 is lost or out-of-range (SN:2102314KMUW0QB009279, BN:02314KMU).
110     |1970-01-01 00:02:18 |Normal      |0x1A00000D  |Asserted    |openUBMC is restarted after AC power supply is restored.
109     |1970-01-01 00:02:18 |Minor       |0x1A000049  |Asserted    |Insecure protocol RMCP is enabled in the system.
108     |1970-01-01 00:04:30 |Major       |0x0300001F  |Asserted    |Server power failure occurred at 2026-04-27 14:17:04 UTC, The power has been already restored.
107     |1970-01-01 00:02:42 |Critical    |0x0300000D  |Asserted    |The AC/DC input of PSU 1 is lost or out-of-range (SN:2102314KMUW0QB009279, BN:02314KMU).
106     |1970-01-01 00:02:19 |Normal      |0x1A00000D  |Asserted    |openUBMC is restarted after AC power supply is restored.
105     |1970-01-01 00:02:19 |Minor       |0x1A000049  |Asserted    |Insecure protocol RMCP is enabled in the system.
104     |2026-04-27 14:17:31 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
103     |2026-04-27 14:16:59 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
102     |2026-04-27 14:00:51 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
101     |2026-04-27 14:00:28 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x10.
100     |2026-04-27 14:00:53 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
99      |2026-04-27 14:00:27 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x10.
98      |2026-04-27 14:01:17 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
97      |2026-04-27 14:00:26 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
96      |2026-04-27 09:27:56 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
95      |2026-04-27 09:27:28 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x10.
94      |2026-04-27 09:27:54 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
93      |2026-04-27 09:27:30 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x10.
92      |2026-04-27 09:27:55 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
91      |2026-04-27 09:27:34 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
90      |2026-04-24 17:08:05 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
89      |2026-04-24 17:07:21 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x10.
88      |2026-04-24 16:58:15 |Major       |0x29000013  |Asserted    |Abnormal Rx signal of optical module is detected on Port 1 on NIC 2 (SF223D-H).
87      |2026-04-24 16:58:14 |Major       |0x29000013  |Asserted    |Abnormal Rx signal of optical module is detected on Port 2 on NIC 2 (SF223D-H).
86      |2026-04-24 16:57:06 |Major       |0x29000014  |Deasserted  |Abnormal Rx signal of optical module is detected on Port 1 on NIC 2 (SF223D-H).
85      |2026-04-24 16:57:05 |Major       |0x29000014  |Deasserted  |Abnormal Rx signal of optical module is detected on Port 2 on NIC 2 (SF223D-H).
84      |2026-04-24 16:56:48 |Normal      |0x2C00000F  |Asserted    |The host was restarted due to unrecognized reason.
83      |2026-04-24 16:53:28 |Major       |0x29000013  |Asserted    |Abnormal Rx signal of optical module is detected on Port 1 on NIC 2 (SF223D-H).
82      |2026-04-24 16:53:28 |Major       |0x29000013  |Asserted    |Abnormal Rx signal of optical module is detected on Port 2 on NIC 2 (SF223D-H).
81      |2026-04-24 16:52:20 |Major       |0x29000014  |Deasserted  |Abnormal Rx signal of optical module is detected on Port 1 on NIC 2 (SF223D-H).
80      |2026-04-24 16:52:19 |Major       |0x29000014  |Deasserted  |Abnormal Rx signal of optical module is detected on Port 2 on NIC 2 (SF223D-H).
79      |2026-04-24 16:52:02 |Normal      |0x2C000011  |Asserted    |The host was restarted by command.
78      |2026-04-24 16:45:58 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x10.
77      |2026-04-24 16:45:31 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
76      |2026-04-24 16:05:43 |Major       |0x29000013  |Asserted    |Abnormal Rx signal of optical module is detected on Port 1 on NIC 2 (SF223D-H).
75      |2026-04-24 16:05:42 |Major       |0x29000013  |Asserted    |Abnormal Rx signal of optical module is detected on Port 2 on NIC 2 (SF223D-H).
74      |2026-04-24 16:04:45 |Major       |0x29000014  |Deasserted  |Abnormal Rx signal of optical module is detected on Port 1 on NIC 2 (SF223D-H).
73      |2026-04-24 16:04:44 |Major       |0x29000014  |Deasserted  |Abnormal Rx signal of optical module is detected on Port 2 on NIC 2 (SF223D-H).
72      |2026-04-24 16:04:28 |Normal      |0x2C000011  |Asserted    |The host was restarted by command.
71      |2026-04-24 15:30:04 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
70      |2026-04-24 15:29:13 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
69      |2026-04-24 15:06:24 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
68      |2026-04-24 15:05:33 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
67      |2026-04-24 11:28:09 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
66      |2026-04-24 11:27:44 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
65      |2026-04-24 10:58:50 |Normal      |0x2C000011  |Asserted    |The host was restarted by command.
64      |2026-04-24 10:41:47 |Normal      |0x2C000011  |Asserted    |The host was restarted by command.
63      |2026-04-24 10:41:45 |Normal      |0x2C000009  |Asserted    |ACPI is in the working state.
62      |2026-04-24 10:03:45 |Normal      |0x2C00000B  |Asserted    |ACPI is in the soft-off state.
61      |2026-04-24 10:03:43 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
60      |2026-04-24 10:03:28 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
59      |2026-04-23 16:30:41 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
58      |2026-04-23 16:30:14 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
57      |2026-04-23 15:20:29 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
56      |2026-04-23 15:20:11 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
55      |2026-04-23 13:40:42 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
54      |2026-04-23 13:40:19 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
53      |2026-04-23 11:02:21 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
52      |2026-04-23 11:02:18 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
51      |2026-04-23 09:19:50 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
50      |2026-04-23 09:19:20 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
49      |2026-04-22 17:14:24 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
48      |2026-04-22 17:14:08 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
47      |2026-04-22 15:54:07 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
46      |2026-04-22 15:53:13 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
45      |2026-04-22 15:17:56 |Normal      |0x1A000058  |Deasserted  |The user 3 has been locked.
44      |2026-04-22 15:12:50 |Normal      |0x1A000057  |Asserted    |The user 3 has been locked.
43      |2026-04-22 10:42:14 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
42      |2026-04-22 10:41:50 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
41      |2026-04-21 15:28:51 |Minor       |0x1A000049  |Asserted    |Insecure protocol RMCP is enabled in the system.
40      |2026-04-21 12:15:33 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
39      |2026-04-21 12:14:47 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
38      |2026-04-21 09:36:35 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
37      |2026-04-21 09:36:05 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
36      |2026-04-17 15:57:09 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
35      |2026-04-17 15:56:18 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
34      |2026-04-17 15:08:27 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
33      |2026-04-17 15:08:08 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
32      |2026-04-17 11:25:41 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
31      |2026-04-17 11:25:19 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
30      |2026-04-16 17:02:47 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
29      |2026-04-16 17:01:58 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
28      |2026-04-16 16:29:48 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
27      |2026-04-16 16:29:23 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
26      |2026-04-16 15:59:37 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
25      |2026-04-16 15:59:10 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
24      |2026-04-16 15:21:41 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
23      |2026-04-16 15:21:15 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
22      |2026-04-16 15:15:40 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
21      |2026-04-16 15:15:20 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
20      |2026-04-16 14:21:14 |Minor       |0x1A000044  |Deasserted  |The data written to the NAND flash in last 15 days exceeds 12G.
19      |2026-04-16 14:20:47 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
18      |2026-04-16 14:20:24 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
17      |2026-04-10 17:12:45 |Minor       |0x12000002  |Deasserted  |The air inlet temperature (41 degrees C) exceeds the overtemperature threshold (41 degrees C).
16      |2026-04-10 16:21:07 |Minor       |0x12000001  |Asserted    |The air inlet temperature (41 degrees C) exceeds the overtemperature threshold (41 degrees C).
15      |2026-04-10 11:30:06 |Minor       |0x12000002  |Deasserted  |The air inlet temperature (41 degrees C) exceeds the overtemperature threshold (41 degrees C).
14      |2026-04-10 11:10:32 |Minor       |0x12000001  |Asserted    |The air inlet temperature (41 degrees C) exceeds the overtemperature threshold (41 degrees C).
13      |2026-04-09 18:41:46 |Minor       |0x12000002  |Deasserted  |The air inlet temperature (42 degrees C) exceeds the overtemperature threshold (41 degrees C).
12      |2026-04-09 17:51:35 |Major       |0x12000004  |Deasserted  |The air inlet temperature (43 degrees C) exceeds the overtemperature threshold (43 degrees C).
11      |2026-04-09 17:38:48 |Minor       |0x12000001  |Asserted    |The air inlet temperature (42 degrees C) exceeds the overtemperature threshold (41 degrees C).
10      |2026-04-09 17:33:03 |Minor       |0x12000002  |Deasserted  |The air inlet temperature (42 degrees C) exceeds the overtemperature threshold (41 degrees C).
9       |2026-04-09 17:31:11 |Minor       |0x12000001  |Asserted    |The air inlet temperature (42 degrees C) exceeds the overtemperature threshold (41 degrees C).
8       |2026-04-09 17:28:06 |Major       |0x12000003  |Asserted    |The air inlet temperature (43 degrees C) exceeds the overtemperature threshold (43 degrees C).
7       |2026-04-09 17:28:06 |Minor       |0x12000002  |Deasserted  |The air inlet temperature (41 degrees C) exceeds the overtemperature threshold (41 degrees C).
6       |2026-04-09 16:14:24 |Minor       |0x12000001  |Asserted    |The air inlet temperature (41 degrees C) exceeds the overtemperature threshold (41 degrees C).
5       |2026-04-07 19:45:52 |Major       |0x29000013  |Asserted    |Abnormal Rx signal of optical module is detected on Port 1 on NIC 2 (SF223D-H).
4       |2026-04-07 19:45:49 |Major       |0x29000013  |Asserted    |Abnormal Rx signal of optical module is detected on Port 2 on NIC 2 (SF223D-H).
3       |2026-04-07 19:44:17 |Normal      |0x2C000009  |Asserted    |ACPI is in the working state.
2       |2026-04-07 19:44:16 |Normal      |0x2C000011  |Asserted    |The host was restarted by command.
1       |2026-04-07 11:03:02 |Normal      |0x1A00000F  |Asserted    |openUBMC event records are cleared.
