ID      |Generation Time     |Severity    |Event Code  |Status      |Event Description
537     |2026-07-06 17:38:18 |Normal      |0x2C00002D  |Asserted    |Power capping failed.
536     |2026-07-06 17:33:06 |Minor       |0x0800006F  |Asserted    |The PCIe card 12 (8576-X1) bandwidth decreased.
535     |2026-07-06 17:30:52 |Normal      |0x2C00002D  |Asserted    |Power capping failed.
534     |2026-07-06 17:30:52 |Normal      |0x2C000095  |Asserted    |Power capping is triggered.
533     |2026-07-06 17:30:20 |Major       |0x0300001F  |Asserted    |Server power failure occurred at 2026-07-06 17:24:30 UTC, The power has been already restored.
532     |2026-07-06 17:30:06 |Normal      |0x2C000009  |Asserted    |ACPI is in the working state.
531     |2026-07-06 17:30:05 |Normal      |0x2C000011  |Asserted    |The host was restarted by command.
530     |2026-07-06 17:28:54 |Critical    |0x0300000D  |Asserted    |The AC/DC input of PSU 1 is lost or out-of-range (SN:G1302262NA241101248, BN:302004098).
529     |2026-07-06 17:28:23 |Minor       |0x1A000049  |Asserted    |Insecure protocol SNMP v2 is enabled in the system.
528     |2026-07-06 17:28:23 |Minor       |0x1A000049  |Asserted    |Insecure protocol SNMP v1 is enabled in the system.
527     |2026-07-06 17:28:22 |Minor       |0x1A000049  |Asserted    |Insecure protocol VNC is enabled in the system.
526     |2026-07-06 17:27:41 |Normal      |0x1A00000D  |Asserted    |openUBMC is restarted after AC power supply is restored.
525     |2026-07-06 17:22:46 |Minor       |0x08000070  |Deasserted  |The PCIe card 12 (8576-X1) bandwidth decreased.
524     |2026-07-06 17:22:44 |Normal      |0x2C00000B  |Asserted    |ACPI is in the soft-off state.
523     |2026-07-06 17:15:50 |Minor       |0x0800006F  |Asserted    |The PCIe card 12 (8576-X1) bandwidth decreased.
522     |2026-07-06 17:14:38 |Normal      |0x2C000095  |Asserted    |Power capping is triggered.
521     |2026-07-06 17:14:14 |Minor       |0x08000070  |Deasserted  |The PCIe card 12 (8576-X1) bandwidth decreased.
520     |2026-07-06 17:14:10 |Normal      |0x2C00000F  |Asserted    |The host was restarted due to unrecognized reason.
519     |2026-07-06 17:07:21 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
518     |2026-07-06 16:09:35 |Normal      |0x2C00002D  |Asserted    |Power capping failed.
517     |2026-07-06 16:02:44 |Normal      |0x2C00002D  |Asserted    |Power capping failed.
516     |2026-07-06 15:14:51 |Minor       |0x0800006F  |Asserted    |The PCIe card 12 (8576-X1) bandwidth decreased.
515     |2026-07-06 15:12:48 |Normal      |0x2C00002D  |Asserted    |Power capping failed.
514     |2026-07-06 15:12:47 |Normal      |0x2C000095  |Asserted    |Power capping is triggered.
513     |2026-07-06 15:11:59 |Normal      |0x2C000011  |Asserted    |The host was restarted by command.
512     |2026-07-06 15:11:59 |Normal      |0x2C000009  |Asserted    |ACPI is in the working state.
511     |2026-07-06 15:08:57 |Major       |0x0300001F  |Asserted    |Server power failure occurred at 2026-07-06 15:03:08 UTC, The power has been already restored.
510     |2026-07-06 15:07:28 |Critical    |0x0300000D  |Asserted    |The AC/DC input of PSU 1 is lost or out-of-range (SN:G1302262NA241101248, BN:302004098).
509     |2026-07-06 15:07:27 |Minor       |0x1A000049  |Asserted    |Insecure protocol SNMP v2 is enabled in the system.
508     |2026-07-06 15:06:59 |Minor       |0x1A000049  |Asserted    |Insecure protocol SNMP v1 is enabled in the system.
507     |2026-07-06 15:06:59 |Normal      |0x1A00000D  |Asserted    |openUBMC is restarted after AC power supply is restored.
506     |2026-07-06 15:06:58 |Minor       |0x1A000049  |Asserted    |Insecure protocol VNC is enabled in the system.
505     |2026-07-06 14:53:21 |Normal      |0x2C00000B  |Asserted    |ACPI is in the soft-off state.
504     |2026-07-06 14:53:20 |Minor       |0x08000070  |Deasserted  |The PCIe card 12 (8576-X1) bandwidth decreased.
503     |2026-07-06 14:51:27 |Normal      |0x2C00002D  |Asserted    |Power capping failed.
502     |2026-07-06 14:48:47 |Major       |0x0300001F  |Asserted    |Server power failure occurred at 2026-07-06 14:43:14 UTC, The power has been already restored.
501     |2026-07-06 14:47:55 |Minor       |0x0800006F  |Asserted    |The PCIe card 12 (8576-X1) bandwidth decreased.
500     |2026-07-06 14:47:52 |Normal      |0x2C00002D  |Asserted    |Power capping failed.
499     |2026-07-06 14:47:26 |Critical    |0x0300000D  |Asserted    |The AC/DC input of PSU 1 is lost or out-of-range (SN:G1302262NA241101248, BN:302004098).
498     |2026-07-06 14:47:26 |Normal      |0x2C000095  |Asserted    |Power capping is triggered.
497     |2026-07-06 14:46:56 |Minor       |0x1A000049  |Asserted    |Insecure protocol SNMP v2 is enabled in the system.
496     |2026-07-06 14:46:56 |Normal      |0x2C000009  |Asserted    |ACPI is in the working state.
495     |2026-07-06 14:46:55 |Minor       |0x1A000049  |Asserted    |Insecure protocol SNMP v1 is enabled in the system.
494     |2026-07-06 14:46:55 |Minor       |0x1A000049  |Asserted    |Insecure protocol VNC is enabled in the system.
493     |2026-07-06 14:46:24 |Normal      |0x1A00000D  |Asserted    |openUBMC is restarted after AC power supply is restored.
492     |2026-07-06 14:46:15 |Normal      |0x2C000017  |Asserted    |The host is restarted after being powered on (Power strategy is 'Turn On').
491     |2026-07-06 14:43:01 |Critical    |0x0300000D  |Asserted    |The AC/DC input of PSU 4 is lost or out-of-range (SN:G1302262NA241101645, BN:302004098).
490     |2026-07-06 14:38:00 |Minor       |0x08000070  |Deasserted  |The PCIe card 12 (8576-X1) bandwidth decreased.
489     |2026-07-06 14:37:58 |Normal      |0x2C00000B  |Asserted    |ACPI is in the soft-off state.
488     |2026-07-06 14:32:13 |Minor       |0x0800006F  |Asserted    |The PCIe card 12 (8576-X1) bandwidth decreased.
487     |2026-07-06 14:31:05 |Normal      |0x2C00002D  |Asserted    |Power capping failed.
486     |2026-07-06 14:31:05 |Normal      |0x2C000095  |Asserted    |Power capping is triggered.
485     |2026-07-06 14:30:19 |Normal      |0x2C000009  |Asserted    |ACPI is in the working state.
484     |2026-07-06 14:30:18 |Normal      |0x2C000011  |Asserted    |The host was restarted by command.
483     |2026-07-06 14:29:29 |Minor       |0x08000070  |Deasserted  |The PCIe card 12 (8576-X1) bandwidth decreased.
482     |2026-07-06 14:29:28 |Normal      |0x2C00000B  |Asserted    |ACPI is in the soft-off state.
481     |2026-07-06 14:27:26 |Normal      |0x2C00002D  |Asserted    |Power capping failed.
480     |2026-07-06 11:27:51 |Normal      |0x2C00002D  |Asserted    |Power capping failed.
479     |2026-07-06 11:25:29 |Normal      |0x2C00002D  |Asserted    |Power capping failed.
478     |2026-07-06 10:23:36 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
477     |2026-07-06 10:23:34 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
476     |2026-07-06 00:21:59 |Normal      |0x2C00002D  |Asserted    |Power capping failed.
475     |2026-07-05 23:00:14 |Normal      |0x2C00002D  |Asserted    |Power capping failed.
474     |2026-07-05 02:09:56 |Normal      |0x2C00002D  |Asserted    |Power capping failed.
473     |2026-07-05 01:56:27 |Normal      |0x2C00002D  |Asserted    |Power capping failed.
472     |2026-07-05 01:29:19 |Normal      |0x2C00002D  |Asserted    |Power capping failed.
471     |2026-07-03 20:45:27 |Normal      |0x1A00002B  |Asserted    |openUBMC failed to synchronize time with the NTP server.
470     |2026-07-03 15:21:25 |Normal      |0x2C000095  |Asserted    |Power capping is triggered.
469     |2026-07-03 15:19:25 |Normal      |0x2C000095  |Asserted    |Power capping is triggered.
468     |2026-07-03 15:18:54 |Minor       |0x0800006F  |Asserted    |The PCIe card 12 (8576-X1) bandwidth decreased.
467     |2026-07-03 15:18:20 |Normal      |0x2C000095  |Asserted    |Power capping is triggered.
466     |2026-07-03 15:17:50 |Minor       |0x08000070  |Deasserted  |The PCIe card 12 (8576-X1) bandwidth decreased.
465     |2026-07-03 15:17:47 |Normal      |0x2C00000F  |Asserted    |The host was restarted due to unrecognized reason.
464     |2026-07-03 15:16:24 |Normal      |0x2C000095  |Asserted    |Power capping is triggered.
463     |2026-07-03 15:14:04 |Normal      |0x2C000095  |Asserted    |Power capping is triggered.
462     |2026-07-03 15:13:04 |Normal      |0x2C000095  |Asserted    |Power capping is triggered.
461     |2026-07-03 15:09:09 |Normal      |0x2C000095  |Asserted    |Power capping is triggered.
460     |2026-07-03 15:07:49 |Normal      |0x2C000095  |Asserted    |Power capping is triggered.
459     |2026-07-03 15:07:17 |Minor       |0x0800006F  |Asserted    |The PCIe card 12 (8576-X1) bandwidth decreased.
458     |2026-07-03 15:06:18 |Normal      |0x2C000095  |Asserted    |Power capping is triggered.
457     |2026-07-03 15:05:34 |Normal      |0x2C000009  |Asserted    |ACPI is in the working state.
456     |2026-07-03 15:05:34 |Normal      |0x2C000011  |Asserted    |The host was restarted by command.
455     |2026-07-02 20:31:37 |Minor       |0x08000070  |Deasserted  |The PCIe card 12 (8576-X1) bandwidth decreased.
454     |2026-07-02 20:31:35 |Normal      |0x2C00000B  |Asserted    |ACPI is in the soft-off state.
453     |2026-07-02 15:54:18 |Minor       |0x0800006F  |Asserted    |The PCIe card 12 (8576-X1) bandwidth decreased.
452     |2026-07-02 15:52:28 |Normal      |0x2C000095  |Asserted    |Power capping is triggered.
451     |2026-07-02 15:51:43 |Normal      |0x2C00002D  |Asserted    |Power capping failed.
450     |2026-07-02 15:51:43 |Normal      |0x2C000009  |Asserted    |ACPI is in the working state.
449     |2026-07-02 15:51:42 |Normal      |0x2C000011  |Asserted    |The host was restarted by command.
448     |2026-07-02 15:51:24 |Minor       |0x08000070  |Deasserted  |The PCIe card 12 (8576-X1) bandwidth decreased.
447     |2026-07-02 15:51:23 |Normal      |0x2C00000B  |Asserted    |ACPI is in the soft-off state.
446     |2026-07-02 15:49:50 |Normal      |0x2C00002D  |Asserted    |Power capping failed.
445     |2026-07-02 15:04:25 |Minor       |0x0800006F  |Asserted    |The PCIe card 12 (8576-X1) bandwidth decreased.
444     |2026-07-02 15:02:35 |Normal      |0x2C000095  |Asserted    |Power capping is triggered.
443     |2026-07-02 15:01:52 |Normal      |0x2C00002D  |Asserted    |Power capping failed.
442     |2026-07-02 15:01:51 |Normal      |0x2C000011  |Asserted    |The host was restarted by command.
441     |2026-07-02 15:01:50 |Normal      |0x2C000009  |Asserted    |ACPI is in the working state.
440     |2026-07-02 14:52:58 |Minor       |0x08000070  |Deasserted  |The PCIe card 12 (8576-X1) bandwidth decreased.
439     |2026-07-02 14:52:57 |Normal      |0x2C00000B  |Asserted    |ACPI is in the soft-off state.
438     |2026-07-02 14:35:54 |Minor       |0x0800006F  |Asserted    |The PCIe card 12 (8576-X1) bandwidth decreased.
437     |2026-07-02 14:34:44 |Normal      |0x2C000095  |Asserted    |Power capping is triggered.
436     |2026-07-02 14:34:19 |Minor       |0x08000070  |Deasserted  |The PCIe card 12 (8576-X1) bandwidth decreased.
435     |2026-07-02 14:34:15 |Normal      |0x2C000011  |Asserted    |The host was restarted by command.
434     |2026-07-02 14:30:26 |Minor       |0x0800006F  |Asserted    |The PCIe card 12 (8576-X1) bandwidth decreased.
433     |2026-07-02 14:28:34 |Normal      |0x2C000095  |Asserted    |Power capping is triggered.
432     |2026-07-02 14:27:51 |Normal      |0x2C00002D  |Asserted    |Power capping failed.
431     |2026-07-02 14:27:50 |Normal      |0x2C000009  |Asserted    |ACPI is in the working state.
430     |2026-07-02 14:27:50 |Normal      |0x2C000011  |Asserted    |The host was restarted by command.
429     |2026-07-02 14:27:09 |Minor       |0x08000070  |Deasserted  |The PCIe card 12 (8576-X1) bandwidth decreased.
428     |2026-07-02 14:27:06 |Normal      |0x2C00000B  |Asserted    |ACPI is in the soft-off state.
427     |2026-07-02 14:24:31 |Normal      |0x2C00002D  |Asserted    |Power capping failed.
426     |2026-07-02 14:22:36 |Normal      |0x2C00002D  |Asserted    |Power capping failed.
425     |2026-07-02 14:14:37 |Normal      |0x2C000095  |Asserted    |Power capping is triggered.
424     |2026-07-02 11:28:54 |Normal      |0x2C00002D  |Asserted    |Power capping failed.
423     |2026-07-02 10:48:55 |Normal      |0x2C00002D  |Asserted    |Power capping failed.
422     |2026-07-02 10:48:55 |Normal      |0x2C00002D  |Asserted    |Power capping failed.
421     |2026-07-02 10:47:20 |Normal      |0x2C00002D  |Asserted    |Power capping failed.
420     |2026-07-02 10:07:50 |Normal      |0x2C00002D  |Asserted    |Power capping failed.
419     |2026-07-01 14:59:56 |Minor       |0x1A000049  |Asserted    |Insecure protocol SNMP v1 is enabled in the system.
418     |2026-07-01 14:59:56 |Minor       |0x1A000049  |Asserted    |Insecure protocol SNMP v2 is enabled in the system.
417     |2026-07-01 14:19:47 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
416     |2026-07-01 14:19:43 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
415     |2026-07-01 14:14:29 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
414     |2026-07-01 14:14:14 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
413     |2026-07-01 14:10:31 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
412     |2026-07-01 14:09:00 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
411     |2026-07-01 14:04:50 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
410     |2026-07-01 14:04:07 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
409     |2026-07-01 13:59:44 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
408     |2026-07-01 13:58:53 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
407     |2026-07-01 13:53:48 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
406     |2026-07-01 13:53:28 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
405     |2026-07-01 13:49:12 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
404     |2026-07-01 13:48:15 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
403     |2026-07-01 13:43:30 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
402     |2026-07-01 13:43:13 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
401     |2026-07-01 13:38:58 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
400     |2026-07-01 13:38:06 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
399     |2026-07-01 13:33:46 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
398     |2026-07-01 13:32:55 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
397     |2026-07-01 13:27:59 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
396     |2026-07-01 13:27:56 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
395     |2026-07-01 13:22:50 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
394     |2026-07-01 13:22:48 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
393     |2026-07-01 13:18:50 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
392     |2026-07-01 13:17:29 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
391     |2026-07-01 13:12:29 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
390     |2026-07-01 13:12:16 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
389     |2026-07-01 13:08:08 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
388     |2026-07-01 13:07:30 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
387     |2026-07-01 13:02:38 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
386     |2026-07-01 13:01:49 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
385     |2026-07-01 12:57:31 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
384     |2026-07-01 12:56:51 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
383     |2026-07-01 12:52:22 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
382     |2026-07-01 12:51:35 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
381     |2026-07-01 12:47:10 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
380     |2026-07-01 12:46:12 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
379     |2026-07-01 12:42:00 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
378     |2026-07-01 12:41:20 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
377     |2026-07-01 12:36:53 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
376     |2026-07-01 12:35:58 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
375     |2026-07-01 12:31:05 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
374     |2026-07-01 12:31:02 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
373     |2026-07-01 12:25:47 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
372     |2026-07-01 12:25:31 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
371     |2026-07-01 12:21:23 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
370     |2026-07-01 12:20:30 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
369     |2026-07-01 12:16:10 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
368     |2026-07-01 12:15:19 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
367     |2026-07-01 12:11:03 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
366     |2026-07-01 12:10:25 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
365     |2026-07-01 12:05:48 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
364     |2026-07-01 12:05:01 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
363     |2026-07-01 12:00:31 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
362     |2026-07-01 11:59:44 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
361     |2026-07-01 11:55:32 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
360     |2026-07-01 11:54:43 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
359     |2026-07-01 11:50:13 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
358     |2026-07-01 11:49:26 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
357     |2026-07-01 11:45:12 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
356     |2026-07-01 11:44:31 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
355     |2026-07-01 11:39:19 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
354     |2026-07-01 11:39:06 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
353     |2026-07-01 11:34:48 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
352     |2026-07-01 11:33:52 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
351     |2026-07-01 11:29:46 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
350     |2026-07-01 11:29:08 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
349     |2026-07-01 11:24:23 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
348     |2026-07-01 11:23:44 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
347     |2026-07-01 11:18:30 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
346     |2026-07-01 11:18:17 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
345     |2026-07-01 11:13:26 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
344     |2026-07-01 11:13:11 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
343     |2026-07-01 11:08:18 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
342     |2026-07-01 11:08:05 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
341     |2026-07-01 11:03:48 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
340     |2026-07-01 11:02:49 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
339     |2026-07-01 10:58:32 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
338     |2026-07-01 10:57:49 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
337     |2026-07-01 10:52:45 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
336     |2026-07-01 10:52:28 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
335     |2026-07-01 10:48:15 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
334     |2026-07-01 10:47:17 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
333     |2026-07-01 10:42:21 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
332     |2026-07-01 10:41:58 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
331     |2026-07-01 10:39:05 |Normal      |0x29000002  |Deasserted  |PCIe Card 12 (8576-X1) Port 1 disconnected.
330     |2026-07-01 10:38:22 |Normal      |0x29000001  |Asserted    |PCIe Card 12 (8576-X1) Port 1 disconnected.
329     |2026-07-01 10:37:07 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
328     |2026-07-01 10:36:51 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
327     |2026-07-01 10:34:00 |Normal      |0x29000002  |Deasserted  |PCIe Card 12 (8576-X1) Port 1 disconnected.
326     |2026-07-01 10:33:14 |Normal      |0x29000001  |Asserted    |PCIe Card 12 (8576-X1) Port 1 disconnected.
325     |2026-07-01 10:32:40 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
324     |2026-07-01 10:31:59 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
323     |2026-07-01 10:26:50 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
322     |2026-07-01 10:26:37 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
321     |2026-07-01 10:22:17 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
320     |2026-07-01 10:21:36 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
319     |2026-07-01 10:17:05 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
318     |2026-07-01 10:16:12 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
317     |2026-07-01 10:10:59 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
316     |2026-07-01 10:10:44 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
315     |2026-07-01 10:06:27 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
314     |2026-07-01 10:06:11 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
313     |2026-07-01 10:01:02 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
312     |2026-07-01 10:00:55 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
311     |2026-07-01 09:55:36 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
310     |2026-07-01 09:55:25 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
309     |2026-07-01 09:50:32 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
308     |2026-07-01 09:50:14 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
307     |2026-07-01 09:45:22 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
306     |2026-07-01 09:45:11 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
305     |2026-07-01 09:40:49 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
304     |2026-07-01 09:40:10 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
303     |2026-07-01 09:35:33 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
302     |2026-07-01 09:34:47 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
301     |2026-07-01 09:29:55 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
300     |2026-07-01 09:29:51 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
299     |2026-07-01 09:24:40 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
298     |2026-07-01 09:24:36 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
297     |2026-07-01 09:20:14 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
296     |2026-07-01 09:19:37 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
295     |2026-07-01 09:14:10 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
294     |2026-07-01 09:14:02 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
293     |2026-07-01 09:09:43 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
292     |2026-07-01 09:08:53 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
291     |2026-07-01 09:04:38 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
290     |2026-07-01 09:03:56 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
289     |2026-07-01 08:59:24 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
288     |2026-07-01 08:58:31 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
287     |2026-07-01 08:54:08 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
286     |2026-07-01 08:53:24 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
285     |2026-07-01 08:49:08 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
284     |2026-07-01 08:48:30 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
283     |2026-07-01 08:43:55 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
282     |2026-07-01 08:43:16 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
281     |2026-07-01 08:38:41 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
280     |2026-07-01 08:38:01 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
279     |2026-07-01 08:32:54 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
278     |2026-07-01 08:32:36 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
277     |2026-07-01 08:28:28 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
276     |2026-07-01 08:27:47 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
275     |2026-07-01 08:22:33 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
274     |2026-07-01 08:22:20 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
273     |2026-07-01 08:18:02 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
272     |2026-07-01 08:17:20 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
271     |2026-07-01 08:12:06 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
270     |2026-07-01 08:11:55 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
269     |2026-07-01 08:07:05 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
268     |2026-07-01 08:07:01 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
267     |2026-07-01 08:01:54 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
266     |2026-07-01 08:01:39 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
265     |2026-07-01 07:57:25 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
264     |2026-07-01 07:56:33 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
263     |2026-07-01 07:51:23 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
262     |2026-07-01 07:51:20 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
261     |2026-07-01 07:47:37 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
260     |2026-07-01 07:46:01 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
259     |2026-07-01 07:41:48 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
258     |2026-07-01 07:40:54 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
257     |2026-07-01 07:35:55 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
256     |2026-07-01 07:35:52 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
255     |2026-07-01 07:30:35 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
254     |2026-07-01 07:30:31 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
253     |2026-07-01 07:26:20 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
252     |2026-07-01 07:25:42 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
251     |2026-07-01 07:21:38 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
250     |2026-07-01 07:20:10 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
249     |2026-07-01 07:16:28 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
248     |2026-07-01 07:14:59 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
247     |2026-07-01 07:10:09 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
246     |2026-07-01 07:10:03 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
245     |2026-07-01 07:05:02 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
244     |2026-07-01 07:04:44 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
243     |2026-07-01 07:00:29 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
242     |2026-07-01 06:59:41 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
241     |2026-07-01 06:54:41 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
240     |2026-07-01 06:54:38 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
239     |2026-07-01 06:49:59 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
238     |2026-07-01 06:49:04 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
237     |2026-07-01 06:44:55 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
236     |2026-07-01 06:43:59 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
235     |2026-07-01 06:39:07 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
234     |2026-07-01 06:38:57 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
233     |2026-07-01 06:34:35 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
232     |2026-07-01 06:33:55 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
231     |2026-07-01 06:29:18 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
230     |2026-07-01 06:28:38 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
229     |2026-07-01 06:24:14 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
228     |2026-07-01 06:23:33 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
227     |2026-07-01 06:19:08 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
226     |2026-07-01 06:18:29 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
225     |2026-07-01 06:13:20 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
224     |2026-07-01 06:13:07 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
223     |2026-07-01 06:08:05 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
222     |2026-07-01 06:07:58 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
221     |2026-07-01 06:02:53 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
220     |2026-07-01 06:02:36 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
219     |2026-07-01 05:57:41 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
218     |2026-07-01 05:57:26 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
217     |2026-07-01 05:53:11 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
216     |2026-07-01 05:52:16 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
215     |2026-07-01 05:47:24 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
214     |2026-07-01 05:47:05 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
213     |2026-07-01 05:42:46 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
212     |2026-07-01 05:42:01 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
211     |2026-07-01 05:37:02 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
210     |2026-07-01 05:36:43 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
209     |2026-07-01 05:31:56 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
208     |2026-07-01 05:31:40 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
207     |2026-07-01 05:26:44 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
206     |2026-07-01 05:26:40 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
205     |2026-07-01 05:22:06 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
204     |2026-07-01 05:21:27 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
203     |2026-07-01 05:16:48 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
202     |2026-07-01 05:16:09 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
201     |2026-07-01 05:11:10 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
200     |2026-07-01 05:10:49 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
199     |2026-07-01 05:07:29 |Normal      |0x2C00002D  |Asserted    |Power capping failed.
198     |2026-07-01 05:05:46 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
197     |2026-07-01 05:05:33 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
196     |2026-07-01 05:01:57 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
195     |2026-07-01 05:00:46 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
194     |2026-07-01 04:57:36 |Normal      |0x2C00002D  |Asserted    |Power capping failed.
193     |2026-07-01 04:55:25 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
192     |2026-07-01 04:55:12 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
191     |2026-07-01 04:52:05 |Normal      |0x2C00002D  |Asserted    |Power capping failed.
190     |2026-07-01 04:50:26 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
189     |2026-07-01 04:50:22 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
188     |2026-07-01 04:45:09 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
187     |2026-07-01 04:45:00 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
186     |2026-07-01 04:40:43 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
185     |2026-07-01 04:40:01 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
184     |2026-07-01 04:34:48 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
183     |2026-07-01 04:34:29 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
182     |2026-07-01 04:30:21 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
181     |2026-07-01 04:29:20 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
180     |2026-07-01 04:26:30 |Normal      |0x2C00002D  |Asserted    |Power capping failed.
179     |2026-07-01 04:25:06 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
178     |2026-07-01 04:24:12 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
177     |2026-07-01 04:21:23 |Normal      |0x2C00002D  |Asserted    |Power capping failed.
176     |2026-07-01 04:19:15 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
175     |2026-07-01 04:19:01 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
174     |2026-07-01 04:14:10 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
173     |2026-07-01 04:13:52 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
172     |2026-07-01 04:09:01 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
171     |2026-07-01 04:08:40 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
170     |2026-07-01 04:03:56 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
169     |2026-07-01 04:03:53 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
168     |2026-07-01 03:59:10 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
167     |2026-07-01 03:58:18 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
166     |2026-07-01 03:53:06 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
165     |2026-07-01 03:52:57 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
164     |2026-07-01 03:48:09 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
163     |2026-07-01 03:48:05 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
162     |2026-07-01 03:43:45 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
161     |2026-07-01 03:43:06 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
160     |2026-07-01 03:37:36 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
159     |2026-07-01 03:37:21 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
158     |2026-07-01 03:32:40 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
157     |2026-07-01 03:32:28 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
156     |2026-07-01 03:28:03 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
155     |2026-07-01 03:27:09 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
154     |2026-07-01 03:22:24 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
153     |2026-07-01 03:22:20 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
152     |2026-07-01 03:17:46 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
151     |2026-07-01 03:16:50 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
150     |2026-07-01 03:11:50 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
149     |2026-07-01 03:11:42 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
148     |2026-07-01 03:07:21 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
147     |2026-07-01 03:06:42 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
146     |2026-07-01 03:01:36 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
145     |2026-07-01 03:01:17 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
144     |2026-07-01 02:57:01 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
143     |2026-07-01 02:56:20 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
142     |2026-07-01 02:51:10 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
141     |2026-07-01 02:51:06 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
140     |2026-07-01 02:46:44 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
139     |2026-07-01 02:46:04 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
138     |2026-07-01 02:40:55 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
137     |2026-07-01 02:40:50 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
136     |2026-07-01 02:37:00 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
135     |2026-07-01 02:35:52 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
134     |2026-07-01 02:31:06 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
133     |2026-07-01 02:30:22 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
132     |2026-07-01 02:25:59 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
131     |2026-07-01 02:25:11 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
130     |2026-07-01 02:20:43 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
129     |2026-07-01 02:19:44 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
128     |2026-07-01 02:15:05 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
127     |2026-07-01 02:14:54 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
126     |2026-07-01 02:10:29 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
125     |2026-07-01 02:09:32 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
124     |2026-07-01 02:05:09 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
123     |2026-07-01 02:04:15 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
122     |2026-07-01 01:59:27 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
121     |2026-07-01 01:59:15 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
120     |2026-07-01 01:54:58 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
119     |2026-07-01 01:53:58 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
118     |2026-07-01 01:49:43 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
117     |2026-07-01 01:49:04 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
116     |2026-07-01 01:45:00 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
115     |2026-07-01 01:43:40 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
114     |2026-07-01 01:39:53 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
113     |2026-07-01 01:38:42 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
112     |2026-07-01 01:34:15 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
111     |2026-07-01 01:33:22 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
110     |2026-07-01 01:28:54 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
109     |2026-07-01 01:28:01 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
108     |2026-07-01 01:23:12 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
107     |2026-07-01 01:23:05 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
106     |2026-07-01 01:18:01 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
105     |2026-07-01 01:17:42 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
104     |2026-07-01 01:13:59 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
103     |2026-07-01 01:12:50 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
102     |2026-07-01 01:07:38 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
101     |2026-07-01 01:07:22 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
100     |2026-07-01 01:02:17 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
99      |2026-07-01 01:02:09 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
98      |2026-07-01 00:57:18 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
97      |2026-07-01 00:57:13 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
96      |2026-07-01 00:52:45 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
95      |2026-07-01 00:51:47 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
94      |2026-07-01 00:47:40 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
93      |2026-07-01 00:47:04 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
92      |2026-07-01 00:42:25 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
91      |2026-07-01 00:41:34 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
90      |2026-07-01 00:36:35 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
89      |2026-07-01 00:36:33 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
88      |2026-07-01 00:31:29 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
87      |2026-07-01 00:31:06 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
86      |2026-07-01 00:26:14 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
85      |2026-07-01 00:25:59 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
84      |2026-07-01 00:22:11 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
83      |2026-07-01 00:21:00 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
82      |2026-07-01 00:16:33 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
81      |2026-07-01 00:15:39 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
80      |2026-07-01 00:10:43 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
79      |2026-07-01 00:10:27 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
78      |2026-07-01 00:05:36 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
77      |2026-07-01 00:05:33 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
76      |2026-07-01 00:01:32 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
75      |2026-07-01 00:00:26 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
74      |2026-06-30 23:55:49 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
73      |2026-06-30 23:54:53 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
72      |2026-06-30 23:50:38 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
71      |2026-06-30 23:49:43 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
70      |2026-06-30 23:44:40 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
69      |2026-06-30 23:44:28 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
68      |2026-06-30 23:39:45 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
67      |2026-06-30 23:39:41 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
66      |2026-06-30 23:34:31 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
65      |2026-06-30 23:34:13 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
64      |2026-06-30 23:29:26 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
63      |2026-06-30 23:29:04 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
62      |2026-06-30 23:24:45 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
61      |2026-06-30 23:23:50 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
60      |2026-06-30 23:19:03 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
59      |2026-06-30 23:18:43 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
58      |2026-06-30 23:14:31 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
57      |2026-06-30 23:13:52 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
56      |2026-06-30 23:09:14 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
55      |2026-06-30 23:08:32 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
54      |2026-06-30 23:04:30 |Normal      |0x2C00002D  |Asserted    |Power capping failed.
53      |2026-06-30 23:03:56 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
52      |2026-06-30 23:03:15 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
51      |2026-06-30 22:58:59 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
50      |2026-06-30 22:58:06 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
49      |2026-06-30 22:54:11 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
48      |2026-06-30 22:52:51 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
47      |2026-06-30 22:47:58 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
46      |2026-06-30 22:47:54 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
45      |2026-06-30 22:43:17 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
44      |2026-06-30 22:42:37 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
43      |2026-06-30 22:38:06 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
42      |2026-06-30 22:37:25 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
41      |2026-06-30 22:32:22 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
40      |2026-06-30 22:32:19 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
39      |2026-06-30 22:27:15 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
38      |2026-06-30 22:27:12 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
37      |2026-06-30 22:22:41 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
36      |2026-06-30 22:21:47 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
35      |2026-06-30 22:17:32 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
34      |2026-06-30 22:16:40 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
33      |2026-06-30 22:11:42 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
32      |2026-06-30 22:11:38 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
31      |2026-06-30 22:07:07 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
30      |2026-06-30 22:06:23 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
29      |2026-06-30 22:01:53 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
28      |2026-06-30 22:01:06 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
27      |2026-06-30 21:56:50 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
26      |2026-06-30 21:56:03 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
25      |2026-06-30 21:51:34 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
24      |2026-06-30 21:50:41 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
23      |2026-06-30 21:47:53 |Normal      |0x2C00002D  |Asserted    |Power capping failed.
22      |2026-06-30 21:45:47 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
21      |2026-06-30 21:45:30 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
20      |2026-06-30 21:41:18 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
19      |2026-06-30 21:40:38 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
18      |2026-06-30 21:35:33 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
17      |2026-06-30 21:35:13 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
16      |2026-06-30 21:30:50 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
15      |2026-06-30 21:30:09 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
14      |2026-06-30 21:25:11 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
13      |2026-06-30 21:24:54 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
12      |2026-06-30 21:19:54 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
11      |2026-06-30 21:19:49 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
10      |2026-06-30 21:15:23 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
9       |2026-06-30 21:14:23 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
8       |2026-06-30 21:09:39 |Normal      |0x1A00006F  |Asserted    |The openUBMC is reset, with the cause code of 0x2.
7       |2026-06-30 21:09:25 |Normal      |0x1A000021  |Asserted    |openUBMC is reset and started.
6       |2026-06-30 21:05:54 |Normal      |0x2C000095  |Asserted    |Power capping is triggered.
5       |2026-06-30 21:00:10 |Minor       |0x0800006F  |Asserted    |The PCIe card 12 (8576-X1) bandwidth decreased.
4       |2026-06-30 20:58:32 |Minor       |0x08000070  |Deasserted  |The PCIe card 12 (8576-X1) bandwidth decreased.
3       |2026-06-30 20:58:28 |Normal      |0x2C000009  |Asserted    |ACPI is in the working state.
2       |2026-06-30 20:58:27 |Normal      |0x2C000011  |Asserted    |The host was restarted by command.
1       |2026-06-30 20:57:41 |Normal      |0x1A00000F  |Asserted    |openUBMC event records are cleared.
